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Dependencies:   mbed

Fork of LG by igor Apu

el_lin.c@30:17c84ed091b3, 2016-02-05 (annotated)

Committer:
igor_v
Date:
Fri Feb 05 23:21:54 2016 +0000
Revision:
30:17c84ed091b3
Parent:
21:bc8c1cec3da6
Child:
47:d902ef6f7564
1

Who changed what in which revision?

UserRevisionLine numberNew contents of line
igor_v 0:8ad47e2b6f00 1
igor_v 0:8ad47e2b6f00 2 /**--------------File Info---------------------------------------------------------------------------------
igor_v 0:8ad47e2b6f00 3 ** File name: el_lin.c
igor_v 0:8ad47e2b6f00 4 ** Last modified Date: 2011-08-22
igor_v 21:bc8c1cec3da6 5 ** Last Version: V1.00
igor_v 0:8ad47e2b6f00 6 **--------------------------------------------------------------------------------------------------------
igor_v 0:8ad47e2b6f00 7 ** Created by: Electrooptica Incor.
igor_v 0:8ad47e2b6f00 8 ** Created date: 2011-08-22
igor_v 0:8ad47e2b6f00 9 ** Version: V1.00
igor_v 21:bc8c1cec3da6 10 **--------------------------------------------------------------------------------------------------------
igor_v 0:8ad47e2b6f00 11 *********************************************************************************************************/
igor_v 1:f2adcae3d304 12
igor_v 1:f2adcae3d304 13 #include "Global.h"
igor_v 1:f2adcae3d304 14
igor_v 0:8ad47e2b6f00 15
igor_v 0:8ad47e2b6f00 16 #define UART1TEST
igor_v 0:8ad47e2b6f00 17 #define UART1REC
igor_v 0:8ad47e2b6f00 18 /*
igor_v 0:8ad47e2b6f00 19 struct {
igor_v 21:bc8c1cec3da6 20 uint32_t rcv_num_byt;
igor_v 0:8ad47e2b6f00 21 uint32_t rcv_num_byt_old;
igor_v 21:bc8c1cec3da6 22 uint32_t rcv_Rdy;
igor_v 0:8ad47e2b6f00 23 char rcv_copy[64];
igor_v 0:8ad47e2b6f00 24 char rcv_buf[64];
igor_v 0:8ad47e2b6f00 25 int32_t rx_buf_copy;
igor_v 21:bc8c1cec3da6 26 int32_t rcv_byt_copy;
igor_v 0:8ad47e2b6f00 27 }RECIEVER;
igor_v 0:8ad47e2b6f00 28
igor_v 0:8ad47e2b6f00 29 struct {
igor_v 0:8ad47e2b6f00 30 uint32_t trm_num_byt;
igor_v 0:8ad47e2b6f00 31 uint32_t trm_rate;
igor_v 0:8ad47e2b6f00 32 uint32_t trm_cycl;
igor_v 0:8ad47e2b6f00 33 uint32_t num_of_par;
igor_v 0:8ad47e2b6f00 34 char trm_buf[64];
igor_v 0:8ad47e2b6f00 35 void* addr_param[16];
igor_v 0:8ad47e2b6f00 36 uint32_t size_param[16];
igor_v 0:8ad47e2b6f00 37 uint32_t trm_ena;
igor_v 0:8ad47e2b6f00 38 }TRANSMITTER;
igor_v 0:8ad47e2b6f00 39 */
igor_v 21:bc8c1cec3da6 40 uint32_t rcv_num_byt;
igor_v 21:bc8c1cec3da6 41 uint32_t rcv_num_byt_old;
igor_v 21:bc8c1cec3da6 42 uint32_t rcv_Rdy;
igor_v 21:bc8c1cec3da6 43 char rcv_copy[64];
igor_v 21:bc8c1cec3da6 44 char rcv_buf[64];
igor_v 21:bc8c1cec3da6 45 int32_t rx_buf_copy;
igor_v 21:bc8c1cec3da6 46 int32_t rcv_byt_copy;
igor_v 0:8ad47e2b6f00 47
igor_v 21:bc8c1cec3da6 48 uint32_t trm_num_byt;
igor_v 21:bc8c1cec3da6 49 uint32_t trm_rate;
igor_v 21:bc8c1cec3da6 50 uint32_t num_of_par;
igor_v 21:bc8c1cec3da6 51 char trm_buf[64];
igor_v 21:bc8c1cec3da6 52 void* addr_param[16];
igor_v 21:bc8c1cec3da6 53 uint32_t size_param[16];
igor_v 21:bc8c1cec3da6 54 uint32_t trm_ena;
igor_v 21:bc8c1cec3da6 55
igor_v 21:bc8c1cec3da6 56 uint32_t line_err;
igor_v 21:bc8c1cec3da6 57 uint32_t line_sts;
igor_v 21:bc8c1cec3da6 58
igor_v 21:bc8c1cec3da6 59 uint32_t EnablLength = 12;
igor_v 21:bc8c1cec3da6 60 uint32_t LLI0_TypeDef[4];
igor_v 21:bc8c1cec3da6 61 uint32_t LLI1_TypeDef[4];
igor_v 21:bc8c1cec3da6 62 uint32_t EnablTx = 0x80;
igor_v 21:bc8c1cec3da6 63 uint32_t EnablDMA = 0;
igor_v 0:8ad47e2b6f00 64 /******************************************************************************
igor_v 0:8ad47e2b6f00 65 ** Function name: DMA_IRQHandler
igor_v 0:8ad47e2b6f00 66 **
igor_v 0:8ad47e2b6f00 67 ** Descriptions: DMA interrupt handler
igor_v 0:8ad47e2b6f00 68 **
igor_v 0:8ad47e2b6f00 69 ** parameters: None
igor_v 0:8ad47e2b6f00 70 ** Returned value: None
igor_v 21:bc8c1cec3da6 71 **
igor_v 0:8ad47e2b6f00 72 ******************************************************************************/
igor_v 21:bc8c1cec3da6 73 int check_lcc(void) //e. CRC checking //r.проверка контрольной суммы
igor_v 0:8ad47e2b6f00 74 {
igor_v 21:bc8c1cec3da6 75 int iCRC_calc, CRC_calc = 0, CRC_real;
igor_v 21:bc8c1cec3da6 76
igor_v 21:bc8c1cec3da6 77 for (iCRC_calc = 1; iCRC_calc < (rcv_num_byt-2); iCRC_calc++)
igor_v 21:bc8c1cec3da6 78 CRC_calc += rcv_buf[iCRC_calc];
igor_v 21:bc8c1cec3da6 79
igor_v 21:bc8c1cec3da6 80 CRC_real = (rcv_buf[rcv_num_byt-2] << 8) | rcv_buf[rcv_num_byt-1];
igor_v 21:bc8c1cec3da6 81
igor_v 21:bc8c1cec3da6 82 return (CRC_real - CRC_calc);
igor_v 0:8ad47e2b6f00 83 }
igor_v 21:bc8c1cec3da6 84 void PacketSafing(void)
igor_v 21:bc8c1cec3da6 85 {
igor_v 21:bc8c1cec3da6 86 /* int j; static char rcv_buf_copy[16];
igor_v 21:bc8c1cec3da6 87 for (j=2; j<rcv_num_byt; j++)
igor_v 21:bc8c1cec3da6 88 {
igor_v 21:bc8c1cec3da6 89 if (rcv_buf[j] == 0xCC);
igor_v 21:bc8c1cec3da6 90 rcv_buf_copy[0] = 0xCC;
igor_v 21:bc8c1cec3da6 91 // if ((rcv_buf[j] < 3) || (rcv_buf[j] == 0x1F))
igor_v 21:bc8c1cec3da6 92 } */
igor_v 21:bc8c1cec3da6 93 }
igor_v 0:8ad47e2b6f00 94
igor_v 0:8ad47e2b6f00 95 /******************************************************************************
igor_v 0:8ad47e2b6f00 96 ** Function name: Line_1_Rcv
igor_v 0:8ad47e2b6f00 97 **
igor_v 0:8ad47e2b6f00 98 ** Descriptions: receive process preparation
igor_v 0:8ad47e2b6f00 99 **
igor_v 0:8ad47e2b6f00 100 ** parameters: None
igor_v 0:8ad47e2b6f00 101 ** Returned value: None
igor_v 21:bc8c1cec3da6 102 **
igor_v 0:8ad47e2b6f00 103 ******************************************************************************/
igor_v 21:bc8c1cec3da6 104 void Line_1_Rcv(void)
igor_v 21:bc8c1cec3da6 105 {
igor_v 21:bc8c1cec3da6 106 static int ToWaitEnd, ErrReg ;
igor_v 21:bc8c1cec3da6 107
igor_v 0:8ad47e2b6f00 108
igor_v 21:bc8c1cec3da6 109
igor_v 0:8ad47e2b6f00 110
igor_v 21:bc8c1cec3da6 111 while ((LPC_UART1->LSR & RecievBufEmpty) != 0) //e. reciever contain some information
igor_v 21:bc8c1cec3da6 112 rcv_buf[rcv_num_byt++] = LPC_UART1->RBR;//чтение информации из буфера.
igor_v 0:8ad47e2b6f00 113
igor_v 21:bc8c1cec3da6 114
igor_v 0:8ad47e2b6f00 115
igor_v 0:8ad47e2b6f00 116
igor_v 21:bc8c1cec3da6 117 if (( ToWaitEnd > 25000)) { //e. end part of packet is absent //r. не дождались конца пакета
igor_v 21:bc8c1cec3da6 118 do
igor_v 21:bc8c1cec3da6 119 rcv_buf[--rcv_num_byt] = 0;
igor_v 21:bc8c1cec3da6 120 while(rcv_num_byt);
igor_v 21:bc8c1cec3da6 121 rcv_num_byt_old = rcv_num_byt;
igor_v 21:bc8c1cec3da6 122 #if defined UART1REC
igor_v 21:bc8c1cec3da6 123 LPC_UART1->FCR |= RX_FIFO_Reset;
igor_v 21:bc8c1cec3da6 124 #else
igor_v 21:bc8c1cec3da6 125 LPC_UART0->FCR |= RX_FIFO_Reset;
igor_v 21:bc8c1cec3da6 126 #endif
igor_v 21:bc8c1cec3da6 127 // L1_Rc_err (TIMEOUT_ERR);
igor_v 21:bc8c1cec3da6 128 ToWaitEnd = 0;
igor_v 21:bc8c1cec3da6 129 return;
igor_v 21:bc8c1cec3da6 130 }
igor_v 21:bc8c1cec3da6 131 if (rcv_num_byt_old == rcv_num_byt) { //e. we have not received any new bytes
igor_v 21:bc8c1cec3da6 132 if (ToWaitEnd) ToWaitEnd++;
igor_v 21:bc8c1cec3da6 133 return;
igor_v 21:bc8c1cec3da6 134 }
igor_v 21:bc8c1cec3da6 135 rcv_num_byt_old = rcv_num_byt;
igor_v 21:bc8c1cec3da6 136
igor_v 21:bc8c1cec3da6 137 if ((rcv_num_byt < 6) || ((rcv_num_byt & 0x0001) == 1)) {
igor_v 21:bc8c1cec3da6 138 ToWaitEnd++;
igor_v 21:bc8c1cec3da6 139 return;
igor_v 21:bc8c1cec3da6 140 }
igor_v 0:8ad47e2b6f00 141
igor_v 21:bc8c1cec3da6 142 if ((!ToWaitEnd) && (rcv_num_byt > 1)) //e. the header of packet has not recieved //r. ожидаем начало пакета
igor_v 21:bc8c1cec3da6 143 if ((rcv_buf[0] != 0xCC) || (( rcv_buf[1] > 2) && ( rcv_buf[1] != 0x1F))) {
igor_v 21:bc8c1cec3da6 144 // L1_Rc_err (HEADER_ERR);
igor_v 21:bc8c1cec3da6 145 ErrReg |= 5;
igor_v 21:bc8c1cec3da6 146 ToWaitEnd++;
igor_v 21:bc8c1cec3da6 147 return;
igor_v 21:bc8c1cec3da6 148 }
igor_v 21:bc8c1cec3da6 149 // if (ErrReg != 0) //e. trying of recovering of packet //r. спасение следующего пакета
igor_v 21:bc8c1cec3da6 150 // PacketSafing();
igor_v 21:bc8c1cec3da6 151
igor_v 21:bc8c1cec3da6 152
igor_v 21:bc8c1cec3da6 153 if (rcv_num_byt == 6) {
igor_v 21:bc8c1cec3da6 154 if ((rcv_buf[2] == 0x0A) || (rcv_buf[2] == 0xE0) || (rcv_buf[2] == 0xE4) || (rcv_buf[2] == 0xE6) || (rcv_buf[2] == 0xE8)) {
igor_v 21:bc8c1cec3da6 155 //e. packet length is not valid, so we have the error //r. ошибка размера пакета
igor_v 21:bc8c1cec3da6 156 ToWaitEnd++;
igor_v 21:bc8c1cec3da6 157 return;
igor_v 0:8ad47e2b6f00 158 }
igor_v 21:bc8c1cec3da6 159
igor_v 21:bc8c1cec3da6 160 } else if (rcv_num_byt == 8) {
igor_v 21:bc8c1cec3da6 161 if ((rcv_buf[2] == 0xE0) || (rcv_buf[2] == 0xE4)) {
igor_v 21:bc8c1cec3da6 162 ToWaitEnd++;
igor_v 21:bc8c1cec3da6 163 return;
igor_v 0:8ad47e2b6f00 164 }
igor_v 21:bc8c1cec3da6 165 }
igor_v 21:bc8c1cec3da6 166 if (check_lcc() != 0) { //e. checksum is bad //r.контрольные суммы не равны
igor_v 0:8ad47e2b6f00 167
igor_v 21:bc8c1cec3da6 168 return;
igor_v 21:bc8c1cec3da6 169 } else { //e. cheksum is not bad //r.контрольные суммы равны
igor_v 21:bc8c1cec3da6 170 rcv_Rdy = 1;
igor_v 21:bc8c1cec3da6 171 }
igor_v 21:bc8c1cec3da6 172 ToWaitEnd = 0;
igor_v 21:bc8c1cec3da6 173
igor_v 21:bc8c1cec3da6 174 return;
igor_v 21:bc8c1cec3da6 175
igor_v 21:bc8c1cec3da6 176 }
igor_v 0:8ad47e2b6f00 177 /*
igor_v 21:bc8c1cec3da6 178 void L1_Rc_err (int Error) //e. error fixing and reciever restart //r. модуль фиксации ошибки и перезапуска приемника
igor_v 0:8ad47e2b6f00 179 {
igor_v 0:8ad47e2b6f00 180 int temp;
igor_v 0:8ad47e2b6f00 181 line_sts |= Error;
igor_v 0:8ad47e2b6f00 182 temp = Copy_SRgR & (~Rcv_Rdy);
igor_v 0:8ad47e2b6f00 183 io_space_write(Sys_RgR, temp);
igor_v 0:8ad47e2b6f00 184 temp |= Rcv_Rdy;
igor_v 0:8ad47e2b6f00 185 asm("nop;");
igor_v 0:8ad47e2b6f00 186 io_space_write(Sys_RgR, temp);
igor_v 21:bc8c1cec3da6 187 return;
igor_v 0:8ad47e2b6f00 188 }
igor_v 0:8ad47e2b6f00 189 */
igor_v 21:bc8c1cec3da6 190
igor_v 0:8ad47e2b6f00 191 /******************************************************************************
igor_v 0:8ad47e2b6f00 192 ** Function name: transm_DAT
igor_v 0:8ad47e2b6f00 193 **
igor_v 0:8ad47e2b6f00 194 ** Descriptions: transmit process preparation
igor_v 0:8ad47e2b6f00 195 **
igor_v 0:8ad47e2b6f00 196 ** parameters: None
igor_v 0:8ad47e2b6f00 197 ** Returned value: None
igor_v 21:bc8c1cec3da6 198 **
igor_v 0:8ad47e2b6f00 199 ******************************************************************************/
igor_v 0:8ad47e2b6f00 200
igor_v 0:8ad47e2b6f00 201
igor_v 0:8ad47e2b6f00 202 void transm_DAT(void)
igor_v 0:8ad47e2b6f00 203 {
igor_v 21:bc8c1cec3da6 204 uint32_t param, param_byte, CRC;
igor_v 21:bc8c1cec3da6 205 int32_t *trans_param;
igor_v 21:bc8c1cec3da6 206
igor_v 21:bc8c1cec3da6 207 if ((LPC_UART1->LSR & TRANS_SHIFT_BUF_EMPTY)) //r. передающий буфер пуст
igor_v 21:bc8c1cec3da6 208 if (!( LPC_GPDMACH1->CConfig & (1<<17)))
igor_v 21:bc8c1cec3da6 209 LPC_GPIO2->FIOCLR |= 8; //switch off UART1 driver
igor_v 0:8ad47e2b6f00 210
igor_v 21:bc8c1cec3da6 211 if (trm_ena == 0) {
igor_v 21:bc8c1cec3da6 212 // LPC_GPIO1->FIOCLR = (0x01<<30); //r.передача требуется?
igor_v 21:bc8c1cec3da6 213 return; //r. если нет, возврат
igor_v 21:bc8c1cec3da6 214 }
igor_v 0:8ad47e2b6f00 215
igor_v 21:bc8c1cec3da6 216 if (!(LPC_UART1->LSR & TRANS_SHIFT_BUF_EMPTY)) //r. передающий буфер пуст
igor_v 21:bc8c1cec3da6 217 return;
igor_v 0:8ad47e2b6f00 218
igor_v 21:bc8c1cec3da6 219 if ( LPC_GPDMACH1->CConfig & (1<<17)) //r. если канал передачи занят, ждать
igor_v 21:bc8c1cec3da6 220 return;
igor_v 0:8ad47e2b6f00 221
igor_v 0:8ad47e2b6f00 222 //#if defined UART1TEST
igor_v 0:8ad47e2b6f00 223 // if (LPC_SC->DMAREQSEL == 0x8) //e. DMA request from UART
igor_v 0:8ad47e2b6f00 224 // LPC_GPIO2->FIOSET |= (1<<3); //e. set enable UART bit
igor_v 0:8ad47e2b6f00 225 //#endif
igor_v 0:8ad47e2b6f00 226
igor_v 21:bc8c1cec3da6 227 trm_ena = 0; //r. сбросить флаг разрешения передачи
igor_v 21:bc8c1cec3da6 228
igor_v 21:bc8c1cec3da6 229 trm_num_byt = 2;
igor_v 21:bc8c1cec3da6 230
igor_v 21:bc8c1cec3da6 231 trm_buf[0] = 0x00dd; //r. заголовок пакета
igor_v 21:bc8c1cec3da6 232 trm_buf[1] = Device_blk.Str.My_Addres; //r. адрес прибора
igor_v 21:bc8c1cec3da6 233
igor_v 21:bc8c1cec3da6 234 CRC = trm_buf[1]; //r.инициализация счетчика контрольной суммы
igor_v 21:bc8c1cec3da6 235 for ( param = 0; param < num_of_par; param++) { //r.цикл формирования блока данных пакета
igor_v 21:bc8c1cec3da6 236 trans_param = (int32_t *)addr_param[param]; //r. чтение адреса одного из выдаваемых в пакете параметров
igor_v 0:8ad47e2b6f00 237
igor_v 21:bc8c1cec3da6 238 for (param_byte = 0; param_byte < size_param[param]; param_byte++) {
igor_v 21:bc8c1cec3da6 239 if ( (param_byte & 0x0001) == 0 ) //r. считываем старший байт
igor_v 21:bc8c1cec3da6 240 trm_buf[trm_num_byt] = (*trans_param >> (8/**(size_param[param]-param_byte-1)*/)) & 0x00ff; //r.размещение передаваемого параметра в пакете
igor_v 21:bc8c1cec3da6 241 else {
igor_v 21:bc8c1cec3da6 242 trm_buf[trm_num_byt] = *trans_param & 0x00ff;
igor_v 21:bc8c1cec3da6 243 trans_param ++; //r.переходим к следующей ячейке памяти
igor_v 21:bc8c1cec3da6 244 }
igor_v 21:bc8c1cec3da6 245 CRC += trm_buf[trm_num_byt]; //r. вычисление текущей контрольной суммы
igor_v 21:bc8c1cec3da6 246 trm_num_byt++; //r. количество бит, отправленных в пакет
igor_v 21:bc8c1cec3da6 247 }
igor_v 21:bc8c1cec3da6 248 }
igor_v 21:bc8c1cec3da6 249 trm_buf[trm_num_byt] = CRC >> 8; //r. запись контрольной суммы в пакет
igor_v 21:bc8c1cec3da6 250 trm_buf[trm_num_byt+1] = CRC & 0x00ff;
igor_v 21:bc8c1cec3da6 251
igor_v 21:bc8c1cec3da6 252 trm_num_byt += 2;
igor_v 21:bc8c1cec3da6 253
igor_v 21:bc8c1cec3da6 254 LPC_GPDMACH1->CSrcAddr = (uint32_t)&trm_buf;
igor_v 0:8ad47e2b6f00 255
igor_v 21:bc8c1cec3da6 256 LPC_GPDMACH1->CControl &= ~0xFFF; //e. reset of numer bytes for transmitting
igor_v 21:bc8c1cec3da6 257 LPC_GPDMACH2->CControl &= ~0xFFF; //e. reset of numer bytes for transmitting
igor_v 21:bc8c1cec3da6 258
igor_v 21:bc8c1cec3da6 259 LPC_GPDMACH1->CLLI = 0; //e. linked list is empty
igor_v 0:8ad47e2b6f00 260
igor_v 21:bc8c1cec3da6 261 if (trm_num_byt > 16) { //e. a packet is too long for FIFO
igor_v 21:bc8c1cec3da6 262 LPC_GPDMACH1->CControl |= 16; //e. set length of first packet part
igor_v 21:bc8c1cec3da6 263 LPC_GPDMACH1->CLLI = (uint32_t)&LLI0_TypeDef; //e. initialize chain for other parts transmitting
igor_v 21:bc8c1cec3da6 264 } else
igor_v 21:bc8c1cec3da6 265 LPC_GPDMACH1->CControl |= trm_num_byt;
igor_v 21:bc8c1cec3da6 266
igor_v 21:bc8c1cec3da6 267 LPC_GPDMACH2->CControl |= 1; //e. set 1 transfert for enable signal
igor_v 0:8ad47e2b6f00 268 #if defined UART1TEST
igor_v 21:bc8c1cec3da6 269 LPC_UART1->TER = 0; //e. disable data output to UART1
igor_v 0:8ad47e2b6f00 270 #endif
igor_v 21:bc8c1cec3da6 271 if (Device_Mode < 4) { //e. work with internal latch
igor_v 21:bc8c1cec3da6 272 LPC_TIM0->TCR = 1; //e. start timer
igor_v 0:8ad47e2b6f00 273 //-------------------debug-----------------------------------------
igor_v 21:bc8c1cec3da6 274 LPC_GPIO2->FIOSET |= 8; //turn on RS-422 driver
igor_v 0:8ad47e2b6f00 275 //-------------------debug-----------------------------------------
igor_v 21:bc8c1cec3da6 276
igor_v 21:bc8c1cec3da6 277 LPC_GPDMACH1->CConfig |= DMAChannelEn; //e. DMA for UART transmition
igor_v 21:bc8c1cec3da6 278 //LPC_GPIO1->FIOSET = (0x1<<30);
igor_v 0:8ad47e2b6f00 279
igor_v 21:bc8c1cec3da6 280 }
igor_v 21:bc8c1cec3da6 281
igor_v 21:bc8c1cec3da6 282 LPC_GPDMACH2->CConfig |= DMAChannelEn; //e. DMA for enable signal
igor_v 21:bc8c1cec3da6 283 return;
igor_v 21:bc8c1cec3da6 284 }
igor_v 0:8ad47e2b6f00 285 /******************************************************************************
igor_v 0:8ad47e2b6f00 286 ** Function name: DMA_Init
igor_v 0:8ad47e2b6f00 287 **
igor_v 21:bc8c1cec3da6 288 ** Descriptions:
igor_v 0:8ad47e2b6f00 289 **
igor_v 21:bc8c1cec3da6 290 ** parameters:
igor_v 21:bc8c1cec3da6 291 ** Returned value:
igor_v 21:bc8c1cec3da6 292 **
igor_v 0:8ad47e2b6f00 293 ******************************************************************************/
igor_v 0:8ad47e2b6f00 294 void DMA_Init( void )
igor_v 0:8ad47e2b6f00 295 {
igor_v 21:bc8c1cec3da6 296 /* Enable CLOCK into GPDMA controller */
igor_v 21:bc8c1cec3da6 297 LPC_SC->PCONP |= GPDMA_POWER_ON;
igor_v 0:8ad47e2b6f00 298
igor_v 21:bc8c1cec3da6 299 /* Select primary function(UART0/1/2/3) in DMA channels,
igor_v 21:bc8c1cec3da6 300 secondary is timer 0/1/2/3. */
igor_v 0:8ad47e2b6f00 301 #if defined UART1TEST
igor_v 21:bc8c1cec3da6 302 LPC_SC->DMAREQSEL = 3;
igor_v 0:8ad47e2b6f00 303 #endif
igor_v 21:bc8c1cec3da6 304 //LPC_GPDMA->Sync = (0x1<<DMA_UART0_RX)|(0x1<<DMA_UART1_TX); //synchronization logic is enabled by default
igor_v 21:bc8c1cec3da6 305 LPC_GPDMA->Config = DMA_ControllerEn | DMA_AHB_Little;
igor_v 21:bc8c1cec3da6 306 while ( !(LPC_GPDMA->Config & DMA_ControllerEn) ); //wait until DMA_Controller switched on
igor_v 21:bc8c1cec3da6 307
igor_v 21:bc8c1cec3da6 308 NVIC_DisableIRQ(DMA_IRQn);
igor_v 21:bc8c1cec3da6 309 return;
igor_v 0:8ad47e2b6f00 310 }
igor_v 0:8ad47e2b6f00 311
igor_v 0:8ad47e2b6f00 312 /******************************************************************************
igor_v 0:8ad47e2b6f00 313 ** Function name: UARTInit
igor_v 0:8ad47e2b6f00 314 **
igor_v 0:8ad47e2b6f00 315 ** Descriptions: Initialisation of UART on 38400 baud
igor_v 0:8ad47e2b6f00 316 **
igor_v 0:8ad47e2b6f00 317 ** parameters: None
igor_v 0:8ad47e2b6f00 318 ** Returned value: None
igor_v 21:bc8c1cec3da6 319 **
igor_v 0:8ad47e2b6f00 320 ******************************************************************************/
igor_v 0:8ad47e2b6f00 321 void UARTInit(void)
igor_v 0:8ad47e2b6f00 322 {
igor_v 21:bc8c1cec3da6 323 uint32_t Fdiv;
igor_v 21:bc8c1cec3da6 324 uint32_t pclk;
igor_v 0:8ad47e2b6f00 325 #if !defined UART1TEST
igor_v 21:bc8c1cec3da6 326 uint32_t baudrate = 38400;
igor_v 0:8ad47e2b6f00 327 #else
igor_v 21:bc8c1cec3da6 328 uint32_t baudrate = 38400;
igor_v 0:8ad47e2b6f00 329 #endif
igor_v 21:bc8c1cec3da6 330 LPC_SC->PCONP |= (1<<3);
igor_v 21:bc8c1cec3da6 331
igor_v 21:bc8c1cec3da6 332 LPC_PINCON->PINSEL0 |= 0x00000050;
igor_v 21:bc8c1cec3da6 333
igor_v 21:bc8c1cec3da6 334 pclk = SystemCoreClock/4;
igor_v 0:8ad47e2b6f00 335
igor_v 21:bc8c1cec3da6 336 LPC_UART0->LCR = word_length_8 |one_stop_bit |no_parity |back_trans_dis |DLAB_access;
igor_v 21:bc8c1cec3da6 337 Fdiv = (pclk / 16) / baudrate;
igor_v 0:8ad47e2b6f00 338 LPC_UART0->DLM = Fdiv / 256;
igor_v 21:bc8c1cec3da6 339 LPC_UART0->DLL = Fdiv % 256;
igor_v 21:bc8c1cec3da6 340 LPC_UART0->LCR &= ~DLAB_access;
igor_v 0:8ad47e2b6f00 341 LPC_UART0->FCR = TX_FIFO_Reset |RX_FIFO_Reset |FIFOs_En |RX_TrigLvl_14; //0x06;
igor_v 21:bc8c1cec3da6 342 LPC_UART0->IER = 0;//RBR_IntEnabl;
igor_v 0:8ad47e2b6f00 343
igor_v 21:bc8c1cec3da6 344 LPC_UART0->FCR |= 0x08; //e. DMA mode select
igor_v 21:bc8c1cec3da6 345 //+++++++++++++++++++++++enable signal initialization++++++++++++++++++++++++++
igor_v 0:8ad47e2b6f00 346 LPC_PINCON->PINSEL1 &= ~0x0000C000; //e. select P0.23 as general purpose
igor_v 21:bc8c1cec3da6 347 LPC_GPIO0->FIODIR |= 0x00800000; //e. P0.23 is output
igor_v 21:bc8c1cec3da6 348 // LPC_GPIO0->FIOMASK |= 0x007F0000; //e. P0.16..P0.22 is not changed by FIOSET writing
igor_v 21:bc8c1cec3da6 349 LPC_GPIO0->FIOCLR |= 0x00800000; // e. clear P0.23
igor_v 0:8ad47e2b6f00 350
igor_v 21:bc8c1cec3da6 351 return;
igor_v 0:8ad47e2b6f00 352 }
igor_v 0:8ad47e2b6f00 353
igor_v 30:17c84ed091b3 354
igor_v 0:8ad47e2b6f00 355 void UART1_Init(void)
igor_v 0:8ad47e2b6f00 356 {
igor_v 21:bc8c1cec3da6 357 uint32_t Fdiv;
igor_v 21:bc8c1cec3da6 358 uint32_t pclk;
igor_v 0:8ad47e2b6f00 359 #if !defined UART1TEST
igor_v 21:bc8c1cec3da6 360 uint32_t baudrate = 256000;
igor_v 21:bc8c1cec3da6 361 #else
igor_v 21:bc8c1cec3da6 362 uint32_t baudrate = 38400;
igor_v 0:8ad47e2b6f00 363 #endif
igor_v 0:8ad47e2b6f00 364 LPC_SC->PCONP |= (1<<4); //switch on UART1
igor_v 21:bc8c1cec3da6 365
igor_v 21:bc8c1cec3da6 366 LPC_PINCON->PINSEL4 |= (2<<0)|(2<<2)|(2<<10)|(2<<14); //P2.0, P2.1, P2.5, P2.7
igor_v 21:bc8c1cec3da6 367
igor_v 21:bc8c1cec3da6 368 pclk = SystemCoreClock/4;
igor_v 0:8ad47e2b6f00 369
igor_v 21:bc8c1cec3da6 370 LPC_UART1->LCR = word_length_8 |one_stop_bit |no_parity |back_trans_dis |DLAB_access;
igor_v 21:bc8c1cec3da6 371 Fdiv = (pclk / 16) / baudrate;
igor_v 0:8ad47e2b6f00 372 LPC_UART1->DLM = Fdiv / 256;
igor_v 21:bc8c1cec3da6 373 LPC_UART1->DLL = Fdiv % 256;
igor_v 21:bc8c1cec3da6 374 LPC_UART1->LCR &= ~DLAB_access;
igor_v 0:8ad47e2b6f00 375 LPC_UART1->FCR = TX_FIFO_Reset |RX_FIFO_Reset |FIFOs_En |RX_TrigLvl_14; //0x06;
igor_v 0:8ad47e2b6f00 376
igor_v 21:bc8c1cec3da6 377 LPC_UART1->RS485CTRL = (1<<5); //(1<<4);
igor_v 0:8ad47e2b6f00 378
igor_v 21:bc8c1cec3da6 379 LPC_UART1->IER = 0;//RBR_IntEnabl;
igor_v 0:8ad47e2b6f00 380
igor_v 21:bc8c1cec3da6 381 LPC_UART1->FCR |= 0x08; //e. DMA mode select
igor_v 21:bc8c1cec3da6 382 return;
igor_v 0:8ad47e2b6f00 383 }
igor_v 0:8ad47e2b6f00 384 //----------------------temp----------------------------
igor_v 0:8ad47e2b6f00 385 /*int UART0_SendByte (int ucData)
igor_v 0:8ad47e2b6f00 386 {
igor_v 0:8ad47e2b6f00 387 // while (!(LPC_UART1->LSR & 0x20));
igor_v 0:8ad47e2b6f00 388 return (LPC_UART0->THR = ucData);
igor_v 0:8ad47e2b6f00 389 }*/
igor_v 0:8ad47e2b6f00 390 //----------------------temp----------------------------
igor_v 0:8ad47e2b6f00 391 int UART1_SendByte (int ucData)
igor_v 0:8ad47e2b6f00 392 {
igor_v 0:8ad47e2b6f00 393 // while (!(LPC_UART1->LSR & 0x20));
igor_v 0:8ad47e2b6f00 394 return (LPC_UART1->THR = ucData);
igor_v 0:8ad47e2b6f00 395 }
igor_v 0:8ad47e2b6f00 396 /******************************************************************************
igor_v 0:8ad47e2b6f00 397 ** Function name: UART_SwitchSpeed
igor_v 0:8ad47e2b6f00 398 **
igor_v 21:bc8c1cec3da6 399 ** Descriptions: Change UART speed
igor_v 0:8ad47e2b6f00 400 **
igor_v 0:8ad47e2b6f00 401 ** parameters: Demanded speed
igor_v 0:8ad47e2b6f00 402 ** Returned value: None
igor_v 21:bc8c1cec3da6 403 **
igor_v 30:17c84ed091b3 404
igor_v 0:8ad47e2b6f00 405 ******************************************************************************/
igor_v 0:8ad47e2b6f00 406 void UART_SwitchSpeed(unsigned Speed)
igor_v 0:8ad47e2b6f00 407 {
igor_v 21:bc8c1cec3da6 408 uint32_t Fdiv;
igor_v 21:bc8c1cec3da6 409 uint32_t pclk;
igor_v 0:8ad47e2b6f00 410
igor_v 21:bc8c1cec3da6 411 pclk = SystemCoreClock/4;
igor_v 0:8ad47e2b6f00 412 #if defined UART1REC
igor_v 21:bc8c1cec3da6 413 LPC_UART1->LCR |= DLAB_access;
igor_v 0:8ad47e2b6f00 414 #else
igor_v 21:bc8c1cec3da6 415 LPC_UART0->LCR |= DLAB_access;
igor_v 0:8ad47e2b6f00 416 #endif
igor_v 21:bc8c1cec3da6 417 switch (Speed) {
igor_v 21:bc8c1cec3da6 418 case Sp38400:
igor_v 21:bc8c1cec3da6 419 Fdiv = (pclk / 16) / 38400;
igor_v 21:bc8c1cec3da6 420 EnablLength = 3240;
igor_v 21:bc8c1cec3da6 421 break;
igor_v 0:8ad47e2b6f00 422
igor_v 21:bc8c1cec3da6 423 case Sp115200:
igor_v 21:bc8c1cec3da6 424 Fdiv = (pclk / 16) /115200;
igor_v 21:bc8c1cec3da6 425 EnablLength = 1090;
igor_v 21:bc8c1cec3da6 426 break;
igor_v 0:8ad47e2b6f00 427
igor_v 21:bc8c1cec3da6 428 case Sp460800:
igor_v 21:bc8c1cec3da6 429 Fdiv = (pclk / 16) / 460800;
igor_v 21:bc8c1cec3da6 430 break;
igor_v 0:8ad47e2b6f00 431
igor_v 21:bc8c1cec3da6 432 case Sp921600:
igor_v 21:bc8c1cec3da6 433 Fdiv = (pclk / 16) / 921600;
igor_v 21:bc8c1cec3da6 434 EnablLength = 140;
igor_v 21:bc8c1cec3da6 435 break;
igor_v 0:8ad47e2b6f00 436
igor_v 21:bc8c1cec3da6 437 }
igor_v 21:bc8c1cec3da6 438 #if defined UART1REC
igor_v 0:8ad47e2b6f00 439 LPC_UART1->DLM = Fdiv / 256;
igor_v 21:bc8c1cec3da6 440 LPC_UART1->DLL = Fdiv % 256;
igor_v 0:8ad47e2b6f00 441 LPC_UART1->LCR &= ~DLAB_access;
igor_v 0:8ad47e2b6f00 442 #else
igor_v 21:bc8c1cec3da6 443 LPC_UART0->DLM = Fdiv / 256;
igor_v 21:bc8c1cec3da6 444 LPC_UART0->DLL = Fdiv % 256;
igor_v 0:8ad47e2b6f00 445 LPC_UART0->LCR &= ~DLAB_access;
igor_v 0:8ad47e2b6f00 446 #endif
igor_v 0:8ad47e2b6f00 447 }
igor_v 0:8ad47e2b6f00 448 /******************************************************************************
igor_v 0:8ad47e2b6f00 449 ** Function name: UART_DMA_Init
igor_v 0:8ad47e2b6f00 450 **
igor_v 0:8ad47e2b6f00 451 ** Descriptions: Initialisation of DMA channel for UART transmitter
igor_v 0:8ad47e2b6f00 452 **
igor_v 0:8ad47e2b6f00 453 ** parameters: None
igor_v 0:8ad47e2b6f00 454 ** Returned value: None
igor_v 21:bc8c1cec3da6 455 **
igor_v 0:8ad47e2b6f00 456 ******************************************************************************/
igor_v 0:8ad47e2b6f00 457 void UART_DMA_Init()
igor_v 0:8ad47e2b6f00 458 {
igor_v 0:8ad47e2b6f00 459 //+++++++++++++++++config channel for UART0+++++++++++++++++++++++++++++++++++++++++++++++
igor_v 21:bc8c1cec3da6 460 LPC_GPDMACH1->CConfig &= ~DMAChannelEn;
igor_v 21:bc8c1cec3da6 461
igor_v 21:bc8c1cec3da6 462 LPC_GPDMA->IntTCClear = DMA1_IntTCClear;
igor_v 21:bc8c1cec3da6 463 LPC_GPDMA->IntErrClr = DMA1_IntErrClear;
igor_v 0:8ad47e2b6f00 464
igor_v 21:bc8c1cec3da6 465 LPC_GPDMACH1->CSrcAddr = (uint32_t)&trm_buf;
igor_v 21:bc8c1cec3da6 466 LPC_GPDMACH1->CDestAddr = UART1_DMA_TX_DST;
igor_v 21:bc8c1cec3da6 467 LPC_GPDMACH1->CControl = SrcBSize_1 | DstBSize_1 | SrcWidth_8b | DstWidth_8b | SrcInc | DstFixed | TCIntDisabl;
igor_v 0:8ad47e2b6f00 468 #if defined UART1TEST
igor_v 21:bc8c1cec3da6 469 LPC_GPDMACH1->CConfig |= MaskTCInt | MaskErrInt | DMA_MEMORY | DstDMA_UART1_TX |(M2P << 11);
igor_v 0:8ad47e2b6f00 470 #else
igor_v 21:bc8c1cec3da6 471 g LPC_GPDMACH1->CConfig |= MaskTCInt | MaskErrInt | DMA_MEMORY | DstDMA_UART0_TX |(M2P << 11);
igor_v 0:8ad47e2b6f00 472 #endif
igor_v 0:8ad47e2b6f00 473
igor_v 21:bc8c1cec3da6 474 EnablDMA = (LPC_GPDMACH1->CConfig)|DMAChannelEn; //save register content for DMA starting in multidrop mode
igor_v 21:bc8c1cec3da6 475 //**********for Rate mode output*****************************
igor_v 21:bc8c1cec3da6 476 #if defined UART1TEST
igor_v 21:bc8c1cec3da6 477 LLI1_TypeDef[0] = (uint32_t)&trm_buf[32];
igor_v 21:bc8c1cec3da6 478 LLI1_TypeDef[1] = UART1_DMA_TX_DST;
igor_v 21:bc8c1cec3da6 479 LLI1_TypeDef[2] = 0;
igor_v 21:bc8c1cec3da6 480 LLI1_TypeDef[3] = (12 & 0x0FFF) | SrcBSize_1 | DstBSize_1 | SrcWidth_8b | DstWidth_8b | SrcInc | DstFixed | TCIntDisabl;
igor_v 0:8ad47e2b6f00 481
igor_v 21:bc8c1cec3da6 482 LLI0_TypeDef[0] = (uint32_t)&trm_buf[16];
igor_v 21:bc8c1cec3da6 483 LLI0_TypeDef[1] = UART1_DMA_TX_DST;
igor_v 21:bc8c1cec3da6 484 LLI0_TypeDef[2] = (uint32_t)&LLI1_TypeDef;
igor_v 21:bc8c1cec3da6 485 LLI0_TypeDef[3] = (16 & 0x0FFF) | SrcBSize_1 | DstBSize_1 | SrcWidth_8b | DstWidth_8b | SrcInc | DstFixed | TCIntDisabl;
igor_v 0:8ad47e2b6f00 486 #else
igor_v 21:bc8c1cec3da6 487 LLI1_TypeDef[0] = (uint32_t)&trm_buf[32];
igor_v 21:bc8c1cec3da6 488 LLI1_TypeDef[1] = UART0_DMA_TX_DST;
igor_v 21:bc8c1cec3da6 489 LLI1_TypeDef[2] = 0;
igor_v 21:bc8c1cec3da6 490 LLI1_TypeDef[3] = (12 & 0x0FFF) | SrcBSize_1 | DstBSize_1 | SrcWidth_8b | DstWidth_8b | SrcInc | DstFixed | TCIntDisabl;
igor_v 0:8ad47e2b6f00 491
igor_v 21:bc8c1cec3da6 492 LLI0_TypeDef[0] = (uint32_t)&trm_buf[16];
igor_v 21:bc8c1cec3da6 493 LLI0_TypeDef[1] = UART0_DMA_TX_DST;
igor_v 21:bc8c1cec3da6 494 LLI0_TypeDef[2] = (uint32_t)&LLI1_TypeDef;
igor_v 21:bc8c1cec3da6 495 LLI0_TypeDef[3] = (16 & 0x0FFF)|SrcBSize_1 |DstBSize_1 |SrcWidth_8b
igor_v 21:bc8c1cec3da6 496 |DstWidth_8b|SrcInc |DstFixed |TCIntDisabl;
igor_v 0:8ad47e2b6f00 497 #endif
igor_v 0:8ad47e2b6f00 498 //++++++++++++++++++++++++++config channel for transmit enable signal+++++++++++++++++++
igor_v 21:bc8c1cec3da6 499 LPC_GPDMACH2->CConfig &= ~DMAChannelEn;
igor_v 0:8ad47e2b6f00 500
igor_v 21:bc8c1cec3da6 501 LPC_GPDMA->IntTCClear = DMA2_IntTCClear;
igor_v 21:bc8c1cec3da6 502 LPC_GPDMA->IntErrClr = DMA2_IntErrClear;
igor_v 0:8ad47e2b6f00 503
igor_v 21:bc8c1cec3da6 504 LPC_GPDMACH2->CSrcAddr = (uint32_t)&EnablTx; //e. content of TX UART1 enable register
igor_v 21:bc8c1cec3da6 505 LPC_GPDMACH2->CDestAddr = 0x40010030; //e. address of TX UART1 enable register (U1TER)
igor_v 0:8ad47e2b6f00 506
igor_v 21:bc8c1cec3da6 507 LPC_GPDMACH2->CControl = SrcBSize_4 |DstBSize_4
igor_v 21:bc8c1cec3da6 508 |SrcWidth_8b |DstWidth_8b|SrcFixed |DstFixed |TCIntEnabl;
igor_v 21:bc8c1cec3da6 509
igor_v 21:bc8c1cec3da6 510 LPC_GPDMACH2->CConfig |= MaskTCInt |MaskErrInt
igor_v 21:bc8c1cec3da6 511 |SrcDMA_UART0_RX |DstDMA_UART0_RX|(M2P << 11);
igor_v 21:bc8c1cec3da6 512 LPC_GPDMACH2->CLLI = 0; //e. linked list is empty
igor_v 0:8ad47e2b6f00 513
igor_v 0:8ad47e2b6f00 514 //++++++++++++++++++++++++++config channel for DMA1 enable signal+++++++++++++++++++
igor_v 0:8ad47e2b6f00 515 #if defined UART1TEST
igor_v 21:bc8c1cec3da6 516 LPC_GPDMACH4->CConfig &= ~DMAChannelEn;
igor_v 21:bc8c1cec3da6 517
igor_v 21:bc8c1cec3da6 518 LPC_GPDMA->IntTCClear = DMA4_IntTCClear;
igor_v 21:bc8c1cec3da6 519 LPC_GPDMA->IntErrClr = DMA4_IntErrClear;
igor_v 21:bc8c1cec3da6 520
igor_v 21:bc8c1cec3da6 521 LPC_GPDMACH4->CSrcAddr = (uint32_t)&EnablDMA; //e. content of TX UART1 enable register
igor_v 21:bc8c1cec3da6 522 LPC_GPDMACH4->CDestAddr = 0x50004130; //e. address of DMA1CConfig register
igor_v 0:8ad47e2b6f00 523
igor_v 21:bc8c1cec3da6 524 LPC_GPDMACH4->CControl = SrcBSize_4 |DstBSize_4
igor_v 21:bc8c1cec3da6 525 |SrcWidth_8b |DstWidth_8b|SrcFixed |DstFixed |TCIntEnabl;
igor_v 0:8ad47e2b6f00 526
igor_v 21:bc8c1cec3da6 527 LPC_GPDMACH4->CConfig |= MaskTCInt |MaskErrInt
igor_v 21:bc8c1cec3da6 528 |SrcDMA_UART0_TX |DstDMA_UART0_TX|(M2P << 11);
igor_v 21:bc8c1cec3da6 529 LPC_GPDMACH4->CLLI = 0; //e. linked list is empty
igor_v 21:bc8c1cec3da6 530 #endif
igor_v 0:8ad47e2b6f00 531 }
igor_v 0:8ad47e2b6f00 532 /******************************************************************************
igor_v 0:8ad47e2b6f00 533 ** End Of File
igor_v 0:8ad47e2b6f00 534 ******************************************************************************/
igor_v 0:8ad47e2b6f00 535
igor_v 21:bc8c1cec3da6 536