Dmitry Kovalev / Mbed 2 deprecated LG2

fork

Dependencies:   mbed

Fork of LG by igor Apu

el_lin.c@1:f2adcae3d304, 2016-01-30 (annotated)

Committer:
igor_v
Date:
Sat Jan 30 13:53:19 2016 +0000
Revision:
1:f2adcae3d304
Parent:
0:8ad47e2b6f00
Child:
21:bc8c1cec3da6
123

Who changed what in which revision?

UserRevisionLine numberNew contents of line
igor_v 0:8ad47e2b6f00 1
igor_v 0:8ad47e2b6f00 2 /**--------------File Info---------------------------------------------------------------------------------
igor_v 0:8ad47e2b6f00 3 ** File name: el_lin.c
igor_v 0:8ad47e2b6f00 4 ** Last modified Date: 2011-08-22
igor_v 0:8ad47e2b6f00 5 ** Last Version: V1.00
igor_v 0:8ad47e2b6f00 6 **--------------------------------------------------------------------------------------------------------
igor_v 0:8ad47e2b6f00 7 ** Created by: Electrooptica Incor.
igor_v 0:8ad47e2b6f00 8 ** Created date: 2011-08-22
igor_v 0:8ad47e2b6f00 9 ** Version: V1.00
igor_v 0:8ad47e2b6f00 10 **--------------------------------------------------------------------------------------------------------
igor_v 0:8ad47e2b6f00 11 *********************************************************************************************************/
igor_v 1:f2adcae3d304 12
igor_v 1:f2adcae3d304 13 #include "Global.h"
igor_v 1:f2adcae3d304 14
igor_v 0:8ad47e2b6f00 15
igor_v 0:8ad47e2b6f00 16 #define UART1TEST
igor_v 0:8ad47e2b6f00 17 #define UART1REC
igor_v 0:8ad47e2b6f00 18 /*
igor_v 0:8ad47e2b6f00 19 struct {
igor_v 0:8ad47e2b6f00 20 uint32_t rcv_num_byt;
igor_v 0:8ad47e2b6f00 21 uint32_t rcv_num_byt_old;
igor_v 0:8ad47e2b6f00 22 uint32_t rcv_Rdy;
igor_v 0:8ad47e2b6f00 23 char rcv_copy[64];
igor_v 0:8ad47e2b6f00 24 char rcv_buf[64];
igor_v 0:8ad47e2b6f00 25 int32_t rx_buf_copy;
igor_v 0:8ad47e2b6f00 26 int32_t rcv_byt_copy;
igor_v 0:8ad47e2b6f00 27 }RECIEVER;
igor_v 0:8ad47e2b6f00 28
igor_v 0:8ad47e2b6f00 29 struct {
igor_v 0:8ad47e2b6f00 30 uint32_t trm_num_byt;
igor_v 0:8ad47e2b6f00 31 uint32_t trm_rate;
igor_v 0:8ad47e2b6f00 32 uint32_t trm_cycl;
igor_v 0:8ad47e2b6f00 33 uint32_t num_of_par;
igor_v 0:8ad47e2b6f00 34 char trm_buf[64];
igor_v 0:8ad47e2b6f00 35 void* addr_param[16];
igor_v 0:8ad47e2b6f00 36 uint32_t size_param[16];
igor_v 0:8ad47e2b6f00 37 uint32_t trm_ena;
igor_v 0:8ad47e2b6f00 38 }TRANSMITTER;
igor_v 0:8ad47e2b6f00 39 */
igor_v 0:8ad47e2b6f00 40 uint32_t rcv_num_byt;
igor_v 0:8ad47e2b6f00 41 uint32_t rcv_num_byt_old;
igor_v 0:8ad47e2b6f00 42 uint32_t rcv_Rdy;
igor_v 0:8ad47e2b6f00 43 char rcv_copy[64];
igor_v 0:8ad47e2b6f00 44 char rcv_buf[64];
igor_v 0:8ad47e2b6f00 45 int32_t rx_buf_copy;
igor_v 0:8ad47e2b6f00 46 int32_t rcv_byt_copy;
igor_v 0:8ad47e2b6f00 47
igor_v 0:8ad47e2b6f00 48 uint32_t trm_num_byt;
igor_v 0:8ad47e2b6f00 49 uint32_t trm_rate;
igor_v 0:8ad47e2b6f00 50 uint32_t num_of_par;
igor_v 0:8ad47e2b6f00 51 char trm_buf[64];
igor_v 0:8ad47e2b6f00 52 void* addr_param[16];
igor_v 0:8ad47e2b6f00 53 uint32_t size_param[16];
igor_v 0:8ad47e2b6f00 54 uint32_t trm_ena;
igor_v 0:8ad47e2b6f00 55
igor_v 0:8ad47e2b6f00 56 uint32_t line_err;
igor_v 0:8ad47e2b6f00 57 uint32_t line_sts;
igor_v 0:8ad47e2b6f00 58
igor_v 0:8ad47e2b6f00 59 uint32_t EnablLength = 12;
igor_v 0:8ad47e2b6f00 60 uint32_t LLI0_TypeDef[4];
igor_v 0:8ad47e2b6f00 61 uint32_t LLI1_TypeDef[4];
igor_v 0:8ad47e2b6f00 62 uint32_t EnablTx = 0x80;
igor_v 0:8ad47e2b6f00 63 uint32_t EnablDMA = 0;
igor_v 0:8ad47e2b6f00 64 /******************************************************************************
igor_v 0:8ad47e2b6f00 65 ** Function name: DMA_IRQHandler
igor_v 0:8ad47e2b6f00 66 **
igor_v 0:8ad47e2b6f00 67 ** Descriptions: DMA interrupt handler
igor_v 0:8ad47e2b6f00 68 **
igor_v 0:8ad47e2b6f00 69 ** parameters: None
igor_v 0:8ad47e2b6f00 70 ** Returned value: None
igor_v 0:8ad47e2b6f00 71 **
igor_v 0:8ad47e2b6f00 72 ******************************************************************************/
igor_v 1:f2adcae3d304 73 int check_lcc(void) //e. CRC checking //r.�������� ����������� �����
igor_v 0:8ad47e2b6f00 74 {
igor_v 0:8ad47e2b6f00 75 int iCRC_calc, CRC_calc = 0, CRC_real;
igor_v 0:8ad47e2b6f00 76
igor_v 0:8ad47e2b6f00 77 for (iCRC_calc = 1; iCRC_calc < (rcv_num_byt-2); iCRC_calc++)
igor_v 0:8ad47e2b6f00 78 CRC_calc += rcv_buf[iCRC_calc];
igor_v 0:8ad47e2b6f00 79
igor_v 0:8ad47e2b6f00 80 CRC_real = (rcv_buf[rcv_num_byt-2] << 8) | rcv_buf[rcv_num_byt-1];
igor_v 0:8ad47e2b6f00 81
igor_v 0:8ad47e2b6f00 82 return (CRC_real - CRC_calc);
igor_v 0:8ad47e2b6f00 83 }
igor_v 0:8ad47e2b6f00 84 void PacketSafing(void)
igor_v 0:8ad47e2b6f00 85 {
igor_v 0:8ad47e2b6f00 86 /* int j; static char rcv_buf_copy[16];
igor_v 0:8ad47e2b6f00 87 for (j=2; j<rcv_num_byt; j++)
igor_v 0:8ad47e2b6f00 88 {
igor_v 0:8ad47e2b6f00 89 if (rcv_buf[j] == 0xCC);
igor_v 0:8ad47e2b6f00 90 rcv_buf_copy[0] = 0xCC;
igor_v 0:8ad47e2b6f00 91 // if ((rcv_buf[j] < 3) || (rcv_buf[j] == 0x1F))
igor_v 0:8ad47e2b6f00 92 } */
igor_v 0:8ad47e2b6f00 93 }
igor_v 0:8ad47e2b6f00 94
igor_v 0:8ad47e2b6f00 95 /******************************************************************************
igor_v 0:8ad47e2b6f00 96 ** Function name: Line_1_Rcv
igor_v 0:8ad47e2b6f00 97 **
igor_v 0:8ad47e2b6f00 98 ** Descriptions: receive process preparation
igor_v 0:8ad47e2b6f00 99 **
igor_v 0:8ad47e2b6f00 100 ** parameters: None
igor_v 0:8ad47e2b6f00 101 ** Returned value: None
igor_v 0:8ad47e2b6f00 102 **
igor_v 0:8ad47e2b6f00 103 ******************************************************************************/
igor_v 0:8ad47e2b6f00 104 void Line_1_Rcv(void)
igor_v 0:8ad47e2b6f00 105 {
igor_v 0:8ad47e2b6f00 106 static int ToWaitEnd, ErrReg ;
igor_v 0:8ad47e2b6f00 107
igor_v 0:8ad47e2b6f00 108
igor_v 0:8ad47e2b6f00 109
igor_v 0:8ad47e2b6f00 110
igor_v 0:8ad47e2b6f00 111 while ((LPC_UART1->LSR & RecievBufEmpty) != 0) //e. reciever contain some information
igor_v 1:f2adcae3d304 112 rcv_buf[rcv_num_byt++] = LPC_UART1->RBR;//������ ���������� �� ������.
igor_v 0:8ad47e2b6f00 113
igor_v 0:8ad47e2b6f00 114
igor_v 0:8ad47e2b6f00 115
igor_v 0:8ad47e2b6f00 116
igor_v 1:f2adcae3d304 117 if (( ToWaitEnd > 25000)) //e. end part of packet is absent //r. �� ��������� ����� ������
igor_v 0:8ad47e2b6f00 118 {
igor_v 0:8ad47e2b6f00 119 do
igor_v 0:8ad47e2b6f00 120 rcv_buf[--rcv_num_byt] = 0;
igor_v 0:8ad47e2b6f00 121 while(rcv_num_byt);
igor_v 0:8ad47e2b6f00 122 rcv_num_byt_old = rcv_num_byt;
igor_v 0:8ad47e2b6f00 123 #if defined UART1REC
igor_v 0:8ad47e2b6f00 124 LPC_UART1->FCR |= RX_FIFO_Reset;
igor_v 0:8ad47e2b6f00 125 #else
igor_v 0:8ad47e2b6f00 126 LPC_UART0->FCR |= RX_FIFO_Reset;
igor_v 0:8ad47e2b6f00 127 #endif
igor_v 0:8ad47e2b6f00 128 // L1_Rc_err (TIMEOUT_ERR);
igor_v 0:8ad47e2b6f00 129 ToWaitEnd = 0;
igor_v 0:8ad47e2b6f00 130 return;
igor_v 0:8ad47e2b6f00 131 }
igor_v 0:8ad47e2b6f00 132 if (rcv_num_byt_old == rcv_num_byt) //e. we have not received any new bytes
igor_v 0:8ad47e2b6f00 133 {
igor_v 0:8ad47e2b6f00 134 if (ToWaitEnd) ToWaitEnd++;
igor_v 0:8ad47e2b6f00 135 return;
igor_v 0:8ad47e2b6f00 136 }
igor_v 0:8ad47e2b6f00 137 rcv_num_byt_old = rcv_num_byt;
igor_v 0:8ad47e2b6f00 138
igor_v 0:8ad47e2b6f00 139 if ((rcv_num_byt < 6) || ((rcv_num_byt & 0x0001) == 1))
igor_v 0:8ad47e2b6f00 140 {
igor_v 0:8ad47e2b6f00 141 ToWaitEnd++;
igor_v 0:8ad47e2b6f00 142 return;
igor_v 0:8ad47e2b6f00 143 }
igor_v 0:8ad47e2b6f00 144
igor_v 1:f2adcae3d304 145 if ((!ToWaitEnd) && (rcv_num_byt > 1)) //e. the header of packet has not recieved //r. ������� ������ ������
igor_v 0:8ad47e2b6f00 146 if ((rcv_buf[0] != 0xCC) || (( rcv_buf[1] > 2) && ( rcv_buf[1] != 0x1F)))
igor_v 0:8ad47e2b6f00 147 {
igor_v 0:8ad47e2b6f00 148 // L1_Rc_err (HEADER_ERR);
igor_v 0:8ad47e2b6f00 149 ErrReg |= 5;
igor_v 0:8ad47e2b6f00 150 ToWaitEnd++;
igor_v 0:8ad47e2b6f00 151 return;
igor_v 0:8ad47e2b6f00 152 }
igor_v 1:f2adcae3d304 153 // if (ErrReg != 0) //e. trying of recovering of packet //r. �������� ���������� ������
igor_v 0:8ad47e2b6f00 154 // PacketSafing();
igor_v 0:8ad47e2b6f00 155
igor_v 0:8ad47e2b6f00 156
igor_v 0:8ad47e2b6f00 157 if (rcv_num_byt == 6)
igor_v 0:8ad47e2b6f00 158 {
igor_v 0:8ad47e2b6f00 159 if ((rcv_buf[2] == 0x0A) || (rcv_buf[2] == 0xE0) || (rcv_buf[2] == 0xE4) || (rcv_buf[2] == 0xE6) || (rcv_buf[2] == 0xE8))
igor_v 1:f2adcae3d304 160 { //e. packet length is not valid, so we have the error //r. ������ ������� ������
igor_v 0:8ad47e2b6f00 161 ToWaitEnd++;
igor_v 0:8ad47e2b6f00 162 return;
igor_v 0:8ad47e2b6f00 163 }
igor_v 0:8ad47e2b6f00 164
igor_v 0:8ad47e2b6f00 165 }
igor_v 0:8ad47e2b6f00 166 else if (rcv_num_byt == 8)
igor_v 0:8ad47e2b6f00 167 {
igor_v 0:8ad47e2b6f00 168 if ((rcv_buf[2] == 0xE0) || (rcv_buf[2] == 0xE4))
igor_v 0:8ad47e2b6f00 169 {
igor_v 0:8ad47e2b6f00 170 ToWaitEnd++;
igor_v 0:8ad47e2b6f00 171 return;
igor_v 0:8ad47e2b6f00 172 }
igor_v 0:8ad47e2b6f00 173 }
igor_v 1:f2adcae3d304 174 if (check_lcc() != 0) //e. checksum is bad //r.����������� ����� �� �����
igor_v 0:8ad47e2b6f00 175 {
igor_v 0:8ad47e2b6f00 176
igor_v 0:8ad47e2b6f00 177 return;
igor_v 0:8ad47e2b6f00 178 }
igor_v 1:f2adcae3d304 179 else //e. cheksum is not bad //r.����������� ����� �����
igor_v 0:8ad47e2b6f00 180 {
igor_v 0:8ad47e2b6f00 181 rcv_Rdy = 1;
igor_v 0:8ad47e2b6f00 182 }
igor_v 0:8ad47e2b6f00 183 ToWaitEnd = 0;
igor_v 0:8ad47e2b6f00 184
igor_v 0:8ad47e2b6f00 185 return;
igor_v 0:8ad47e2b6f00 186
igor_v 0:8ad47e2b6f00 187 }
igor_v 0:8ad47e2b6f00 188 /*
igor_v 1:f2adcae3d304 189 void L1_Rc_err (int Error) //e. error fixing and reciever restart //r. ������ �������� ������ � ����������� ���������
igor_v 0:8ad47e2b6f00 190 {
igor_v 0:8ad47e2b6f00 191 int temp;
igor_v 0:8ad47e2b6f00 192 line_sts |= Error;
igor_v 0:8ad47e2b6f00 193 temp = Copy_SRgR & (~Rcv_Rdy);
igor_v 0:8ad47e2b6f00 194 io_space_write(Sys_RgR, temp);
igor_v 0:8ad47e2b6f00 195 temp |= Rcv_Rdy;
igor_v 0:8ad47e2b6f00 196 asm("nop;");
igor_v 0:8ad47e2b6f00 197 io_space_write(Sys_RgR, temp);
igor_v 0:8ad47e2b6f00 198 return;
igor_v 0:8ad47e2b6f00 199 }
igor_v 0:8ad47e2b6f00 200 */
igor_v 0:8ad47e2b6f00 201
igor_v 0:8ad47e2b6f00 202 /******************************************************************************
igor_v 0:8ad47e2b6f00 203 ** Function name: transm_DAT
igor_v 0:8ad47e2b6f00 204 **
igor_v 0:8ad47e2b6f00 205 ** Descriptions: transmit process preparation
igor_v 0:8ad47e2b6f00 206 **
igor_v 0:8ad47e2b6f00 207 ** parameters: None
igor_v 0:8ad47e2b6f00 208 ** Returned value: None
igor_v 0:8ad47e2b6f00 209 **
igor_v 0:8ad47e2b6f00 210 ******************************************************************************/
igor_v 0:8ad47e2b6f00 211
igor_v 0:8ad47e2b6f00 212
igor_v 0:8ad47e2b6f00 213 void transm_DAT(void)
igor_v 0:8ad47e2b6f00 214 {
igor_v 0:8ad47e2b6f00 215 uint32_t param, param_byte, CRC;
igor_v 0:8ad47e2b6f00 216 int32_t *trans_param;
igor_v 0:8ad47e2b6f00 217
igor_v 1:f2adcae3d304 218 if ((LPC_UART1->LSR & TRANS_SHIFT_BUF_EMPTY)) //r. ���������� ����� ����
igor_v 0:8ad47e2b6f00 219 if (!( LPC_GPDMACH1->CConfig & (1<<17)))
igor_v 0:8ad47e2b6f00 220 LPC_GPIO2->FIOCLR |= 8; //switch off UART1 driver
igor_v 0:8ad47e2b6f00 221
igor_v 0:8ad47e2b6f00 222 if (trm_ena == 0)
igor_v 0:8ad47e2b6f00 223 {
igor_v 1:f2adcae3d304 224 // LPC_GPIO1->FIOCLR = (0x01<<30); //r.�������� ���������?
igor_v 1:f2adcae3d304 225 return; //r. ���� ���, �������
igor_v 0:8ad47e2b6f00 226 }
igor_v 0:8ad47e2b6f00 227
igor_v 1:f2adcae3d304 228 if (!(LPC_UART1->LSR & TRANS_SHIFT_BUF_EMPTY)) //r. ���������� ����� ����
igor_v 0:8ad47e2b6f00 229 return;
igor_v 0:8ad47e2b6f00 230
igor_v 1:f2adcae3d304 231 if ( LPC_GPDMACH1->CConfig & (1<<17)) //r. ���� ����� �������� �����, �����
igor_v 0:8ad47e2b6f00 232 return;
igor_v 0:8ad47e2b6f00 233
igor_v 0:8ad47e2b6f00 234 //#if defined UART1TEST
igor_v 0:8ad47e2b6f00 235 // if (LPC_SC->DMAREQSEL == 0x8) //e. DMA request from UART
igor_v 0:8ad47e2b6f00 236 // LPC_GPIO2->FIOSET |= (1<<3); //e. set enable UART bit
igor_v 0:8ad47e2b6f00 237 //#endif
igor_v 0:8ad47e2b6f00 238
igor_v 1:f2adcae3d304 239 trm_ena = 0; //r. �������� ���� ���������� ��������
igor_v 0:8ad47e2b6f00 240
igor_v 0:8ad47e2b6f00 241 trm_num_byt = 2;
igor_v 0:8ad47e2b6f00 242
igor_v 1:f2adcae3d304 243 trm_buf[0] = 0x00dd; //r. ��������� ������
igor_v 1:f2adcae3d304 244 trm_buf[1] = Device_blk.Str.My_Addres; //r. ����� �������
igor_v 0:8ad47e2b6f00 245
igor_v 1:f2adcae3d304 246 CRC = trm_buf[1]; //r.������������� �������� ����������� �����
igor_v 1:f2adcae3d304 247 for ( param = 0; param < num_of_par; param++) //r.���� ������������ ����� ������ ������
igor_v 0:8ad47e2b6f00 248 {
igor_v 1:f2adcae3d304 249 trans_param = (int32_t *)addr_param[param]; //r. ������ ������ ������ �� ���������� � ������ ����������
igor_v 0:8ad47e2b6f00 250
igor_v 0:8ad47e2b6f00 251 for (param_byte = 0; param_byte < size_param[param]; param_byte++)
igor_v 0:8ad47e2b6f00 252 {
igor_v 1:f2adcae3d304 253 if ( (param_byte & 0x0001) == 0 ) //r. ��������� ������� ����
igor_v 1:f2adcae3d304 254 trm_buf[trm_num_byt] = (*trans_param >> (8/**(size_param[param]-param_byte-1)*/)) & 0x00ff; //r.���������� ������������� ��������� � ������
igor_v 0:8ad47e2b6f00 255 else
igor_v 0:8ad47e2b6f00 256 {
igor_v 0:8ad47e2b6f00 257 trm_buf[trm_num_byt] = *trans_param & 0x00ff;
igor_v 1:f2adcae3d304 258 trans_param ++; //r.��������� � ��������� ������ ������
igor_v 0:8ad47e2b6f00 259 }
igor_v 1:f2adcae3d304 260 CRC += trm_buf[trm_num_byt]; //r. ���������� ������� ����������� �����
igor_v 1:f2adcae3d304 261 trm_num_byt++; //r. ���������� ���, ������������ � �����
igor_v 0:8ad47e2b6f00 262 }
igor_v 0:8ad47e2b6f00 263 }
igor_v 1:f2adcae3d304 264 trm_buf[trm_num_byt] = CRC >> 8; //r. ������ ����������� ����� � �����
igor_v 0:8ad47e2b6f00 265 trm_buf[trm_num_byt+1] = CRC & 0x00ff;
igor_v 0:8ad47e2b6f00 266
igor_v 0:8ad47e2b6f00 267 trm_num_byt += 2;
igor_v 0:8ad47e2b6f00 268
igor_v 0:8ad47e2b6f00 269 LPC_GPDMACH1->CSrcAddr = (uint32_t)&trm_buf;
igor_v 0:8ad47e2b6f00 270
igor_v 0:8ad47e2b6f00 271 LPC_GPDMACH1->CControl &= ~0xFFF; //e. reset of numer bytes for transmitting
igor_v 0:8ad47e2b6f00 272 LPC_GPDMACH2->CControl &= ~0xFFF; //e. reset of numer bytes for transmitting
igor_v 0:8ad47e2b6f00 273
igor_v 0:8ad47e2b6f00 274 LPC_GPDMACH1->CLLI = 0; //e. linked list is empty
igor_v 0:8ad47e2b6f00 275
igor_v 0:8ad47e2b6f00 276 if (trm_num_byt > 16) //e. a packet is too long for FIFO
igor_v 0:8ad47e2b6f00 277 {
igor_v 0:8ad47e2b6f00 278 LPC_GPDMACH1->CControl |= 16; //e. set length of first packet part
igor_v 0:8ad47e2b6f00 279 LPC_GPDMACH1->CLLI = (uint32_t)&LLI0_TypeDef; //e. initialize chain for other parts transmitting
igor_v 0:8ad47e2b6f00 280 }
igor_v 0:8ad47e2b6f00 281 else
igor_v 0:8ad47e2b6f00 282 LPC_GPDMACH1->CControl |= trm_num_byt;
igor_v 0:8ad47e2b6f00 283
igor_v 0:8ad47e2b6f00 284 LPC_GPDMACH2->CControl |= 1; //e. set 1 transfert for enable signal
igor_v 0:8ad47e2b6f00 285 #if defined UART1TEST
igor_v 0:8ad47e2b6f00 286 LPC_UART1->TER = 0; //e. disable data output to UART1
igor_v 0:8ad47e2b6f00 287 #endif
igor_v 0:8ad47e2b6f00 288 if (Device_Mode < 4) //e. work with internal latch
igor_v 0:8ad47e2b6f00 289 {
igor_v 0:8ad47e2b6f00 290 LPC_TIM0->TCR = 1; //e. start timer
igor_v 0:8ad47e2b6f00 291 //-------------------debug-----------------------------------------
igor_v 0:8ad47e2b6f00 292 LPC_GPIO2->FIOSET |= 8; //turn on RS-422 driver
igor_v 0:8ad47e2b6f00 293 //-------------------debug-----------------------------------------
igor_v 0:8ad47e2b6f00 294
igor_v 0:8ad47e2b6f00 295 LPC_GPDMACH1->CConfig |= DMAChannelEn; //e. DMA for UART transmition
igor_v 0:8ad47e2b6f00 296 //LPC_GPIO1->FIOSET = (0x1<<30);
igor_v 0:8ad47e2b6f00 297
igor_v 0:8ad47e2b6f00 298 }
igor_v 0:8ad47e2b6f00 299
igor_v 0:8ad47e2b6f00 300 LPC_GPDMACH2->CConfig |= DMAChannelEn; //e. DMA for enable signal
igor_v 0:8ad47e2b6f00 301 return;
igor_v 0:8ad47e2b6f00 302 }
igor_v 0:8ad47e2b6f00 303 /******************************************************************************
igor_v 0:8ad47e2b6f00 304 ** Function name: DMA_Init
igor_v 0:8ad47e2b6f00 305 **
igor_v 0:8ad47e2b6f00 306 ** Descriptions:
igor_v 0:8ad47e2b6f00 307 **
igor_v 0:8ad47e2b6f00 308 ** parameters:
igor_v 0:8ad47e2b6f00 309 ** Returned value:
igor_v 0:8ad47e2b6f00 310 **
igor_v 0:8ad47e2b6f00 311 ******************************************************************************/
igor_v 0:8ad47e2b6f00 312 void DMA_Init( void )
igor_v 0:8ad47e2b6f00 313 {
igor_v 0:8ad47e2b6f00 314 /* Enable CLOCK into GPDMA controller */
igor_v 0:8ad47e2b6f00 315 LPC_SC->PCONP |= GPDMA_POWER_ON;
igor_v 0:8ad47e2b6f00 316
igor_v 0:8ad47e2b6f00 317 /* Select primary function(UART0/1/2/3) in DMA channels,
igor_v 0:8ad47e2b6f00 318 secondary is timer 0/1/2/3. */
igor_v 0:8ad47e2b6f00 319 #if defined UART1TEST
igor_v 0:8ad47e2b6f00 320 LPC_SC->DMAREQSEL = 3;
igor_v 0:8ad47e2b6f00 321 #endif
igor_v 0:8ad47e2b6f00 322 //LPC_GPDMA->Sync = (0x1<<DMA_UART0_RX)|(0x1<<DMA_UART1_TX); //synchronization logic is enabled by default
igor_v 0:8ad47e2b6f00 323 LPC_GPDMA->Config = DMA_ControllerEn | DMA_AHB_Little;
igor_v 0:8ad47e2b6f00 324 while ( !(LPC_GPDMA->Config & DMA_ControllerEn) ); //wait until DMA_Controller switched on
igor_v 0:8ad47e2b6f00 325
igor_v 0:8ad47e2b6f00 326 NVIC_DisableIRQ(DMA_IRQn);
igor_v 0:8ad47e2b6f00 327 return;
igor_v 0:8ad47e2b6f00 328 }
igor_v 0:8ad47e2b6f00 329
igor_v 0:8ad47e2b6f00 330 /******************************************************************************
igor_v 0:8ad47e2b6f00 331 ** Function name: UARTInit
igor_v 0:8ad47e2b6f00 332 **
igor_v 0:8ad47e2b6f00 333 ** Descriptions: Initialisation of UART on 38400 baud
igor_v 0:8ad47e2b6f00 334 **
igor_v 0:8ad47e2b6f00 335 ** parameters: None
igor_v 0:8ad47e2b6f00 336 ** Returned value: None
igor_v 0:8ad47e2b6f00 337 **
igor_v 0:8ad47e2b6f00 338 ******************************************************************************/
igor_v 0:8ad47e2b6f00 339 void UARTInit(void)
igor_v 0:8ad47e2b6f00 340 {
igor_v 0:8ad47e2b6f00 341 uint32_t Fdiv;
igor_v 0:8ad47e2b6f00 342 uint32_t pclk;
igor_v 0:8ad47e2b6f00 343 #if !defined UART1TEST
igor_v 0:8ad47e2b6f00 344 uint32_t baudrate = 38400;
igor_v 0:8ad47e2b6f00 345 #else
igor_v 0:8ad47e2b6f00 346 uint32_t baudrate = 38400;
igor_v 0:8ad47e2b6f00 347 #endif
igor_v 0:8ad47e2b6f00 348 LPC_SC->PCONP |= (1<<3);
igor_v 0:8ad47e2b6f00 349
igor_v 0:8ad47e2b6f00 350 LPC_PINCON->PINSEL0 |= 0x00000050;
igor_v 0:8ad47e2b6f00 351
igor_v 0:8ad47e2b6f00 352 pclk = SystemCoreClock/4;
igor_v 0:8ad47e2b6f00 353
igor_v 0:8ad47e2b6f00 354 LPC_UART0->LCR = word_length_8 |one_stop_bit |no_parity |back_trans_dis |DLAB_access;
igor_v 0:8ad47e2b6f00 355 Fdiv = (pclk / 16) / baudrate;
igor_v 0:8ad47e2b6f00 356 LPC_UART0->DLM = Fdiv / 256;
igor_v 0:8ad47e2b6f00 357 LPC_UART0->DLL = Fdiv % 256;
igor_v 0:8ad47e2b6f00 358 LPC_UART0->LCR &= ~DLAB_access;
igor_v 0:8ad47e2b6f00 359 LPC_UART0->FCR = TX_FIFO_Reset |RX_FIFO_Reset |FIFOs_En |RX_TrigLvl_14; //0x06;
igor_v 0:8ad47e2b6f00 360 LPC_UART0->IER = 0;//RBR_IntEnabl;
igor_v 0:8ad47e2b6f00 361
igor_v 0:8ad47e2b6f00 362 LPC_UART0->FCR |= 0x08; //e. DMA mode select
igor_v 0:8ad47e2b6f00 363 //+++++++++++++++++++++++enable signal initialization++++++++++++++++++++++++++
igor_v 0:8ad47e2b6f00 364 LPC_PINCON->PINSEL1 &= ~0x0000C000; //e. select P0.23 as general purpose
igor_v 0:8ad47e2b6f00 365 LPC_GPIO0->FIODIR |= 0x00800000; //e. P0.23 is output
igor_v 0:8ad47e2b6f00 366 // LPC_GPIO0->FIOMASK |= 0x007F0000; //e. P0.16..P0.22 is not changed by FIOSET writing
igor_v 0:8ad47e2b6f00 367 LPC_GPIO0->FIOCLR |= 0x00800000; // e. clear P0.23
igor_v 0:8ad47e2b6f00 368
igor_v 0:8ad47e2b6f00 369 return;
igor_v 0:8ad47e2b6f00 370 }
igor_v 0:8ad47e2b6f00 371
igor_v 0:8ad47e2b6f00 372 void UART1_Init(void)
igor_v 0:8ad47e2b6f00 373 {
igor_v 0:8ad47e2b6f00 374 uint32_t Fdiv;
igor_v 0:8ad47e2b6f00 375 uint32_t pclk;
igor_v 0:8ad47e2b6f00 376 #if !defined UART1TEST
igor_v 0:8ad47e2b6f00 377 uint32_t baudrate = 256000;
igor_v 0:8ad47e2b6f00 378 #else
igor_v 0:8ad47e2b6f00 379 uint32_t baudrate = 38400;
igor_v 0:8ad47e2b6f00 380 #endif
igor_v 0:8ad47e2b6f00 381 LPC_SC->PCONP |= (1<<4); //switch on UART1
igor_v 0:8ad47e2b6f00 382
igor_v 0:8ad47e2b6f00 383 LPC_PINCON->PINSEL4 |= (2<<0)|(2<<2)|(2<<10)|(2<<14); //P2.0, P2.1, P2.5, P2.7
igor_v 0:8ad47e2b6f00 384
igor_v 0:8ad47e2b6f00 385 pclk = SystemCoreClock/4;
igor_v 0:8ad47e2b6f00 386
igor_v 0:8ad47e2b6f00 387 LPC_UART1->LCR = word_length_8 |one_stop_bit |no_parity |back_trans_dis |DLAB_access;
igor_v 0:8ad47e2b6f00 388 Fdiv = (pclk / 16) / baudrate;
igor_v 0:8ad47e2b6f00 389 LPC_UART1->DLM = Fdiv / 256;
igor_v 0:8ad47e2b6f00 390 LPC_UART1->DLL = Fdiv % 256;
igor_v 0:8ad47e2b6f00 391 LPC_UART1->LCR &= ~DLAB_access;
igor_v 0:8ad47e2b6f00 392 LPC_UART1->FCR = TX_FIFO_Reset |RX_FIFO_Reset |FIFOs_En |RX_TrigLvl_14; //0x06;
igor_v 0:8ad47e2b6f00 393
igor_v 0:8ad47e2b6f00 394 LPC_UART1->RS485CTRL = (1<<5); //(1<<4);
igor_v 0:8ad47e2b6f00 395
igor_v 0:8ad47e2b6f00 396 LPC_UART1->IER = 0;//RBR_IntEnabl;
igor_v 0:8ad47e2b6f00 397
igor_v 0:8ad47e2b6f00 398 LPC_UART1->FCR |= 0x08; //e. DMA mode select
igor_v 0:8ad47e2b6f00 399 return;
igor_v 0:8ad47e2b6f00 400 }
igor_v 0:8ad47e2b6f00 401 //----------------------temp----------------------------
igor_v 0:8ad47e2b6f00 402 /*int UART0_SendByte (int ucData)
igor_v 0:8ad47e2b6f00 403 {
igor_v 0:8ad47e2b6f00 404 // while (!(LPC_UART1->LSR & 0x20));
igor_v 0:8ad47e2b6f00 405 return (LPC_UART0->THR = ucData);
igor_v 0:8ad47e2b6f00 406 }*/
igor_v 0:8ad47e2b6f00 407 //----------------------temp----------------------------
igor_v 0:8ad47e2b6f00 408 int UART1_SendByte (int ucData)
igor_v 0:8ad47e2b6f00 409 {
igor_v 0:8ad47e2b6f00 410 // while (!(LPC_UART1->LSR & 0x20));
igor_v 0:8ad47e2b6f00 411 return (LPC_UART1->THR = ucData);
igor_v 0:8ad47e2b6f00 412 }
igor_v 0:8ad47e2b6f00 413 /******************************************************************************
igor_v 0:8ad47e2b6f00 414 ** Function name: UART_SwitchSpeed
igor_v 0:8ad47e2b6f00 415 **
igor_v 0:8ad47e2b6f00 416 ** Descriptions: Change UART speed
igor_v 0:8ad47e2b6f00 417 **
igor_v 0:8ad47e2b6f00 418 ** parameters: Demanded speed
igor_v 0:8ad47e2b6f00 419 ** Returned value: None
igor_v 0:8ad47e2b6f00 420 **
igor_v 0:8ad47e2b6f00 421 ******************************************************************************/
igor_v 0:8ad47e2b6f00 422 void UART_SwitchSpeed(unsigned Speed)
igor_v 0:8ad47e2b6f00 423 {
igor_v 0:8ad47e2b6f00 424 uint32_t Fdiv;
igor_v 0:8ad47e2b6f00 425 uint32_t pclk;
igor_v 0:8ad47e2b6f00 426
igor_v 0:8ad47e2b6f00 427 pclk = SystemCoreClock/4;
igor_v 0:8ad47e2b6f00 428 #if defined UART1REC
igor_v 0:8ad47e2b6f00 429 LPC_UART1->LCR |= DLAB_access;
igor_v 0:8ad47e2b6f00 430 #else
igor_v 0:8ad47e2b6f00 431 LPC_UART0->LCR |= DLAB_access;
igor_v 0:8ad47e2b6f00 432 #endif
igor_v 0:8ad47e2b6f00 433 switch (Speed)
igor_v 0:8ad47e2b6f00 434 {
igor_v 0:8ad47e2b6f00 435 case Sp38400:
igor_v 0:8ad47e2b6f00 436 Fdiv = (pclk / 16) / 38400;
igor_v 0:8ad47e2b6f00 437 EnablLength = 3240;
igor_v 0:8ad47e2b6f00 438 break;
igor_v 0:8ad47e2b6f00 439
igor_v 0:8ad47e2b6f00 440 case Sp115200:
igor_v 0:8ad47e2b6f00 441 Fdiv = (pclk / 16) /115200;
igor_v 0:8ad47e2b6f00 442 EnablLength = 1090;
igor_v 0:8ad47e2b6f00 443 break;
igor_v 0:8ad47e2b6f00 444
igor_v 0:8ad47e2b6f00 445 case Sp460800:
igor_v 0:8ad47e2b6f00 446 Fdiv = (pclk / 16) / 460800;
igor_v 0:8ad47e2b6f00 447 break;
igor_v 0:8ad47e2b6f00 448
igor_v 0:8ad47e2b6f00 449 case Sp921600:
igor_v 0:8ad47e2b6f00 450 Fdiv = (pclk / 16) / 921600;
igor_v 0:8ad47e2b6f00 451 EnablLength = 140;
igor_v 0:8ad47e2b6f00 452 break;
igor_v 0:8ad47e2b6f00 453
igor_v 0:8ad47e2b6f00 454 }
igor_v 0:8ad47e2b6f00 455 #if defined UART1REC
igor_v 0:8ad47e2b6f00 456 LPC_UART1->DLM = Fdiv / 256;
igor_v 0:8ad47e2b6f00 457 LPC_UART1->DLL = Fdiv % 256;
igor_v 0:8ad47e2b6f00 458 LPC_UART1->LCR &= ~DLAB_access;
igor_v 0:8ad47e2b6f00 459 #else
igor_v 0:8ad47e2b6f00 460 LPC_UART0->DLM = Fdiv / 256;
igor_v 0:8ad47e2b6f00 461 LPC_UART0->DLL = Fdiv % 256;
igor_v 0:8ad47e2b6f00 462 LPC_UART0->LCR &= ~DLAB_access;
igor_v 0:8ad47e2b6f00 463 #endif
igor_v 0:8ad47e2b6f00 464 }
igor_v 0:8ad47e2b6f00 465 /******************************************************************************
igor_v 0:8ad47e2b6f00 466 ** Function name: UART_DMA_Init
igor_v 0:8ad47e2b6f00 467 **
igor_v 0:8ad47e2b6f00 468 ** Descriptions: Initialisation of DMA channel for UART transmitter
igor_v 0:8ad47e2b6f00 469 **
igor_v 0:8ad47e2b6f00 470 ** parameters: None
igor_v 0:8ad47e2b6f00 471 ** Returned value: None
igor_v 0:8ad47e2b6f00 472 **
igor_v 0:8ad47e2b6f00 473 ******************************************************************************/
igor_v 0:8ad47e2b6f00 474 void UART_DMA_Init()
igor_v 0:8ad47e2b6f00 475 {
igor_v 0:8ad47e2b6f00 476 //+++++++++++++++++config channel for UART0+++++++++++++++++++++++++++++++++++++++++++++++
igor_v 0:8ad47e2b6f00 477 LPC_GPDMACH1->CConfig &= ~DMAChannelEn;
igor_v 0:8ad47e2b6f00 478
igor_v 0:8ad47e2b6f00 479 LPC_GPDMA->IntTCClear = DMA1_IntTCClear;
igor_v 0:8ad47e2b6f00 480 LPC_GPDMA->IntErrClr = DMA1_IntErrClear;
igor_v 0:8ad47e2b6f00 481
igor_v 0:8ad47e2b6f00 482 LPC_GPDMACH1->CSrcAddr = (uint32_t)&trm_buf;
igor_v 0:8ad47e2b6f00 483 LPC_GPDMACH1->CDestAddr = UART1_DMA_TX_DST;
igor_v 0:8ad47e2b6f00 484 LPC_GPDMACH1->CControl = SrcBSize_1 | DstBSize_1 | SrcWidth_8b | DstWidth_8b | SrcInc | DstFixed | TCIntDisabl;
igor_v 0:8ad47e2b6f00 485 #if defined UART1TEST
igor_v 0:8ad47e2b6f00 486 LPC_GPDMACH1->CConfig |= MaskTCInt | MaskErrInt | DMA_MEMORY | DstDMA_UART1_TX |(M2P << 11);
igor_v 0:8ad47e2b6f00 487 #else
igor_v 0:8ad47e2b6f00 488 g LPC_GPDMACH1->CConfig |= MaskTCInt | MaskErrInt | DMA_MEMORY | DstDMA_UART0_TX |(M2P << 11);
igor_v 0:8ad47e2b6f00 489 #endif
igor_v 0:8ad47e2b6f00 490
igor_v 0:8ad47e2b6f00 491 EnablDMA = (LPC_GPDMACH1->CConfig)|DMAChannelEn; //save register content for DMA starting in multidrop mode
igor_v 0:8ad47e2b6f00 492 //**********for Rate mode output*****************************
igor_v 0:8ad47e2b6f00 493 #if defined UART1TEST
igor_v 0:8ad47e2b6f00 494 LLI1_TypeDef[0] = (uint32_t)&trm_buf[32];
igor_v 0:8ad47e2b6f00 495 LLI1_TypeDef[1] = UART1_DMA_TX_DST;
igor_v 0:8ad47e2b6f00 496 LLI1_TypeDef[2] = 0;
igor_v 0:8ad47e2b6f00 497 LLI1_TypeDef[3] = (12 & 0x0FFF) | SrcBSize_1 | DstBSize_1 | SrcWidth_8b | DstWidth_8b | SrcInc | DstFixed | TCIntDisabl;
igor_v 0:8ad47e2b6f00 498
igor_v 0:8ad47e2b6f00 499 LLI0_TypeDef[0] = (uint32_t)&trm_buf[16];
igor_v 0:8ad47e2b6f00 500 LLI0_TypeDef[1] = UART1_DMA_TX_DST;
igor_v 0:8ad47e2b6f00 501 LLI0_TypeDef[2] = (uint32_t)&LLI1_TypeDef;
igor_v 0:8ad47e2b6f00 502 LLI0_TypeDef[3] = (16 & 0x0FFF) | SrcBSize_1 | DstBSize_1 | SrcWidth_8b | DstWidth_8b | SrcInc | DstFixed | TCIntDisabl;
igor_v 0:8ad47e2b6f00 503 #else
igor_v 0:8ad47e2b6f00 504 LLI1_TypeDef[0] = (uint32_t)&trm_buf[32];
igor_v 0:8ad47e2b6f00 505 LLI1_TypeDef[1] = UART0_DMA_TX_DST;
igor_v 0:8ad47e2b6f00 506 LLI1_TypeDef[2] = 0;
igor_v 0:8ad47e2b6f00 507 LLI1_TypeDef[3] = (12 & 0x0FFF) | SrcBSize_1 | DstBSize_1 | SrcWidth_8b | DstWidth_8b | SrcInc | DstFixed | TCIntDisabl;
igor_v 0:8ad47e2b6f00 508
igor_v 0:8ad47e2b6f00 509 LLI0_TypeDef[0] = (uint32_t)&trm_buf[16];
igor_v 0:8ad47e2b6f00 510 LLI0_TypeDef[1] = UART0_DMA_TX_DST;
igor_v 0:8ad47e2b6f00 511 LLI0_TypeDef[2] = (uint32_t)&LLI1_TypeDef;
igor_v 0:8ad47e2b6f00 512 LLI0_TypeDef[3] = (16 & 0x0FFF)|SrcBSize_1 |DstBSize_1 |SrcWidth_8b
igor_v 0:8ad47e2b6f00 513 |DstWidth_8b|SrcInc |DstFixed |TCIntDisabl;
igor_v 0:8ad47e2b6f00 514 #endif
igor_v 0:8ad47e2b6f00 515 //++++++++++++++++++++++++++config channel for transmit enable signal+++++++++++++++++++
igor_v 0:8ad47e2b6f00 516 LPC_GPDMACH2->CConfig &= ~DMAChannelEn;
igor_v 0:8ad47e2b6f00 517
igor_v 0:8ad47e2b6f00 518 LPC_GPDMA->IntTCClear = DMA2_IntTCClear;
igor_v 0:8ad47e2b6f00 519 LPC_GPDMA->IntErrClr = DMA2_IntErrClear;
igor_v 0:8ad47e2b6f00 520
igor_v 0:8ad47e2b6f00 521 LPC_GPDMACH2->CSrcAddr = (uint32_t)&EnablTx; //e. content of TX UART1 enable register
igor_v 0:8ad47e2b6f00 522 LPC_GPDMACH2->CDestAddr = 0x40010030; //e. address of TX UART1 enable register (U1TER)
igor_v 0:8ad47e2b6f00 523
igor_v 0:8ad47e2b6f00 524 LPC_GPDMACH2->CControl = SrcBSize_4 |DstBSize_4
igor_v 0:8ad47e2b6f00 525 |SrcWidth_8b |DstWidth_8b|SrcFixed |DstFixed |TCIntEnabl;
igor_v 0:8ad47e2b6f00 526
igor_v 0:8ad47e2b6f00 527 LPC_GPDMACH2->CConfig |= MaskTCInt |MaskErrInt
igor_v 0:8ad47e2b6f00 528 |SrcDMA_UART0_RX |DstDMA_UART0_RX|(M2P << 11);
igor_v 0:8ad47e2b6f00 529 LPC_GPDMACH2->CLLI = 0; //e. linked list is empty
igor_v 0:8ad47e2b6f00 530
igor_v 0:8ad47e2b6f00 531 //++++++++++++++++++++++++++config channel for DMA1 enable signal+++++++++++++++++++
igor_v 0:8ad47e2b6f00 532 #if defined UART1TEST
igor_v 0:8ad47e2b6f00 533 LPC_GPDMACH4->CConfig &= ~DMAChannelEn;
igor_v 0:8ad47e2b6f00 534
igor_v 0:8ad47e2b6f00 535 LPC_GPDMA->IntTCClear = DMA4_IntTCClear;
igor_v 0:8ad47e2b6f00 536 LPC_GPDMA->IntErrClr = DMA4_IntErrClear;
igor_v 0:8ad47e2b6f00 537
igor_v 0:8ad47e2b6f00 538 LPC_GPDMACH4->CSrcAddr = (uint32_t)&EnablDMA; //e. content of TX UART1 enable register
igor_v 0:8ad47e2b6f00 539 LPC_GPDMACH4->CDestAddr = 0x50004130; //e. address of DMA1CConfig register
igor_v 0:8ad47e2b6f00 540
igor_v 0:8ad47e2b6f00 541 LPC_GPDMACH4->CControl = SrcBSize_4 |DstBSize_4
igor_v 0:8ad47e2b6f00 542 |SrcWidth_8b |DstWidth_8b|SrcFixed |DstFixed |TCIntEnabl;
igor_v 0:8ad47e2b6f00 543
igor_v 0:8ad47e2b6f00 544 LPC_GPDMACH4->CConfig |= MaskTCInt |MaskErrInt
igor_v 0:8ad47e2b6f00 545 |SrcDMA_UART0_TX |DstDMA_UART0_TX|(M2P << 11);
igor_v 0:8ad47e2b6f00 546 LPC_GPDMACH4->CLLI = 0; //e. linked list is empty
igor_v 0:8ad47e2b6f00 547 #endif
igor_v 0:8ad47e2b6f00 548 }
igor_v 0:8ad47e2b6f00 549 /******************************************************************************
igor_v 0:8ad47e2b6f00 550 ** End Of File
igor_v 0:8ad47e2b6f00 551 ******************************************************************************/
igor_v 0:8ad47e2b6f00 552