Dmitry Kovalev / Mbed 2 deprecated LG2

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Dependencies:   mbed

Fork of LG by igor Apu

el_lin.h@0:8ad47e2b6f00, 2016-01-30 (annotated)

Committer:
igor_v
Date:
Sat Jan 30 13:00:39 2016 +0000
Revision:
0:8ad47e2b6f00
Child:
21:bc8c1cec3da6
2016_01_30;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
igor_v 0:8ad47e2b6f00 1
igor_v 0:8ad47e2b6f00 2 /**--------------File Info---------------------------------------------------------------------------------
igor_v 0:8ad47e2b6f00 3 ** File name: el_lin.h
igor_v 0:8ad47e2b6f00 4 ** Last modified Date: 2011-08-22
igor_v 0:8ad47e2b6f00 5 ** Last Version: V1.00
igor_v 0:8ad47e2b6f00 6 ** Descriptions:
igor_v 0:8ad47e2b6f00 7 **
igor_v 0:8ad47e2b6f00 8 **--------------------------------------------------------------------------------------------------------
igor_v 0:8ad47e2b6f00 9 ** Created by: Electrooptika incor.
igor_v 0:8ad47e2b6f00 10 ** Created date: 2011-08-22
igor_v 0:8ad47e2b6f00 11 ** Version: V1.00
igor_v 0:8ad47e2b6f00 12 **
igor_v 0:8ad47e2b6f00 13 **--------------------------------------------------------------------------------------------------------
igor_v 0:8ad47e2b6f00 14 *********************************************************************************************************/
igor_v 0:8ad47e2b6f00 15 #ifndef __DMA_H
igor_v 0:8ad47e2b6f00 16 #define __DMA_H
igor_v 0:8ad47e2b6f00 17
igor_v 0:8ad47e2b6f00 18
igor_v 0:8ad47e2b6f00 19
igor_v 0:8ad47e2b6f00 20 #define STRT_ERR 0x0080 //e. error of the start bit //r. îøèáêà ñòàðò-áèòà
igor_v 0:8ad47e2b6f00 21 #define STOP_ERR 0x0040 //e. error of the stop bit //r. îøèáêà ñòîï-áèòà
igor_v 0:8ad47e2b6f00 22 #define SIZE_ERR 0x0004 //e. size of the received data packet mismatches the agreement //r. ðàçìåð ïðèíÿòîãî ïàêåòà íå ñîîòâåòñòâóåò ñîãëàøåíèþ
igor_v 0:8ad47e2b6f00 23 #define LCC_ERR 0x0002 //e. checksum has not coincided //r. íå ñîâïàëà êîíòðîëüíàÿ ñóììà
igor_v 0:8ad47e2b6f00 24 #define NO_CMD_ERR 0x0100 //e. in the received packet there is no attribute of command //r. â ïðèíÿòîì ïàêåòå íåò ïðèçíàêà êîìàíäû
igor_v 0:8ad47e2b6f00 25 #define CODE_ERR 0x0200 //e. unknown code of a command //r. íåèçâåñòíûé êîä êîìàíäû
igor_v 0:8ad47e2b6f00 26 #define MODE_ERR 0x0400 //e. code of a command mismatches a current mode //r. êîä êîìàíäû íå ñîîòâåòñòâóåò òåêóùåìó ðåæèìó
igor_v 0:8ad47e2b6f00 27 #define PARAM_ERR 0x0800 //e. parameters of a command was set incorrectly //r. íåâåðíî çàäàííûå ïàðàìåòðû êîìàíäû
igor_v 0:8ad47e2b6f00 28 #define MAXSIZE_ERR 0x1000 //e. receiver buffer overflow //r. ïåðåïîëíåíèå áóôåðà ïðèåìíèêà
igor_v 0:8ad47e2b6f00 29 #define ADDR_ERR 0x2000 //e. incorrect address of the device //r. íåâåðíûé àäðåñ óñòðîéñòâà
igor_v 0:8ad47e2b6f00 30 #define READ_ERR 0x4000 //e. stop of link because of untimely data read //r. îñòàíîâ ñâÿçè íåñâîåâðåìåííûì ÷òåíèåì äàííûõ
igor_v 0:8ad47e2b6f00 31 #define WASQ_ERR 0x8000 //e. error of waiting of authentic answer //r. îøèáêà îæèäàíèÿ äîñòîâåðíîãî îòâåòà
igor_v 0:8ad47e2b6f00 32
igor_v 0:8ad47e2b6f00 33 #define Trm_En_Rd 0x0080 //e. a mask of permission/readiness of transmitter of the 2 line //r. ìàñêà ðàçðåøåíèÿ/ãîòîâíîñòè ïåðåäàò÷èêà ëèíèè 2
igor_v 0:8ad47e2b6f00 34 #define Rcv_Rdy 0x0040 //e. a mask of the readiness bit of the receiver //r. ìàñêà áèòà ãîòîâíîñòè ïðèåìíèêà
igor_v 0:8ad47e2b6f00 35 #define Rcv_Ferr 0x0020 //e. a mask of the "format error" bit //r. ìàñêà áèòà "îøèáêà ôîðìàòà"
igor_v 0:8ad47e2b6f00 36 #define Rcv_Tout 0x0010 //e. a mask of the "time-out" bit //r. ìàñêà áèòà "òàéì-àóò"
igor_v 0:8ad47e2b6f00 37 #define Rcv_Rful 0x0008 //e. a mask of the "stack is full" bit //r. ìàñêà áèòà "ñòåê ïîëîí"
igor_v 0:8ad47e2b6f00 38
igor_v 0:8ad47e2b6f00 39
igor_v 0:8ad47e2b6f00 40 #define FIFOs_En 0x00000001
igor_v 0:8ad47e2b6f00 41 #define RX_FIFO_Reset 0x00000002
igor_v 0:8ad47e2b6f00 42 #define TX_FIFO_Reset 0x00000004
igor_v 0:8ad47e2b6f00 43 #define DMA_Mode_UART 0x00000008
igor_v 0:8ad47e2b6f00 44 #define RX_TrigLvl_1 0x00000000
igor_v 0:8ad47e2b6f00 45 #define RX_TrigLvl_4 0x00000040
igor_v 0:8ad47e2b6f00 46 #define RX_TrigLvl_8 0x00000080
igor_v 0:8ad47e2b6f00 47 #define RX_TrigLvl_14 0x000000C0
igor_v 0:8ad47e2b6f00 48
igor_v 0:8ad47e2b6f00 49 #define word_length_8 0x00000003
igor_v 0:8ad47e2b6f00 50
igor_v 0:8ad47e2b6f00 51 #define one_stop_bit 0x00000000
igor_v 0:8ad47e2b6f00 52
igor_v 0:8ad47e2b6f00 53 #define no_parity 0x00000000
igor_v 0:8ad47e2b6f00 54
igor_v 0:8ad47e2b6f00 55 #define back_trans_dis 0x00000000
igor_v 0:8ad47e2b6f00 56
igor_v 0:8ad47e2b6f00 57 #define DLAB_access 0x00000080
igor_v 0:8ad47e2b6f00 58
igor_v 0:8ad47e2b6f00 59 #define TRANS_SHIFT_BUF_EMPTY 0x00000040
igor_v 0:8ad47e2b6f00 60 #define DMA_BUSY 0x00020000
igor_v 0:8ad47e2b6f00 61 #define RecievBufEmpty 0x00000001
igor_v 0:8ad47e2b6f00 62 #define DIS_ALL_INT 0x00000000
igor_v 0:8ad47e2b6f00 63 #define RBR_IntEnabl 0x00000001
igor_v 0:8ad47e2b6f00 64 /* Second half of the second RAM is used for GPDMA operation. */
igor_v 0:8ad47e2b6f00 65
igor_v 0:8ad47e2b6f00 66 #define DMA_UART0_TX 8
igor_v 0:8ad47e2b6f00 67 #define DMA_UART0_RX 9
igor_v 0:8ad47e2b6f00 68 #define DMA_UART1_TX 10
igor_v 0:8ad47e2b6f00 69 #define DMA_UART1_RX 11
igor_v 0:8ad47e2b6f00 70 #define DMA_UART2_TX 12
igor_v 0:8ad47e2b6f00 71 #define DMA_UART2_RX 13
igor_v 0:8ad47e2b6f00 72 #define DMA_UART3_TX 14
igor_v 0:8ad47e2b6f00 73 #define DMA_UART3_RX 15
igor_v 0:8ad47e2b6f00 74
igor_v 0:8ad47e2b6f00 75 #define DMA_MEMORY 0
igor_v 0:8ad47e2b6f00 76 #define SrcDMA_UART0_RX DMA_UART0_RX << 1
igor_v 0:8ad47e2b6f00 77 #define SrcDMA_UART0_TX DMA_UART0_TX << 1
igor_v 0:8ad47e2b6f00 78 #define SrcDMA_UART1_TX DMA_UART1_TX << 1
igor_v 0:8ad47e2b6f00 79 #define DstDMA_UART0_TX DMA_UART0_TX << 6
igor_v 0:8ad47e2b6f00 80 #define DstDMA_UART1_TX DMA_UART1_TX << 6
igor_v 0:8ad47e2b6f00 81 #define DstDMA_UART0_RX DMA_UART0_RX << 6
igor_v 0:8ad47e2b6f00 82 #define SrcDMA_UART1_RX DMA_UART1_RX << 1
igor_v 0:8ad47e2b6f00 83 #define DstDMA_UART1_RX DMA_UART1_RX << 6
igor_v 0:8ad47e2b6f00 84
igor_v 0:8ad47e2b6f00 85 /* UART0 TX and RX */
igor_v 0:8ad47e2b6f00 86 #define UART0_DMA_TX_SRC 0x2007C800 /* starting addr of DATA register in UART0 */
igor_v 0:8ad47e2b6f00 87 #define UART0_DMA_TX_DST LPC_UART0_BASE
igor_v 0:8ad47e2b6f00 88 #define UART0_DMA_RX_SRC LPC_UART0_BASE
igor_v 0:8ad47e2b6f00 89 #define UART0_DMA_RX_DST 0x2007C900
igor_v 0:8ad47e2b6f00 90
igor_v 0:8ad47e2b6f00 91 #define UART2_DMA_TX_DST LPC_UART2_BASE
igor_v 0:8ad47e2b6f00 92 #define UART1_DMA_TX_DST LPC_UART1_BASE
igor_v 0:8ad47e2b6f00 93
igor_v 0:8ad47e2b6f00 94 #define GPDMA_POWER_ON 0x20000000
igor_v 0:8ad47e2b6f00 95
igor_v 0:8ad47e2b6f00 96 #define UART_REQ 0x00000000
igor_v 0:8ad47e2b6f00 97
igor_v 0:8ad47e2b6f00 98 //To clear particular DMA TC-interrupts
igor_v 0:8ad47e2b6f00 99 #define DMA0_IntTCClear 0x00000001
igor_v 0:8ad47e2b6f00 100 #define DMA1_IntTCClear 0x00000002
igor_v 0:8ad47e2b6f00 101 #define DMA2_IntTCClear 0x00000004
igor_v 0:8ad47e2b6f00 102 #define DMA3_IntTCClear 0x00000008
igor_v 0:8ad47e2b6f00 103 #define DMA4_IntTCClear 0x00000010
igor_v 0:8ad47e2b6f00 104 #define DMA5_IntTCClear 0x00000020
igor_v 0:8ad47e2b6f00 105 #define DMA6_IntTCClear 0x00000040
igor_v 0:8ad47e2b6f00 106 #define DMA7_IntTCClear 0x00000080
igor_v 0:8ad47e2b6f00 107
igor_v 0:8ad47e2b6f00 108 //To clear particular DMA Error-interrupts
igor_v 0:8ad47e2b6f00 109 #define DMA0_IntErrClear 0x00000001
igor_v 0:8ad47e2b6f00 110 #define DMA1_IntErrClear 0x00000002
igor_v 0:8ad47e2b6f00 111 #define DMA2_IntErrClear 0x00000004
igor_v 0:8ad47e2b6f00 112 #define DMA3_IntErrClear 0x00000008
igor_v 0:8ad47e2b6f00 113 #define DMA4_IntErrClear 0x00000010
igor_v 0:8ad47e2b6f00 114 #define DMA5_IntErrClear 0x00000020
igor_v 0:8ad47e2b6f00 115 #define DMA6_IntErrClear 0x00000040
igor_v 0:8ad47e2b6f00 116 #define DMA7_IntErrClear 0x00000080
igor_v 0:8ad47e2b6f00 117 #define DMACH1_IntTCPend 0x00000002
igor_v 0:8ad47e2b6f00 118
igor_v 0:8ad47e2b6f00 119 #define DMA_ControllerEn 0x00000001
igor_v 0:8ad47e2b6f00 120
igor_v 0:8ad47e2b6f00 121 #define DMA_AHB_Little 0x00000000
igor_v 0:8ad47e2b6f00 122 #define DMA_AHB_Big 0x00000002
igor_v 0:8ad47e2b6f00 123
igor_v 0:8ad47e2b6f00 124 #define SrcBSize_1 0x00000000
igor_v 0:8ad47e2b6f00 125 #define SrcBSize_4 0x00001000
igor_v 0:8ad47e2b6f00 126 #define SrcBSize_8 0x00002000
igor_v 0:8ad47e2b6f00 127 #define SrcBSize_16 0x00003000
igor_v 0:8ad47e2b6f00 128 #define SrcBSize_32 0x00004000
igor_v 0:8ad47e2b6f00 129 #define SrcBSize_64 0x00005000
igor_v 0:8ad47e2b6f00 130 #define SrcBSize_128 0x00006000
igor_v 0:8ad47e2b6f00 131 #define SrcBSize_256 0x00007000
igor_v 0:8ad47e2b6f00 132
igor_v 0:8ad47e2b6f00 133 #define DstBSize_1 0x00000000
igor_v 0:8ad47e2b6f00 134 #define DstBSize_4 0x00008000
igor_v 0:8ad47e2b6f00 135 #define DstBSize_8 0x00010000
igor_v 0:8ad47e2b6f00 136 #define DstBSize_16 0x00018000
igor_v 0:8ad47e2b6f00 137 #define DstBSize_32 0x00020000
igor_v 0:8ad47e2b6f00 138 #define DstBSize_64 0x00028000
igor_v 0:8ad47e2b6f00 139 #define DstBSize_128 0x00030000
igor_v 0:8ad47e2b6f00 140 #define DstBSize_256 0x00038000
igor_v 0:8ad47e2b6f00 141
igor_v 0:8ad47e2b6f00 142 #define SrcWidth_8b 0x00000000
igor_v 0:8ad47e2b6f00 143 #define SrcWidth_16b 0x00020000
igor_v 0:8ad47e2b6f00 144 #define SrcWidth_32b 0x00040000
igor_v 0:8ad47e2b6f00 145
igor_v 0:8ad47e2b6f00 146 #define DstWidth_8b 0x00000000
igor_v 0:8ad47e2b6f00 147 #define DstWidth_16b 0x00200000
igor_v 0:8ad47e2b6f00 148 #define DstWidth_32b 0x00400000
igor_v 0:8ad47e2b6f00 149
igor_v 0:8ad47e2b6f00 150 #define SrcInc 0x04000000
igor_v 0:8ad47e2b6f00 151 #define SrcFixed 0x00000000
igor_v 0:8ad47e2b6f00 152
igor_v 0:8ad47e2b6f00 153 #define DstInc 0x08000000
igor_v 0:8ad47e2b6f00 154 #define DstFixed 0x00000000
igor_v 0:8ad47e2b6f00 155
igor_v 0:8ad47e2b6f00 156 #define TCIntEnabl 0x80000000
igor_v 0:8ad47e2b6f00 157 #define TCIntDisabl 0x00000000
igor_v 0:8ad47e2b6f00 158
igor_v 0:8ad47e2b6f00 159 #define DMAChannelEn 0x00000001
igor_v 0:8ad47e2b6f00 160 #define DMAChannelDis 0x00000000
igor_v 0:8ad47e2b6f00 161
igor_v 0:8ad47e2b6f00 162 #define CH2_ENABLED 0x00000004
igor_v 0:8ad47e2b6f00 163
igor_v 0:8ad47e2b6f00 164 #define DONtMaskTCInt 0x00008000
igor_v 0:8ad47e2b6f00 165 #define MaskTCInt 0x00000000
igor_v 0:8ad47e2b6f00 166 #define DONtMaskErrInt 0x00004000
igor_v 0:8ad47e2b6f00 167 #define MaskErrInt 0x00000000
igor_v 0:8ad47e2b6f00 168
igor_v 0:8ad47e2b6f00 169 #define INT_DMA_Disabl 0x04000000
igor_v 0:8ad47e2b6f00 170 /* DMA mode */
igor_v 0:8ad47e2b6f00 171 #define M2M 0x00
igor_v 0:8ad47e2b6f00 172 #define M2P 0x01
igor_v 0:8ad47e2b6f00 173 #define P2M 0x02
igor_v 0:8ad47e2b6f00 174 #define P2P 0x03
igor_v 0:8ad47e2b6f00 175
igor_v 0:8ad47e2b6f00 176 #define Sp38400 0x00000
igor_v 0:8ad47e2b6f00 177 #define Sp115200 0x00010
igor_v 0:8ad47e2b6f00 178 #define Sp460800 0x00020
igor_v 0:8ad47e2b6f00 179 #define Sp921600 0x00030
igor_v 0:8ad47e2b6f00 180
igor_v 0:8ad47e2b6f00 181 extern unsigned int trm_num_byt;
igor_v 0:8ad47e2b6f00 182 extern unsigned int rcv_num_byt;
igor_v 0:8ad47e2b6f00 183 extern unsigned int rcv_Rdy;
igor_v 0:8ad47e2b6f00 184 extern char trm_buf[64];
igor_v 0:8ad47e2b6f00 185 extern char rcv_buf[64];
igor_v 0:8ad47e2b6f00 186 extern char rcv_copy[64];
igor_v 0:8ad47e2b6f00 187 extern unsigned int trm_cycl;
igor_v 0:8ad47e2b6f00 188 extern unsigned int num_of_par;
igor_v 0:8ad47e2b6f00 189 extern void* addr_param[16];
igor_v 0:8ad47e2b6f00 190 extern unsigned int size_param[16];
igor_v 0:8ad47e2b6f00 191 extern unsigned int trm_rate;
igor_v 0:8ad47e2b6f00 192 extern unsigned int trm_cycl;
igor_v 0:8ad47e2b6f00 193 extern unsigned int rcv_num_byt_old;
igor_v 0:8ad47e2b6f00 194 extern int rcv_byt_copy;
igor_v 0:8ad47e2b6f00 195 extern unsigned int trm_ena;
igor_v 0:8ad47e2b6f00 196 extern int cycl_phase;
igor_v 0:8ad47e2b6f00 197 extern unsigned int line_err;
igor_v 0:8ad47e2b6f00 198 extern unsigned int line_sts;
igor_v 0:8ad47e2b6f00 199 extern int rx_buf_copy;
igor_v 0:8ad47e2b6f00 200 extern char zeros;
igor_v 0:8ad47e2b6f00 201 extern unsigned int SystemCoreClock;
igor_v 0:8ad47e2b6f00 202
igor_v 0:8ad47e2b6f00 203 extern void DMA_Init(void);
igor_v 0:8ad47e2b6f00 204 extern void transm_DAT(void);
igor_v 0:8ad47e2b6f00 205 extern void Line_1_Rcv(void);
igor_v 0:8ad47e2b6f00 206
igor_v 0:8ad47e2b6f00 207 extern void UARTInit(void);
igor_v 0:8ad47e2b6f00 208 extern void UART1_Init(void);
igor_v 0:8ad47e2b6f00 209 //extern int UART0_SendByte(int);
igor_v 0:8ad47e2b6f00 210 extern int UART1_SendByte(int);
igor_v 0:8ad47e2b6f00 211 extern void UART_SwitchSpeed(unsigned);
igor_v 0:8ad47e2b6f00 212 extern void UART_DMA_Init(void);
igor_v 0:8ad47e2b6f00 213 extern void SystemCoreClockUpdate (void);
igor_v 0:8ad47e2b6f00 214
igor_v 0:8ad47e2b6f00 215 #endif /* end __DMA_H */
igor_v 0:8ad47e2b6f00 216
igor_v 0:8ad47e2b6f00 217