Martin Kojtal / mbed-dev

forked

targets/TARGET_STM/gpio_irq_api.c@170:19eb464bc2be, 2017-08-03 (annotated)

Committer:
Kojto
Date:
Thu Aug 03 13:13:39 2017 +0100
Revision:
170:19eb464bc2be
Parent:
160:d5399cc887bb 
This updates the lib to the mbed lib v 148

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 160:d5399cc887bb 1 /* mbed Microcontroller Library
<> 160:d5399cc887bb 2 *******************************************************************************
<> 160:d5399cc887bb 3 * Copyright (c) 2014, STMicroelectronics
<> 160:d5399cc887bb 4 * All rights reserved.
<> 160:d5399cc887bb 5 *
<> 160:d5399cc887bb 6 * Redistribution and use in source and binary forms, with or without
<> 160:d5399cc887bb 7 * modification, are permitted provided that the following conditions are met:
<> 160:d5399cc887bb 8 *
<> 160:d5399cc887bb 9 * 1. Redistributions of source code must retain the above copyright notice,
<> 160:d5399cc887bb 10 * this list of conditions and the following disclaimer.
<> 160:d5399cc887bb 11 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 160:d5399cc887bb 12 * this list of conditions and the following disclaimer in the documentation
<> 160:d5399cc887bb 13 * and/or other materials provided with the distribution.
<> 160:d5399cc887bb 14 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 160:d5399cc887bb 15 * may be used to endorse or promote products derived from this software
<> 160:d5399cc887bb 16 * without specific prior written permission.
<> 160:d5399cc887bb 17 *
<> 160:d5399cc887bb 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 160:d5399cc887bb 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 160:d5399cc887bb 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 160:d5399cc887bb 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 160:d5399cc887bb 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 160:d5399cc887bb 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 160:d5399cc887bb 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 160:d5399cc887bb 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 160:d5399cc887bb 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 160:d5399cc887bb 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 160:d5399cc887bb 28 *******************************************************************************
<> 160:d5399cc887bb 29 */
<> 160:d5399cc887bb 30 #include <stddef.h>
<> 160:d5399cc887bb 31 #include "cmsis.h"
<> 160:d5399cc887bb 32 #include "gpio_irq_api.h"
<> 160:d5399cc887bb 33 #include "pinmap.h"
<> 160:d5399cc887bb 34 #include "mbed_error.h"
<> 160:d5399cc887bb 35 #include "gpio_irq_device.h"
<> 160:d5399cc887bb 36
<> 160:d5399cc887bb 37 #define EDGE_NONE (0)
<> 160:d5399cc887bb 38 #define EDGE_RISE (1)
<> 160:d5399cc887bb 39 #define EDGE_FALL (2)
<> 160:d5399cc887bb 40 #define EDGE_BOTH (3)
<> 160:d5399cc887bb 41
<> 160:d5399cc887bb 42
<> 160:d5399cc887bb 43 typedef struct gpio_channel {
<> 160:d5399cc887bb 44 uint32_t pin_mask; // bitmask representing which pins are configured for receiving interrupts
<> 160:d5399cc887bb 45 uint32_t channel_ids[MAX_PIN_LINE]; // mbed "gpio_irq_t gpio_irq" field of instance
<> 160:d5399cc887bb 46 GPIO_TypeDef* channel_gpio[MAX_PIN_LINE]; // base address of gpio port group
<> 160:d5399cc887bb 47 uint32_t channel_pin[MAX_PIN_LINE]; // pin number in port group
<> 160:d5399cc887bb 48 } gpio_channel_t;
<> 160:d5399cc887bb 49
<> 160:d5399cc887bb 50 static gpio_irq_handler irq_handler;
<> 160:d5399cc887bb 51
<> 160:d5399cc887bb 52 static gpio_channel_t channels[CHANNEL_NUM] = {
<> 160:d5399cc887bb 53 #ifdef EXTI_IRQ0_NUM_LINES
<> 160:d5399cc887bb 54 {.pin_mask = 0},
<> 160:d5399cc887bb 55 #endif
<> 160:d5399cc887bb 56 #ifdef EXTI_IRQ1_NUM_LINES
<> 160:d5399cc887bb 57 {.pin_mask = 0},
<> 160:d5399cc887bb 58 #endif
<> 160:d5399cc887bb 59 #ifdef EXTI_IRQ2_NUM_LINES
<> 160:d5399cc887bb 60 {.pin_mask = 0},
<> 160:d5399cc887bb 61 #endif
<> 160:d5399cc887bb 62 #ifdef EXTI_IRQ3_NUM_LINES
<> 160:d5399cc887bb 63 {.pin_mask = 0},
<> 160:d5399cc887bb 64 #endif
<> 160:d5399cc887bb 65 #ifdef EXTI_IRQ4_NUM_LINES
<> 160:d5399cc887bb 66 {.pin_mask = 0},
<> 160:d5399cc887bb 67 #endif
<> 160:d5399cc887bb 68 #ifdef EXTI_IRQ5_NUM_LINES
<> 160:d5399cc887bb 69 {.pin_mask = 0},
<> 160:d5399cc887bb 70 #endif
<> 160:d5399cc887bb 71 #ifdef EXTI_IRQ6_NUM_LINES
<> 160:d5399cc887bb 72 {.pin_mask = 0}
<> 160:d5399cc887bb 73 #endif
<> 160:d5399cc887bb 74 };
<> 160:d5399cc887bb 75
<> 160:d5399cc887bb 76 static void handle_interrupt_in(uint32_t irq_index, uint32_t max_num_pin_line)
<> 160:d5399cc887bb 77 {
<> 160:d5399cc887bb 78 gpio_channel_t *gpio_channel = &channels[irq_index];
<> 160:d5399cc887bb 79 uint32_t gpio_idx;
<> 160:d5399cc887bb 80
<> 160:d5399cc887bb 81 for (gpio_idx = 0; gpio_idx < max_num_pin_line; gpio_idx++) {
<> 160:d5399cc887bb 82 uint32_t current_mask = (1 << gpio_idx);
<> 160:d5399cc887bb 83
<> 160:d5399cc887bb 84 if (gpio_channel->pin_mask & current_mask) {
<> 160:d5399cc887bb 85 // Retrieve the gpio and pin that generate the irq
<> 160:d5399cc887bb 86 GPIO_TypeDef *gpio = (GPIO_TypeDef *)(gpio_channel->channel_gpio[gpio_idx]);
<> 160:d5399cc887bb 87 uint32_t pin = (uint32_t)(1 << (gpio_channel->channel_pin[gpio_idx]));
<> 160:d5399cc887bb 88
<> 160:d5399cc887bb 89 // Clear interrupt flag
<> 160:d5399cc887bb 90 if (__HAL_GPIO_EXTI_GET_FLAG(pin) != RESET) {
<> 160:d5399cc887bb 91 __HAL_GPIO_EXTI_CLEAR_FLAG(pin);
<> 160:d5399cc887bb 92
Kojto 170:19eb464bc2be 93 if (gpio_channel->channel_ids[gpio_idx] == 0) {
<> 160:d5399cc887bb 94 continue;
Kojto 170:19eb464bc2be 95 }
<> 160:d5399cc887bb 96
<> 160:d5399cc887bb 97 // Check which edge has generated the irq
<> 160:d5399cc887bb 98 if ((gpio->IDR & pin) == 0) {
<> 160:d5399cc887bb 99 irq_handler(gpio_channel->channel_ids[gpio_idx], IRQ_FALL);
<> 160:d5399cc887bb 100 } else {
<> 160:d5399cc887bb 101 irq_handler(gpio_channel->channel_ids[gpio_idx], IRQ_RISE);
<> 160:d5399cc887bb 102 }
Kojto 170:19eb464bc2be 103 return;
<> 160:d5399cc887bb 104 }
<> 160:d5399cc887bb 105 }
<> 160:d5399cc887bb 106 }
Kojto 170:19eb464bc2be 107 error("Unexpected Spurious interrupt, index %d\r\n", irq_index);
<> 160:d5399cc887bb 108 }
<> 160:d5399cc887bb 109
<> 160:d5399cc887bb 110
<> 160:d5399cc887bb 111 #ifdef EXTI_IRQ0_NUM_LINES
<> 160:d5399cc887bb 112 // EXTI line 0
<> 160:d5399cc887bb 113 static void gpio_irq0(void)
<> 160:d5399cc887bb 114 {
<> 160:d5399cc887bb 115 handle_interrupt_in(0, EXTI_IRQ0_NUM_LINES);
<> 160:d5399cc887bb 116 }
<> 160:d5399cc887bb 117 #endif
<> 160:d5399cc887bb 118 #ifdef EXTI_IRQ1_NUM_LINES
<> 160:d5399cc887bb 119 // EXTI line 1
<> 160:d5399cc887bb 120 static void gpio_irq1(void)
<> 160:d5399cc887bb 121 {
<> 160:d5399cc887bb 122 handle_interrupt_in(1, EXTI_IRQ1_NUM_LINES);
<> 160:d5399cc887bb 123 }
<> 160:d5399cc887bb 124 #endif
<> 160:d5399cc887bb 125 #ifdef EXTI_IRQ2_NUM_LINES
<> 160:d5399cc887bb 126 // EXTI line 2
<> 160:d5399cc887bb 127 static void gpio_irq2(void)
<> 160:d5399cc887bb 128 {
<> 160:d5399cc887bb 129 handle_interrupt_in(2, EXTI_IRQ2_NUM_LINES);
<> 160:d5399cc887bb 130 }
<> 160:d5399cc887bb 131 #endif
<> 160:d5399cc887bb 132 #ifdef EXTI_IRQ3_NUM_LINES
<> 160:d5399cc887bb 133 // EXTI line 3
<> 160:d5399cc887bb 134 static void gpio_irq3(void)
<> 160:d5399cc887bb 135 {
<> 160:d5399cc887bb 136 handle_interrupt_in(3, EXTI_IRQ3_NUM_LINES);
<> 160:d5399cc887bb 137 }
<> 160:d5399cc887bb 138 #endif
<> 160:d5399cc887bb 139 #ifdef EXTI_IRQ4_NUM_LINES
<> 160:d5399cc887bb 140 // EXTI line 4
<> 160:d5399cc887bb 141 static void gpio_irq4(void)
<> 160:d5399cc887bb 142 {
<> 160:d5399cc887bb 143 handle_interrupt_in(4, EXTI_IRQ4_NUM_LINES);
<> 160:d5399cc887bb 144 }
<> 160:d5399cc887bb 145 #endif
<> 160:d5399cc887bb 146 #ifdef EXTI_IRQ5_NUM_LINES
<> 160:d5399cc887bb 147 // EXTI lines 5 to 9
<> 160:d5399cc887bb 148 static void gpio_irq5(void)
<> 160:d5399cc887bb 149 {
<> 160:d5399cc887bb 150 handle_interrupt_in(5, EXTI_IRQ5_NUM_LINES);
<> 160:d5399cc887bb 151 }
<> 160:d5399cc887bb 152 #endif
<> 160:d5399cc887bb 153 #ifdef EXTI_IRQ6_NUM_LINES
<> 160:d5399cc887bb 154 // EXTI lines 10 to 15
<> 160:d5399cc887bb 155 static void gpio_irq6(void)
<> 160:d5399cc887bb 156 {
<> 160:d5399cc887bb 157 handle_interrupt_in(6, EXTI_IRQ6_NUM_LINES);
<> 160:d5399cc887bb 158 }
<> 160:d5399cc887bb 159 #endif
<> 160:d5399cc887bb 160
<> 160:d5399cc887bb 161 extern GPIO_TypeDef *Set_GPIO_Clock(uint32_t port_idx);
<> 160:d5399cc887bb 162 extern void pin_function_gpiomode(PinName pin, uint32_t gpiomode);
<> 160:d5399cc887bb 163
<> 160:d5399cc887bb 164 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
<> 160:d5399cc887bb 165 {
<> 160:d5399cc887bb 166 uint32_t vector = 0;
<> 160:d5399cc887bb 167 uint32_t irq_index;
<> 160:d5399cc887bb 168 gpio_channel_t *gpio_channel;
<> 160:d5399cc887bb 169 uint32_t gpio_idx;
<> 160:d5399cc887bb 170
<> 160:d5399cc887bb 171 if (pin == NC) return -1;
<> 160:d5399cc887bb 172
<> 160:d5399cc887bb 173 /* Enable SYSCFG Clock */
<> 160:d5399cc887bb 174 __HAL_RCC_SYSCFG_CLK_ENABLE();
<> 160:d5399cc887bb 175
<> 160:d5399cc887bb 176 uint32_t port_index = STM_PORT(pin);
<> 160:d5399cc887bb 177 uint32_t pin_index = STM_PIN(pin);
<> 160:d5399cc887bb 178 irq_index = pin_lines_desc[pin_index].irq_index;
<> 160:d5399cc887bb 179
<> 160:d5399cc887bb 180 switch (irq_index) {
<> 160:d5399cc887bb 181 #ifdef EXTI_IRQ0_NUM_LINES
<> 160:d5399cc887bb 182 case 0:
<> 160:d5399cc887bb 183 vector = (uint32_t)&gpio_irq0;
<> 160:d5399cc887bb 184 break;
<> 160:d5399cc887bb 185 #endif
<> 160:d5399cc887bb 186 #ifdef EXTI_IRQ1_NUM_LINES
<> 160:d5399cc887bb 187 case 1:
<> 160:d5399cc887bb 188 vector = (uint32_t)&gpio_irq1;
<> 160:d5399cc887bb 189 break;
<> 160:d5399cc887bb 190 #endif
<> 160:d5399cc887bb 191 #ifdef EXTI_IRQ2_NUM_LINES
<> 160:d5399cc887bb 192 case 2:
<> 160:d5399cc887bb 193 vector = (uint32_t)&gpio_irq2;
<> 160:d5399cc887bb 194 break;
<> 160:d5399cc887bb 195 #endif
<> 160:d5399cc887bb 196 #ifdef EXTI_IRQ3_NUM_LINES
<> 160:d5399cc887bb 197 case 3:
<> 160:d5399cc887bb 198 vector = (uint32_t)&gpio_irq3;
<> 160:d5399cc887bb 199 break;
<> 160:d5399cc887bb 200 #endif
<> 160:d5399cc887bb 201 #ifdef EXTI_IRQ4_NUM_LINES
<> 160:d5399cc887bb 202 case 4:
<> 160:d5399cc887bb 203 vector = (uint32_t)&gpio_irq4;
<> 160:d5399cc887bb 204 break;
<> 160:d5399cc887bb 205 #endif
<> 160:d5399cc887bb 206 #ifdef EXTI_IRQ5_NUM_LINES
<> 160:d5399cc887bb 207 case 5:
<> 160:d5399cc887bb 208 vector = (uint32_t)&gpio_irq5;
<> 160:d5399cc887bb 209 break;
<> 160:d5399cc887bb 210 #endif
<> 160:d5399cc887bb 211 #ifdef EXTI_IRQ6_NUM_LINES
<> 160:d5399cc887bb 212 case 6:
<> 160:d5399cc887bb 213 vector = (uint32_t)&gpio_irq6;
<> 160:d5399cc887bb 214 break;
<> 160:d5399cc887bb 215 #endif
<> 160:d5399cc887bb 216 default:
<> 160:d5399cc887bb 217 error("InterruptIn error: pin not supported.\n");
<> 160:d5399cc887bb 218 return -1;
<> 160:d5399cc887bb 219 }
<> 160:d5399cc887bb 220
<> 160:d5399cc887bb 221 // Enable GPIO clock
<> 160:d5399cc887bb 222 GPIO_TypeDef *gpio_add = Set_GPIO_Clock(port_index);
<> 160:d5399cc887bb 223
<> 160:d5399cc887bb 224 // Save informations for future use
<> 160:d5399cc887bb 225 obj->irq_n = pin_lines_desc[pin_index].irq_n;
<> 160:d5399cc887bb 226 obj->irq_index = pin_lines_desc[pin_index].irq_index;
<> 160:d5399cc887bb 227 obj->event = EDGE_NONE;
<> 160:d5399cc887bb 228 obj->pin = pin;
<> 160:d5399cc887bb 229
<> 160:d5399cc887bb 230 gpio_channel = &channels[irq_index];
<> 160:d5399cc887bb 231 gpio_idx = pin_lines_desc[pin_index].gpio_idx;
<> 160:d5399cc887bb 232 gpio_channel->pin_mask |= (1 << gpio_idx);
<> 160:d5399cc887bb 233 gpio_channel->channel_ids[gpio_idx] = id;
<> 160:d5399cc887bb 234 gpio_channel->channel_gpio[gpio_idx] = gpio_add;
<> 160:d5399cc887bb 235 gpio_channel->channel_pin[gpio_idx] = pin_index;
<> 160:d5399cc887bb 236
<> 160:d5399cc887bb 237 irq_handler = handler;
<> 160:d5399cc887bb 238
<> 160:d5399cc887bb 239 // Enable EXTI interrupt
<> 160:d5399cc887bb 240 NVIC_SetVector(obj->irq_n, vector);
<> 160:d5399cc887bb 241 gpio_irq_enable(obj);
<> 160:d5399cc887bb 242
<> 160:d5399cc887bb 243 return 0;
<> 160:d5399cc887bb 244 }
<> 160:d5399cc887bb 245
<> 160:d5399cc887bb 246 void gpio_irq_free(gpio_irq_t *obj)
<> 160:d5399cc887bb 247 {
<> 160:d5399cc887bb 248 uint32_t gpio_idx = pin_lines_desc[STM_PIN(obj->pin)].gpio_idx;
<> 160:d5399cc887bb 249 gpio_channel_t *gpio_channel = &channels[obj->irq_index];
<> 160:d5399cc887bb 250
<> 160:d5399cc887bb 251 gpio_irq_disable(obj);
<> 160:d5399cc887bb 252 gpio_channel->pin_mask &= ~(1 << gpio_idx);
<> 160:d5399cc887bb 253 gpio_channel->channel_ids[gpio_idx] = 0;
<> 160:d5399cc887bb 254 gpio_channel->channel_gpio[gpio_idx] = 0;
<> 160:d5399cc887bb 255 gpio_channel->channel_pin[gpio_idx] = 0;
<> 160:d5399cc887bb 256 }
<> 160:d5399cc887bb 257
<> 160:d5399cc887bb 258 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
<> 160:d5399cc887bb 259 {
Kojto 170:19eb464bc2be 260 /* Enable / Disable Edge triggered interrupt and store event */
<> 160:d5399cc887bb 261 if (event == IRQ_RISE) {
<> 160:d5399cc887bb 262 if (enable) {
<> 160:d5399cc887bb 263 LL_EXTI_EnableRisingTrig_0_31(1 << STM_PIN(obj->pin));
Kojto 170:19eb464bc2be 264 obj->event |= IRQ_RISE;
<> 160:d5399cc887bb 265 } else {
<> 160:d5399cc887bb 266 LL_EXTI_DisableRisingTrig_0_31(1 << STM_PIN(obj->pin));
Kojto 170:19eb464bc2be 267 obj->event &= ~IRQ_RISE;
<> 160:d5399cc887bb 268 }
<> 160:d5399cc887bb 269 }
<> 160:d5399cc887bb 270 if (event == IRQ_FALL) {
<> 160:d5399cc887bb 271 if (enable) {
<> 160:d5399cc887bb 272 LL_EXTI_EnableFallingTrig_0_31(1 << STM_PIN(obj->pin));
Kojto 170:19eb464bc2be 273 obj->event |= IRQ_FALL;
<> 160:d5399cc887bb 274 } else {
<> 160:d5399cc887bb 275 LL_EXTI_DisableFallingTrig_0_31(1 << STM_PIN(obj->pin));
Kojto 170:19eb464bc2be 276 obj->event &= ~IRQ_FALL;
<> 160:d5399cc887bb 277 }
<> 160:d5399cc887bb 278 }
<> 160:d5399cc887bb 279 }
<> 160:d5399cc887bb 280
<> 160:d5399cc887bb 281 void gpio_irq_enable(gpio_irq_t *obj)
<> 160:d5399cc887bb 282 {
<> 160:d5399cc887bb 283 uint32_t temp = 0;
<> 160:d5399cc887bb 284 uint32_t port_index = STM_PORT(obj->pin);
<> 160:d5399cc887bb 285 uint32_t pin_index = STM_PIN(obj->pin);
<> 160:d5399cc887bb 286
<> 160:d5399cc887bb 287 /* Select Source */
<> 160:d5399cc887bb 288 temp = SYSCFG->EXTICR[pin_index >> 2];
<> 160:d5399cc887bb 289 CLEAR_BIT(temp, (0x0FU) << (4U * (pin_index & 0x03U)));
<> 160:d5399cc887bb 290 SET_BIT(temp, port_index << (4U * (pin_index & 0x03U)));
<> 160:d5399cc887bb 291 SYSCFG->EXTICR[pin_index >> 2] = temp;
<> 160:d5399cc887bb 292
<> 160:d5399cc887bb 293 LL_EXTI_EnableIT_0_31(1 << pin_index);
<> 160:d5399cc887bb 294
Kojto 170:19eb464bc2be 295 /* Restore previous edge interrupt configuration if applicable */
Kojto 170:19eb464bc2be 296 if (obj->event & IRQ_RISE) {
Kojto 170:19eb464bc2be 297 LL_EXTI_EnableRisingTrig_0_31(1 << STM_PIN(obj->pin));
Kojto 170:19eb464bc2be 298 }
Kojto 170:19eb464bc2be 299 if (obj->event & IRQ_FALL) {
Kojto 170:19eb464bc2be 300 LL_EXTI_EnableFallingTrig_0_31(1 << STM_PIN(obj->pin));
Kojto 170:19eb464bc2be 301 }
Kojto 170:19eb464bc2be 302
<> 160:d5399cc887bb 303 NVIC_EnableIRQ(obj->irq_n);
<> 160:d5399cc887bb 304 }
<> 160:d5399cc887bb 305
<> 160:d5399cc887bb 306 void gpio_irq_disable(gpio_irq_t *obj)
<> 160:d5399cc887bb 307 {
<> 160:d5399cc887bb 308 /* Clear EXTI line configuration */
Kojto 170:19eb464bc2be 309 LL_EXTI_DisableRisingTrig_0_31(1 << STM_PIN(obj->pin));
Kojto 170:19eb464bc2be 310 LL_EXTI_DisableFallingTrig_0_31(1 << STM_PIN(obj->pin));
<> 160:d5399cc887bb 311 LL_EXTI_DisableIT_0_31(1 << STM_PIN(obj->pin));
<> 160:d5399cc887bb 312 NVIC_DisableIRQ(obj->irq_n);
<> 160:d5399cc887bb 313 NVIC_ClearPendingIRQ(obj->irq_n);
<> 160:d5399cc887bb 314 }