forked

Committer:
Kojto
Date:
Thu Aug 03 13:13:39 2017 +0100
Revision:
170:19eb464bc2be
Parent:
167:e84263d55307
This updates the lib to the mbed lib v 148

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**************************************************************************//**
<> 149:156823d33999 2 * @file core_cm4.h
<> 149:156823d33999 3 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
AnnaBridge 167:e84263d55307 4 * @version V5.0.2
AnnaBridge 167:e84263d55307 5 * @date 13. February 2017
AnnaBridge 167:e84263d55307 6 ******************************************************************************/
AnnaBridge 167:e84263d55307 7 /*
AnnaBridge 167:e84263d55307 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge 167:e84263d55307 9 *
AnnaBridge 167:e84263d55307 10 * SPDX-License-Identifier: Apache-2.0
<> 149:156823d33999 11 *
AnnaBridge 167:e84263d55307 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 167:e84263d55307 13 * not use this file except in compliance with the License.
AnnaBridge 167:e84263d55307 14 * You may obtain a copy of the License at
AnnaBridge 167:e84263d55307 15 *
AnnaBridge 167:e84263d55307 16 * www.apache.org/licenses/LICENSE-2.0
<> 149:156823d33999 17 *
AnnaBridge 167:e84263d55307 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 167:e84263d55307 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 167:e84263d55307 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 167:e84263d55307 21 * See the License for the specific language governing permissions and
AnnaBridge 167:e84263d55307 22 * limitations under the License.
AnnaBridge 167:e84263d55307 23 */
<> 149:156823d33999 24
AnnaBridge 167:e84263d55307 25 #if defined ( __ICCARM__ )
AnnaBridge 167:e84263d55307 26 #pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge 167:e84263d55307 27 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 167:e84263d55307 28 #pragma clang system_header /* treat file as system include file */
<> 149:156823d33999 29 #endif
<> 149:156823d33999 30
<> 149:156823d33999 31 #ifndef __CORE_CM4_H_GENERIC
<> 149:156823d33999 32 #define __CORE_CM4_H_GENERIC
<> 149:156823d33999 33
AnnaBridge 167:e84263d55307 34 #include <stdint.h>
AnnaBridge 167:e84263d55307 35
<> 149:156823d33999 36 #ifdef __cplusplus
<> 149:156823d33999 37 extern "C" {
<> 149:156823d33999 38 #endif
<> 149:156823d33999 39
AnnaBridge 167:e84263d55307 40 /**
AnnaBridge 167:e84263d55307 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
<> 149:156823d33999 42 CMSIS violates the following MISRA-C:2004 rules:
<> 149:156823d33999 43
<> 149:156823d33999 44 \li Required Rule 8.5, object/function definition in header file.<br>
<> 149:156823d33999 45 Function definitions in header files are used to allow 'inlining'.
<> 149:156823d33999 46
<> 149:156823d33999 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
<> 149:156823d33999 48 Unions are used for effective representation of core registers.
<> 149:156823d33999 49
<> 149:156823d33999 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
<> 149:156823d33999 51 Function-like macros are used to allow more efficient code.
<> 149:156823d33999 52 */
<> 149:156823d33999 53
<> 149:156823d33999 54
<> 149:156823d33999 55 /*******************************************************************************
<> 149:156823d33999 56 * CMSIS definitions
<> 149:156823d33999 57 ******************************************************************************/
AnnaBridge 167:e84263d55307 58 /**
AnnaBridge 167:e84263d55307 59 \ingroup Cortex_M4
<> 149:156823d33999 60 @{
<> 149:156823d33999 61 */
<> 149:156823d33999 62
<> 149:156823d33999 63 /* CMSIS CM4 definitions */
AnnaBridge 167:e84263d55307 64 #define __CM4_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
AnnaBridge 167:e84263d55307 65 #define __CM4_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
AnnaBridge 167:e84263d55307 66 #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
AnnaBridge 167:e84263d55307 67 __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
<> 149:156823d33999 68
AnnaBridge 167:e84263d55307 69 #define __CORTEX_M (4U) /*!< Cortex-M Core */
<> 149:156823d33999 70
<> 149:156823d33999 71 /** __FPU_USED indicates whether an FPU is used or not.
<> 149:156823d33999 72 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
<> 149:156823d33999 73 */
<> 149:156823d33999 74 #if defined ( __CC_ARM )
<> 149:156823d33999 75 #if defined __TARGET_FPU_VFP
AnnaBridge 167:e84263d55307 76 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge 167:e84263d55307 77 #define __FPU_USED 1U
AnnaBridge 167:e84263d55307 78 #else
AnnaBridge 167:e84263d55307 79 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 167:e84263d55307 80 #define __FPU_USED 0U
AnnaBridge 167:e84263d55307 81 #endif
AnnaBridge 167:e84263d55307 82 #else
AnnaBridge 167:e84263d55307 83 #define __FPU_USED 0U
AnnaBridge 167:e84263d55307 84 #endif
AnnaBridge 167:e84263d55307 85
AnnaBridge 167:e84263d55307 86 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 167:e84263d55307 87 #if defined __ARM_PCS_VFP
AnnaBridge 167:e84263d55307 88 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge 167:e84263d55307 89 #define __FPU_USED 1U
<> 149:156823d33999 90 #else
<> 149:156823d33999 91 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 167:e84263d55307 92 #define __FPU_USED 0U
<> 149:156823d33999 93 #endif
<> 149:156823d33999 94 #else
AnnaBridge 167:e84263d55307 95 #define __FPU_USED 0U
<> 149:156823d33999 96 #endif
<> 149:156823d33999 97
<> 149:156823d33999 98 #elif defined ( __GNUC__ )
<> 149:156823d33999 99 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge 167:e84263d55307 100 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge 167:e84263d55307 101 #define __FPU_USED 1U
<> 149:156823d33999 102 #else
AnnaBridge 167:e84263d55307 103 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 167:e84263d55307 104 #define __FPU_USED 0U
<> 149:156823d33999 105 #endif
<> 149:156823d33999 106 #else
AnnaBridge 167:e84263d55307 107 #define __FPU_USED 0U
<> 149:156823d33999 108 #endif
<> 149:156823d33999 109
<> 149:156823d33999 110 #elif defined ( __ICCARM__ )
<> 149:156823d33999 111 #if defined __ARMVFP__
AnnaBridge 167:e84263d55307 112 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge 167:e84263d55307 113 #define __FPU_USED 1U
<> 149:156823d33999 114 #else
AnnaBridge 167:e84263d55307 115 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 167:e84263d55307 116 #define __FPU_USED 0U
<> 149:156823d33999 117 #endif
<> 149:156823d33999 118 #else
AnnaBridge 167:e84263d55307 119 #define __FPU_USED 0U
<> 149:156823d33999 120 #endif
<> 149:156823d33999 121
AnnaBridge 167:e84263d55307 122 #elif defined ( __TI_ARM__ )
<> 149:156823d33999 123 #if defined __TI_VFP_SUPPORT__
AnnaBridge 167:e84263d55307 124 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge 167:e84263d55307 125 #define __FPU_USED 1U
<> 149:156823d33999 126 #else
AnnaBridge 167:e84263d55307 127 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 167:e84263d55307 128 #define __FPU_USED 0U
<> 149:156823d33999 129 #endif
<> 149:156823d33999 130 #else
AnnaBridge 167:e84263d55307 131 #define __FPU_USED 0U
<> 149:156823d33999 132 #endif
<> 149:156823d33999 133
<> 149:156823d33999 134 #elif defined ( __TASKING__ )
<> 149:156823d33999 135 #if defined __FPU_VFP__
AnnaBridge 167:e84263d55307 136 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge 167:e84263d55307 137 #define __FPU_USED 1U
<> 149:156823d33999 138 #else
<> 149:156823d33999 139 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 167:e84263d55307 140 #define __FPU_USED 0U
<> 149:156823d33999 141 #endif
<> 149:156823d33999 142 #else
AnnaBridge 167:e84263d55307 143 #define __FPU_USED 0U
<> 149:156823d33999 144 #endif
<> 149:156823d33999 145
AnnaBridge 167:e84263d55307 146 #elif defined ( __CSMC__ )
AnnaBridge 167:e84263d55307 147 #if ( __CSMC__ & 0x400U)
AnnaBridge 167:e84263d55307 148 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge 167:e84263d55307 149 #define __FPU_USED 1U
<> 149:156823d33999 150 #else
<> 149:156823d33999 151 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 167:e84263d55307 152 #define __FPU_USED 0U
<> 149:156823d33999 153 #endif
<> 149:156823d33999 154 #else
AnnaBridge 167:e84263d55307 155 #define __FPU_USED 0U
<> 149:156823d33999 156 #endif
AnnaBridge 167:e84263d55307 157
<> 149:156823d33999 158 #endif
<> 149:156823d33999 159
AnnaBridge 167:e84263d55307 160 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge 167:e84263d55307 161
<> 149:156823d33999 162
<> 149:156823d33999 163 #ifdef __cplusplus
<> 149:156823d33999 164 }
<> 149:156823d33999 165 #endif
<> 149:156823d33999 166
<> 149:156823d33999 167 #endif /* __CORE_CM4_H_GENERIC */
<> 149:156823d33999 168
<> 149:156823d33999 169 #ifndef __CMSIS_GENERIC
<> 149:156823d33999 170
<> 149:156823d33999 171 #ifndef __CORE_CM4_H_DEPENDANT
<> 149:156823d33999 172 #define __CORE_CM4_H_DEPENDANT
<> 149:156823d33999 173
<> 149:156823d33999 174 #ifdef __cplusplus
<> 149:156823d33999 175 extern "C" {
<> 149:156823d33999 176 #endif
<> 149:156823d33999 177
<> 149:156823d33999 178 /* check device defines and use defaults */
<> 149:156823d33999 179 #if defined __CHECK_DEVICE_DEFINES
<> 149:156823d33999 180 #ifndef __CM4_REV
AnnaBridge 167:e84263d55307 181 #define __CM4_REV 0x0000U
<> 149:156823d33999 182 #warning "__CM4_REV not defined in device header file; using default!"
<> 149:156823d33999 183 #endif
<> 149:156823d33999 184
<> 149:156823d33999 185 #ifndef __FPU_PRESENT
AnnaBridge 167:e84263d55307 186 #define __FPU_PRESENT 0U
<> 149:156823d33999 187 #warning "__FPU_PRESENT not defined in device header file; using default!"
<> 149:156823d33999 188 #endif
<> 149:156823d33999 189
<> 149:156823d33999 190 #ifndef __MPU_PRESENT
AnnaBridge 167:e84263d55307 191 #define __MPU_PRESENT 0U
<> 149:156823d33999 192 #warning "__MPU_PRESENT not defined in device header file; using default!"
<> 149:156823d33999 193 #endif
<> 149:156823d33999 194
<> 149:156823d33999 195 #ifndef __NVIC_PRIO_BITS
AnnaBridge 167:e84263d55307 196 #define __NVIC_PRIO_BITS 3U
<> 149:156823d33999 197 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
<> 149:156823d33999 198 #endif
<> 149:156823d33999 199
<> 149:156823d33999 200 #ifndef __Vendor_SysTickConfig
AnnaBridge 167:e84263d55307 201 #define __Vendor_SysTickConfig 0U
<> 149:156823d33999 202 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
<> 149:156823d33999 203 #endif
<> 149:156823d33999 204 #endif
<> 149:156823d33999 205
<> 149:156823d33999 206 /* IO definitions (access restrictions to peripheral registers) */
<> 149:156823d33999 207 /**
<> 149:156823d33999 208 \defgroup CMSIS_glob_defs CMSIS Global Defines
<> 149:156823d33999 209
<> 149:156823d33999 210 <strong>IO Type Qualifiers</strong> are used
<> 149:156823d33999 211 \li to specify the access to peripheral variables.
<> 149:156823d33999 212 \li for automatic generation of peripheral register debug information.
<> 149:156823d33999 213 */
<> 149:156823d33999 214 #ifdef __cplusplus
AnnaBridge 167:e84263d55307 215 #define __I volatile /*!< Defines 'read only' permissions */
<> 149:156823d33999 216 #else
AnnaBridge 167:e84263d55307 217 #define __I volatile const /*!< Defines 'read only' permissions */
<> 149:156823d33999 218 #endif
AnnaBridge 167:e84263d55307 219 #define __O volatile /*!< Defines 'write only' permissions */
AnnaBridge 167:e84263d55307 220 #define __IO volatile /*!< Defines 'read / write' permissions */
<> 149:156823d33999 221
AnnaBridge 167:e84263d55307 222 /* following defines should be used for structure members */
AnnaBridge 167:e84263d55307 223 #define __IM volatile const /*! Defines 'read only' structure member permissions */
AnnaBridge 167:e84263d55307 224 #define __OM volatile /*! Defines 'write only' structure member permissions */
AnnaBridge 167:e84263d55307 225 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
<> 150:02e0a0aed4ec 226
<> 149:156823d33999 227 /*@} end of group Cortex_M4 */
<> 149:156823d33999 228
<> 149:156823d33999 229
<> 149:156823d33999 230
<> 149:156823d33999 231 /*******************************************************************************
<> 149:156823d33999 232 * Register Abstraction
<> 149:156823d33999 233 Core Register contain:
<> 149:156823d33999 234 - Core Register
<> 149:156823d33999 235 - Core NVIC Register
<> 149:156823d33999 236 - Core SCB Register
<> 149:156823d33999 237 - Core SysTick Register
<> 149:156823d33999 238 - Core Debug Register
<> 149:156823d33999 239 - Core MPU Register
<> 149:156823d33999 240 - Core FPU Register
<> 149:156823d33999 241 ******************************************************************************/
AnnaBridge 167:e84263d55307 242 /**
AnnaBridge 167:e84263d55307 243 \defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge 167:e84263d55307 244 \brief Type definitions and defines for Cortex-M processor based devices.
<> 149:156823d33999 245 */
<> 149:156823d33999 246
AnnaBridge 167:e84263d55307 247 /**
AnnaBridge 167:e84263d55307 248 \ingroup CMSIS_core_register
AnnaBridge 167:e84263d55307 249 \defgroup CMSIS_CORE Status and Control Registers
AnnaBridge 167:e84263d55307 250 \brief Core Register type definitions.
<> 149:156823d33999 251 @{
<> 149:156823d33999 252 */
<> 149:156823d33999 253
AnnaBridge 167:e84263d55307 254 /**
AnnaBridge 167:e84263d55307 255 \brief Union type to access the Application Program Status Register (APSR).
<> 149:156823d33999 256 */
<> 149:156823d33999 257 typedef union
<> 149:156823d33999 258 {
<> 149:156823d33999 259 struct
<> 149:156823d33999 260 {
AnnaBridge 167:e84263d55307 261 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
AnnaBridge 167:e84263d55307 262 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
AnnaBridge 167:e84263d55307 263 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
AnnaBridge 167:e84263d55307 264 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
AnnaBridge 167:e84263d55307 265 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 167:e84263d55307 266 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 167:e84263d55307 267 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 167:e84263d55307 268 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 167:e84263d55307 269 } b; /*!< Structure used for bit access */
AnnaBridge 167:e84263d55307 270 uint32_t w; /*!< Type used for word access */
<> 149:156823d33999 271 } APSR_Type;
<> 149:156823d33999 272
<> 149:156823d33999 273 /* APSR Register Definitions */
AnnaBridge 167:e84263d55307 274 #define APSR_N_Pos 31U /*!< APSR: N Position */
<> 149:156823d33999 275 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
<> 149:156823d33999 276
AnnaBridge 167:e84263d55307 277 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
<> 149:156823d33999 278 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
<> 149:156823d33999 279
AnnaBridge 167:e84263d55307 280 #define APSR_C_Pos 29U /*!< APSR: C Position */
<> 149:156823d33999 281 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
<> 149:156823d33999 282
AnnaBridge 167:e84263d55307 283 #define APSR_V_Pos 28U /*!< APSR: V Position */
<> 149:156823d33999 284 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
<> 149:156823d33999 285
AnnaBridge 167:e84263d55307 286 #define APSR_Q_Pos 27U /*!< APSR: Q Position */
<> 149:156823d33999 287 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
<> 149:156823d33999 288
AnnaBridge 167:e84263d55307 289 #define APSR_GE_Pos 16U /*!< APSR: GE Position */
<> 149:156823d33999 290 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
<> 149:156823d33999 291
<> 149:156823d33999 292
AnnaBridge 167:e84263d55307 293 /**
AnnaBridge 167:e84263d55307 294 \brief Union type to access the Interrupt Program Status Register (IPSR).
<> 149:156823d33999 295 */
<> 149:156823d33999 296 typedef union
<> 149:156823d33999 297 {
<> 149:156823d33999 298 struct
<> 149:156823d33999 299 {
AnnaBridge 167:e84263d55307 300 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 167:e84263d55307 301 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
AnnaBridge 167:e84263d55307 302 } b; /*!< Structure used for bit access */
AnnaBridge 167:e84263d55307 303 uint32_t w; /*!< Type used for word access */
<> 149:156823d33999 304 } IPSR_Type;
<> 149:156823d33999 305
<> 149:156823d33999 306 /* IPSR Register Definitions */
AnnaBridge 167:e84263d55307 307 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
<> 149:156823d33999 308 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
<> 149:156823d33999 309
<> 149:156823d33999 310
AnnaBridge 167:e84263d55307 311 /**
AnnaBridge 167:e84263d55307 312 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
<> 149:156823d33999 313 */
<> 149:156823d33999 314 typedef union
<> 149:156823d33999 315 {
<> 149:156823d33999 316 struct
<> 149:156823d33999 317 {
AnnaBridge 167:e84263d55307 318 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 167:e84263d55307 319 uint32_t _reserved0:1; /*!< bit: 9 Reserved */
AnnaBridge 167:e84263d55307 320 uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
AnnaBridge 167:e84263d55307 321 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
AnnaBridge 167:e84263d55307 322 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
AnnaBridge 167:e84263d55307 323 uint32_t T:1; /*!< bit: 24 Thumb bit */
AnnaBridge 167:e84263d55307 324 uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
AnnaBridge 167:e84263d55307 325 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
AnnaBridge 167:e84263d55307 326 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 167:e84263d55307 327 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 167:e84263d55307 328 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 167:e84263d55307 329 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 167:e84263d55307 330 } b; /*!< Structure used for bit access */
AnnaBridge 167:e84263d55307 331 uint32_t w; /*!< Type used for word access */
<> 149:156823d33999 332 } xPSR_Type;
<> 149:156823d33999 333
<> 149:156823d33999 334 /* xPSR Register Definitions */
AnnaBridge 167:e84263d55307 335 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
<> 149:156823d33999 336 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
<> 149:156823d33999 337
AnnaBridge 167:e84263d55307 338 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
<> 149:156823d33999 339 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
<> 149:156823d33999 340
AnnaBridge 167:e84263d55307 341 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
<> 149:156823d33999 342 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
<> 149:156823d33999 343
AnnaBridge 167:e84263d55307 344 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
<> 149:156823d33999 345 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
<> 149:156823d33999 346
AnnaBridge 167:e84263d55307 347 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
<> 149:156823d33999 348 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
<> 149:156823d33999 349
AnnaBridge 167:e84263d55307 350 #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
AnnaBridge 167:e84263d55307 351 #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
<> 149:156823d33999 352
AnnaBridge 167:e84263d55307 353 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
<> 149:156823d33999 354 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
<> 149:156823d33999 355
AnnaBridge 167:e84263d55307 356 #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
<> 149:156823d33999 357 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
<> 149:156823d33999 358
AnnaBridge 167:e84263d55307 359 #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
AnnaBridge 167:e84263d55307 360 #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
AnnaBridge 167:e84263d55307 361
AnnaBridge 167:e84263d55307 362 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
<> 149:156823d33999 363 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
<> 149:156823d33999 364
<> 149:156823d33999 365
AnnaBridge 167:e84263d55307 366 /**
AnnaBridge 167:e84263d55307 367 \brief Union type to access the Control Registers (CONTROL).
<> 149:156823d33999 368 */
<> 149:156823d33999 369 typedef union
<> 149:156823d33999 370 {
<> 149:156823d33999 371 struct
<> 149:156823d33999 372 {
<> 149:156823d33999 373 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
AnnaBridge 167:e84263d55307 374 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
AnnaBridge 167:e84263d55307 375 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
AnnaBridge 167:e84263d55307 376 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
AnnaBridge 167:e84263d55307 377 } b; /*!< Structure used for bit access */
AnnaBridge 167:e84263d55307 378 uint32_t w; /*!< Type used for word access */
<> 149:156823d33999 379 } CONTROL_Type;
<> 149:156823d33999 380
<> 149:156823d33999 381 /* CONTROL Register Definitions */
AnnaBridge 167:e84263d55307 382 #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
<> 149:156823d33999 383 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
<> 149:156823d33999 384
AnnaBridge 167:e84263d55307 385 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
<> 149:156823d33999 386 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
<> 149:156823d33999 387
AnnaBridge 167:e84263d55307 388 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
<> 149:156823d33999 389 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
<> 149:156823d33999 390
<> 149:156823d33999 391 /*@} end of group CMSIS_CORE */
<> 149:156823d33999 392
<> 149:156823d33999 393
AnnaBridge 167:e84263d55307 394 /**
AnnaBridge 167:e84263d55307 395 \ingroup CMSIS_core_register
AnnaBridge 167:e84263d55307 396 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge 167:e84263d55307 397 \brief Type definitions for the NVIC Registers
<> 149:156823d33999 398 @{
<> 149:156823d33999 399 */
<> 149:156823d33999 400
AnnaBridge 167:e84263d55307 401 /**
AnnaBridge 167:e84263d55307 402 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
<> 149:156823d33999 403 */
<> 149:156823d33999 404 typedef struct
<> 149:156823d33999 405 {
AnnaBridge 167:e84263d55307 406 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
AnnaBridge 167:e84263d55307 407 uint32_t RESERVED0[24U];
AnnaBridge 167:e84263d55307 408 __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
AnnaBridge 167:e84263d55307 409 uint32_t RSERVED1[24U];
AnnaBridge 167:e84263d55307 410 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
AnnaBridge 167:e84263d55307 411 uint32_t RESERVED2[24U];
AnnaBridge 167:e84263d55307 412 __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
AnnaBridge 167:e84263d55307 413 uint32_t RESERVED3[24U];
AnnaBridge 167:e84263d55307 414 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
AnnaBridge 167:e84263d55307 415 uint32_t RESERVED4[56U];
AnnaBridge 167:e84263d55307 416 __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
AnnaBridge 167:e84263d55307 417 uint32_t RESERVED5[644U];
AnnaBridge 167:e84263d55307 418 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
<> 149:156823d33999 419 } NVIC_Type;
<> 149:156823d33999 420
<> 149:156823d33999 421 /* Software Triggered Interrupt Register Definitions */
AnnaBridge 167:e84263d55307 422 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
<> 149:156823d33999 423 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
<> 149:156823d33999 424
<> 149:156823d33999 425 /*@} end of group CMSIS_NVIC */
<> 149:156823d33999 426
<> 149:156823d33999 427
AnnaBridge 167:e84263d55307 428 /**
AnnaBridge 167:e84263d55307 429 \ingroup CMSIS_core_register
AnnaBridge 167:e84263d55307 430 \defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge 167:e84263d55307 431 \brief Type definitions for the System Control Block Registers
<> 149:156823d33999 432 @{
<> 149:156823d33999 433 */
<> 149:156823d33999 434
AnnaBridge 167:e84263d55307 435 /**
AnnaBridge 167:e84263d55307 436 \brief Structure type to access the System Control Block (SCB).
<> 149:156823d33999 437 */
<> 149:156823d33999 438 typedef struct
<> 149:156823d33999 439 {
AnnaBridge 167:e84263d55307 440 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
AnnaBridge 167:e84263d55307 441 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
AnnaBridge 167:e84263d55307 442 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
AnnaBridge 167:e84263d55307 443 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
AnnaBridge 167:e84263d55307 444 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
AnnaBridge 167:e84263d55307 445 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
AnnaBridge 167:e84263d55307 446 __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
AnnaBridge 167:e84263d55307 447 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
AnnaBridge 167:e84263d55307 448 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
AnnaBridge 167:e84263d55307 449 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
AnnaBridge 167:e84263d55307 450 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
AnnaBridge 167:e84263d55307 451 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
AnnaBridge 167:e84263d55307 452 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
AnnaBridge 167:e84263d55307 453 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
AnnaBridge 167:e84263d55307 454 __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
AnnaBridge 167:e84263d55307 455 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
AnnaBridge 167:e84263d55307 456 __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
AnnaBridge 167:e84263d55307 457 __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
AnnaBridge 167:e84263d55307 458 __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
AnnaBridge 167:e84263d55307 459 uint32_t RESERVED0[5U];
AnnaBridge 167:e84263d55307 460 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
<> 149:156823d33999 461 } SCB_Type;
<> 149:156823d33999 462
<> 149:156823d33999 463 /* SCB CPUID Register Definitions */
AnnaBridge 167:e84263d55307 464 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
<> 149:156823d33999 465 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
<> 149:156823d33999 466
AnnaBridge 167:e84263d55307 467 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
<> 149:156823d33999 468 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
<> 149:156823d33999 469
AnnaBridge 167:e84263d55307 470 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
<> 149:156823d33999 471 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
<> 149:156823d33999 472
AnnaBridge 167:e84263d55307 473 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
<> 149:156823d33999 474 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
<> 149:156823d33999 475
AnnaBridge 167:e84263d55307 476 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
<> 149:156823d33999 477 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
<> 149:156823d33999 478
<> 149:156823d33999 479 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 167:e84263d55307 480 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
<> 149:156823d33999 481 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
<> 149:156823d33999 482
AnnaBridge 167:e84263d55307 483 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
<> 149:156823d33999 484 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
<> 149:156823d33999 485
AnnaBridge 167:e84263d55307 486 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
<> 149:156823d33999 487 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
<> 149:156823d33999 488
AnnaBridge 167:e84263d55307 489 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
<> 149:156823d33999 490 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
<> 149:156823d33999 491
AnnaBridge 167:e84263d55307 492 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
<> 149:156823d33999 493 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
<> 149:156823d33999 494
AnnaBridge 167:e84263d55307 495 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
<> 149:156823d33999 496 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
<> 149:156823d33999 497
AnnaBridge 167:e84263d55307 498 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
<> 149:156823d33999 499 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
<> 149:156823d33999 500
AnnaBridge 167:e84263d55307 501 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
<> 149:156823d33999 502 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
<> 149:156823d33999 503
AnnaBridge 167:e84263d55307 504 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
<> 149:156823d33999 505 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
<> 149:156823d33999 506
AnnaBridge 167:e84263d55307 507 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
<> 149:156823d33999 508 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
<> 149:156823d33999 509
<> 149:156823d33999 510 /* SCB Vector Table Offset Register Definitions */
AnnaBridge 167:e84263d55307 511 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
<> 149:156823d33999 512 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
<> 149:156823d33999 513
<> 149:156823d33999 514 /* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge 167:e84263d55307 515 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
<> 149:156823d33999 516 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
<> 149:156823d33999 517
AnnaBridge 167:e84263d55307 518 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
<> 149:156823d33999 519 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
<> 149:156823d33999 520
AnnaBridge 167:e84263d55307 521 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
<> 149:156823d33999 522 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
<> 149:156823d33999 523
AnnaBridge 167:e84263d55307 524 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
<> 149:156823d33999 525 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
<> 149:156823d33999 526
AnnaBridge 167:e84263d55307 527 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
<> 149:156823d33999 528 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
<> 149:156823d33999 529
AnnaBridge 167:e84263d55307 530 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
<> 149:156823d33999 531 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
<> 149:156823d33999 532
AnnaBridge 167:e84263d55307 533 #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
<> 149:156823d33999 534 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
<> 149:156823d33999 535
<> 149:156823d33999 536 /* SCB System Control Register Definitions */
AnnaBridge 167:e84263d55307 537 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
<> 149:156823d33999 538 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
<> 149:156823d33999 539
AnnaBridge 167:e84263d55307 540 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
<> 149:156823d33999 541 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
<> 149:156823d33999 542
AnnaBridge 167:e84263d55307 543 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
<> 149:156823d33999 544 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
<> 149:156823d33999 545
<> 149:156823d33999 546 /* SCB Configuration Control Register Definitions */
AnnaBridge 167:e84263d55307 547 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
<> 149:156823d33999 548 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
<> 149:156823d33999 549
AnnaBridge 167:e84263d55307 550 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
<> 149:156823d33999 551 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
<> 149:156823d33999 552
AnnaBridge 167:e84263d55307 553 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
<> 149:156823d33999 554 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
<> 149:156823d33999 555
AnnaBridge 167:e84263d55307 556 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
<> 149:156823d33999 557 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
<> 149:156823d33999 558
AnnaBridge 167:e84263d55307 559 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
<> 149:156823d33999 560 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
<> 149:156823d33999 561
AnnaBridge 167:e84263d55307 562 #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
<> 149:156823d33999 563 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
<> 149:156823d33999 564
<> 149:156823d33999 565 /* SCB System Handler Control and State Register Definitions */
AnnaBridge 167:e84263d55307 566 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
<> 149:156823d33999 567 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
<> 149:156823d33999 568
AnnaBridge 167:e84263d55307 569 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
<> 149:156823d33999 570 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
<> 149:156823d33999 571
AnnaBridge 167:e84263d55307 572 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
<> 149:156823d33999 573 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
<> 149:156823d33999 574
AnnaBridge 167:e84263d55307 575 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
<> 149:156823d33999 576 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
<> 149:156823d33999 577
AnnaBridge 167:e84263d55307 578 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
<> 149:156823d33999 579 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
<> 149:156823d33999 580
AnnaBridge 167:e84263d55307 581 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
<> 149:156823d33999 582 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
<> 149:156823d33999 583
AnnaBridge 167:e84263d55307 584 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
<> 149:156823d33999 585 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
<> 149:156823d33999 586
AnnaBridge 167:e84263d55307 587 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
<> 149:156823d33999 588 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
<> 149:156823d33999 589
AnnaBridge 167:e84263d55307 590 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
<> 149:156823d33999 591 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
<> 149:156823d33999 592
AnnaBridge 167:e84263d55307 593 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
<> 149:156823d33999 594 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
<> 149:156823d33999 595
AnnaBridge 167:e84263d55307 596 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
<> 149:156823d33999 597 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
<> 149:156823d33999 598
AnnaBridge 167:e84263d55307 599 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
<> 149:156823d33999 600 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
<> 149:156823d33999 601
AnnaBridge 167:e84263d55307 602 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
<> 149:156823d33999 603 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
<> 149:156823d33999 604
AnnaBridge 167:e84263d55307 605 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
<> 149:156823d33999 606 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
<> 149:156823d33999 607
AnnaBridge 167:e84263d55307 608 /* SCB Configurable Fault Status Register Definitions */
AnnaBridge 167:e84263d55307 609 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
<> 149:156823d33999 610 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
<> 149:156823d33999 611
AnnaBridge 167:e84263d55307 612 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
<> 149:156823d33999 613 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
<> 149:156823d33999 614
AnnaBridge 167:e84263d55307 615 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
<> 149:156823d33999 616 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
<> 149:156823d33999 617
AnnaBridge 167:e84263d55307 618 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge 167:e84263d55307 619 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
AnnaBridge 167:e84263d55307 620 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
AnnaBridge 167:e84263d55307 621
AnnaBridge 167:e84263d55307 622 #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
AnnaBridge 167:e84263d55307 623 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
AnnaBridge 167:e84263d55307 624
AnnaBridge 167:e84263d55307 625 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
AnnaBridge 167:e84263d55307 626 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
AnnaBridge 167:e84263d55307 627
AnnaBridge 167:e84263d55307 628 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
AnnaBridge 167:e84263d55307 629 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
AnnaBridge 167:e84263d55307 630
AnnaBridge 167:e84263d55307 631 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
AnnaBridge 167:e84263d55307 632 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
AnnaBridge 167:e84263d55307 633
AnnaBridge 167:e84263d55307 634 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
AnnaBridge 167:e84263d55307 635 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
AnnaBridge 167:e84263d55307 636
AnnaBridge 167:e84263d55307 637 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge 167:e84263d55307 638 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
AnnaBridge 167:e84263d55307 639 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
AnnaBridge 167:e84263d55307 640
AnnaBridge 167:e84263d55307 641 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
AnnaBridge 167:e84263d55307 642 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
AnnaBridge 167:e84263d55307 643
AnnaBridge 167:e84263d55307 644 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
AnnaBridge 167:e84263d55307 645 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
AnnaBridge 167:e84263d55307 646
AnnaBridge 167:e84263d55307 647 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
AnnaBridge 167:e84263d55307 648 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
AnnaBridge 167:e84263d55307 649
AnnaBridge 167:e84263d55307 650 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
AnnaBridge 167:e84263d55307 651 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
AnnaBridge 167:e84263d55307 652
AnnaBridge 167:e84263d55307 653 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
AnnaBridge 167:e84263d55307 654 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
AnnaBridge 167:e84263d55307 655
AnnaBridge 167:e84263d55307 656 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
AnnaBridge 167:e84263d55307 657 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
AnnaBridge 167:e84263d55307 658
AnnaBridge 167:e84263d55307 659 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge 167:e84263d55307 660 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
AnnaBridge 167:e84263d55307 661 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
AnnaBridge 167:e84263d55307 662
AnnaBridge 167:e84263d55307 663 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
AnnaBridge 167:e84263d55307 664 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
AnnaBridge 167:e84263d55307 665
AnnaBridge 167:e84263d55307 666 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
AnnaBridge 167:e84263d55307 667 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
AnnaBridge 167:e84263d55307 668
AnnaBridge 167:e84263d55307 669 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
AnnaBridge 167:e84263d55307 670 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
AnnaBridge 167:e84263d55307 671
AnnaBridge 167:e84263d55307 672 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
AnnaBridge 167:e84263d55307 673 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
AnnaBridge 167:e84263d55307 674
AnnaBridge 167:e84263d55307 675 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
AnnaBridge 167:e84263d55307 676 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
AnnaBridge 167:e84263d55307 677
AnnaBridge 167:e84263d55307 678 /* SCB Hard Fault Status Register Definitions */
AnnaBridge 167:e84263d55307 679 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
<> 149:156823d33999 680 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
<> 149:156823d33999 681
AnnaBridge 167:e84263d55307 682 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
<> 149:156823d33999 683 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
<> 149:156823d33999 684
AnnaBridge 167:e84263d55307 685 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
<> 149:156823d33999 686 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
<> 149:156823d33999 687
<> 149:156823d33999 688 /* SCB Debug Fault Status Register Definitions */
AnnaBridge 167:e84263d55307 689 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
<> 149:156823d33999 690 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
<> 149:156823d33999 691
AnnaBridge 167:e84263d55307 692 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
<> 149:156823d33999 693 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
<> 149:156823d33999 694
AnnaBridge 167:e84263d55307 695 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
<> 149:156823d33999 696 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
<> 149:156823d33999 697
AnnaBridge 167:e84263d55307 698 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
<> 149:156823d33999 699 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
<> 149:156823d33999 700
AnnaBridge 167:e84263d55307 701 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
<> 149:156823d33999 702 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
<> 149:156823d33999 703
<> 149:156823d33999 704 /*@} end of group CMSIS_SCB */
<> 149:156823d33999 705
<> 149:156823d33999 706
AnnaBridge 167:e84263d55307 707 /**
AnnaBridge 167:e84263d55307 708 \ingroup CMSIS_core_register
AnnaBridge 167:e84263d55307 709 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
AnnaBridge 167:e84263d55307 710 \brief Type definitions for the System Control and ID Register not in the SCB
<> 149:156823d33999 711 @{
<> 149:156823d33999 712 */
<> 149:156823d33999 713
AnnaBridge 167:e84263d55307 714 /**
AnnaBridge 167:e84263d55307 715 \brief Structure type to access the System Control and ID Register not in the SCB.
<> 149:156823d33999 716 */
<> 149:156823d33999 717 typedef struct
<> 149:156823d33999 718 {
AnnaBridge 167:e84263d55307 719 uint32_t RESERVED0[1U];
AnnaBridge 167:e84263d55307 720 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
AnnaBridge 167:e84263d55307 721 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
<> 149:156823d33999 722 } SCnSCB_Type;
<> 149:156823d33999 723
<> 149:156823d33999 724 /* Interrupt Controller Type Register Definitions */
AnnaBridge 167:e84263d55307 725 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
<> 149:156823d33999 726 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
<> 149:156823d33999 727
<> 149:156823d33999 728 /* Auxiliary Control Register Definitions */
AnnaBridge 167:e84263d55307 729 #define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
<> 149:156823d33999 730 #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
<> 149:156823d33999 731
AnnaBridge 167:e84263d55307 732 #define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
<> 149:156823d33999 733 #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
<> 149:156823d33999 734
AnnaBridge 167:e84263d55307 735 #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
<> 149:156823d33999 736 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
<> 149:156823d33999 737
AnnaBridge 167:e84263d55307 738 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
<> 149:156823d33999 739 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
<> 149:156823d33999 740
AnnaBridge 167:e84263d55307 741 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
<> 149:156823d33999 742 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
<> 149:156823d33999 743
<> 149:156823d33999 744 /*@} end of group CMSIS_SCnotSCB */
<> 149:156823d33999 745
<> 149:156823d33999 746
AnnaBridge 167:e84263d55307 747 /**
AnnaBridge 167:e84263d55307 748 \ingroup CMSIS_core_register
AnnaBridge 167:e84263d55307 749 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge 167:e84263d55307 750 \brief Type definitions for the System Timer Registers.
<> 149:156823d33999 751 @{
<> 149:156823d33999 752 */
<> 149:156823d33999 753
AnnaBridge 167:e84263d55307 754 /**
AnnaBridge 167:e84263d55307 755 \brief Structure type to access the System Timer (SysTick).
<> 149:156823d33999 756 */
<> 149:156823d33999 757 typedef struct
<> 149:156823d33999 758 {
AnnaBridge 167:e84263d55307 759 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
AnnaBridge 167:e84263d55307 760 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
AnnaBridge 167:e84263d55307 761 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
AnnaBridge 167:e84263d55307 762 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
<> 149:156823d33999 763 } SysTick_Type;
<> 149:156823d33999 764
<> 149:156823d33999 765 /* SysTick Control / Status Register Definitions */
AnnaBridge 167:e84263d55307 766 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
<> 149:156823d33999 767 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
<> 149:156823d33999 768
AnnaBridge 167:e84263d55307 769 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
<> 149:156823d33999 770 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
<> 149:156823d33999 771
AnnaBridge 167:e84263d55307 772 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
<> 149:156823d33999 773 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
<> 149:156823d33999 774
AnnaBridge 167:e84263d55307 775 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
<> 149:156823d33999 776 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
<> 149:156823d33999 777
<> 149:156823d33999 778 /* SysTick Reload Register Definitions */
AnnaBridge 167:e84263d55307 779 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
<> 149:156823d33999 780 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
<> 149:156823d33999 781
<> 149:156823d33999 782 /* SysTick Current Register Definitions */
AnnaBridge 167:e84263d55307 783 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
<> 149:156823d33999 784 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
<> 149:156823d33999 785
<> 149:156823d33999 786 /* SysTick Calibration Register Definitions */
AnnaBridge 167:e84263d55307 787 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
<> 149:156823d33999 788 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
<> 149:156823d33999 789
AnnaBridge 167:e84263d55307 790 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
<> 149:156823d33999 791 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
<> 149:156823d33999 792
AnnaBridge 167:e84263d55307 793 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
<> 149:156823d33999 794 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
<> 149:156823d33999 795
<> 149:156823d33999 796 /*@} end of group CMSIS_SysTick */
<> 149:156823d33999 797
<> 149:156823d33999 798
AnnaBridge 167:e84263d55307 799 /**
AnnaBridge 167:e84263d55307 800 \ingroup CMSIS_core_register
AnnaBridge 167:e84263d55307 801 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
AnnaBridge 167:e84263d55307 802 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
<> 149:156823d33999 803 @{
<> 149:156823d33999 804 */
<> 149:156823d33999 805
AnnaBridge 167:e84263d55307 806 /**
AnnaBridge 167:e84263d55307 807 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
<> 149:156823d33999 808 */
<> 149:156823d33999 809 typedef struct
<> 149:156823d33999 810 {
AnnaBridge 167:e84263d55307 811 __OM union
<> 149:156823d33999 812 {
AnnaBridge 167:e84263d55307 813 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
AnnaBridge 167:e84263d55307 814 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
AnnaBridge 167:e84263d55307 815 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
AnnaBridge 167:e84263d55307 816 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
AnnaBridge 167:e84263d55307 817 uint32_t RESERVED0[864U];
AnnaBridge 167:e84263d55307 818 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
AnnaBridge 167:e84263d55307 819 uint32_t RESERVED1[15U];
AnnaBridge 167:e84263d55307 820 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
AnnaBridge 167:e84263d55307 821 uint32_t RESERVED2[15U];
AnnaBridge 167:e84263d55307 822 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
AnnaBridge 167:e84263d55307 823 uint32_t RESERVED3[29U];
AnnaBridge 167:e84263d55307 824 __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
AnnaBridge 167:e84263d55307 825 __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
AnnaBridge 167:e84263d55307 826 __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
AnnaBridge 167:e84263d55307 827 uint32_t RESERVED4[43U];
AnnaBridge 167:e84263d55307 828 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
AnnaBridge 167:e84263d55307 829 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
AnnaBridge 167:e84263d55307 830 uint32_t RESERVED5[6U];
AnnaBridge 167:e84263d55307 831 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
AnnaBridge 167:e84263d55307 832 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
AnnaBridge 167:e84263d55307 833 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
AnnaBridge 167:e84263d55307 834 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
AnnaBridge 167:e84263d55307 835 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
AnnaBridge 167:e84263d55307 836 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
AnnaBridge 167:e84263d55307 837 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
AnnaBridge 167:e84263d55307 838 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
AnnaBridge 167:e84263d55307 839 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
AnnaBridge 167:e84263d55307 840 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
AnnaBridge 167:e84263d55307 841 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
AnnaBridge 167:e84263d55307 842 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
<> 149:156823d33999 843 } ITM_Type;
<> 149:156823d33999 844
<> 149:156823d33999 845 /* ITM Trace Privilege Register Definitions */
AnnaBridge 167:e84263d55307 846 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
<> 149:156823d33999 847 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
<> 149:156823d33999 848
<> 149:156823d33999 849 /* ITM Trace Control Register Definitions */
AnnaBridge 167:e84263d55307 850 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
<> 149:156823d33999 851 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
<> 149:156823d33999 852
AnnaBridge 167:e84263d55307 853 #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
<> 149:156823d33999 854 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
<> 149:156823d33999 855
AnnaBridge 167:e84263d55307 856 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
<> 149:156823d33999 857 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
<> 149:156823d33999 858
AnnaBridge 167:e84263d55307 859 #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
<> 149:156823d33999 860 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
<> 149:156823d33999 861
AnnaBridge 167:e84263d55307 862 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
<> 149:156823d33999 863 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
<> 149:156823d33999 864
AnnaBridge 167:e84263d55307 865 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
<> 149:156823d33999 866 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
<> 149:156823d33999 867
AnnaBridge 167:e84263d55307 868 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
<> 149:156823d33999 869 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
<> 149:156823d33999 870
AnnaBridge 167:e84263d55307 871 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
<> 149:156823d33999 872 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
<> 149:156823d33999 873
AnnaBridge 167:e84263d55307 874 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
<> 149:156823d33999 875 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
<> 149:156823d33999 876
<> 149:156823d33999 877 /* ITM Integration Write Register Definitions */
AnnaBridge 167:e84263d55307 878 #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
<> 149:156823d33999 879 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
<> 149:156823d33999 880
<> 149:156823d33999 881 /* ITM Integration Read Register Definitions */
AnnaBridge 167:e84263d55307 882 #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
<> 149:156823d33999 883 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
<> 149:156823d33999 884
<> 149:156823d33999 885 /* ITM Integration Mode Control Register Definitions */
AnnaBridge 167:e84263d55307 886 #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
<> 149:156823d33999 887 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
<> 149:156823d33999 888
<> 149:156823d33999 889 /* ITM Lock Status Register Definitions */
AnnaBridge 167:e84263d55307 890 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
<> 149:156823d33999 891 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
<> 149:156823d33999 892
AnnaBridge 167:e84263d55307 893 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
<> 149:156823d33999 894 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
<> 149:156823d33999 895
AnnaBridge 167:e84263d55307 896 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
<> 149:156823d33999 897 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
<> 149:156823d33999 898
<> 149:156823d33999 899 /*@}*/ /* end of group CMSIS_ITM */
<> 149:156823d33999 900
<> 149:156823d33999 901
AnnaBridge 167:e84263d55307 902 /**
AnnaBridge 167:e84263d55307 903 \ingroup CMSIS_core_register
AnnaBridge 167:e84263d55307 904 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
AnnaBridge 167:e84263d55307 905 \brief Type definitions for the Data Watchpoint and Trace (DWT)
<> 149:156823d33999 906 @{
<> 149:156823d33999 907 */
<> 149:156823d33999 908
AnnaBridge 167:e84263d55307 909 /**
AnnaBridge 167:e84263d55307 910 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
<> 149:156823d33999 911 */
<> 149:156823d33999 912 typedef struct
<> 149:156823d33999 913 {
AnnaBridge 167:e84263d55307 914 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
AnnaBridge 167:e84263d55307 915 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
AnnaBridge 167:e84263d55307 916 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
AnnaBridge 167:e84263d55307 917 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
AnnaBridge 167:e84263d55307 918 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
AnnaBridge 167:e84263d55307 919 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
AnnaBridge 167:e84263d55307 920 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
AnnaBridge 167:e84263d55307 921 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
AnnaBridge 167:e84263d55307 922 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
AnnaBridge 167:e84263d55307 923 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
AnnaBridge 167:e84263d55307 924 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
AnnaBridge 167:e84263d55307 925 uint32_t RESERVED0[1U];
AnnaBridge 167:e84263d55307 926 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
AnnaBridge 167:e84263d55307 927 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
AnnaBridge 167:e84263d55307 928 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
AnnaBridge 167:e84263d55307 929 uint32_t RESERVED1[1U];
AnnaBridge 167:e84263d55307 930 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
AnnaBridge 167:e84263d55307 931 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
AnnaBridge 167:e84263d55307 932 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
AnnaBridge 167:e84263d55307 933 uint32_t RESERVED2[1U];
AnnaBridge 167:e84263d55307 934 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
AnnaBridge 167:e84263d55307 935 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
AnnaBridge 167:e84263d55307 936 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
<> 149:156823d33999 937 } DWT_Type;
<> 149:156823d33999 938
<> 149:156823d33999 939 /* DWT Control Register Definitions */
AnnaBridge 167:e84263d55307 940 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
<> 149:156823d33999 941 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
<> 149:156823d33999 942
AnnaBridge 167:e84263d55307 943 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
<> 149:156823d33999 944 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
<> 149:156823d33999 945
AnnaBridge 167:e84263d55307 946 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
<> 149:156823d33999 947 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
<> 149:156823d33999 948
AnnaBridge 167:e84263d55307 949 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
<> 149:156823d33999 950 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
<> 149:156823d33999 951
AnnaBridge 167:e84263d55307 952 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
<> 149:156823d33999 953 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
<> 149:156823d33999 954
AnnaBridge 167:e84263d55307 955 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
<> 149:156823d33999 956 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
<> 149:156823d33999 957
AnnaBridge 167:e84263d55307 958 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
<> 149:156823d33999 959 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
<> 149:156823d33999 960
AnnaBridge 167:e84263d55307 961 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
<> 149:156823d33999 962 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
<> 149:156823d33999 963
AnnaBridge 167:e84263d55307 964 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
<> 149:156823d33999 965 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
<> 149:156823d33999 966
AnnaBridge 167:e84263d55307 967 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
<> 149:156823d33999 968 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
<> 149:156823d33999 969
AnnaBridge 167:e84263d55307 970 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
<> 149:156823d33999 971 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
<> 149:156823d33999 972
AnnaBridge 167:e84263d55307 973 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
<> 149:156823d33999 974 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
<> 149:156823d33999 975
AnnaBridge 167:e84263d55307 976 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
<> 149:156823d33999 977 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
<> 149:156823d33999 978
AnnaBridge 167:e84263d55307 979 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
<> 149:156823d33999 980 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
<> 149:156823d33999 981
AnnaBridge 167:e84263d55307 982 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
<> 149:156823d33999 983 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
<> 149:156823d33999 984
AnnaBridge 167:e84263d55307 985 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
<> 149:156823d33999 986 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
<> 149:156823d33999 987
AnnaBridge 167:e84263d55307 988 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
<> 149:156823d33999 989 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
<> 149:156823d33999 990
AnnaBridge 167:e84263d55307 991 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
<> 149:156823d33999 992 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
<> 149:156823d33999 993
<> 149:156823d33999 994 /* DWT CPI Count Register Definitions */
AnnaBridge 167:e84263d55307 995 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
<> 149:156823d33999 996 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
<> 149:156823d33999 997
<> 149:156823d33999 998 /* DWT Exception Overhead Count Register Definitions */
AnnaBridge 167:e84263d55307 999 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
<> 149:156823d33999 1000 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
<> 149:156823d33999 1001
<> 149:156823d33999 1002 /* DWT Sleep Count Register Definitions */
AnnaBridge 167:e84263d55307 1003 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
<> 149:156823d33999 1004 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
<> 149:156823d33999 1005
<> 149:156823d33999 1006 /* DWT LSU Count Register Definitions */
AnnaBridge 167:e84263d55307 1007 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
<> 149:156823d33999 1008 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
<> 149:156823d33999 1009
<> 149:156823d33999 1010 /* DWT Folded-instruction Count Register Definitions */
AnnaBridge 167:e84263d55307 1011 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
<> 149:156823d33999 1012 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
<> 149:156823d33999 1013
<> 149:156823d33999 1014 /* DWT Comparator Mask Register Definitions */
AnnaBridge 167:e84263d55307 1015 #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
<> 149:156823d33999 1016 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
<> 149:156823d33999 1017
<> 149:156823d33999 1018 /* DWT Comparator Function Register Definitions */
AnnaBridge 167:e84263d55307 1019 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
<> 149:156823d33999 1020 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
<> 149:156823d33999 1021
AnnaBridge 167:e84263d55307 1022 #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
<> 149:156823d33999 1023 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
<> 149:156823d33999 1024
AnnaBridge 167:e84263d55307 1025 #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
<> 149:156823d33999 1026 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
<> 149:156823d33999 1027
AnnaBridge 167:e84263d55307 1028 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
<> 149:156823d33999 1029 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
<> 149:156823d33999 1030
AnnaBridge 167:e84263d55307 1031 #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
<> 149:156823d33999 1032 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
<> 149:156823d33999 1033
AnnaBridge 167:e84263d55307 1034 #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
<> 149:156823d33999 1035 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
<> 149:156823d33999 1036
AnnaBridge 167:e84263d55307 1037 #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
<> 149:156823d33999 1038 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
<> 149:156823d33999 1039
AnnaBridge 167:e84263d55307 1040 #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
<> 149:156823d33999 1041 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
<> 149:156823d33999 1042
AnnaBridge 167:e84263d55307 1043 #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
<> 149:156823d33999 1044 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
<> 149:156823d33999 1045
<> 149:156823d33999 1046 /*@}*/ /* end of group CMSIS_DWT */
<> 149:156823d33999 1047
<> 149:156823d33999 1048
AnnaBridge 167:e84263d55307 1049 /**
AnnaBridge 167:e84263d55307 1050 \ingroup CMSIS_core_register
AnnaBridge 167:e84263d55307 1051 \defgroup CMSIS_TPI Trace Port Interface (TPI)
AnnaBridge 167:e84263d55307 1052 \brief Type definitions for the Trace Port Interface (TPI)
<> 149:156823d33999 1053 @{
<> 149:156823d33999 1054 */
<> 149:156823d33999 1055
AnnaBridge 167:e84263d55307 1056 /**
AnnaBridge 167:e84263d55307 1057 \brief Structure type to access the Trace Port Interface Register (TPI).
<> 149:156823d33999 1058 */
<> 149:156823d33999 1059 typedef struct
<> 149:156823d33999 1060 {
AnnaBridge 167:e84263d55307 1061 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
AnnaBridge 167:e84263d55307 1062 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
AnnaBridge 167:e84263d55307 1063 uint32_t RESERVED0[2U];
AnnaBridge 167:e84263d55307 1064 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
AnnaBridge 167:e84263d55307 1065 uint32_t RESERVED1[55U];
AnnaBridge 167:e84263d55307 1066 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
AnnaBridge 167:e84263d55307 1067 uint32_t RESERVED2[131U];
AnnaBridge 167:e84263d55307 1068 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
AnnaBridge 167:e84263d55307 1069 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
AnnaBridge 167:e84263d55307 1070 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
AnnaBridge 167:e84263d55307 1071 uint32_t RESERVED3[759U];
AnnaBridge 167:e84263d55307 1072 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
AnnaBridge 167:e84263d55307 1073 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
AnnaBridge 167:e84263d55307 1074 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
AnnaBridge 167:e84263d55307 1075 uint32_t RESERVED4[1U];
AnnaBridge 167:e84263d55307 1076 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
AnnaBridge 167:e84263d55307 1077 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
AnnaBridge 167:e84263d55307 1078 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
AnnaBridge 167:e84263d55307 1079 uint32_t RESERVED5[39U];
AnnaBridge 167:e84263d55307 1080 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
AnnaBridge 167:e84263d55307 1081 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
AnnaBridge 167:e84263d55307 1082 uint32_t RESERVED7[8U];
AnnaBridge 167:e84263d55307 1083 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
AnnaBridge 167:e84263d55307 1084 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
<> 149:156823d33999 1085 } TPI_Type;
<> 149:156823d33999 1086
<> 149:156823d33999 1087 /* TPI Asynchronous Clock Prescaler Register Definitions */
AnnaBridge 167:e84263d55307 1088 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
<> 149:156823d33999 1089 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
<> 149:156823d33999 1090
<> 149:156823d33999 1091 /* TPI Selected Pin Protocol Register Definitions */
AnnaBridge 167:e84263d55307 1092 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
<> 149:156823d33999 1093 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
<> 149:156823d33999 1094
<> 149:156823d33999 1095 /* TPI Formatter and Flush Status Register Definitions */
AnnaBridge 167:e84263d55307 1096 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
<> 149:156823d33999 1097 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
<> 149:156823d33999 1098
AnnaBridge 167:e84263d55307 1099 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
<> 149:156823d33999 1100 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
<> 149:156823d33999 1101
AnnaBridge 167:e84263d55307 1102 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
<> 149:156823d33999 1103 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
<> 149:156823d33999 1104
AnnaBridge 167:e84263d55307 1105 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
<> 149:156823d33999 1106 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
<> 149:156823d33999 1107
<> 149:156823d33999 1108 /* TPI Formatter and Flush Control Register Definitions */
AnnaBridge 167:e84263d55307 1109 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
<> 149:156823d33999 1110 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
<> 149:156823d33999 1111
AnnaBridge 167:e84263d55307 1112 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
<> 149:156823d33999 1113 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
<> 149:156823d33999 1114
<> 149:156823d33999 1115 /* TPI TRIGGER Register Definitions */
AnnaBridge 167:e84263d55307 1116 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
<> 149:156823d33999 1117 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
<> 149:156823d33999 1118
<> 149:156823d33999 1119 /* TPI Integration ETM Data Register Definitions (FIFO0) */
AnnaBridge 167:e84263d55307 1120 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
<> 149:156823d33999 1121 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
<> 149:156823d33999 1122
AnnaBridge 167:e84263d55307 1123 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
<> 149:156823d33999 1124 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
<> 149:156823d33999 1125
AnnaBridge 167:e84263d55307 1126 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
<> 149:156823d33999 1127 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
<> 149:156823d33999 1128
AnnaBridge 167:e84263d55307 1129 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
<> 149:156823d33999 1130 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
<> 149:156823d33999 1131
AnnaBridge 167:e84263d55307 1132 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
<> 149:156823d33999 1133 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
<> 149:156823d33999 1134
AnnaBridge 167:e84263d55307 1135 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
<> 149:156823d33999 1136 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
<> 149:156823d33999 1137
AnnaBridge 167:e84263d55307 1138 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
<> 149:156823d33999 1139 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
<> 149:156823d33999 1140
<> 149:156823d33999 1141 /* TPI ITATBCTR2 Register Definitions */
AnnaBridge 167:e84263d55307 1142 #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
<> 149:156823d33999 1143 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
<> 149:156823d33999 1144
<> 149:156823d33999 1145 /* TPI Integration ITM Data Register Definitions (FIFO1) */
AnnaBridge 167:e84263d55307 1146 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
<> 149:156823d33999 1147 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
<> 149:156823d33999 1148
AnnaBridge 167:e84263d55307 1149 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
<> 149:156823d33999 1150 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
<> 149:156823d33999 1151
AnnaBridge 167:e84263d55307 1152 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
<> 149:156823d33999 1153 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
<> 149:156823d33999 1154
AnnaBridge 167:e84263d55307 1155 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
<> 149:156823d33999 1156 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
<> 149:156823d33999 1157
AnnaBridge 167:e84263d55307 1158 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
<> 149:156823d33999 1159 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
<> 149:156823d33999 1160
AnnaBridge 167:e84263d55307 1161 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
<> 149:156823d33999 1162 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
<> 149:156823d33999 1163
AnnaBridge 167:e84263d55307 1164 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
<> 149:156823d33999 1165 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
<> 149:156823d33999 1166
<> 149:156823d33999 1167 /* TPI ITATBCTR0 Register Definitions */
AnnaBridge 167:e84263d55307 1168 #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
<> 149:156823d33999 1169 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
<> 149:156823d33999 1170
<> 149:156823d33999 1171 /* TPI Integration Mode Control Register Definitions */
AnnaBridge 167:e84263d55307 1172 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
<> 149:156823d33999 1173 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
<> 149:156823d33999 1174
<> 149:156823d33999 1175 /* TPI DEVID Register Definitions */
AnnaBridge 167:e84263d55307 1176 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
<> 149:156823d33999 1177 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
<> 149:156823d33999 1178
AnnaBridge 167:e84263d55307 1179 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
<> 149:156823d33999 1180 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
<> 149:156823d33999 1181
AnnaBridge 167:e84263d55307 1182 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
<> 149:156823d33999 1183 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
<> 149:156823d33999 1184
AnnaBridge 167:e84263d55307 1185 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
<> 149:156823d33999 1186 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
<> 149:156823d33999 1187
AnnaBridge 167:e84263d55307 1188 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
<> 149:156823d33999 1189 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
<> 149:156823d33999 1190
AnnaBridge 167:e84263d55307 1191 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
<> 149:156823d33999 1192 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
<> 149:156823d33999 1193
<> 149:156823d33999 1194 /* TPI DEVTYPE Register Definitions */
AnnaBridge 167:e84263d55307 1195 #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
<> 149:156823d33999 1196 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
<> 149:156823d33999 1197
AnnaBridge 167:e84263d55307 1198 #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
<> 149:156823d33999 1199 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
<> 149:156823d33999 1200
<> 149:156823d33999 1201 /*@}*/ /* end of group CMSIS_TPI */
<> 149:156823d33999 1202
<> 149:156823d33999 1203
AnnaBridge 167:e84263d55307 1204 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 167:e84263d55307 1205 /**
AnnaBridge 167:e84263d55307 1206 \ingroup CMSIS_core_register
AnnaBridge 167:e84263d55307 1207 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
AnnaBridge 167:e84263d55307 1208 \brief Type definitions for the Memory Protection Unit (MPU)
<> 149:156823d33999 1209 @{
<> 149:156823d33999 1210 */
<> 149:156823d33999 1211
AnnaBridge 167:e84263d55307 1212 /**
AnnaBridge 167:e84263d55307 1213 \brief Structure type to access the Memory Protection Unit (MPU).
<> 149:156823d33999 1214 */
<> 149:156823d33999 1215 typedef struct
<> 149:156823d33999 1216 {
AnnaBridge 167:e84263d55307 1217 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
AnnaBridge 167:e84263d55307 1218 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
AnnaBridge 167:e84263d55307 1219 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
AnnaBridge 167:e84263d55307 1220 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
AnnaBridge 167:e84263d55307 1221 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
AnnaBridge 167:e84263d55307 1222 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
AnnaBridge 167:e84263d55307 1223 __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
AnnaBridge 167:e84263d55307 1224 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
AnnaBridge 167:e84263d55307 1225 __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
AnnaBridge 167:e84263d55307 1226 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
AnnaBridge 167:e84263d55307 1227 __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
<> 149:156823d33999 1228 } MPU_Type;
<> 149:156823d33999 1229
AnnaBridge 167:e84263d55307 1230 /* MPU Type Register Definitions */
AnnaBridge 167:e84263d55307 1231 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
<> 149:156823d33999 1232 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
<> 149:156823d33999 1233
AnnaBridge 167:e84263d55307 1234 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
<> 149:156823d33999 1235 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
<> 149:156823d33999 1236
AnnaBridge 167:e84263d55307 1237 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
<> 149:156823d33999 1238 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
<> 149:156823d33999 1239
AnnaBridge 167:e84263d55307 1240 /* MPU Control Register Definitions */
AnnaBridge 167:e84263d55307 1241 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
<> 149:156823d33999 1242 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
<> 149:156823d33999 1243
AnnaBridge 167:e84263d55307 1244 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
<> 149:156823d33999 1245 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
<> 149:156823d33999 1246
AnnaBridge 167:e84263d55307 1247 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
<> 149:156823d33999 1248 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
<> 149:156823d33999 1249
AnnaBridge 167:e84263d55307 1250 /* MPU Region Number Register Definitions */
AnnaBridge 167:e84263d55307 1251 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
<> 149:156823d33999 1252 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
<> 149:156823d33999 1253
AnnaBridge 167:e84263d55307 1254 /* MPU Region Base Address Register Definitions */
AnnaBridge 167:e84263d55307 1255 #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
<> 149:156823d33999 1256 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
<> 149:156823d33999 1257
AnnaBridge 167:e84263d55307 1258 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
<> 149:156823d33999 1259 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
<> 149:156823d33999 1260
AnnaBridge 167:e84263d55307 1261 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
<> 149:156823d33999 1262 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
<> 149:156823d33999 1263
AnnaBridge 167:e84263d55307 1264 /* MPU Region Attribute and Size Register Definitions */
AnnaBridge 167:e84263d55307 1265 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
<> 149:156823d33999 1266 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
<> 149:156823d33999 1267
AnnaBridge 167:e84263d55307 1268 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
<> 149:156823d33999 1269 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
<> 149:156823d33999 1270
AnnaBridge 167:e84263d55307 1271 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
<> 149:156823d33999 1272 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
<> 149:156823d33999 1273
AnnaBridge 167:e84263d55307 1274 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
<> 149:156823d33999 1275 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
<> 149:156823d33999 1276
AnnaBridge 167:e84263d55307 1277 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
<> 149:156823d33999 1278 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
<> 149:156823d33999 1279
AnnaBridge 167:e84263d55307 1280 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
<> 149:156823d33999 1281 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
<> 149:156823d33999 1282
AnnaBridge 167:e84263d55307 1283 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
<> 149:156823d33999 1284 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
<> 149:156823d33999 1285
AnnaBridge 167:e84263d55307 1286 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
<> 149:156823d33999 1287 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
<> 149:156823d33999 1288
AnnaBridge 167:e84263d55307 1289 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
<> 149:156823d33999 1290 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
<> 149:156823d33999 1291
AnnaBridge 167:e84263d55307 1292 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
<> 149:156823d33999 1293 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
<> 149:156823d33999 1294
<> 149:156823d33999 1295 /*@} end of group CMSIS_MPU */
AnnaBridge 167:e84263d55307 1296 #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
<> 149:156823d33999 1297
<> 149:156823d33999 1298
AnnaBridge 167:e84263d55307 1299 /**
AnnaBridge 167:e84263d55307 1300 \ingroup CMSIS_core_register
AnnaBridge 167:e84263d55307 1301 \defgroup CMSIS_FPU Floating Point Unit (FPU)
AnnaBridge 167:e84263d55307 1302 \brief Type definitions for the Floating Point Unit (FPU)
<> 149:156823d33999 1303 @{
<> 149:156823d33999 1304 */
<> 149:156823d33999 1305
AnnaBridge 167:e84263d55307 1306 /**
AnnaBridge 167:e84263d55307 1307 \brief Structure type to access the Floating Point Unit (FPU).
<> 149:156823d33999 1308 */
<> 149:156823d33999 1309 typedef struct
<> 149:156823d33999 1310 {
AnnaBridge 167:e84263d55307 1311 uint32_t RESERVED0[1U];
AnnaBridge 167:e84263d55307 1312 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
AnnaBridge 167:e84263d55307 1313 __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
AnnaBridge 167:e84263d55307 1314 __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
AnnaBridge 167:e84263d55307 1315 __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
AnnaBridge 167:e84263d55307 1316 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
<> 149:156823d33999 1317 } FPU_Type;
<> 149:156823d33999 1318
AnnaBridge 167:e84263d55307 1319 /* Floating-Point Context Control Register Definitions */
AnnaBridge 167:e84263d55307 1320 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
<> 149:156823d33999 1321 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
<> 149:156823d33999 1322
AnnaBridge 167:e84263d55307 1323 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
<> 149:156823d33999 1324 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
<> 149:156823d33999 1325
AnnaBridge 167:e84263d55307 1326 #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
<> 149:156823d33999 1327 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
<> 149:156823d33999 1328
AnnaBridge 167:e84263d55307 1329 #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
<> 149:156823d33999 1330 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
<> 149:156823d33999 1331
AnnaBridge 167:e84263d55307 1332 #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
<> 149:156823d33999 1333 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
<> 149:156823d33999 1334
AnnaBridge 167:e84263d55307 1335 #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
<> 149:156823d33999 1336 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
<> 149:156823d33999 1337
AnnaBridge 167:e84263d55307 1338 #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
<> 149:156823d33999 1339 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
<> 149:156823d33999 1340
AnnaBridge 167:e84263d55307 1341 #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
<> 149:156823d33999 1342 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
<> 149:156823d33999 1343
AnnaBridge 167:e84263d55307 1344 #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
<> 149:156823d33999 1345 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
<> 149:156823d33999 1346
AnnaBridge 167:e84263d55307 1347 /* Floating-Point Context Address Register Definitions */
AnnaBridge 167:e84263d55307 1348 #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
<> 149:156823d33999 1349 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
<> 149:156823d33999 1350
AnnaBridge 167:e84263d55307 1351 /* Floating-Point Default Status Control Register Definitions */
AnnaBridge 167:e84263d55307 1352 #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
<> 149:156823d33999 1353 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
<> 149:156823d33999 1354
AnnaBridge 167:e84263d55307 1355 #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
<> 149:156823d33999 1356 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
<> 149:156823d33999 1357
AnnaBridge 167:e84263d55307 1358 #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
<> 149:156823d33999 1359 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
<> 149:156823d33999 1360
AnnaBridge 167:e84263d55307 1361 #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
<> 149:156823d33999 1362 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
<> 149:156823d33999 1363
AnnaBridge 167:e84263d55307 1364 /* Media and FP Feature Register 0 Definitions */
AnnaBridge 167:e84263d55307 1365 #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
<> 149:156823d33999 1366 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
<> 149:156823d33999 1367
AnnaBridge 167:e84263d55307 1368 #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
<> 149:156823d33999 1369 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
<> 149:156823d33999 1370
AnnaBridge 167:e84263d55307 1371 #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
<> 149:156823d33999 1372 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
<> 149:156823d33999 1373
AnnaBridge 167:e84263d55307 1374 #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
<> 149:156823d33999 1375 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
<> 149:156823d33999 1376
AnnaBridge 167:e84263d55307 1377 #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
<> 149:156823d33999 1378 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
<> 149:156823d33999 1379
AnnaBridge 167:e84263d55307 1380 #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
<> 149:156823d33999 1381 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
<> 149:156823d33999 1382
AnnaBridge 167:e84263d55307 1383 #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
<> 149:156823d33999 1384 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
<> 149:156823d33999 1385
AnnaBridge 167:e84263d55307 1386 #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
<> 149:156823d33999 1387 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
<> 149:156823d33999 1388
AnnaBridge 167:e84263d55307 1389 /* Media and FP Feature Register 1 Definitions */
AnnaBridge 167:e84263d55307 1390 #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
<> 149:156823d33999 1391 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
<> 149:156823d33999 1392
AnnaBridge 167:e84263d55307 1393 #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
<> 149:156823d33999 1394 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
<> 149:156823d33999 1395
AnnaBridge 167:e84263d55307 1396 #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
<> 149:156823d33999 1397 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
<> 149:156823d33999 1398
AnnaBridge 167:e84263d55307 1399 #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
<> 149:156823d33999 1400 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
<> 149:156823d33999 1401
<> 149:156823d33999 1402 /*@} end of group CMSIS_FPU */
<> 149:156823d33999 1403
<> 149:156823d33999 1404
AnnaBridge 167:e84263d55307 1405 /**
AnnaBridge 167:e84263d55307 1406 \ingroup CMSIS_core_register
AnnaBridge 167:e84263d55307 1407 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge 167:e84263d55307 1408 \brief Type definitions for the Core Debug Registers
<> 149:156823d33999 1409 @{
<> 149:156823d33999 1410 */
<> 149:156823d33999 1411
AnnaBridge 167:e84263d55307 1412 /**
AnnaBridge 167:e84263d55307 1413 \brief Structure type to access the Core Debug Register (CoreDebug).
<> 149:156823d33999 1414 */
<> 149:156823d33999 1415 typedef struct
<> 149:156823d33999 1416 {
AnnaBridge 167:e84263d55307 1417 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
AnnaBridge 167:e84263d55307 1418 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
AnnaBridge 167:e84263d55307 1419 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
AnnaBridge 167:e84263d55307 1420 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
<> 149:156823d33999 1421 } CoreDebug_Type;
<> 149:156823d33999 1422
AnnaBridge 167:e84263d55307 1423 /* Debug Halting Control and Status Register Definitions */
AnnaBridge 167:e84263d55307 1424 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
<> 149:156823d33999 1425 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
<> 149:156823d33999 1426
AnnaBridge 167:e84263d55307 1427 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
<> 149:156823d33999 1428 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
<> 149:156823d33999 1429
AnnaBridge 167:e84263d55307 1430 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
<> 149:156823d33999 1431 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
<> 149:156823d33999 1432
AnnaBridge 167:e84263d55307 1433 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
<> 149:156823d33999 1434 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
<> 149:156823d33999 1435
AnnaBridge 167:e84263d55307 1436 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
<> 149:156823d33999 1437 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
<> 149:156823d33999 1438
AnnaBridge 167:e84263d55307 1439 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
<> 149:156823d33999 1440 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
<> 149:156823d33999 1441
AnnaBridge 167:e84263d55307 1442 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
<> 149:156823d33999 1443 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
<> 149:156823d33999 1444
AnnaBridge 167:e84263d55307 1445 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
<> 149:156823d33999 1446 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
<> 149:156823d33999 1447
AnnaBridge 167:e84263d55307 1448 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
<> 149:156823d33999 1449 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
<> 149:156823d33999 1450
AnnaBridge 167:e84263d55307 1451 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
<> 149:156823d33999 1452 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
<> 149:156823d33999 1453
AnnaBridge 167:e84263d55307 1454 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
<> 149:156823d33999 1455 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
<> 149:156823d33999 1456
AnnaBridge 167:e84263d55307 1457 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
<> 149:156823d33999 1458 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
<> 149:156823d33999 1459
AnnaBridge 167:e84263d55307 1460 /* Debug Core Register Selector Register Definitions */
AnnaBridge 167:e84263d55307 1461 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
<> 149:156823d33999 1462 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
<> 149:156823d33999 1463
AnnaBridge 167:e84263d55307 1464 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
<> 149:156823d33999 1465 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
<> 149:156823d33999 1466
AnnaBridge 167:e84263d55307 1467 /* Debug Exception and Monitor Control Register Definitions */
AnnaBridge 167:e84263d55307 1468 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
<> 149:156823d33999 1469 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
<> 149:156823d33999 1470
AnnaBridge 167:e84263d55307 1471 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
<> 149:156823d33999 1472 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
<> 149:156823d33999 1473
AnnaBridge 167:e84263d55307 1474 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
<> 149:156823d33999 1475 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
<> 149:156823d33999 1476
AnnaBridge 167:e84263d55307 1477 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
<> 149:156823d33999 1478 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
<> 149:156823d33999 1479
AnnaBridge 167:e84263d55307 1480 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
<> 149:156823d33999 1481 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
<> 149:156823d33999 1482
AnnaBridge 167:e84263d55307 1483 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
<> 149:156823d33999 1484 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
<> 149:156823d33999 1485
AnnaBridge 167:e84263d55307 1486 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
<> 149:156823d33999 1487 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
<> 149:156823d33999 1488
AnnaBridge 167:e84263d55307 1489 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
<> 149:156823d33999 1490 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
<> 149:156823d33999 1491
AnnaBridge 167:e84263d55307 1492 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
<> 149:156823d33999 1493 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
<> 149:156823d33999 1494
AnnaBridge 167:e84263d55307 1495 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
<> 149:156823d33999 1496 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
<> 149:156823d33999 1497
AnnaBridge 167:e84263d55307 1498 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
<> 149:156823d33999 1499 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
<> 149:156823d33999 1500
AnnaBridge 167:e84263d55307 1501 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
<> 149:156823d33999 1502 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
<> 149:156823d33999 1503
AnnaBridge 167:e84263d55307 1504 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
<> 149:156823d33999 1505 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
<> 149:156823d33999 1506
<> 149:156823d33999 1507 /*@} end of group CMSIS_CoreDebug */
<> 149:156823d33999 1508
<> 149:156823d33999 1509
AnnaBridge 167:e84263d55307 1510 /**
AnnaBridge 167:e84263d55307 1511 \ingroup CMSIS_core_register
AnnaBridge 167:e84263d55307 1512 \defgroup CMSIS_core_bitfield Core register bit field macros
AnnaBridge 167:e84263d55307 1513 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
<> 149:156823d33999 1514 @{
<> 149:156823d33999 1515 */
<> 149:156823d33999 1516
AnnaBridge 167:e84263d55307 1517 /**
AnnaBridge 167:e84263d55307 1518 \brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge 167:e84263d55307 1519 \param[in] field Name of the register bit field.
AnnaBridge 167:e84263d55307 1520 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge 167:e84263d55307 1521 \return Masked and shifted value.
AnnaBridge 167:e84263d55307 1522 */
AnnaBridge 167:e84263d55307 1523 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge 167:e84263d55307 1524
AnnaBridge 167:e84263d55307 1525 /**
AnnaBridge 167:e84263d55307 1526 \brief Mask and shift a register value to extract a bit filed value.
AnnaBridge 167:e84263d55307 1527 \param[in] field Name of the register bit field.
AnnaBridge 167:e84263d55307 1528 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge 167:e84263d55307 1529 \return Masked and shifted bit field value.
AnnaBridge 167:e84263d55307 1530 */
AnnaBridge 167:e84263d55307 1531 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge 167:e84263d55307 1532
AnnaBridge 167:e84263d55307 1533 /*@} end of group CMSIS_core_bitfield */
AnnaBridge 167:e84263d55307 1534
AnnaBridge 167:e84263d55307 1535
AnnaBridge 167:e84263d55307 1536 /**
AnnaBridge 167:e84263d55307 1537 \ingroup CMSIS_core_register
AnnaBridge 167:e84263d55307 1538 \defgroup CMSIS_core_base Core Definitions
AnnaBridge 167:e84263d55307 1539 \brief Definitions for base addresses, unions, and structures.
AnnaBridge 167:e84263d55307 1540 @{
AnnaBridge 167:e84263d55307 1541 */
AnnaBridge 167:e84263d55307 1542
AnnaBridge 167:e84263d55307 1543 /* Memory mapping of Core Hardware */
AnnaBridge 167:e84263d55307 1544 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
AnnaBridge 167:e84263d55307 1545 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
AnnaBridge 167:e84263d55307 1546 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
AnnaBridge 167:e84263d55307 1547 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
AnnaBridge 167:e84263d55307 1548 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
AnnaBridge 167:e84263d55307 1549 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
AnnaBridge 167:e84263d55307 1550 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
AnnaBridge 167:e84263d55307 1551 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
<> 149:156823d33999 1552
<> 149:156823d33999 1553 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
AnnaBridge 167:e84263d55307 1554 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
AnnaBridge 167:e84263d55307 1555 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
AnnaBridge 167:e84263d55307 1556 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
AnnaBridge 167:e84263d55307 1557 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
AnnaBridge 167:e84263d55307 1558 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
AnnaBridge 167:e84263d55307 1559 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
AnnaBridge 167:e84263d55307 1560 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
<> 149:156823d33999 1561
AnnaBridge 167:e84263d55307 1562 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 167:e84263d55307 1563 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
AnnaBridge 167:e84263d55307 1564 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
<> 149:156823d33999 1565 #endif
<> 149:156823d33999 1566
AnnaBridge 167:e84263d55307 1567 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
AnnaBridge 167:e84263d55307 1568 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
<> 149:156823d33999 1569
<> 149:156823d33999 1570 /*@} */
<> 149:156823d33999 1571
<> 149:156823d33999 1572
<> 149:156823d33999 1573
<> 149:156823d33999 1574 /*******************************************************************************
<> 149:156823d33999 1575 * Hardware Abstraction Layer
<> 149:156823d33999 1576 Core Function Interface contains:
<> 149:156823d33999 1577 - Core NVIC Functions
<> 149:156823d33999 1578 - Core SysTick Functions
<> 149:156823d33999 1579 - Core Debug Functions
<> 149:156823d33999 1580 - Core Register Access Functions
<> 149:156823d33999 1581 ******************************************************************************/
AnnaBridge 167:e84263d55307 1582 /**
AnnaBridge 167:e84263d55307 1583 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
<> 149:156823d33999 1584 */
<> 149:156823d33999 1585
<> 149:156823d33999 1586
<> 149:156823d33999 1587
<> 149:156823d33999 1588 /* ########################## NVIC functions #################################### */
AnnaBridge 167:e84263d55307 1589 /**
AnnaBridge 167:e84263d55307 1590 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 167:e84263d55307 1591 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge 167:e84263d55307 1592 \brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge 167:e84263d55307 1593 @{
<> 149:156823d33999 1594 */
<> 149:156823d33999 1595
<> 149:156823d33999 1596 #ifdef CMSIS_NVIC_VIRTUAL
<> 149:156823d33999 1597 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
<> 149:156823d33999 1598 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
<> 149:156823d33999 1599 #endif
<> 149:156823d33999 1600 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
<> 149:156823d33999 1601 #else
<> 149:156823d33999 1602 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
<> 149:156823d33999 1603 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
<> 149:156823d33999 1604 #define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge 167:e84263d55307 1605 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
<> 149:156823d33999 1606 #define NVIC_DisableIRQ __NVIC_DisableIRQ
<> 149:156823d33999 1607 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
<> 149:156823d33999 1608 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
<> 149:156823d33999 1609 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
<> 149:156823d33999 1610 #define NVIC_GetActive __NVIC_GetActive
<> 149:156823d33999 1611 #define NVIC_SetPriority __NVIC_SetPriority
<> 149:156823d33999 1612 #define NVIC_GetPriority __NVIC_GetPriority
<> 149:156823d33999 1613 #define NVIC_SystemReset __NVIC_SystemReset
<> 149:156823d33999 1614 #endif /* CMSIS_NVIC_VIRTUAL */
<> 149:156823d33999 1615
<> 149:156823d33999 1616 #ifdef CMSIS_VECTAB_VIRTUAL
<> 149:156823d33999 1617 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 167:e84263d55307 1618 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
<> 149:156823d33999 1619 #endif
<> 149:156823d33999 1620 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
<> 149:156823d33999 1621 #else
<> 149:156823d33999 1622 #define NVIC_SetVector __NVIC_SetVector
<> 149:156823d33999 1623 #define NVIC_GetVector __NVIC_GetVector
AnnaBridge 167:e84263d55307 1624 #endif /* (CMSIS_VECTAB_VIRTUAL) */
AnnaBridge 167:e84263d55307 1625
AnnaBridge 167:e84263d55307 1626 #define NVIC_USER_IRQ_OFFSET 16
AnnaBridge 167:e84263d55307 1627
<> 149:156823d33999 1628
<> 149:156823d33999 1629
AnnaBridge 167:e84263d55307 1630 /**
AnnaBridge 167:e84263d55307 1631 \brief Set Priority Grouping
AnnaBridge 167:e84263d55307 1632 \details Sets the priority grouping field using the required unlock sequence.
AnnaBridge 167:e84263d55307 1633 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
AnnaBridge 167:e84263d55307 1634 Only values from 0..7 are used.
AnnaBridge 167:e84263d55307 1635 In case of a conflict between priority grouping and available
AnnaBridge 167:e84263d55307 1636 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge 167:e84263d55307 1637 \param [in] PriorityGroup Priority grouping field.
<> 149:156823d33999 1638 */
<> 149:156823d33999 1639 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
<> 149:156823d33999 1640 {
<> 149:156823d33999 1641 uint32_t reg_value;
<> 149:156823d33999 1642 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
<> 149:156823d33999 1643
<> 149:156823d33999 1644 reg_value = SCB->AIRCR; /* read old register configuration */
AnnaBridge 167:e84263d55307 1645 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
<> 149:156823d33999 1646 reg_value = (reg_value |
<> 149:156823d33999 1647 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
AnnaBridge 167:e84263d55307 1648 (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
<> 149:156823d33999 1649 SCB->AIRCR = reg_value;
<> 149:156823d33999 1650 }
<> 149:156823d33999 1651
<> 149:156823d33999 1652
AnnaBridge 167:e84263d55307 1653 /**
AnnaBridge 167:e84263d55307 1654 \brief Get Priority Grouping
AnnaBridge 167:e84263d55307 1655 \details Reads the priority grouping field from the NVIC Interrupt Controller.
AnnaBridge 167:e84263d55307 1656 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
<> 149:156823d33999 1657 */
<> 149:156823d33999 1658 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
<> 149:156823d33999 1659 {
<> 149:156823d33999 1660 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
<> 149:156823d33999 1661 }
<> 149:156823d33999 1662
<> 149:156823d33999 1663
AnnaBridge 167:e84263d55307 1664 /**
AnnaBridge 167:e84263d55307 1665 \brief Enable Interrupt
AnnaBridge 167:e84263d55307 1666 \details Enables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 167:e84263d55307 1667 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:e84263d55307 1668 \note IRQn must not be negative.
<> 149:156823d33999 1669 */
<> 149:156823d33999 1670 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
<> 149:156823d33999 1671 {
AnnaBridge 167:e84263d55307 1672 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:e84263d55307 1673 {
AnnaBridge 167:e84263d55307 1674 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 167:e84263d55307 1675 }
<> 149:156823d33999 1676 }
<> 149:156823d33999 1677
<> 149:156823d33999 1678
AnnaBridge 167:e84263d55307 1679 /**
AnnaBridge 167:e84263d55307 1680 \brief Get Interrupt Enable status
AnnaBridge 167:e84263d55307 1681 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
AnnaBridge 167:e84263d55307 1682 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:e84263d55307 1683 \return 0 Interrupt is not enabled.
AnnaBridge 167:e84263d55307 1684 \return 1 Interrupt is enabled.
AnnaBridge 167:e84263d55307 1685 \note IRQn must not be negative.
<> 149:156823d33999 1686 */
AnnaBridge 167:e84263d55307 1687 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
<> 149:156823d33999 1688 {
AnnaBridge 167:e84263d55307 1689 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:e84263d55307 1690 {
AnnaBridge 167:e84263d55307 1691 return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 167:e84263d55307 1692 }
AnnaBridge 167:e84263d55307 1693 else
AnnaBridge 167:e84263d55307 1694 {
AnnaBridge 167:e84263d55307 1695 return(0U);
AnnaBridge 167:e84263d55307 1696 }
<> 149:156823d33999 1697 }
<> 149:156823d33999 1698
<> 149:156823d33999 1699
AnnaBridge 167:e84263d55307 1700 /**
AnnaBridge 167:e84263d55307 1701 \brief Disable Interrupt
AnnaBridge 167:e84263d55307 1702 \details Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 167:e84263d55307 1703 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:e84263d55307 1704 \note IRQn must not be negative.
<> 149:156823d33999 1705 */
AnnaBridge 167:e84263d55307 1706 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
<> 149:156823d33999 1707 {
AnnaBridge 167:e84263d55307 1708 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:e84263d55307 1709 {
AnnaBridge 167:e84263d55307 1710 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 167:e84263d55307 1711 __DSB();
AnnaBridge 167:e84263d55307 1712 __ISB();
AnnaBridge 167:e84263d55307 1713 }
<> 149:156823d33999 1714 }
<> 149:156823d33999 1715
<> 149:156823d33999 1716
AnnaBridge 167:e84263d55307 1717 /**
AnnaBridge 167:e84263d55307 1718 \brief Get Pending Interrupt
AnnaBridge 167:e84263d55307 1719 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
AnnaBridge 167:e84263d55307 1720 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:e84263d55307 1721 \return 0 Interrupt status is not pending.
AnnaBridge 167:e84263d55307 1722 \return 1 Interrupt status is pending.
AnnaBridge 167:e84263d55307 1723 \note IRQn must not be negative.
<> 149:156823d33999 1724 */
AnnaBridge 167:e84263d55307 1725 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
<> 149:156823d33999 1726 {
AnnaBridge 167:e84263d55307 1727 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:e84263d55307 1728 {
AnnaBridge 167:e84263d55307 1729 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 167:e84263d55307 1730 }
AnnaBridge 167:e84263d55307 1731 else
AnnaBridge 167:e84263d55307 1732 {
AnnaBridge 167:e84263d55307 1733 return(0U);
AnnaBridge 167:e84263d55307 1734 }
<> 149:156823d33999 1735 }
<> 149:156823d33999 1736
<> 149:156823d33999 1737
AnnaBridge 167:e84263d55307 1738 /**
AnnaBridge 167:e84263d55307 1739 \brief Set Pending Interrupt
AnnaBridge 167:e84263d55307 1740 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 167:e84263d55307 1741 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:e84263d55307 1742 \note IRQn must not be negative.
<> 149:156823d33999 1743 */
AnnaBridge 167:e84263d55307 1744 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
<> 149:156823d33999 1745 {
AnnaBridge 167:e84263d55307 1746 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:e84263d55307 1747 {
AnnaBridge 167:e84263d55307 1748 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 149:156823d33999 1749 }
<> 149:156823d33999 1750 }
<> 149:156823d33999 1751
<> 149:156823d33999 1752
AnnaBridge 167:e84263d55307 1753 /**
AnnaBridge 167:e84263d55307 1754 \brief Clear Pending Interrupt
AnnaBridge 167:e84263d55307 1755 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 167:e84263d55307 1756 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:e84263d55307 1757 \note IRQn must not be negative.
AnnaBridge 167:e84263d55307 1758 */
AnnaBridge 167:e84263d55307 1759 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge 167:e84263d55307 1760 {
AnnaBridge 167:e84263d55307 1761 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:e84263d55307 1762 {
AnnaBridge 167:e84263d55307 1763 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 167:e84263d55307 1764 }
AnnaBridge 167:e84263d55307 1765 }
<> 149:156823d33999 1766
<> 149:156823d33999 1767
AnnaBridge 167:e84263d55307 1768 /**
AnnaBridge 167:e84263d55307 1769 \brief Get Active Interrupt
AnnaBridge 167:e84263d55307 1770 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
AnnaBridge 167:e84263d55307 1771 \param [in] IRQn Device specific interrupt number.
AnnaBridge 167:e84263d55307 1772 \return 0 Interrupt status is not active.
AnnaBridge 167:e84263d55307 1773 \return 1 Interrupt status is active.
AnnaBridge 167:e84263d55307 1774 \note IRQn must not be negative.
AnnaBridge 167:e84263d55307 1775 */
AnnaBridge 167:e84263d55307 1776 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
AnnaBridge 167:e84263d55307 1777 {
AnnaBridge 167:e84263d55307 1778 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:e84263d55307 1779 {
AnnaBridge 167:e84263d55307 1780 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 167:e84263d55307 1781 }
AnnaBridge 167:e84263d55307 1782 else
AnnaBridge 167:e84263d55307 1783 {
AnnaBridge 167:e84263d55307 1784 return(0U);
AnnaBridge 167:e84263d55307 1785 }
AnnaBridge 167:e84263d55307 1786 }
AnnaBridge 167:e84263d55307 1787
AnnaBridge 167:e84263d55307 1788
AnnaBridge 167:e84263d55307 1789 /**
AnnaBridge 167:e84263d55307 1790 \brief Set Interrupt Priority
AnnaBridge 167:e84263d55307 1791 \details Sets the priority of a device specific interrupt or a processor exception.
AnnaBridge 167:e84263d55307 1792 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 167:e84263d55307 1793 or negative to specify a processor exception.
AnnaBridge 167:e84263d55307 1794 \param [in] IRQn Interrupt number.
AnnaBridge 167:e84263d55307 1795 \param [in] priority Priority to set.
AnnaBridge 167:e84263d55307 1796 \note The priority cannot be set for every processor exception.
AnnaBridge 167:e84263d55307 1797 */
AnnaBridge 167:e84263d55307 1798 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge 167:e84263d55307 1799 {
AnnaBridge 167:e84263d55307 1800 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:e84263d55307 1801 {
AnnaBridge 167:e84263d55307 1802 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge 167:e84263d55307 1803 }
AnnaBridge 167:e84263d55307 1804 else
AnnaBridge 167:e84263d55307 1805 {
AnnaBridge 167:e84263d55307 1806 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge 167:e84263d55307 1807 }
AnnaBridge 167:e84263d55307 1808 }
AnnaBridge 167:e84263d55307 1809
AnnaBridge 167:e84263d55307 1810
AnnaBridge 167:e84263d55307 1811 /**
AnnaBridge 167:e84263d55307 1812 \brief Get Interrupt Priority
AnnaBridge 167:e84263d55307 1813 \details Reads the priority of a device specific interrupt or a processor exception.
AnnaBridge 167:e84263d55307 1814 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 167:e84263d55307 1815 or negative to specify a processor exception.
AnnaBridge 167:e84263d55307 1816 \param [in] IRQn Interrupt number.
AnnaBridge 167:e84263d55307 1817 \return Interrupt Priority.
AnnaBridge 167:e84263d55307 1818 Value is aligned automatically to the implemented priority bits of the microcontroller.
<> 149:156823d33999 1819 */
<> 149:156823d33999 1820 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
<> 149:156823d33999 1821 {
<> 149:156823d33999 1822
AnnaBridge 167:e84263d55307 1823 if ((int32_t)(IRQn) >= 0)
AnnaBridge 167:e84263d55307 1824 {
AnnaBridge 167:e84263d55307 1825 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
<> 149:156823d33999 1826 }
AnnaBridge 167:e84263d55307 1827 else
AnnaBridge 167:e84263d55307 1828 {
AnnaBridge 167:e84263d55307 1829 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
<> 149:156823d33999 1830 }
<> 149:156823d33999 1831 }
<> 149:156823d33999 1832
<> 149:156823d33999 1833
AnnaBridge 167:e84263d55307 1834 /**
AnnaBridge 167:e84263d55307 1835 \brief Encode Priority
AnnaBridge 167:e84263d55307 1836 \details Encodes the priority for an interrupt with the given priority group,
AnnaBridge 167:e84263d55307 1837 preemptive priority value, and subpriority value.
AnnaBridge 167:e84263d55307 1838 In case of a conflict between priority grouping and available
AnnaBridge 167:e84263d55307 1839 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge 167:e84263d55307 1840 \param [in] PriorityGroup Used priority group.
AnnaBridge 167:e84263d55307 1841 \param [in] PreemptPriority Preemptive priority value (starting from 0).
AnnaBridge 167:e84263d55307 1842 \param [in] SubPriority Subpriority value (starting from 0).
AnnaBridge 167:e84263d55307 1843 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
<> 149:156823d33999 1844 */
<> 149:156823d33999 1845 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
<> 149:156823d33999 1846 {
<> 149:156823d33999 1847 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
<> 149:156823d33999 1848 uint32_t PreemptPriorityBits;
<> 149:156823d33999 1849 uint32_t SubPriorityBits;
<> 149:156823d33999 1850
<> 149:156823d33999 1851 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
<> 149:156823d33999 1852 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
<> 149:156823d33999 1853
<> 149:156823d33999 1854 return (
<> 149:156823d33999 1855 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
<> 149:156823d33999 1856 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
<> 149:156823d33999 1857 );
<> 149:156823d33999 1858 }
<> 149:156823d33999 1859
<> 149:156823d33999 1860
AnnaBridge 167:e84263d55307 1861 /**
AnnaBridge 167:e84263d55307 1862 \brief Decode Priority
AnnaBridge 167:e84263d55307 1863 \details Decodes an interrupt priority value with a given priority group to
AnnaBridge 167:e84263d55307 1864 preemptive priority value and subpriority value.
AnnaBridge 167:e84263d55307 1865 In case of a conflict between priority grouping and available
AnnaBridge 167:e84263d55307 1866 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
AnnaBridge 167:e84263d55307 1867 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
AnnaBridge 167:e84263d55307 1868 \param [in] PriorityGroup Used priority group.
AnnaBridge 167:e84263d55307 1869 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
AnnaBridge 167:e84263d55307 1870 \param [out] pSubPriority Subpriority value (starting from 0).
<> 149:156823d33999 1871 */
AnnaBridge 167:e84263d55307 1872 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
<> 149:156823d33999 1873 {
<> 149:156823d33999 1874 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
<> 149:156823d33999 1875 uint32_t PreemptPriorityBits;
<> 149:156823d33999 1876 uint32_t SubPriorityBits;
<> 149:156823d33999 1877
<> 149:156823d33999 1878 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
<> 149:156823d33999 1879 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
<> 149:156823d33999 1880
<> 149:156823d33999 1881 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
<> 149:156823d33999 1882 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
<> 149:156823d33999 1883 }
<> 149:156823d33999 1884
<> 149:156823d33999 1885
AnnaBridge 167:e84263d55307 1886 /**
AnnaBridge 167:e84263d55307 1887 \brief Set Interrupt Vector
AnnaBridge 167:e84263d55307 1888 \details Sets an interrupt vector in SRAM based interrupt vector table.
AnnaBridge 167:e84263d55307 1889 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 167:e84263d55307 1890 or negative to specify a processor exception.
AnnaBridge 167:e84263d55307 1891 VTOR must been relocated to SRAM before.
AnnaBridge 167:e84263d55307 1892 \param [in] IRQn Interrupt number
AnnaBridge 167:e84263d55307 1893 \param [in] vector Address of interrupt handler function
AnnaBridge 167:e84263d55307 1894 */
AnnaBridge 167:e84263d55307 1895 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
AnnaBridge 167:e84263d55307 1896 {
AnnaBridge 167:e84263d55307 1897 uint32_t *vectors = (uint32_t *)SCB->VTOR;
AnnaBridge 167:e84263d55307 1898 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
AnnaBridge 167:e84263d55307 1899 }
AnnaBridge 167:e84263d55307 1900
<> 149:156823d33999 1901
AnnaBridge 167:e84263d55307 1902 /**
AnnaBridge 167:e84263d55307 1903 \brief Get Interrupt Vector
AnnaBridge 167:e84263d55307 1904 \details Reads an interrupt vector from interrupt vector table.
AnnaBridge 167:e84263d55307 1905 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 167:e84263d55307 1906 or negative to specify a processor exception.
AnnaBridge 167:e84263d55307 1907 \param [in] IRQn Interrupt number.
AnnaBridge 167:e84263d55307 1908 \return Address of interrupt handler function
AnnaBridge 167:e84263d55307 1909 */
AnnaBridge 167:e84263d55307 1910 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
AnnaBridge 167:e84263d55307 1911 {
AnnaBridge 167:e84263d55307 1912 uint32_t *vectors = (uint32_t *)SCB->VTOR;
AnnaBridge 167:e84263d55307 1913 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
AnnaBridge 167:e84263d55307 1914 }
AnnaBridge 167:e84263d55307 1915
AnnaBridge 167:e84263d55307 1916
AnnaBridge 167:e84263d55307 1917 /**
AnnaBridge 167:e84263d55307 1918 \brief System Reset
AnnaBridge 167:e84263d55307 1919 \details Initiates a system reset request to reset the MCU.
<> 149:156823d33999 1920 */
<> 149:156823d33999 1921 __STATIC_INLINE void __NVIC_SystemReset(void)
<> 149:156823d33999 1922 {
<> 149:156823d33999 1923 __DSB(); /* Ensure all outstanding memory accesses included
<> 149:156823d33999 1924 buffered write are completed before reset */
<> 149:156823d33999 1925 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
<> 149:156823d33999 1926 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
<> 149:156823d33999 1927 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
<> 149:156823d33999 1928 __DSB(); /* Ensure completion of memory access */
AnnaBridge 167:e84263d55307 1929
AnnaBridge 167:e84263d55307 1930 for(;;) /* wait until reset */
AnnaBridge 167:e84263d55307 1931 {
AnnaBridge 167:e84263d55307 1932 __NOP();
AnnaBridge 167:e84263d55307 1933 }
<> 149:156823d33999 1934 }
<> 149:156823d33999 1935
<> 149:156823d33999 1936 /*@} end of CMSIS_Core_NVICFunctions */
<> 149:156823d33999 1937
<> 149:156823d33999 1938
AnnaBridge 167:e84263d55307 1939 /* ########################## FPU functions #################################### */
AnnaBridge 167:e84263d55307 1940 /**
AnnaBridge 167:e84263d55307 1941 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 167:e84263d55307 1942 \defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge 167:e84263d55307 1943 \brief Function that provides FPU type.
<> 149:156823d33999 1944 @{
<> 149:156823d33999 1945 */
<> 149:156823d33999 1946
AnnaBridge 167:e84263d55307 1947 /**
AnnaBridge 167:e84263d55307 1948 \brief get FPU type
AnnaBridge 167:e84263d55307 1949 \details returns the FPU type
AnnaBridge 167:e84263d55307 1950 \returns
AnnaBridge 167:e84263d55307 1951 - \b 0: No FPU
AnnaBridge 167:e84263d55307 1952 - \b 1: Single precision FPU
AnnaBridge 167:e84263d55307 1953 - \b 2: Double + Single precision FPU
AnnaBridge 167:e84263d55307 1954 */
AnnaBridge 167:e84263d55307 1955 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
AnnaBridge 167:e84263d55307 1956 {
AnnaBridge 167:e84263d55307 1957 uint32_t mvfr0;
<> 149:156823d33999 1958
AnnaBridge 167:e84263d55307 1959 mvfr0 = FPU->MVFR0;
AnnaBridge 167:e84263d55307 1960 if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
AnnaBridge 167:e84263d55307 1961 {
AnnaBridge 167:e84263d55307 1962 return 1U; /* Single precision FPU */
AnnaBridge 167:e84263d55307 1963 }
AnnaBridge 167:e84263d55307 1964 else
AnnaBridge 167:e84263d55307 1965 {
AnnaBridge 167:e84263d55307 1966 return 0U; /* No FPU */
AnnaBridge 167:e84263d55307 1967 }
AnnaBridge 167:e84263d55307 1968 }
<> 149:156823d33999 1969
<> 149:156823d33999 1970
AnnaBridge 167:e84263d55307 1971 /*@} end of CMSIS_Core_FpuFunctions */
AnnaBridge 167:e84263d55307 1972
AnnaBridge 167:e84263d55307 1973
<> 149:156823d33999 1974
AnnaBridge 167:e84263d55307 1975 /* ################################## SysTick function ############################################ */
AnnaBridge 167:e84263d55307 1976 /**
AnnaBridge 167:e84263d55307 1977 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 167:e84263d55307 1978 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge 167:e84263d55307 1979 \brief Functions that configure the System.
AnnaBridge 167:e84263d55307 1980 @{
AnnaBridge 167:e84263d55307 1981 */
<> 149:156823d33999 1982
AnnaBridge 167:e84263d55307 1983 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
<> 149:156823d33999 1984
AnnaBridge 167:e84263d55307 1985 /**
AnnaBridge 167:e84263d55307 1986 \brief System Tick Configuration
AnnaBridge 167:e84263d55307 1987 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge 167:e84263d55307 1988 Counter is in free running mode to generate periodic interrupts.
AnnaBridge 167:e84263d55307 1989 \param [in] ticks Number of ticks between two interrupts.
AnnaBridge 167:e84263d55307 1990 \return 0 Function succeeded.
AnnaBridge 167:e84263d55307 1991 \return 1 Function failed.
AnnaBridge 167:e84263d55307 1992 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge 167:e84263d55307 1993 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge 167:e84263d55307 1994 must contain a vendor-specific implementation of this function.
<> 149:156823d33999 1995 */
<> 149:156823d33999 1996 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
<> 149:156823d33999 1997 {
AnnaBridge 167:e84263d55307 1998 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge 167:e84263d55307 1999 {
AnnaBridge 167:e84263d55307 2000 return (1UL); /* Reload value impossible */
AnnaBridge 167:e84263d55307 2001 }
<> 149:156823d33999 2002
<> 149:156823d33999 2003 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
<> 149:156823d33999 2004 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
<> 149:156823d33999 2005 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
<> 149:156823d33999 2006 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
<> 149:156823d33999 2007 SysTick_CTRL_TICKINT_Msk |
<> 149:156823d33999 2008 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
<> 149:156823d33999 2009 return (0UL); /* Function successful */
<> 149:156823d33999 2010 }
<> 149:156823d33999 2011
<> 149:156823d33999 2012 #endif
<> 149:156823d33999 2013
<> 149:156823d33999 2014 /*@} end of CMSIS_Core_SysTickFunctions */
<> 149:156823d33999 2015
<> 149:156823d33999 2016
<> 149:156823d33999 2017
<> 149:156823d33999 2018 /* ##################################### Debug In/Output function ########################################### */
AnnaBridge 167:e84263d55307 2019 /**
AnnaBridge 167:e84263d55307 2020 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 167:e84263d55307 2021 \defgroup CMSIS_core_DebugFunctions ITM Functions
AnnaBridge 167:e84263d55307 2022 \brief Functions that access the ITM debug interface.
<> 149:156823d33999 2023 @{
<> 149:156823d33999 2024 */
<> 149:156823d33999 2025
AnnaBridge 167:e84263d55307 2026 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
AnnaBridge 167:e84263d55307 2027 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
<> 149:156823d33999 2028
<> 149:156823d33999 2029
AnnaBridge 167:e84263d55307 2030 /**
AnnaBridge 167:e84263d55307 2031 \brief ITM Send Character
AnnaBridge 167:e84263d55307 2032 \details Transmits a character via the ITM channel 0, and
AnnaBridge 167:e84263d55307 2033 \li Just returns when no debugger is connected that has booked the output.
AnnaBridge 167:e84263d55307 2034 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
AnnaBridge 167:e84263d55307 2035 \param [in] ch Character to transmit.
AnnaBridge 167:e84263d55307 2036 \returns Character to transmit.
<> 149:156823d33999 2037 */
<> 149:156823d33999 2038 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
<> 149:156823d33999 2039 {
<> 149:156823d33999 2040 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
<> 149:156823d33999 2041 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
<> 149:156823d33999 2042 {
AnnaBridge 167:e84263d55307 2043 while (ITM->PORT[0U].u32 == 0UL)
AnnaBridge 167:e84263d55307 2044 {
AnnaBridge 167:e84263d55307 2045 __NOP();
AnnaBridge 167:e84263d55307 2046 }
AnnaBridge 167:e84263d55307 2047 ITM->PORT[0U].u8 = (uint8_t)ch;
<> 149:156823d33999 2048 }
<> 149:156823d33999 2049 return (ch);
<> 149:156823d33999 2050 }
<> 149:156823d33999 2051
<> 149:156823d33999 2052
AnnaBridge 167:e84263d55307 2053 /**
AnnaBridge 167:e84263d55307 2054 \brief ITM Receive Character
AnnaBridge 167:e84263d55307 2055 \details Inputs a character via the external variable \ref ITM_RxBuffer.
AnnaBridge 167:e84263d55307 2056 \return Received character.
AnnaBridge 167:e84263d55307 2057 \return -1 No character pending.
<> 149:156823d33999 2058 */
AnnaBridge 167:e84263d55307 2059 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
AnnaBridge 167:e84263d55307 2060 {
<> 149:156823d33999 2061 int32_t ch = -1; /* no character available */
<> 149:156823d33999 2062
AnnaBridge 167:e84263d55307 2063 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
AnnaBridge 167:e84263d55307 2064 {
<> 149:156823d33999 2065 ch = ITM_RxBuffer;
<> 149:156823d33999 2066 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
<> 149:156823d33999 2067 }
<> 149:156823d33999 2068
<> 149:156823d33999 2069 return (ch);
<> 149:156823d33999 2070 }
<> 149:156823d33999 2071
<> 149:156823d33999 2072
AnnaBridge 167:e84263d55307 2073 /**
AnnaBridge 167:e84263d55307 2074 \brief ITM Check Character
AnnaBridge 167:e84263d55307 2075 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
AnnaBridge 167:e84263d55307 2076 \return 0 No character available.
AnnaBridge 167:e84263d55307 2077 \return 1 Character available.
<> 149:156823d33999 2078 */
AnnaBridge 167:e84263d55307 2079 __STATIC_INLINE int32_t ITM_CheckChar (void)
AnnaBridge 167:e84263d55307 2080 {
<> 149:156823d33999 2081
AnnaBridge 167:e84263d55307 2082 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
AnnaBridge 167:e84263d55307 2083 {
AnnaBridge 167:e84263d55307 2084 return (0); /* no character available */
AnnaBridge 167:e84263d55307 2085 }
AnnaBridge 167:e84263d55307 2086 else
AnnaBridge 167:e84263d55307 2087 {
AnnaBridge 167:e84263d55307 2088 return (1); /* character available */
<> 149:156823d33999 2089 }
<> 149:156823d33999 2090 }
<> 149:156823d33999 2091
<> 149:156823d33999 2092 /*@} end of CMSIS_core_DebugFunctions */
<> 149:156823d33999 2093
<> 149:156823d33999 2094
<> 149:156823d33999 2095
<> 149:156823d33999 2096
<> 149:156823d33999 2097 #ifdef __cplusplus
<> 149:156823d33999 2098 }
<> 149:156823d33999 2099 #endif
<> 149:156823d33999 2100
<> 149:156823d33999 2101 #endif /* __CORE_CM4_H_DEPENDANT */
<> 149:156823d33999 2102
<> 149:156823d33999 2103 #endif /* __CMSIS_GENERIC */