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Some code for a eavesdropper device.
Dependencies: FastIO FastPWM mbed
main.cpp@0:050184ab5c0d, 2014-09-02 (annotated)
- Committer:
- Josvth
- Date:
- Tue Sep 02 08:20:13 2014 +0000
- Revision:
- 0:050184ab5c0d
Commit!
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Josvth | 0:050184ab5c0d | 1 | #include "mbed.h" |
Josvth | 0:050184ab5c0d | 2 | #include "FastIO.h" |
Josvth | 0:050184ab5c0d | 3 | #include "FastPWM.h" |
Josvth | 0:050184ab5c0d | 4 | |
Josvth | 0:050184ab5c0d | 5 | FastOut<LED1> led; |
Josvth | 0:050184ab5c0d | 6 | |
Josvth | 0:050184ab5c0d | 7 | //Pin 29 and 30 are connected to pin 21 |
Josvth | 0:050184ab5c0d | 8 | FastIn<p29> CAP_2_1_input; |
Josvth | 0:050184ab5c0d | 9 | FastIn<p30> CAP_2_0_input; |
Josvth | 0:050184ab5c0d | 10 | FastPWM pwm(p21); |
Josvth | 0:050184ab5c0d | 11 | |
Josvth | 0:050184ab5c0d | 12 | |
Josvth | 0:050184ab5c0d | 13 | Serial pc(USBTX, USBRX); // tx, rx |
Josvth | 0:050184ab5c0d | 14 | |
Josvth | 0:050184ab5c0d | 15 | #define TIM2CR0 LPC_TIM2->CR0 |
Josvth | 0:050184ab5c0d | 16 | #define TIM2CR1 LPC_TIM2->CR1 |
Josvth | 0:050184ab5c0d | 17 | |
Josvth | 0:050184ab5c0d | 18 | //void _cap_2_1_falling() { |
Josvth | 0:050184ab5c0d | 19 | // pc.printf("Interrupt: %X\n", LPC_TIM2->IR); |
Josvth | 0:050184ab5c0d | 20 | //led = 1; |
Josvth | 0:050184ab5c0d | 21 | //} |
Josvth | 0:050184ab5c0d | 22 | |
Josvth | 0:050184ab5c0d | 23 | int main() |
Josvth | 0:050184ab5c0d | 24 | { |
Josvth | 0:050184ab5c0d | 25 | |
Josvth | 0:050184ab5c0d | 26 | unsigned int ticks = 226; |
Josvth | 0:050184ab5c0d | 27 | |
Josvth | 0:050184ab5c0d | 28 | // This signal should give a manchester encoded 101010101 |
Josvth | 0:050184ab5c0d | 29 | pwm.period_ticks(ticks); |
Josvth | 0:050184ab5c0d | 30 | pwm.pulsewidth_ticks(ticks / 2); |
Josvth | 0:050184ab5c0d | 31 | |
Josvth | 0:050184ab5c0d | 32 | // Setup TIM2 |
Josvth | 0:050184ab5c0d | 33 | |
Josvth | 0:050184ab5c0d | 34 | // SC |
Josvth | 0:050184ab5c0d | 35 | LPC_SC->PCONP |= (1<<22); // Power on the Timer2 |
Josvth | 0:050184ab5c0d | 36 | LPC_SC->PCLKSEL1 &= ~(3<<12); // Select CCLK/4 for TIM2 (whipes previous clock setting) |
Josvth | 0:050184ab5c0d | 37 | LPC_SC->PCLKSEL1 |= (1<<12); // Select CCLK for TIM2 |
Josvth | 0:050184ab5c0d | 38 | |
Josvth | 0:050184ab5c0d | 39 | // CCR |
Josvth | 0:050184ab5c0d | 40 | LPC_TIM2->CCR |= (3 << 1); // Set CAP2.0 on falling edge with interrupt |
Josvth | 0:050184ab5c0d | 41 | LPC_TIM2->CCR |= (1 << 3); // Set CAP2.1 on rising edge |
Josvth | 0:050184ab5c0d | 42 | |
Josvth | 0:050184ab5c0d | 43 | pc.printf("CCR: %X\n", LPC_TIM2->CCR); |
Josvth | 0:050184ab5c0d | 44 | |
Josvth | 0:050184ab5c0d | 45 | // TCR |
Josvth | 0:050184ab5c0d | 46 | LPC_TIM2->TCR = 0x0002; // Reset TIM2 |
Josvth | 0:050184ab5c0d | 47 | LPC_TIM2->TCR = 0x0001; // Enable TIM2 |
Josvth | 0:050184ab5c0d | 48 | |
Josvth | 0:050184ab5c0d | 49 | bool buffer [16]; |
Josvth | 0:050184ab5c0d | 50 | int bits = 0; |
Josvth | 0:050184ab5c0d | 51 | |
Josvth | 0:050184ab5c0d | 52 | //NVIC_DisableIRQ(TIMER2_IRQn); |
Josvth | 0:050184ab5c0d | 53 | //NVIC_SetVector(TIMER2_IRQn, (uint32_t)&_cap_2_1_falling); |
Josvth | 0:050184ab5c0d | 54 | //NVIC_EnableIRQ(TIMER2_IRQn); |
Josvth | 0:050184ab5c0d | 55 | |
Josvth | 0:050184ab5c0d | 56 | while(1) { |
Josvth | 0:050184ab5c0d | 57 | |
Josvth | 0:050184ab5c0d | 58 | //pc.printf("Interrupt: %X\n", LPC_TIM2->IR); |
Josvth | 0:050184ab5c0d | 59 | |
Josvth | 0:050184ab5c0d | 60 | // Poll CRO (falling edge) intterupt |
Josvth | 0:050184ab5c0d | 61 | if (LPC_TIM2->IR & (1 << 4)) { |
Josvth | 0:050184ab5c0d | 62 | |
Josvth | 0:050184ab5c0d | 63 | led = 1; |
Josvth | 0:050184ab5c0d | 64 | |
Josvth | 0:050184ab5c0d | 65 | wait(100); |
Josvth | 0:050184ab5c0d | 66 | |
Josvth | 0:050184ab5c0d | 67 | led = 0; |
Josvth | 0:050184ab5c0d | 68 | |
Josvth | 0:050184ab5c0d | 69 | int diff = (TIM2CR0 - TIM2CR1) % 0xFFFFFFFF; |
Josvth | 0:050184ab5c0d | 70 | |
Josvth | 0:050184ab5c0d | 71 | if (diff > 90 && diff < 136) { // Check if diff is equal to T=1/848kHz with 20% error |
Josvth | 0:050184ab5c0d | 72 | // bit transition |
Josvth | 0:050184ab5c0d | 73 | |
Josvth | 0:050184ab5c0d | 74 | if (bits == 0) { // Start of sequence |
Josvth | 0:050184ab5c0d | 75 | buffer[0] = 1; |
Josvth | 0:050184ab5c0d | 76 | } else { |
Josvth | 0:050184ab5c0d | 77 | buffer[bits] = !buffer[bits-1]; |
Josvth | 0:050184ab5c0d | 78 | } |
Josvth | 0:050184ab5c0d | 79 | |
Josvth | 0:050184ab5c0d | 80 | pc.printf("Trasition: %u\n", diff); |
Josvth | 0:050184ab5c0d | 81 | |
Josvth | 0:050184ab5c0d | 82 | } else if (diff > 45 && diff < 68) { // Check if diff is equal to T/2 |
Josvth | 0:050184ab5c0d | 83 | // repeat last bit |
Josvth | 0:050184ab5c0d | 84 | |
Josvth | 0:050184ab5c0d | 85 | if (bits == 0) { // Start of sequence |
Josvth | 0:050184ab5c0d | 86 | buffer[0] = 1; |
Josvth | 0:050184ab5c0d | 87 | } else { |
Josvth | 0:050184ab5c0d | 88 | buffer[bits] = buffer[bits-1]; |
Josvth | 0:050184ab5c0d | 89 | } |
Josvth | 0:050184ab5c0d | 90 | |
Josvth | 0:050184ab5c0d | 91 | pc.printf("Repeat: %u\n", diff); |
Josvth | 0:050184ab5c0d | 92 | |
Josvth | 0:050184ab5c0d | 93 | } else { |
Josvth | 0:050184ab5c0d | 94 | // error, default to 1 |
Josvth | 0:050184ab5c0d | 95 | pc.printf("Error: %u\n", diff); |
Josvth | 0:050184ab5c0d | 96 | } |
Josvth | 0:050184ab5c0d | 97 | |
Josvth | 0:050184ab5c0d | 98 | bits = bits + 1 % 16; |
Josvth | 0:050184ab5c0d | 99 | |
Josvth | 0:050184ab5c0d | 100 | LPC_TIM2->IR |= (1 << 4); // Clear IR by writing a one |
Josvth | 0:050184ab5c0d | 101 | |
Josvth | 0:050184ab5c0d | 102 | } |
Josvth | 0:050184ab5c0d | 103 | |
Josvth | 0:050184ab5c0d | 104 | // if (bits == 0) { |
Josvth | 0:050184ab5c0d | 105 | // |
Josvth | 0:050184ab5c0d | 106 | // for (int i = 0; i< 16; i++) { |
Josvth | 0:050184ab5c0d | 107 | // pc.printf("%u", (int) buffer[i]); |
Josvth | 0:050184ab5c0d | 108 | // } |
Josvth | 0:050184ab5c0d | 109 | // |
Josvth | 0:050184ab5c0d | 110 | // pc.printf("\n"); |
Josvth | 0:050184ab5c0d | 111 | // |
Josvth | 0:050184ab5c0d | 112 | // } |
Josvth | 0:050184ab5c0d | 113 | |
Josvth | 0:050184ab5c0d | 114 | // // Poll CRO (rising edge) intterupt |
Josvth | 0:050184ab5c0d | 115 | // if (LCP_TIM2-IR != (1 << 5)) { |
Josvth | 0:050184ab5c0d | 116 | // |
Josvth | 0:050184ab5c0d | 117 | // int diff = (TIM2CR1 - TIM2CR2) % 0xFFFFFFFF; |
Josvth | 0:050184ab5c0d | 118 | // |
Josvth | 0:050184ab5c0d | 119 | // // Do checks |
Josvth | 0:050184ab5c0d | 120 | // |
Josvth | 0:050184ab5c0d | 121 | // // End checks |
Josvth | 0:050184ab5c0d | 122 | // |
Josvth | 0:050184ab5c0d | 123 | // |
Josvth | 0:050184ab5c0d | 124 | // LCP_TIM2->IR &= ~(1 << 5); |
Josvth | 0:050184ab5c0d | 125 | // } |
Josvth | 0:050184ab5c0d | 126 | |
Josvth | 0:050184ab5c0d | 127 | |
Josvth | 0:050184ab5c0d | 128 | |
Josvth | 0:050184ab5c0d | 129 | } |
Josvth | 0:050184ab5c0d | 130 | |
Josvth | 0:050184ab5c0d | 131 | } |