Johannes Stratmann
added prescaler for 16 bit pwm in LPC1347 target
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mbed official
Diff: targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/SMM_MPS2.h
- Revision:
- 80:bdf1132a57cf
- Parent:
- 0:9b334a45a8ff
- Child:
- 144:ef7eb2e8f9f7
diff -r 7f02dc905b68 -r bdf1132a57cf targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/SMM_MPS2.h
--- a/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/SMM_MPS2.h Wed Mar 02 10:15:13 2016 +0000
+++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M7/SMM_MPS2.h Wed Mar 02 14:30:11 2016 +0000
@@ -1,6 +1,6 @@
/* MPS2 CMSIS Library
*
-* Copyright (c) 2006-2015 ARM Limited
+* Copyright (c) 2006-2016 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -30,7 +30,7 @@
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* File: smm_mps2.h
-* Release: Version 1.0
+* Release: Version 1.1
*******************************************************************************/
#ifndef __SMM_MPS2_H
@@ -65,11 +65,14 @@
// Bit[31:0] : reload value for prescale counter
__IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter
// current value of the pre-scaler counter
- // The Cycle Up Counter increment when the prescale down counter reach 0
- // The pre-scaler counter is reloaded with PRESCALE after reaching 0.
+ // The Cycle Up Counter increment when the prescale down counter reach 0
+ // The pre-scaler counter is reloaded with PRESCALE after reaching 0.
uint32_t RESERVED4[9];
__IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */
- // [31:7] : Reserved
+ // [31:10] : Reserved
+ // [9] : SHIELD_1_SPI_nCS
+ // [8] : SHIELD_0_SPI_nCS
+ // [7] : ADC_SPI_nCS
// [6] : CLCD_BL_CTRL
// [5] : CLCD_RD
// [4] : CLCD_RS
@@ -93,6 +96,12 @@
#define CLCD_RD_Msk (1UL<<CLCD_RD_Pos)
#define CLCD_BL_Pos 6
#define CLCD_BL_Msk (1UL<<CLCD_BL_Pos)
+#define ADC_nCS_Pos 7
+#define ADC_nCS_Msk (1UL<<ADC_nCS_Pos)
+#define SHIELD_0_nCS_Pos 8
+#define SHIELD_0_nCS_Msk (1UL<<SHIELD_0_nCS_Pos)
+#define SHIELD_1_nCS_Pos 9
+#define SHIELD_1_nCS_Msk (1UL<<SHIELD_1_nCS_Pos)
/******************************************************************************/
/* SCC Register declaration */
@@ -402,14 +411,14 @@
};
/*!< Offset: 0x00C Divide ratio Register (R/W) */
__IO uint32_t DIVIDE; // <h> Divide ratio for Left/Right clock </h>
- // <o.9..0> TX error (default 0x80)
+ // <o.9..0> TX error (default 0x80)
/*!< Offset: 0x010 Transmit Buffer ( /W) */
__O uint32_t TXBUF; // <h> Transmit buffer </h>
- // <o.15..0> Right channel
+ // <o.15..0> Right channel
// <o.31..16> Left channel
/*!< Offset: 0x014 Receive Buffer (R/ ) */
__I uint32_t RXBUF; // <h> Receive buffer </h>
- // <o.15..0> Right channel
+ // <o.15..0> Right channel
// <o.31..16> Left channel
uint32_t RESERVED1[186];
__IO uint32_t ITCR; // <h> Integration Test Control Register </h>
@@ -556,13 +565,18 @@
#define MPS2_TSC_I2C_BASE (0x40022000ul) /* Touch Screen I2C Base Address */
#define MPS2_AAIC_I2C_BASE (0x40023000ul) /* Audio Interface I2C Base Address */
#define MPS2_AAIC_I2S_BASE (0x40024000ul) /* Audio Interface I2S Base Address */
+#define MPS2_SSP2_BASE (0x40025000ul) /* adc SSP Base Address */
+#define MPS2_SSP3_BASE (0x40026000ul) /* Shield 0 SSP Base Address */
+#define MPS2_SSP4_BASE (0x40027000ul) /* Shield 1 SSP Base Address */
#define MPS2_FPGAIO_BASE (0x40028000ul) /* FPGAIO Base Address */
+#define MPS2_SHIELD0_I2C_BASE (0x40029000ul) /* Shield 0 I2C Base Address */
+#define MPS2_SHIELD1_I2C_BASE (0x4002A000ul) /* Shield 1 I2C Base Address */
#define MPS2_SCC_BASE (0x4002F000ul) /* SCC Base Address */
#define SMSC9220_BASE (0xA0000000ul) /* Ethernet SMSC9220 Base Address */
+#define MPS2_VGA_TEXT_BUFFER (0x41000000ul) /* VGA Text Buffer Address */
#define MPS2_VGA_BUFFER (0x41100000ul) /* VGA Buffer Base Address */
-#define MPS2_VGA_TEXT_BUFFER (0x41000000ul) /* VGA Text Buffer Address */
/******************************************************************************/
/* Peripheral declaration */
@@ -571,11 +585,16 @@
#define SMSC9220 ((SMSC9220_TypeDef *) SMSC9220_BASE )
#define MPS2_TS_I2C ((MPS2_I2C_TypeDef *) MPS2_TSC_I2C_BASE )
#define MPS2_AAIC_I2C ((MPS2_I2C_TypeDef *) MPS2_AAIC_I2C_BASE )
+#define MPS2_SHIELD0_I2C ((MPS2_I2C_TypeDef *) MPS2_SHIELD0_I2C_BASE )
+#define MPS2_SHIELD1_I2C ((MPS2_I2C_TypeDef *) MPS2_SHIELD1_I2C_BASE )
#define MPS2_AAIC_I2S ((MPS2_I2S_TypeDef *) MPS2_AAIC_I2S_BASE )
#define MPS2_FPGAIO ((MPS2_FPGAIO_TypeDef *) MPS2_FPGAIO_BASE )
#define MPS2_SCC ((MPS2_SCC_TypeDef *) MPS2_SCC_BASE )
#define MPS2_SSP0 ((MPS2_SSP_TypeDef *) MPS2_SSP0_BASE )
#define MPS2_SSP1 ((MPS2_SSP_TypeDef *) MPS2_SSP1_BASE )
+#define MPS2_SSP2 ((MPS2_SSP_TypeDef *) MPS2_SSP2_BASE )
+#define MPS2_SSP3 ((MPS2_SSP_TypeDef *) MPS2_SSP3_BASE )
+#define MPS2_SSP4 ((MPS2_SSP_TypeDef *) MPS2_SSP4_BASE )
/******************************************************************************/
/* General Function Definitions */