added prescaler for 16 bit pwm in LPC1347 target
Fork of mbed-dev by
targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_cmu.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)
- Committer:
- <>
- Date:
- Fri Sep 02 15:07:44 2016 +0100
- Revision:
- 144:ef7eb2e8f9f7
- Parent:
- 50:a417edff4437
This updates the lib to the mbed lib v125
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 2 | * @file em_cmu.c |
<> | 144:ef7eb2e8f9f7 | 3 | * @brief Clock management unit (CMU) Peripheral API |
<> | 144:ef7eb2e8f9f7 | 4 | * @version 4.2.1 |
<> | 144:ef7eb2e8f9f7 | 5 | ******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 6 | * @section License |
<> | 144:ef7eb2e8f9f7 | 7 | * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b> |
<> | 144:ef7eb2e8f9f7 | 8 | ******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 9 | * |
<> | 144:ef7eb2e8f9f7 | 10 | * Permission is granted to anyone to use this software for any purpose, |
<> | 144:ef7eb2e8f9f7 | 11 | * including commercial applications, and to alter it and redistribute it |
<> | 144:ef7eb2e8f9f7 | 12 | * freely, subject to the following restrictions: |
<> | 144:ef7eb2e8f9f7 | 13 | * |
<> | 144:ef7eb2e8f9f7 | 14 | * 1. The origin of this software must not be misrepresented; you must not |
<> | 144:ef7eb2e8f9f7 | 15 | * claim that you wrote the original software. |
<> | 144:ef7eb2e8f9f7 | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
<> | 144:ef7eb2e8f9f7 | 17 | * misrepresented as being the original software. |
<> | 144:ef7eb2e8f9f7 | 18 | * 3. This notice may not be removed or altered from any source distribution. |
<> | 144:ef7eb2e8f9f7 | 19 | * |
<> | 144:ef7eb2e8f9f7 | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no |
<> | 144:ef7eb2e8f9f7 | 21 | * obligation to support this Software. Silicon Labs is providing the |
<> | 144:ef7eb2e8f9f7 | 22 | * Software "AS IS", with no express or implied warranties of any kind, |
<> | 144:ef7eb2e8f9f7 | 23 | * including, but not limited to, any implied warranties of merchantability |
<> | 144:ef7eb2e8f9f7 | 24 | * or fitness for any particular purpose or warranties against infringement |
<> | 144:ef7eb2e8f9f7 | 25 | * of any proprietary rights of a third party. |
<> | 144:ef7eb2e8f9f7 | 26 | * |
<> | 144:ef7eb2e8f9f7 | 27 | * Silicon Labs will not be liable for any consequential, incidental, or |
<> | 144:ef7eb2e8f9f7 | 28 | * special damages, or any other relief, or for any claim by any third party, |
<> | 144:ef7eb2e8f9f7 | 29 | * arising from your use of this Software. |
<> | 144:ef7eb2e8f9f7 | 30 | * |
<> | 144:ef7eb2e8f9f7 | 31 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 32 | #include "em_cmu.h" |
<> | 144:ef7eb2e8f9f7 | 33 | #if defined( CMU_PRESENT ) |
<> | 144:ef7eb2e8f9f7 | 34 | |
<> | 144:ef7eb2e8f9f7 | 35 | #include <stddef.h> |
<> | 144:ef7eb2e8f9f7 | 36 | #include <limits.h> |
<> | 144:ef7eb2e8f9f7 | 37 | #include "em_assert.h" |
<> | 144:ef7eb2e8f9f7 | 38 | #include "em_bus.h" |
<> | 144:ef7eb2e8f9f7 | 39 | #include "em_emu.h" |
<> | 144:ef7eb2e8f9f7 | 40 | #include "em_system.h" |
<> | 144:ef7eb2e8f9f7 | 41 | |
<> | 144:ef7eb2e8f9f7 | 42 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 43 | * @addtogroup EM_Library |
<> | 144:ef7eb2e8f9f7 | 44 | * @{ |
<> | 144:ef7eb2e8f9f7 | 45 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 46 | |
<> | 144:ef7eb2e8f9f7 | 47 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 48 | * @addtogroup CMU |
<> | 144:ef7eb2e8f9f7 | 49 | * @brief Clock management unit (CMU) Peripheral API |
<> | 144:ef7eb2e8f9f7 | 50 | * @{ |
<> | 144:ef7eb2e8f9f7 | 51 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 52 | |
<> | 144:ef7eb2e8f9f7 | 53 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 54 | ****************************** DEFINES ************************************ |
<> | 144:ef7eb2e8f9f7 | 55 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 56 | |
<> | 144:ef7eb2e8f9f7 | 57 | /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ |
<> | 144:ef7eb2e8f9f7 | 58 | |
<> | 144:ef7eb2e8f9f7 | 59 | #if defined( _SILICON_LABS_32B_PLATFORM_2 ) |
<> | 144:ef7eb2e8f9f7 | 60 | /** Maximum allowed core frequency when using 0 wait-states on flash access. */ |
<> | 144:ef7eb2e8f9f7 | 61 | #define CMU_MAX_FREQ_0WS 26000000 |
<> | 144:ef7eb2e8f9f7 | 62 | /** Maximum allowed core frequency when using 1 wait-states on flash access */ |
<> | 144:ef7eb2e8f9f7 | 63 | #define CMU_MAX_FREQ_1WS 40000000 |
<> | 144:ef7eb2e8f9f7 | 64 | #elif defined( _SILICON_LABS_32B_PLATFORM_1 ) |
<> | 144:ef7eb2e8f9f7 | 65 | /** Maximum allowed core frequency when using 0 wait-states on flash access. */ |
<> | 144:ef7eb2e8f9f7 | 66 | #define CMU_MAX_FREQ_0WS 16000000 |
<> | 144:ef7eb2e8f9f7 | 67 | /** Maximum allowed core frequency when using 1 wait-states on flash access */ |
<> | 144:ef7eb2e8f9f7 | 68 | #define CMU_MAX_FREQ_1WS 32000000 |
<> | 144:ef7eb2e8f9f7 | 69 | #else |
<> | 144:ef7eb2e8f9f7 | 70 | #error "Unkown MCU platform." |
<> | 144:ef7eb2e8f9f7 | 71 | #endif |
<> | 144:ef7eb2e8f9f7 | 72 | |
<> | 144:ef7eb2e8f9f7 | 73 | #if defined( CMU_CTRL_HFLE ) |
<> | 144:ef7eb2e8f9f7 | 74 | /** Maximum frequency for HFLE needs to be enabled on Giant, Leopard and |
<> | 144:ef7eb2e8f9f7 | 75 | Wonder. */ |
<> | 144:ef7eb2e8f9f7 | 76 | #if defined( _EFM32_WONDER_FAMILY ) \ |
<> | 144:ef7eb2e8f9f7 | 77 | || defined( _EZR32_LEOPARD_FAMILY ) \ |
<> | 144:ef7eb2e8f9f7 | 78 | || defined( _EZR32_WONDER_FAMILY ) |
<> | 144:ef7eb2e8f9f7 | 79 | #define CMU_MAX_FREQ_HFLE() 24000000 |
<> | 144:ef7eb2e8f9f7 | 80 | #elif defined ( _EFM32_GIANT_FAMILY ) |
<> | 144:ef7eb2e8f9f7 | 81 | #define CMU_MAX_FREQ_HFLE() (maxFreqHfle()) |
<> | 144:ef7eb2e8f9f7 | 82 | #else |
<> | 144:ef7eb2e8f9f7 | 83 | #error Invalid part/device. |
<> | 144:ef7eb2e8f9f7 | 84 | #endif |
<> | 144:ef7eb2e8f9f7 | 85 | #endif |
<> | 144:ef7eb2e8f9f7 | 86 | |
<> | 144:ef7eb2e8f9f7 | 87 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 88 | ************************** LOCAL VARIABLES ******************************** |
<> | 144:ef7eb2e8f9f7 | 89 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 90 | |
<> | 144:ef7eb2e8f9f7 | 91 | #if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK ) |
<> | 144:ef7eb2e8f9f7 | 92 | static CMU_AUXHFRCOFreq_TypeDef auxHfrcoFreq = cmuAUXHFRCOFreq_19M0Hz; |
<> | 144:ef7eb2e8f9f7 | 93 | #endif |
<> | 144:ef7eb2e8f9f7 | 94 | |
<> | 144:ef7eb2e8f9f7 | 95 | /** @endcond */ |
<> | 144:ef7eb2e8f9f7 | 96 | |
<> | 144:ef7eb2e8f9f7 | 97 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 98 | ************************** LOCAL FUNCTIONS ******************************** |
<> | 144:ef7eb2e8f9f7 | 99 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 100 | |
<> | 144:ef7eb2e8f9f7 | 101 | /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ |
<> | 144:ef7eb2e8f9f7 | 102 | |
<> | 144:ef7eb2e8f9f7 | 103 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 104 | * @brief |
<> | 144:ef7eb2e8f9f7 | 105 | * Get the AUX clock frequency. Used by MSC flash programming and LESENSE, |
<> | 144:ef7eb2e8f9f7 | 106 | * by default also as debug clock. |
<> | 144:ef7eb2e8f9f7 | 107 | * |
<> | 144:ef7eb2e8f9f7 | 108 | * @return |
<> | 144:ef7eb2e8f9f7 | 109 | * AUX Frequency in Hz |
<> | 144:ef7eb2e8f9f7 | 110 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 111 | static uint32_t auxClkGet(void) |
<> | 144:ef7eb2e8f9f7 | 112 | { |
<> | 144:ef7eb2e8f9f7 | 113 | uint32_t ret; |
<> | 144:ef7eb2e8f9f7 | 114 | |
<> | 144:ef7eb2e8f9f7 | 115 | #if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK ) |
<> | 144:ef7eb2e8f9f7 | 116 | ret = auxHfrcoFreq; |
<> | 144:ef7eb2e8f9f7 | 117 | |
<> | 144:ef7eb2e8f9f7 | 118 | #elif defined( _CMU_AUXHFRCOCTRL_BAND_MASK ) |
<> | 144:ef7eb2e8f9f7 | 119 | /* All Geckos from TG and newer */ |
<> | 144:ef7eb2e8f9f7 | 120 | switch(CMU->AUXHFRCOCTRL & _CMU_AUXHFRCOCTRL_BAND_MASK) |
<> | 144:ef7eb2e8f9f7 | 121 | { |
<> | 144:ef7eb2e8f9f7 | 122 | case CMU_AUXHFRCOCTRL_BAND_1MHZ: |
<> | 144:ef7eb2e8f9f7 | 123 | ret = 1000000; |
<> | 144:ef7eb2e8f9f7 | 124 | break; |
<> | 144:ef7eb2e8f9f7 | 125 | |
<> | 144:ef7eb2e8f9f7 | 126 | case CMU_AUXHFRCOCTRL_BAND_7MHZ: |
<> | 144:ef7eb2e8f9f7 | 127 | ret = 7000000; |
<> | 144:ef7eb2e8f9f7 | 128 | break; |
<> | 144:ef7eb2e8f9f7 | 129 | |
<> | 144:ef7eb2e8f9f7 | 130 | case CMU_AUXHFRCOCTRL_BAND_11MHZ: |
<> | 144:ef7eb2e8f9f7 | 131 | ret = 11000000; |
<> | 144:ef7eb2e8f9f7 | 132 | break; |
<> | 144:ef7eb2e8f9f7 | 133 | |
<> | 144:ef7eb2e8f9f7 | 134 | case CMU_AUXHFRCOCTRL_BAND_14MHZ: |
<> | 144:ef7eb2e8f9f7 | 135 | ret = 14000000; |
<> | 144:ef7eb2e8f9f7 | 136 | break; |
<> | 144:ef7eb2e8f9f7 | 137 | |
<> | 144:ef7eb2e8f9f7 | 138 | case CMU_AUXHFRCOCTRL_BAND_21MHZ: |
<> | 144:ef7eb2e8f9f7 | 139 | ret = 21000000; |
<> | 144:ef7eb2e8f9f7 | 140 | break; |
<> | 144:ef7eb2e8f9f7 | 141 | |
<> | 144:ef7eb2e8f9f7 | 142 | #if defined( _CMU_AUXHFRCOCTRL_BAND_28MHZ ) |
<> | 144:ef7eb2e8f9f7 | 143 | case CMU_AUXHFRCOCTRL_BAND_28MHZ: |
<> | 144:ef7eb2e8f9f7 | 144 | ret = 28000000; |
<> | 144:ef7eb2e8f9f7 | 145 | break; |
<> | 144:ef7eb2e8f9f7 | 146 | #endif |
<> | 144:ef7eb2e8f9f7 | 147 | |
<> | 144:ef7eb2e8f9f7 | 148 | default: |
<> | 144:ef7eb2e8f9f7 | 149 | EFM_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 150 | ret = 0; |
<> | 144:ef7eb2e8f9f7 | 151 | break; |
<> | 144:ef7eb2e8f9f7 | 152 | } |
<> | 144:ef7eb2e8f9f7 | 153 | |
<> | 144:ef7eb2e8f9f7 | 154 | #else |
<> | 144:ef7eb2e8f9f7 | 155 | /* Gecko has a fixed 14Mhz AUXHFRCO clock */ |
<> | 144:ef7eb2e8f9f7 | 156 | ret = 14000000; |
<> | 144:ef7eb2e8f9f7 | 157 | |
<> | 144:ef7eb2e8f9f7 | 158 | #endif |
<> | 144:ef7eb2e8f9f7 | 159 | |
<> | 144:ef7eb2e8f9f7 | 160 | return ret; |
<> | 144:ef7eb2e8f9f7 | 161 | } |
<> | 144:ef7eb2e8f9f7 | 162 | |
<> | 144:ef7eb2e8f9f7 | 163 | |
<> | 144:ef7eb2e8f9f7 | 164 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 165 | * @brief |
<> | 144:ef7eb2e8f9f7 | 166 | * Get the Debug Trace clock frequency |
<> | 144:ef7eb2e8f9f7 | 167 | * |
<> | 144:ef7eb2e8f9f7 | 168 | * @return |
<> | 144:ef7eb2e8f9f7 | 169 | * Debug Trace frequency in Hz |
<> | 144:ef7eb2e8f9f7 | 170 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 171 | static uint32_t dbgClkGet(void) |
<> | 144:ef7eb2e8f9f7 | 172 | { |
<> | 144:ef7eb2e8f9f7 | 173 | uint32_t ret; |
<> | 144:ef7eb2e8f9f7 | 174 | CMU_Select_TypeDef clk; |
<> | 144:ef7eb2e8f9f7 | 175 | |
<> | 144:ef7eb2e8f9f7 | 176 | /* Get selected clock source */ |
<> | 144:ef7eb2e8f9f7 | 177 | clk = CMU_ClockSelectGet(cmuClock_DBG); |
<> | 144:ef7eb2e8f9f7 | 178 | |
<> | 144:ef7eb2e8f9f7 | 179 | switch(clk) |
<> | 144:ef7eb2e8f9f7 | 180 | { |
<> | 144:ef7eb2e8f9f7 | 181 | case cmuSelect_HFCLK: |
<> | 144:ef7eb2e8f9f7 | 182 | ret = SystemHFClockGet(); |
<> | 144:ef7eb2e8f9f7 | 183 | #if defined( _CMU_CTRL_HFCLKDIV_MASK ) |
<> | 144:ef7eb2e8f9f7 | 184 | /* Family with an additional divider. */ |
<> | 144:ef7eb2e8f9f7 | 185 | ret = ret / (1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK) |
<> | 144:ef7eb2e8f9f7 | 186 | >> _CMU_CTRL_HFCLKDIV_SHIFT)); |
<> | 144:ef7eb2e8f9f7 | 187 | #endif |
<> | 144:ef7eb2e8f9f7 | 188 | break; |
<> | 144:ef7eb2e8f9f7 | 189 | |
<> | 144:ef7eb2e8f9f7 | 190 | case cmuSelect_AUXHFRCO: |
<> | 144:ef7eb2e8f9f7 | 191 | ret = auxClkGet(); |
<> | 144:ef7eb2e8f9f7 | 192 | break; |
<> | 144:ef7eb2e8f9f7 | 193 | |
<> | 144:ef7eb2e8f9f7 | 194 | default: |
<> | 144:ef7eb2e8f9f7 | 195 | EFM_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 196 | ret = 0; |
<> | 144:ef7eb2e8f9f7 | 197 | break; |
<> | 144:ef7eb2e8f9f7 | 198 | } |
<> | 144:ef7eb2e8f9f7 | 199 | return ret; |
<> | 144:ef7eb2e8f9f7 | 200 | } |
<> | 144:ef7eb2e8f9f7 | 201 | |
<> | 144:ef7eb2e8f9f7 | 202 | |
<> | 144:ef7eb2e8f9f7 | 203 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 204 | * @brief |
<> | 144:ef7eb2e8f9f7 | 205 | * Configure flash access wait states in order to support given core clock |
<> | 144:ef7eb2e8f9f7 | 206 | * frequency. |
<> | 144:ef7eb2e8f9f7 | 207 | * |
<> | 144:ef7eb2e8f9f7 | 208 | * @param[in] coreFreq |
<> | 144:ef7eb2e8f9f7 | 209 | * Core clock frequency to configure flash wait-states for |
<> | 144:ef7eb2e8f9f7 | 210 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 211 | static void flashWaitStateControl(uint32_t coreFreq) |
<> | 144:ef7eb2e8f9f7 | 212 | { |
<> | 144:ef7eb2e8f9f7 | 213 | uint32_t mode; |
<> | 144:ef7eb2e8f9f7 | 214 | bool mscLocked; |
<> | 144:ef7eb2e8f9f7 | 215 | #if defined( MSC_READCTRL_MODE_WS0SCBTP ) |
<> | 144:ef7eb2e8f9f7 | 216 | bool scbtpEn; /* Suppressed Conditional Branch Target Prefetch setting. */ |
<> | 144:ef7eb2e8f9f7 | 217 | #endif |
<> | 144:ef7eb2e8f9f7 | 218 | |
<> | 144:ef7eb2e8f9f7 | 219 | /* Make sure the MSC is unlocked */ |
<> | 144:ef7eb2e8f9f7 | 220 | mscLocked = MSC->LOCK; |
<> | 144:ef7eb2e8f9f7 | 221 | MSC->LOCK = MSC_UNLOCK_CODE; |
<> | 144:ef7eb2e8f9f7 | 222 | |
<> | 144:ef7eb2e8f9f7 | 223 | /* Get mode and SCBTP enable */ |
<> | 144:ef7eb2e8f9f7 | 224 | mode = MSC->READCTRL & _MSC_READCTRL_MODE_MASK; |
<> | 144:ef7eb2e8f9f7 | 225 | #if defined( MSC_READCTRL_MODE_WS0SCBTP ) |
<> | 144:ef7eb2e8f9f7 | 226 | switch(mode) |
<> | 144:ef7eb2e8f9f7 | 227 | { |
<> | 144:ef7eb2e8f9f7 | 228 | case MSC_READCTRL_MODE_WS0: |
<> | 144:ef7eb2e8f9f7 | 229 | case MSC_READCTRL_MODE_WS1: |
<> | 144:ef7eb2e8f9f7 | 230 | #if defined( MSC_READCTRL_MODE_WS2 ) |
<> | 144:ef7eb2e8f9f7 | 231 | case MSC_READCTRL_MODE_WS2: |
<> | 144:ef7eb2e8f9f7 | 232 | #endif |
<> | 144:ef7eb2e8f9f7 | 233 | scbtpEn = false; |
<> | 144:ef7eb2e8f9f7 | 234 | break; |
<> | 144:ef7eb2e8f9f7 | 235 | |
<> | 144:ef7eb2e8f9f7 | 236 | default: /* WSxSCBTP */ |
<> | 144:ef7eb2e8f9f7 | 237 | scbtpEn = true; |
<> | 144:ef7eb2e8f9f7 | 238 | break; |
<> | 144:ef7eb2e8f9f7 | 239 | } |
<> | 144:ef7eb2e8f9f7 | 240 | #endif |
<> | 144:ef7eb2e8f9f7 | 241 | |
<> | 144:ef7eb2e8f9f7 | 242 | |
<> | 144:ef7eb2e8f9f7 | 243 | /* Set mode based on the core clock frequency and SCBTP enable */ |
<> | 144:ef7eb2e8f9f7 | 244 | #if defined( MSC_READCTRL_MODE_WS0SCBTP ) |
<> | 144:ef7eb2e8f9f7 | 245 | if (false) |
<> | 144:ef7eb2e8f9f7 | 246 | { |
<> | 144:ef7eb2e8f9f7 | 247 | } |
<> | 144:ef7eb2e8f9f7 | 248 | #if defined( MSC_READCTRL_MODE_WS2 ) |
<> | 144:ef7eb2e8f9f7 | 249 | else if (coreFreq > CMU_MAX_FREQ_1WS) |
<> | 144:ef7eb2e8f9f7 | 250 | { |
<> | 144:ef7eb2e8f9f7 | 251 | mode = (scbtpEn ? MSC_READCTRL_MODE_WS2SCBTP : MSC_READCTRL_MODE_WS2); |
<> | 144:ef7eb2e8f9f7 | 252 | } |
<> | 144:ef7eb2e8f9f7 | 253 | #endif |
<> | 144:ef7eb2e8f9f7 | 254 | else if ((coreFreq <= CMU_MAX_FREQ_1WS) && (coreFreq > CMU_MAX_FREQ_0WS)) |
<> | 144:ef7eb2e8f9f7 | 255 | { |
<> | 144:ef7eb2e8f9f7 | 256 | mode = (scbtpEn ? MSC_READCTRL_MODE_WS1SCBTP : MSC_READCTRL_MODE_WS1); |
<> | 144:ef7eb2e8f9f7 | 257 | } |
<> | 144:ef7eb2e8f9f7 | 258 | else |
<> | 144:ef7eb2e8f9f7 | 259 | { |
<> | 144:ef7eb2e8f9f7 | 260 | mode = (scbtpEn ? MSC_READCTRL_MODE_WS0SCBTP : MSC_READCTRL_MODE_WS0); |
<> | 144:ef7eb2e8f9f7 | 261 | } |
<> | 144:ef7eb2e8f9f7 | 262 | |
<> | 144:ef7eb2e8f9f7 | 263 | #else /* If MODE and SCBTP is in separate register fields */ |
<> | 144:ef7eb2e8f9f7 | 264 | |
<> | 144:ef7eb2e8f9f7 | 265 | if (false) |
<> | 144:ef7eb2e8f9f7 | 266 | { |
<> | 144:ef7eb2e8f9f7 | 267 | } |
<> | 144:ef7eb2e8f9f7 | 268 | #if defined( MSC_READCTRL_MODE_WS2 ) |
<> | 144:ef7eb2e8f9f7 | 269 | else if (coreFreq > CMU_MAX_FREQ_1WS) |
<> | 144:ef7eb2e8f9f7 | 270 | { |
<> | 144:ef7eb2e8f9f7 | 271 | mode = MSC_READCTRL_MODE_WS2; |
<> | 144:ef7eb2e8f9f7 | 272 | } |
<> | 144:ef7eb2e8f9f7 | 273 | #endif |
<> | 144:ef7eb2e8f9f7 | 274 | else if ((coreFreq <= CMU_MAX_FREQ_1WS) && (coreFreq > CMU_MAX_FREQ_0WS)) |
<> | 144:ef7eb2e8f9f7 | 275 | { |
<> | 144:ef7eb2e8f9f7 | 276 | mode = MSC_READCTRL_MODE_WS1; |
<> | 144:ef7eb2e8f9f7 | 277 | } |
<> | 144:ef7eb2e8f9f7 | 278 | else |
<> | 144:ef7eb2e8f9f7 | 279 | { |
<> | 144:ef7eb2e8f9f7 | 280 | mode = MSC_READCTRL_MODE_WS0; |
<> | 144:ef7eb2e8f9f7 | 281 | } |
<> | 144:ef7eb2e8f9f7 | 282 | #endif |
<> | 144:ef7eb2e8f9f7 | 283 | |
<> | 144:ef7eb2e8f9f7 | 284 | /* BUS_RegMaskedWrite cannot be used here as it would temporarely set the |
<> | 144:ef7eb2e8f9f7 | 285 | mode field to WS0 */ |
<> | 144:ef7eb2e8f9f7 | 286 | MSC->READCTRL = (MSC->READCTRL &~_MSC_READCTRL_MODE_MASK) | mode; |
<> | 144:ef7eb2e8f9f7 | 287 | |
<> | 144:ef7eb2e8f9f7 | 288 | if (mscLocked) |
<> | 144:ef7eb2e8f9f7 | 289 | { |
<> | 144:ef7eb2e8f9f7 | 290 | MSC->LOCK = 0; |
<> | 144:ef7eb2e8f9f7 | 291 | } |
<> | 144:ef7eb2e8f9f7 | 292 | } |
<> | 144:ef7eb2e8f9f7 | 293 | |
<> | 144:ef7eb2e8f9f7 | 294 | |
<> | 144:ef7eb2e8f9f7 | 295 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 296 | * @brief |
<> | 144:ef7eb2e8f9f7 | 297 | * Configure flash access wait states to most conservative setting for |
<> | 144:ef7eb2e8f9f7 | 298 | * this target. Retain SCBTP (Suppressed Conditional Branch Target Prefetch) |
<> | 144:ef7eb2e8f9f7 | 299 | * setting. |
<> | 144:ef7eb2e8f9f7 | 300 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 301 | static void flashWaitStateMax(void) |
<> | 144:ef7eb2e8f9f7 | 302 | { |
<> | 144:ef7eb2e8f9f7 | 303 | flashWaitStateControl(SystemMaxCoreClockGet()); |
<> | 144:ef7eb2e8f9f7 | 304 | } |
<> | 144:ef7eb2e8f9f7 | 305 | |
<> | 144:ef7eb2e8f9f7 | 306 | |
<> | 144:ef7eb2e8f9f7 | 307 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 308 | * @brief |
<> | 144:ef7eb2e8f9f7 | 309 | * Get the LFnCLK frequency based on current configuration. |
<> | 144:ef7eb2e8f9f7 | 310 | * |
<> | 144:ef7eb2e8f9f7 | 311 | * @param[in] lfClkBranch |
<> | 144:ef7eb2e8f9f7 | 312 | * Selected LF branch |
<> | 144:ef7eb2e8f9f7 | 313 | * |
<> | 144:ef7eb2e8f9f7 | 314 | * @return |
<> | 144:ef7eb2e8f9f7 | 315 | * The LFnCLK frequency in Hz. If no LFnCLK is selected (disabled), 0 is |
<> | 144:ef7eb2e8f9f7 | 316 | * returned. |
<> | 144:ef7eb2e8f9f7 | 317 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 318 | static uint32_t lfClkGet(CMU_Clock_TypeDef lfClkBranch) |
<> | 144:ef7eb2e8f9f7 | 319 | { |
<> | 144:ef7eb2e8f9f7 | 320 | uint32_t sel; |
<> | 144:ef7eb2e8f9f7 | 321 | uint32_t ret = 0; |
<> | 144:ef7eb2e8f9f7 | 322 | |
<> | 144:ef7eb2e8f9f7 | 323 | switch (lfClkBranch) |
<> | 144:ef7eb2e8f9f7 | 324 | { |
<> | 144:ef7eb2e8f9f7 | 325 | case cmuClock_LFA: |
<> | 144:ef7eb2e8f9f7 | 326 | case cmuClock_LFB: |
<> | 144:ef7eb2e8f9f7 | 327 | #if defined( _CMU_LFCCLKEN0_MASK ) |
<> | 144:ef7eb2e8f9f7 | 328 | case cmuClock_LFC: |
<> | 144:ef7eb2e8f9f7 | 329 | #endif |
<> | 144:ef7eb2e8f9f7 | 330 | #if defined( _CMU_LFECLKSEL_MASK ) |
<> | 144:ef7eb2e8f9f7 | 331 | case cmuClock_LFE: |
<> | 144:ef7eb2e8f9f7 | 332 | #endif |
<> | 144:ef7eb2e8f9f7 | 333 | break; |
<> | 144:ef7eb2e8f9f7 | 334 | |
<> | 144:ef7eb2e8f9f7 | 335 | default: |
<> | 144:ef7eb2e8f9f7 | 336 | EFM_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 337 | break; |
<> | 144:ef7eb2e8f9f7 | 338 | } |
<> | 144:ef7eb2e8f9f7 | 339 | |
<> | 144:ef7eb2e8f9f7 | 340 | sel = CMU_ClockSelectGet(lfClkBranch); |
<> | 144:ef7eb2e8f9f7 | 341 | |
<> | 144:ef7eb2e8f9f7 | 342 | /* Get clock select field */ |
<> | 144:ef7eb2e8f9f7 | 343 | switch (lfClkBranch) |
<> | 144:ef7eb2e8f9f7 | 344 | { |
<> | 144:ef7eb2e8f9f7 | 345 | case cmuClock_LFA: |
<> | 144:ef7eb2e8f9f7 | 346 | #if defined( _CMU_LFCLKSEL_MASK ) |
<> | 144:ef7eb2e8f9f7 | 347 | sel = (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFA_MASK) >> _CMU_LFCLKSEL_LFA_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 348 | #elif defined( _CMU_LFACLKSEL_MASK ) |
<> | 144:ef7eb2e8f9f7 | 349 | sel = (CMU->LFACLKSEL & _CMU_LFACLKSEL_LFA_MASK) >> _CMU_LFACLKSEL_LFA_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 350 | #else |
<> | 144:ef7eb2e8f9f7 | 351 | EFM_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 352 | #endif |
<> | 144:ef7eb2e8f9f7 | 353 | break; |
<> | 144:ef7eb2e8f9f7 | 354 | |
<> | 144:ef7eb2e8f9f7 | 355 | case cmuClock_LFB: |
<> | 144:ef7eb2e8f9f7 | 356 | #if defined( _CMU_LFCLKSEL_MASK ) |
<> | 144:ef7eb2e8f9f7 | 357 | sel = (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFB_MASK) >> _CMU_LFCLKSEL_LFB_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 358 | #elif defined( _CMU_LFBCLKSEL_MASK ) |
<> | 144:ef7eb2e8f9f7 | 359 | sel = (CMU->LFBCLKSEL & _CMU_LFBCLKSEL_LFB_MASK) >> _CMU_LFBCLKSEL_LFB_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 360 | #else |
<> | 144:ef7eb2e8f9f7 | 361 | EFM_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 362 | #endif |
<> | 144:ef7eb2e8f9f7 | 363 | break; |
<> | 144:ef7eb2e8f9f7 | 364 | |
<> | 144:ef7eb2e8f9f7 | 365 | #if defined( _CMU_LFCCLKEN0_MASK ) |
<> | 144:ef7eb2e8f9f7 | 366 | case cmuClock_LFC: |
<> | 144:ef7eb2e8f9f7 | 367 | sel = (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFC_MASK) >> _CMU_LFCLKSEL_LFC_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 368 | break; |
<> | 144:ef7eb2e8f9f7 | 369 | #endif |
<> | 144:ef7eb2e8f9f7 | 370 | |
<> | 144:ef7eb2e8f9f7 | 371 | #if defined( _CMU_LFECLKSEL_MASK ) |
<> | 144:ef7eb2e8f9f7 | 372 | case cmuClock_LFE: |
<> | 144:ef7eb2e8f9f7 | 373 | sel = (CMU->LFECLKSEL & _CMU_LFECLKSEL_LFE_MASK) >> _CMU_LFECLKSEL_LFE_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 374 | break; |
<> | 144:ef7eb2e8f9f7 | 375 | #endif |
<> | 144:ef7eb2e8f9f7 | 376 | |
<> | 144:ef7eb2e8f9f7 | 377 | default: |
<> | 144:ef7eb2e8f9f7 | 378 | EFM_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 379 | break; |
<> | 144:ef7eb2e8f9f7 | 380 | } |
<> | 144:ef7eb2e8f9f7 | 381 | |
<> | 144:ef7eb2e8f9f7 | 382 | /* Get clock frequency */ |
<> | 144:ef7eb2e8f9f7 | 383 | #if defined( _CMU_LFCLKSEL_MASK ) |
<> | 144:ef7eb2e8f9f7 | 384 | switch (sel) |
<> | 144:ef7eb2e8f9f7 | 385 | { |
<> | 144:ef7eb2e8f9f7 | 386 | case _CMU_LFCLKSEL_LFA_LFRCO: |
<> | 144:ef7eb2e8f9f7 | 387 | ret = SystemLFRCOClockGet(); |
<> | 144:ef7eb2e8f9f7 | 388 | break; |
<> | 144:ef7eb2e8f9f7 | 389 | |
<> | 144:ef7eb2e8f9f7 | 390 | case _CMU_LFCLKSEL_LFA_LFXO: |
<> | 144:ef7eb2e8f9f7 | 391 | ret = SystemLFXOClockGet(); |
<> | 144:ef7eb2e8f9f7 | 392 | break; |
<> | 144:ef7eb2e8f9f7 | 393 | |
<> | 144:ef7eb2e8f9f7 | 394 | #if defined( _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 ) |
<> | 144:ef7eb2e8f9f7 | 395 | case _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2: |
<> | 144:ef7eb2e8f9f7 | 396 | #if defined( CMU_CTRL_HFLE ) |
<> | 144:ef7eb2e8f9f7 | 397 | /* Family which can use an extra div 4 divider */ |
<> | 144:ef7eb2e8f9f7 | 398 | /* (and must if >32MHz) or HFLE is set. */ |
<> | 144:ef7eb2e8f9f7 | 399 | if(((CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK) |
<> | 144:ef7eb2e8f9f7 | 400 | == CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4) |
<> | 144:ef7eb2e8f9f7 | 401 | || (CMU->CTRL & CMU_CTRL_HFLE)) |
<> | 144:ef7eb2e8f9f7 | 402 | { |
<> | 144:ef7eb2e8f9f7 | 403 | ret = SystemCoreClockGet() / 4U; |
<> | 144:ef7eb2e8f9f7 | 404 | } |
<> | 144:ef7eb2e8f9f7 | 405 | else |
<> | 144:ef7eb2e8f9f7 | 406 | { |
<> | 144:ef7eb2e8f9f7 | 407 | ret = SystemCoreClockGet() / 2U; |
<> | 144:ef7eb2e8f9f7 | 408 | } |
<> | 144:ef7eb2e8f9f7 | 409 | #else |
<> | 144:ef7eb2e8f9f7 | 410 | ret = SystemCoreClockGet() / 2U; |
<> | 144:ef7eb2e8f9f7 | 411 | #endif |
<> | 144:ef7eb2e8f9f7 | 412 | break; |
<> | 144:ef7eb2e8f9f7 | 413 | #endif |
<> | 144:ef7eb2e8f9f7 | 414 | |
<> | 144:ef7eb2e8f9f7 | 415 | case _CMU_LFCLKSEL_LFA_DISABLED: |
<> | 144:ef7eb2e8f9f7 | 416 | ret = 0; |
<> | 144:ef7eb2e8f9f7 | 417 | #if defined( CMU_LFCLKSEL_LFAE ) |
<> | 144:ef7eb2e8f9f7 | 418 | /* Check LF Extended bit setting for LFA or LFB ULFRCO clock */ |
<> | 144:ef7eb2e8f9f7 | 419 | if ((lfClkBranch == cmuClock_LFA) || (lfClkBranch == cmuClock_LFB)) |
<> | 144:ef7eb2e8f9f7 | 420 | { |
<> | 144:ef7eb2e8f9f7 | 421 | if (CMU->LFCLKSEL >> (lfClkBranch == cmuClock_LFA |
<> | 144:ef7eb2e8f9f7 | 422 | ? _CMU_LFCLKSEL_LFAE_SHIFT |
<> | 144:ef7eb2e8f9f7 | 423 | : _CMU_LFCLKSEL_LFBE_SHIFT)) |
<> | 144:ef7eb2e8f9f7 | 424 | { |
<> | 144:ef7eb2e8f9f7 | 425 | ret = SystemULFRCOClockGet(); |
<> | 144:ef7eb2e8f9f7 | 426 | } |
<> | 144:ef7eb2e8f9f7 | 427 | } |
<> | 144:ef7eb2e8f9f7 | 428 | #endif |
<> | 144:ef7eb2e8f9f7 | 429 | break; |
<> | 144:ef7eb2e8f9f7 | 430 | |
<> | 144:ef7eb2e8f9f7 | 431 | default: |
<> | 144:ef7eb2e8f9f7 | 432 | EFM_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 433 | ret = 0U; |
<> | 144:ef7eb2e8f9f7 | 434 | break; |
<> | 144:ef7eb2e8f9f7 | 435 | } |
<> | 144:ef7eb2e8f9f7 | 436 | #endif /* _CMU_LFCLKSEL_MASK */ |
<> | 144:ef7eb2e8f9f7 | 437 | |
<> | 144:ef7eb2e8f9f7 | 438 | #if defined( _CMU_LFACLKSEL_MASK ) |
<> | 144:ef7eb2e8f9f7 | 439 | switch (sel) |
<> | 144:ef7eb2e8f9f7 | 440 | { |
<> | 144:ef7eb2e8f9f7 | 441 | case _CMU_LFACLKSEL_LFA_LFRCO: |
<> | 144:ef7eb2e8f9f7 | 442 | ret = SystemLFRCOClockGet(); |
<> | 144:ef7eb2e8f9f7 | 443 | break; |
<> | 144:ef7eb2e8f9f7 | 444 | |
<> | 144:ef7eb2e8f9f7 | 445 | case _CMU_LFACLKSEL_LFA_LFXO: |
<> | 144:ef7eb2e8f9f7 | 446 | ret = SystemLFXOClockGet(); |
<> | 144:ef7eb2e8f9f7 | 447 | break; |
<> | 144:ef7eb2e8f9f7 | 448 | |
<> | 144:ef7eb2e8f9f7 | 449 | case _CMU_LFACLKSEL_LFA_ULFRCO: |
<> | 144:ef7eb2e8f9f7 | 450 | ret = SystemULFRCOClockGet(); |
<> | 144:ef7eb2e8f9f7 | 451 | break; |
<> | 144:ef7eb2e8f9f7 | 452 | |
<> | 144:ef7eb2e8f9f7 | 453 | #if defined( _CMU_LFACLKSEL_LFA_HFCLKLE ) |
<> | 144:ef7eb2e8f9f7 | 454 | case _CMU_LFACLKSEL_LFA_HFCLKLE: |
<> | 144:ef7eb2e8f9f7 | 455 | ret = ((CMU->HFPRESC & _CMU_HFPRESC_HFCLKLEPRESC_MASK) |
<> | 144:ef7eb2e8f9f7 | 456 | == CMU_HFPRESC_HFCLKLEPRESC_DIV4) |
<> | 144:ef7eb2e8f9f7 | 457 | ? SystemCoreClockGet() / 4U |
<> | 144:ef7eb2e8f9f7 | 458 | : SystemCoreClockGet() / 2U; |
<> | 144:ef7eb2e8f9f7 | 459 | break; |
<> | 144:ef7eb2e8f9f7 | 460 | #elif defined( _CMU_LFBCLKSEL_LFB_HFCLKLE ) |
<> | 144:ef7eb2e8f9f7 | 461 | case _CMU_LFBCLKSEL_LFB_HFCLKLE: |
<> | 144:ef7eb2e8f9f7 | 462 | ret = ((CMU->HFPRESC & _CMU_HFPRESC_HFCLKLEPRESC_MASK) |
<> | 144:ef7eb2e8f9f7 | 463 | == CMU_HFPRESC_HFCLKLEPRESC_DIV4) |
<> | 144:ef7eb2e8f9f7 | 464 | ? SystemCoreClockGet() / 4U |
<> | 144:ef7eb2e8f9f7 | 465 | : SystemCoreClockGet() / 2U; |
<> | 144:ef7eb2e8f9f7 | 466 | break; |
<> | 144:ef7eb2e8f9f7 | 467 | #endif |
<> | 144:ef7eb2e8f9f7 | 468 | |
<> | 144:ef7eb2e8f9f7 | 469 | case _CMU_LFACLKSEL_LFA_DISABLED: |
<> | 144:ef7eb2e8f9f7 | 470 | ret = 0; |
<> | 144:ef7eb2e8f9f7 | 471 | break; |
<> | 144:ef7eb2e8f9f7 | 472 | } |
<> | 144:ef7eb2e8f9f7 | 473 | #endif |
<> | 144:ef7eb2e8f9f7 | 474 | |
<> | 144:ef7eb2e8f9f7 | 475 | return ret; |
<> | 144:ef7eb2e8f9f7 | 476 | } |
<> | 144:ef7eb2e8f9f7 | 477 | |
<> | 144:ef7eb2e8f9f7 | 478 | |
<> | 144:ef7eb2e8f9f7 | 479 | #if defined( CMU_CTRL_HFLE ) \ |
<> | 144:ef7eb2e8f9f7 | 480 | && !defined( _EFM32_WONDER_FAMILY ) \ |
<> | 144:ef7eb2e8f9f7 | 481 | && !defined( _EZR32_LEOPARD_FAMILY ) \ |
<> | 144:ef7eb2e8f9f7 | 482 | && !defined( _EZR32_WONDER_FAMILY ) |
<> | 144:ef7eb2e8f9f7 | 483 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 484 | * @brief |
<> | 144:ef7eb2e8f9f7 | 485 | * Return max allowed frequency for low energy peripherals. |
<> | 144:ef7eb2e8f9f7 | 486 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 487 | static uint32_t maxFreqHfle(void) |
<> | 144:ef7eb2e8f9f7 | 488 | { |
<> | 144:ef7eb2e8f9f7 | 489 | uint16_t majorMinorRev; |
<> | 144:ef7eb2e8f9f7 | 490 | |
<> | 144:ef7eb2e8f9f7 | 491 | switch (SYSTEM_GetFamily()) |
<> | 144:ef7eb2e8f9f7 | 492 | { |
<> | 144:ef7eb2e8f9f7 | 493 | case systemPartFamilyEfm32Leopard: |
<> | 144:ef7eb2e8f9f7 | 494 | /* CHIP MAJOR bit [5:0] */ |
<> | 144:ef7eb2e8f9f7 | 495 | majorMinorRev = (((ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK) |
<> | 144:ef7eb2e8f9f7 | 496 | >> _ROMTABLE_PID0_REVMAJOR_SHIFT) << 8); |
<> | 144:ef7eb2e8f9f7 | 497 | /* CHIP MINOR bit [7:4] */ |
<> | 144:ef7eb2e8f9f7 | 498 | majorMinorRev |= (((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK) |
<> | 144:ef7eb2e8f9f7 | 499 | >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) << 4); |
<> | 144:ef7eb2e8f9f7 | 500 | /* CHIP MINOR bit [3:0] */ |
<> | 144:ef7eb2e8f9f7 | 501 | majorMinorRev |= ((ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK) |
<> | 144:ef7eb2e8f9f7 | 502 | >> _ROMTABLE_PID3_REVMINORLSB_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 503 | |
<> | 144:ef7eb2e8f9f7 | 504 | if (majorMinorRev >= 0x0204) |
<> | 144:ef7eb2e8f9f7 | 505 | return 24000000; |
<> | 144:ef7eb2e8f9f7 | 506 | else |
<> | 144:ef7eb2e8f9f7 | 507 | return 32000000; |
<> | 144:ef7eb2e8f9f7 | 508 | |
<> | 144:ef7eb2e8f9f7 | 509 | case systemPartFamilyEfm32Giant: |
<> | 144:ef7eb2e8f9f7 | 510 | return 32000000; |
<> | 144:ef7eb2e8f9f7 | 511 | |
<> | 144:ef7eb2e8f9f7 | 512 | default: |
<> | 144:ef7eb2e8f9f7 | 513 | /* Invalid device family. */ |
<> | 144:ef7eb2e8f9f7 | 514 | EFM_ASSERT(false); |
<> | 144:ef7eb2e8f9f7 | 515 | return 0; |
<> | 144:ef7eb2e8f9f7 | 516 | } |
<> | 144:ef7eb2e8f9f7 | 517 | } |
<> | 144:ef7eb2e8f9f7 | 518 | #endif |
<> | 144:ef7eb2e8f9f7 | 519 | |
<> | 144:ef7eb2e8f9f7 | 520 | |
<> | 144:ef7eb2e8f9f7 | 521 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 522 | * @brief |
<> | 144:ef7eb2e8f9f7 | 523 | * Wait for ongoing sync of register(s) to low frequency domain to complete. |
<> | 144:ef7eb2e8f9f7 | 524 | * |
<> | 144:ef7eb2e8f9f7 | 525 | * @param[in] mask |
<> | 144:ef7eb2e8f9f7 | 526 | * Bitmask corresponding to SYNCBUSY register defined bits, indicating |
<> | 144:ef7eb2e8f9f7 | 527 | * registers that must complete any ongoing synchronization. |
<> | 144:ef7eb2e8f9f7 | 528 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 529 | __STATIC_INLINE void syncReg(uint32_t mask) |
<> | 144:ef7eb2e8f9f7 | 530 | { |
<> | 144:ef7eb2e8f9f7 | 531 | /* Avoid deadlock if modifying the same register twice when freeze mode is */ |
<> | 144:ef7eb2e8f9f7 | 532 | /* activated. */ |
<> | 144:ef7eb2e8f9f7 | 533 | if (CMU->FREEZE & CMU_FREEZE_REGFREEZE) |
<> | 144:ef7eb2e8f9f7 | 534 | return; |
<> | 144:ef7eb2e8f9f7 | 535 | |
<> | 144:ef7eb2e8f9f7 | 536 | /* Wait for any pending previous write operation to have been completed */ |
<> | 144:ef7eb2e8f9f7 | 537 | /* in low frequency domain */ |
<> | 144:ef7eb2e8f9f7 | 538 | while (CMU->SYNCBUSY & mask) |
<> | 144:ef7eb2e8f9f7 | 539 | { |
<> | 144:ef7eb2e8f9f7 | 540 | } |
<> | 144:ef7eb2e8f9f7 | 541 | } |
<> | 144:ef7eb2e8f9f7 | 542 | |
<> | 144:ef7eb2e8f9f7 | 543 | |
<> | 144:ef7eb2e8f9f7 | 544 | #if defined(USB_PRESENT) |
<> | 144:ef7eb2e8f9f7 | 545 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 546 | * @brief |
<> | 144:ef7eb2e8f9f7 | 547 | * Get the USBC frequency |
<> | 144:ef7eb2e8f9f7 | 548 | * |
<> | 144:ef7eb2e8f9f7 | 549 | * @return |
<> | 144:ef7eb2e8f9f7 | 550 | * USBC frequency in Hz |
<> | 144:ef7eb2e8f9f7 | 551 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 552 | static uint32_t usbCClkGet(void) |
<> | 144:ef7eb2e8f9f7 | 553 | { |
<> | 144:ef7eb2e8f9f7 | 554 | uint32_t ret; |
<> | 144:ef7eb2e8f9f7 | 555 | CMU_Select_TypeDef clk; |
<> | 144:ef7eb2e8f9f7 | 556 | |
<> | 144:ef7eb2e8f9f7 | 557 | /* Get selected clock source */ |
<> | 144:ef7eb2e8f9f7 | 558 | clk = CMU_ClockSelectGet(cmuClock_USBC); |
<> | 144:ef7eb2e8f9f7 | 559 | |
<> | 144:ef7eb2e8f9f7 | 560 | switch(clk) |
<> | 144:ef7eb2e8f9f7 | 561 | { |
<> | 144:ef7eb2e8f9f7 | 562 | case cmuSelect_LFXO: |
<> | 144:ef7eb2e8f9f7 | 563 | ret = SystemLFXOClockGet(); |
<> | 144:ef7eb2e8f9f7 | 564 | break; |
<> | 144:ef7eb2e8f9f7 | 565 | case cmuSelect_LFRCO: |
<> | 144:ef7eb2e8f9f7 | 566 | ret = SystemLFRCOClockGet(); |
<> | 144:ef7eb2e8f9f7 | 567 | break; |
<> | 144:ef7eb2e8f9f7 | 568 | case cmuSelect_HFCLK: |
<> | 144:ef7eb2e8f9f7 | 569 | ret = SystemHFClockGet(); |
<> | 144:ef7eb2e8f9f7 | 570 | break; |
<> | 144:ef7eb2e8f9f7 | 571 | default: |
<> | 144:ef7eb2e8f9f7 | 572 | /* Clock is not enabled */ |
<> | 144:ef7eb2e8f9f7 | 573 | ret = 0; |
<> | 144:ef7eb2e8f9f7 | 574 | break; |
<> | 144:ef7eb2e8f9f7 | 575 | } |
<> | 144:ef7eb2e8f9f7 | 576 | return ret; |
<> | 144:ef7eb2e8f9f7 | 577 | } |
<> | 144:ef7eb2e8f9f7 | 578 | #endif |
<> | 144:ef7eb2e8f9f7 | 579 | |
<> | 144:ef7eb2e8f9f7 | 580 | |
<> | 144:ef7eb2e8f9f7 | 581 | /** @endcond */ |
<> | 144:ef7eb2e8f9f7 | 582 | |
<> | 144:ef7eb2e8f9f7 | 583 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 584 | ************************** GLOBAL FUNCTIONS ******************************* |
<> | 144:ef7eb2e8f9f7 | 585 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 586 | |
<> | 144:ef7eb2e8f9f7 | 587 | #if defined( _CMU_AUXHFRCOCTRL_BAND_MASK ) |
<> | 144:ef7eb2e8f9f7 | 588 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 589 | * @brief |
<> | 144:ef7eb2e8f9f7 | 590 | * Get AUXHFRCO band in use. |
<> | 144:ef7eb2e8f9f7 | 591 | * |
<> | 144:ef7eb2e8f9f7 | 592 | * @return |
<> | 144:ef7eb2e8f9f7 | 593 | * AUXHFRCO band in use. |
<> | 144:ef7eb2e8f9f7 | 594 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 595 | CMU_AUXHFRCOBand_TypeDef CMU_AUXHFRCOBandGet(void) |
<> | 144:ef7eb2e8f9f7 | 596 | { |
<> | 144:ef7eb2e8f9f7 | 597 | return (CMU_AUXHFRCOBand_TypeDef)((CMU->AUXHFRCOCTRL |
<> | 144:ef7eb2e8f9f7 | 598 | & _CMU_AUXHFRCOCTRL_BAND_MASK) |
<> | 144:ef7eb2e8f9f7 | 599 | >> _CMU_AUXHFRCOCTRL_BAND_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 600 | } |
<> | 144:ef7eb2e8f9f7 | 601 | #endif /* _CMU_AUXHFRCOCTRL_BAND_MASK */ |
<> | 144:ef7eb2e8f9f7 | 602 | |
<> | 144:ef7eb2e8f9f7 | 603 | |
<> | 144:ef7eb2e8f9f7 | 604 | #if defined( _CMU_AUXHFRCOCTRL_BAND_MASK ) |
<> | 144:ef7eb2e8f9f7 | 605 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 606 | * @brief |
<> | 144:ef7eb2e8f9f7 | 607 | * Set AUXHFRCO band and the tuning value based on the value in the |
<> | 144:ef7eb2e8f9f7 | 608 | * calibration table made during production. |
<> | 144:ef7eb2e8f9f7 | 609 | * |
<> | 144:ef7eb2e8f9f7 | 610 | * @param[in] band |
<> | 144:ef7eb2e8f9f7 | 611 | * AUXHFRCO band to activate. |
<> | 144:ef7eb2e8f9f7 | 612 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 613 | void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOBand_TypeDef band) |
<> | 144:ef7eb2e8f9f7 | 614 | { |
<> | 144:ef7eb2e8f9f7 | 615 | uint32_t tuning; |
<> | 144:ef7eb2e8f9f7 | 616 | |
<> | 144:ef7eb2e8f9f7 | 617 | /* Read tuning value from calibration table */ |
<> | 144:ef7eb2e8f9f7 | 618 | switch (band) |
<> | 144:ef7eb2e8f9f7 | 619 | { |
<> | 144:ef7eb2e8f9f7 | 620 | case cmuAUXHFRCOBand_1MHz: |
<> | 144:ef7eb2e8f9f7 | 621 | tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND1_MASK) |
<> | 144:ef7eb2e8f9f7 | 622 | >> _DEVINFO_AUXHFRCOCAL0_BAND1_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 623 | break; |
<> | 144:ef7eb2e8f9f7 | 624 | |
<> | 144:ef7eb2e8f9f7 | 625 | case cmuAUXHFRCOBand_7MHz: |
<> | 144:ef7eb2e8f9f7 | 626 | tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND7_MASK) |
<> | 144:ef7eb2e8f9f7 | 627 | >> _DEVINFO_AUXHFRCOCAL0_BAND7_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 628 | break; |
<> | 144:ef7eb2e8f9f7 | 629 | |
<> | 144:ef7eb2e8f9f7 | 630 | case cmuAUXHFRCOBand_11MHz: |
<> | 144:ef7eb2e8f9f7 | 631 | tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND11_MASK) |
<> | 144:ef7eb2e8f9f7 | 632 | >> _DEVINFO_AUXHFRCOCAL0_BAND11_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 633 | break; |
<> | 144:ef7eb2e8f9f7 | 634 | |
<> | 144:ef7eb2e8f9f7 | 635 | case cmuAUXHFRCOBand_14MHz: |
<> | 144:ef7eb2e8f9f7 | 636 | tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND14_MASK) |
<> | 144:ef7eb2e8f9f7 | 637 | >> _DEVINFO_AUXHFRCOCAL0_BAND14_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 638 | break; |
<> | 144:ef7eb2e8f9f7 | 639 | |
<> | 144:ef7eb2e8f9f7 | 640 | case cmuAUXHFRCOBand_21MHz: |
<> | 144:ef7eb2e8f9f7 | 641 | tuning = (DEVINFO->AUXHFRCOCAL1 & _DEVINFO_AUXHFRCOCAL1_BAND21_MASK) |
<> | 144:ef7eb2e8f9f7 | 642 | >> _DEVINFO_AUXHFRCOCAL1_BAND21_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 643 | break; |
<> | 144:ef7eb2e8f9f7 | 644 | |
<> | 144:ef7eb2e8f9f7 | 645 | #if defined( _CMU_AUXHFRCOCTRL_BAND_28MHZ ) |
<> | 144:ef7eb2e8f9f7 | 646 | case cmuAUXHFRCOBand_28MHz: |
<> | 144:ef7eb2e8f9f7 | 647 | tuning = (DEVINFO->AUXHFRCOCAL1 & _DEVINFO_AUXHFRCOCAL1_BAND28_MASK) |
<> | 144:ef7eb2e8f9f7 | 648 | >> _DEVINFO_AUXHFRCOCAL1_BAND28_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 649 | break; |
<> | 144:ef7eb2e8f9f7 | 650 | #endif |
<> | 144:ef7eb2e8f9f7 | 651 | |
<> | 144:ef7eb2e8f9f7 | 652 | default: |
<> | 144:ef7eb2e8f9f7 | 653 | EFM_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 654 | return; |
<> | 144:ef7eb2e8f9f7 | 655 | } |
<> | 144:ef7eb2e8f9f7 | 656 | |
<> | 144:ef7eb2e8f9f7 | 657 | /* Set band/tuning */ |
<> | 144:ef7eb2e8f9f7 | 658 | CMU->AUXHFRCOCTRL = (CMU->AUXHFRCOCTRL & |
<> | 144:ef7eb2e8f9f7 | 659 | ~(_CMU_AUXHFRCOCTRL_BAND_MASK |
<> | 144:ef7eb2e8f9f7 | 660 | | _CMU_AUXHFRCOCTRL_TUNING_MASK)) |
<> | 144:ef7eb2e8f9f7 | 661 | | (band << _CMU_AUXHFRCOCTRL_BAND_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 662 | | (tuning << _CMU_AUXHFRCOCTRL_TUNING_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 663 | |
<> | 144:ef7eb2e8f9f7 | 664 | } |
<> | 144:ef7eb2e8f9f7 | 665 | #endif /* _CMU_AUXHFRCOCTRL_BAND_MASK */ |
<> | 144:ef7eb2e8f9f7 | 666 | |
<> | 144:ef7eb2e8f9f7 | 667 | |
<> | 144:ef7eb2e8f9f7 | 668 | #if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK ) |
<> | 144:ef7eb2e8f9f7 | 669 | /**************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 670 | * @brief |
<> | 144:ef7eb2e8f9f7 | 671 | * Get a pointer to the AUXHFRCO frequency calibration word in DEVINFO |
<> | 144:ef7eb2e8f9f7 | 672 | * |
<> | 144:ef7eb2e8f9f7 | 673 | * @param[in] freq |
<> | 144:ef7eb2e8f9f7 | 674 | * Frequency in Hz |
<> | 144:ef7eb2e8f9f7 | 675 | * |
<> | 144:ef7eb2e8f9f7 | 676 | * @return |
<> | 144:ef7eb2e8f9f7 | 677 | * AUXHFRCO calibration word for a given frequency |
<> | 144:ef7eb2e8f9f7 | 678 | *****************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 679 | static uint32_t CMU_AUXHFRCODevinfoGet(CMU_AUXHFRCOFreq_TypeDef freq) |
<> | 144:ef7eb2e8f9f7 | 680 | { |
<> | 144:ef7eb2e8f9f7 | 681 | switch (freq) |
<> | 144:ef7eb2e8f9f7 | 682 | { |
<> | 144:ef7eb2e8f9f7 | 683 | /* 1, 2 and 4MHz share the same calibration word */ |
<> | 144:ef7eb2e8f9f7 | 684 | case cmuAUXHFRCOFreq_1M0Hz: |
<> | 144:ef7eb2e8f9f7 | 685 | case cmuAUXHFRCOFreq_2M0Hz: |
<> | 144:ef7eb2e8f9f7 | 686 | case cmuAUXHFRCOFreq_4M0Hz: |
<> | 144:ef7eb2e8f9f7 | 687 | return DEVINFO->AUXHFRCOCAL0; |
<> | 144:ef7eb2e8f9f7 | 688 | |
<> | 144:ef7eb2e8f9f7 | 689 | case cmuAUXHFRCOFreq_7M0Hz: |
<> | 144:ef7eb2e8f9f7 | 690 | return DEVINFO->AUXHFRCOCAL3; |
<> | 144:ef7eb2e8f9f7 | 691 | |
<> | 144:ef7eb2e8f9f7 | 692 | case cmuAUXHFRCOFreq_13M0Hz: |
<> | 144:ef7eb2e8f9f7 | 693 | return DEVINFO->AUXHFRCOCAL6; |
<> | 144:ef7eb2e8f9f7 | 694 | |
<> | 144:ef7eb2e8f9f7 | 695 | case cmuAUXHFRCOFreq_16M0Hz: |
<> | 144:ef7eb2e8f9f7 | 696 | return DEVINFO->AUXHFRCOCAL7; |
<> | 144:ef7eb2e8f9f7 | 697 | |
<> | 144:ef7eb2e8f9f7 | 698 | case cmuAUXHFRCOFreq_19M0Hz: |
<> | 144:ef7eb2e8f9f7 | 699 | return DEVINFO->AUXHFRCOCAL8; |
<> | 144:ef7eb2e8f9f7 | 700 | |
<> | 144:ef7eb2e8f9f7 | 701 | case cmuAUXHFRCOFreq_26M0Hz: |
<> | 144:ef7eb2e8f9f7 | 702 | return DEVINFO->AUXHFRCOCAL10; |
<> | 144:ef7eb2e8f9f7 | 703 | |
<> | 144:ef7eb2e8f9f7 | 704 | case cmuAUXHFRCOFreq_32M0Hz: |
<> | 144:ef7eb2e8f9f7 | 705 | return DEVINFO->AUXHFRCOCAL11; |
<> | 144:ef7eb2e8f9f7 | 706 | |
<> | 144:ef7eb2e8f9f7 | 707 | case cmuAUXHFRCOFreq_38M0Hz: |
<> | 144:ef7eb2e8f9f7 | 708 | return DEVINFO->AUXHFRCOCAL12; |
<> | 144:ef7eb2e8f9f7 | 709 | |
<> | 144:ef7eb2e8f9f7 | 710 | default: /* cmuAUXHFRCOFreq_UserDefined */ |
<> | 144:ef7eb2e8f9f7 | 711 | return 0; |
<> | 144:ef7eb2e8f9f7 | 712 | } |
<> | 144:ef7eb2e8f9f7 | 713 | } |
<> | 144:ef7eb2e8f9f7 | 714 | #endif /* _CMU_AUXHFRCOCTRL_FREQRANGE_MASK */ |
<> | 144:ef7eb2e8f9f7 | 715 | |
<> | 144:ef7eb2e8f9f7 | 716 | |
<> | 144:ef7eb2e8f9f7 | 717 | #if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK ) |
<> | 144:ef7eb2e8f9f7 | 718 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 719 | * @brief |
<> | 144:ef7eb2e8f9f7 | 720 | * Get AUXHFRCO frequency enumeration in use |
<> | 144:ef7eb2e8f9f7 | 721 | * |
<> | 144:ef7eb2e8f9f7 | 722 | * @return |
<> | 144:ef7eb2e8f9f7 | 723 | * AUXHFRCO frequency enumeration in use |
<> | 144:ef7eb2e8f9f7 | 724 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 725 | CMU_AUXHFRCOFreq_TypeDef CMU_AUXHFRCOFreqGet(void) |
<> | 144:ef7eb2e8f9f7 | 726 | { |
<> | 144:ef7eb2e8f9f7 | 727 | return auxHfrcoFreq; |
<> | 144:ef7eb2e8f9f7 | 728 | } |
<> | 144:ef7eb2e8f9f7 | 729 | #endif /* _CMU_AUXHFRCOCTRL_FREQRANGE_MASK */ |
<> | 144:ef7eb2e8f9f7 | 730 | |
<> | 144:ef7eb2e8f9f7 | 731 | |
<> | 144:ef7eb2e8f9f7 | 732 | #if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK ) |
<> | 144:ef7eb2e8f9f7 | 733 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 734 | * @brief |
<> | 144:ef7eb2e8f9f7 | 735 | * Set AUXHFRCO calibration for the selected target frequency |
<> | 144:ef7eb2e8f9f7 | 736 | * |
<> | 144:ef7eb2e8f9f7 | 737 | * @param[in] frequency |
<> | 144:ef7eb2e8f9f7 | 738 | * AUXHFRCO frequency to set |
<> | 144:ef7eb2e8f9f7 | 739 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 740 | void CMU_AUXHFRCOFreqSet(CMU_AUXHFRCOFreq_TypeDef freq) |
<> | 144:ef7eb2e8f9f7 | 741 | { |
<> | 144:ef7eb2e8f9f7 | 742 | uint32_t freqCal; |
<> | 144:ef7eb2e8f9f7 | 743 | |
<> | 144:ef7eb2e8f9f7 | 744 | /* Get DEVINFO index, set global auxHfrcoFreq */ |
<> | 144:ef7eb2e8f9f7 | 745 | freqCal = CMU_AUXHFRCODevinfoGet(freq); |
<> | 144:ef7eb2e8f9f7 | 746 | EFM_ASSERT((freqCal != 0) && (freqCal != UINT_MAX)); |
<> | 144:ef7eb2e8f9f7 | 747 | auxHfrcoFreq = freq; |
<> | 144:ef7eb2e8f9f7 | 748 | |
<> | 144:ef7eb2e8f9f7 | 749 | /* Wait for any previous sync to complete, and then set calibration data |
<> | 144:ef7eb2e8f9f7 | 750 | for the selected frequency. */ |
<> | 144:ef7eb2e8f9f7 | 751 | while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT)); |
<> | 144:ef7eb2e8f9f7 | 752 | |
<> | 144:ef7eb2e8f9f7 | 753 | /* Set divider in AUXHFRCOCTRL for 1, 2 and 4MHz */ |
<> | 144:ef7eb2e8f9f7 | 754 | switch(freq) |
<> | 144:ef7eb2e8f9f7 | 755 | { |
<> | 144:ef7eb2e8f9f7 | 756 | case cmuAUXHFRCOFreq_1M0Hz: |
<> | 144:ef7eb2e8f9f7 | 757 | freqCal = (freqCal & ~_CMU_AUXHFRCOCTRL_CLKDIV_MASK) |
<> | 144:ef7eb2e8f9f7 | 758 | | CMU_AUXHFRCOCTRL_CLKDIV_DIV4; |
<> | 144:ef7eb2e8f9f7 | 759 | break; |
<> | 144:ef7eb2e8f9f7 | 760 | |
<> | 144:ef7eb2e8f9f7 | 761 | case cmuAUXHFRCOFreq_2M0Hz: |
<> | 144:ef7eb2e8f9f7 | 762 | freqCal = (freqCal & ~_CMU_AUXHFRCOCTRL_CLKDIV_MASK) |
<> | 144:ef7eb2e8f9f7 | 763 | | CMU_AUXHFRCOCTRL_CLKDIV_DIV2; |
<> | 144:ef7eb2e8f9f7 | 764 | break; |
<> | 144:ef7eb2e8f9f7 | 765 | |
<> | 144:ef7eb2e8f9f7 | 766 | case cmuAUXHFRCOFreq_4M0Hz: |
<> | 144:ef7eb2e8f9f7 | 767 | freqCal = (freqCal & ~_CMU_AUXHFRCOCTRL_CLKDIV_MASK) |
<> | 144:ef7eb2e8f9f7 | 768 | | CMU_AUXHFRCOCTRL_CLKDIV_DIV1; |
<> | 144:ef7eb2e8f9f7 | 769 | break; |
<> | 144:ef7eb2e8f9f7 | 770 | |
<> | 144:ef7eb2e8f9f7 | 771 | default: |
<> | 144:ef7eb2e8f9f7 | 772 | break; |
<> | 144:ef7eb2e8f9f7 | 773 | } |
<> | 144:ef7eb2e8f9f7 | 774 | CMU->AUXHFRCOCTRL = freqCal; |
<> | 144:ef7eb2e8f9f7 | 775 | } |
<> | 144:ef7eb2e8f9f7 | 776 | #endif /* _CMU_AUXHFRCOCTRL_FREQRANGE_MASK */ |
<> | 144:ef7eb2e8f9f7 | 777 | |
<> | 144:ef7eb2e8f9f7 | 778 | |
<> | 144:ef7eb2e8f9f7 | 779 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 780 | * @brief |
<> | 144:ef7eb2e8f9f7 | 781 | * Calibrate clock. |
<> | 144:ef7eb2e8f9f7 | 782 | * |
<> | 144:ef7eb2e8f9f7 | 783 | * @details |
<> | 144:ef7eb2e8f9f7 | 784 | * Run a calibration for HFCLK against a selectable reference clock. Please |
<> | 144:ef7eb2e8f9f7 | 785 | * refer to the reference manual, CMU chapter, for further details. |
<> | 144:ef7eb2e8f9f7 | 786 | * |
<> | 144:ef7eb2e8f9f7 | 787 | * @note |
<> | 144:ef7eb2e8f9f7 | 788 | * This function will not return until calibration measurement is completed. |
<> | 144:ef7eb2e8f9f7 | 789 | * |
<> | 144:ef7eb2e8f9f7 | 790 | * @param[in] HFCycles |
<> | 144:ef7eb2e8f9f7 | 791 | * The number of HFCLK cycles to run calibration. Increasing this number |
<> | 144:ef7eb2e8f9f7 | 792 | * increases precision, but the calibration will take more time. |
<> | 144:ef7eb2e8f9f7 | 793 | * |
<> | 144:ef7eb2e8f9f7 | 794 | * @param[in] ref |
<> | 144:ef7eb2e8f9f7 | 795 | * The reference clock used to compare HFCLK with. |
<> | 144:ef7eb2e8f9f7 | 796 | * |
<> | 144:ef7eb2e8f9f7 | 797 | * @return |
<> | 144:ef7eb2e8f9f7 | 798 | * The number of ticks the reference clock after HFCycles ticks on the HF |
<> | 144:ef7eb2e8f9f7 | 799 | * clock. |
<> | 144:ef7eb2e8f9f7 | 800 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 801 | uint32_t CMU_Calibrate(uint32_t HFCycles, CMU_Osc_TypeDef ref) |
<> | 144:ef7eb2e8f9f7 | 802 | { |
<> | 144:ef7eb2e8f9f7 | 803 | EFM_ASSERT(HFCycles <= (_CMU_CALCNT_CALCNT_MASK >> _CMU_CALCNT_CALCNT_SHIFT)); |
<> | 144:ef7eb2e8f9f7 | 804 | |
<> | 144:ef7eb2e8f9f7 | 805 | /* Set reference clock source */ |
<> | 144:ef7eb2e8f9f7 | 806 | switch (ref) |
<> | 144:ef7eb2e8f9f7 | 807 | { |
<> | 144:ef7eb2e8f9f7 | 808 | case cmuOsc_LFXO: |
<> | 144:ef7eb2e8f9f7 | 809 | CMU->CALCTRL = CMU_CALCTRL_UPSEL_LFXO; |
<> | 144:ef7eb2e8f9f7 | 810 | break; |
<> | 144:ef7eb2e8f9f7 | 811 | |
<> | 144:ef7eb2e8f9f7 | 812 | case cmuOsc_LFRCO: |
<> | 144:ef7eb2e8f9f7 | 813 | CMU->CALCTRL = CMU_CALCTRL_UPSEL_LFRCO; |
<> | 144:ef7eb2e8f9f7 | 814 | break; |
<> | 144:ef7eb2e8f9f7 | 815 | |
<> | 144:ef7eb2e8f9f7 | 816 | case cmuOsc_HFXO: |
<> | 144:ef7eb2e8f9f7 | 817 | CMU->CALCTRL = CMU_CALCTRL_UPSEL_HFXO; |
<> | 144:ef7eb2e8f9f7 | 818 | break; |
<> | 144:ef7eb2e8f9f7 | 819 | |
<> | 144:ef7eb2e8f9f7 | 820 | case cmuOsc_HFRCO: |
<> | 144:ef7eb2e8f9f7 | 821 | CMU->CALCTRL = CMU_CALCTRL_UPSEL_HFRCO; |
<> | 144:ef7eb2e8f9f7 | 822 | break; |
<> | 144:ef7eb2e8f9f7 | 823 | |
<> | 144:ef7eb2e8f9f7 | 824 | case cmuOsc_AUXHFRCO: |
<> | 144:ef7eb2e8f9f7 | 825 | CMU->CALCTRL = CMU_CALCTRL_UPSEL_AUXHFRCO; |
<> | 144:ef7eb2e8f9f7 | 826 | break; |
<> | 144:ef7eb2e8f9f7 | 827 | |
<> | 144:ef7eb2e8f9f7 | 828 | default: |
<> | 144:ef7eb2e8f9f7 | 829 | EFM_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 830 | return 0; |
<> | 144:ef7eb2e8f9f7 | 831 | } |
<> | 144:ef7eb2e8f9f7 | 832 | |
<> | 144:ef7eb2e8f9f7 | 833 | /* Set top value */ |
<> | 144:ef7eb2e8f9f7 | 834 | CMU->CALCNT = HFCycles; |
<> | 144:ef7eb2e8f9f7 | 835 | |
<> | 144:ef7eb2e8f9f7 | 836 | /* Start calibration */ |
<> | 144:ef7eb2e8f9f7 | 837 | CMU->CMD = CMU_CMD_CALSTART; |
<> | 144:ef7eb2e8f9f7 | 838 | |
<> | 144:ef7eb2e8f9f7 | 839 | #if defined( CMU_STATUS_CALRDY ) |
<> | 144:ef7eb2e8f9f7 | 840 | /* Wait until calibration completes */ |
<> | 144:ef7eb2e8f9f7 | 841 | while (!BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALRDY_SHIFT)) |
<> | 144:ef7eb2e8f9f7 | 842 | { |
<> | 144:ef7eb2e8f9f7 | 843 | } |
<> | 144:ef7eb2e8f9f7 | 844 | #else |
<> | 144:ef7eb2e8f9f7 | 845 | /* Wait until calibration completes */ |
<> | 144:ef7eb2e8f9f7 | 846 | while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALBSY_SHIFT)) |
<> | 144:ef7eb2e8f9f7 | 847 | { |
<> | 144:ef7eb2e8f9f7 | 848 | } |
<> | 144:ef7eb2e8f9f7 | 849 | #endif |
<> | 144:ef7eb2e8f9f7 | 850 | |
<> | 144:ef7eb2e8f9f7 | 851 | return CMU->CALCNT; |
<> | 144:ef7eb2e8f9f7 | 852 | } |
<> | 144:ef7eb2e8f9f7 | 853 | |
<> | 144:ef7eb2e8f9f7 | 854 | |
<> | 144:ef7eb2e8f9f7 | 855 | #if defined( _CMU_CALCTRL_UPSEL_MASK ) && defined( _CMU_CALCTRL_DOWNSEL_MASK ) |
<> | 144:ef7eb2e8f9f7 | 856 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 857 | * @brief |
<> | 144:ef7eb2e8f9f7 | 858 | * Configure clock calibration |
<> | 144:ef7eb2e8f9f7 | 859 | * |
<> | 144:ef7eb2e8f9f7 | 860 | * @details |
<> | 144:ef7eb2e8f9f7 | 861 | * Configure a calibration for a selectable clock source against another |
<> | 144:ef7eb2e8f9f7 | 862 | * selectable reference clock. |
<> | 144:ef7eb2e8f9f7 | 863 | * Refer to the reference manual, CMU chapter, for further details. |
<> | 144:ef7eb2e8f9f7 | 864 | * |
<> | 144:ef7eb2e8f9f7 | 865 | * @note |
<> | 144:ef7eb2e8f9f7 | 866 | * After configuration, a call to CMU_CalibrateStart() is required, and |
<> | 144:ef7eb2e8f9f7 | 867 | * the resulting calibration value can be read out with the |
<> | 144:ef7eb2e8f9f7 | 868 | * CMU_CalibrateCountGet() function call. |
<> | 144:ef7eb2e8f9f7 | 869 | * |
<> | 144:ef7eb2e8f9f7 | 870 | * @param[in] downCycles |
<> | 144:ef7eb2e8f9f7 | 871 | * The number of downSel clock cycles to run calibration. Increasing this |
<> | 144:ef7eb2e8f9f7 | 872 | * number increases precision, but the calibration will take more time. |
<> | 144:ef7eb2e8f9f7 | 873 | * |
<> | 144:ef7eb2e8f9f7 | 874 | * @param[in] downSel |
<> | 144:ef7eb2e8f9f7 | 875 | * The clock which will be counted down downCycles |
<> | 144:ef7eb2e8f9f7 | 876 | * |
<> | 144:ef7eb2e8f9f7 | 877 | * @param[in] upSel |
<> | 144:ef7eb2e8f9f7 | 878 | * The reference clock, the number of cycles generated by this clock will |
<> | 144:ef7eb2e8f9f7 | 879 | * be counted and added up, the result can be given with the |
<> | 144:ef7eb2e8f9f7 | 880 | * CMU_CalibrateCountGet() function call. |
<> | 144:ef7eb2e8f9f7 | 881 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 882 | void CMU_CalibrateConfig(uint32_t downCycles, CMU_Osc_TypeDef downSel, |
<> | 144:ef7eb2e8f9f7 | 883 | CMU_Osc_TypeDef upSel) |
<> | 144:ef7eb2e8f9f7 | 884 | { |
<> | 144:ef7eb2e8f9f7 | 885 | /* Keep untouched configuration settings */ |
<> | 144:ef7eb2e8f9f7 | 886 | uint32_t calCtrl = CMU->CALCTRL |
<> | 144:ef7eb2e8f9f7 | 887 | & ~(_CMU_CALCTRL_UPSEL_MASK | _CMU_CALCTRL_DOWNSEL_MASK); |
<> | 144:ef7eb2e8f9f7 | 888 | |
<> | 144:ef7eb2e8f9f7 | 889 | /* 20 bits of precision to calibration count register */ |
<> | 144:ef7eb2e8f9f7 | 890 | EFM_ASSERT(downCycles <= (_CMU_CALCNT_CALCNT_MASK >> _CMU_CALCNT_CALCNT_SHIFT)); |
<> | 144:ef7eb2e8f9f7 | 891 | |
<> | 144:ef7eb2e8f9f7 | 892 | /* Set down counting clock source - down counter */ |
<> | 144:ef7eb2e8f9f7 | 893 | switch (downSel) |
<> | 144:ef7eb2e8f9f7 | 894 | { |
<> | 144:ef7eb2e8f9f7 | 895 | case cmuOsc_LFXO: |
<> | 144:ef7eb2e8f9f7 | 896 | calCtrl |= CMU_CALCTRL_DOWNSEL_LFXO; |
<> | 144:ef7eb2e8f9f7 | 897 | break; |
<> | 144:ef7eb2e8f9f7 | 898 | |
<> | 144:ef7eb2e8f9f7 | 899 | case cmuOsc_LFRCO: |
<> | 144:ef7eb2e8f9f7 | 900 | calCtrl |= CMU_CALCTRL_DOWNSEL_LFRCO; |
<> | 144:ef7eb2e8f9f7 | 901 | break; |
<> | 144:ef7eb2e8f9f7 | 902 | |
<> | 144:ef7eb2e8f9f7 | 903 | case cmuOsc_HFXO: |
<> | 144:ef7eb2e8f9f7 | 904 | calCtrl |= CMU_CALCTRL_DOWNSEL_HFXO; |
<> | 144:ef7eb2e8f9f7 | 905 | break; |
<> | 144:ef7eb2e8f9f7 | 906 | |
<> | 144:ef7eb2e8f9f7 | 907 | case cmuOsc_HFRCO: |
<> | 144:ef7eb2e8f9f7 | 908 | calCtrl |= CMU_CALCTRL_DOWNSEL_HFRCO; |
<> | 144:ef7eb2e8f9f7 | 909 | break; |
<> | 144:ef7eb2e8f9f7 | 910 | |
<> | 144:ef7eb2e8f9f7 | 911 | case cmuOsc_AUXHFRCO: |
<> | 144:ef7eb2e8f9f7 | 912 | calCtrl |= CMU_CALCTRL_DOWNSEL_AUXHFRCO; |
<> | 144:ef7eb2e8f9f7 | 913 | break; |
<> | 144:ef7eb2e8f9f7 | 914 | |
<> | 144:ef7eb2e8f9f7 | 915 | default: |
<> | 144:ef7eb2e8f9f7 | 916 | EFM_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 917 | break; |
<> | 144:ef7eb2e8f9f7 | 918 | } |
<> | 144:ef7eb2e8f9f7 | 919 | |
<> | 144:ef7eb2e8f9f7 | 920 | /* Set top value to be counted down by the downSel clock */ |
<> | 144:ef7eb2e8f9f7 | 921 | CMU->CALCNT = downCycles; |
<> | 144:ef7eb2e8f9f7 | 922 | |
<> | 144:ef7eb2e8f9f7 | 923 | /* Set reference clock source - up counter */ |
<> | 144:ef7eb2e8f9f7 | 924 | switch (upSel) |
<> | 144:ef7eb2e8f9f7 | 925 | { |
<> | 144:ef7eb2e8f9f7 | 926 | case cmuOsc_LFXO: |
<> | 144:ef7eb2e8f9f7 | 927 | calCtrl |= CMU_CALCTRL_UPSEL_LFXO; |
<> | 144:ef7eb2e8f9f7 | 928 | break; |
<> | 144:ef7eb2e8f9f7 | 929 | |
<> | 144:ef7eb2e8f9f7 | 930 | case cmuOsc_LFRCO: |
<> | 144:ef7eb2e8f9f7 | 931 | calCtrl |= CMU_CALCTRL_UPSEL_LFRCO; |
<> | 144:ef7eb2e8f9f7 | 932 | break; |
<> | 144:ef7eb2e8f9f7 | 933 | |
<> | 144:ef7eb2e8f9f7 | 934 | case cmuOsc_HFXO: |
<> | 144:ef7eb2e8f9f7 | 935 | calCtrl |= CMU_CALCTRL_UPSEL_HFXO; |
<> | 144:ef7eb2e8f9f7 | 936 | break; |
<> | 144:ef7eb2e8f9f7 | 937 | |
<> | 144:ef7eb2e8f9f7 | 938 | case cmuOsc_HFRCO: |
<> | 144:ef7eb2e8f9f7 | 939 | calCtrl |= CMU_CALCTRL_UPSEL_HFRCO; |
<> | 144:ef7eb2e8f9f7 | 940 | break; |
<> | 144:ef7eb2e8f9f7 | 941 | |
<> | 144:ef7eb2e8f9f7 | 942 | case cmuOsc_AUXHFRCO: |
<> | 144:ef7eb2e8f9f7 | 943 | calCtrl |= CMU_CALCTRL_UPSEL_AUXHFRCO; |
<> | 144:ef7eb2e8f9f7 | 944 | break; |
<> | 144:ef7eb2e8f9f7 | 945 | |
<> | 144:ef7eb2e8f9f7 | 946 | default: |
<> | 144:ef7eb2e8f9f7 | 947 | EFM_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 948 | break; |
<> | 144:ef7eb2e8f9f7 | 949 | } |
<> | 144:ef7eb2e8f9f7 | 950 | |
<> | 144:ef7eb2e8f9f7 | 951 | CMU->CALCTRL = calCtrl; |
<> | 144:ef7eb2e8f9f7 | 952 | } |
<> | 144:ef7eb2e8f9f7 | 953 | #endif |
<> | 144:ef7eb2e8f9f7 | 954 | |
<> | 144:ef7eb2e8f9f7 | 955 | |
<> | 144:ef7eb2e8f9f7 | 956 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 957 | * @brief |
<> | 144:ef7eb2e8f9f7 | 958 | * Get calibration count register |
<> | 144:ef7eb2e8f9f7 | 959 | * @note |
<> | 144:ef7eb2e8f9f7 | 960 | * If continuous calibrartion mode is active, calibration busy will almost |
<> | 144:ef7eb2e8f9f7 | 961 | * always be off, and we just need to read the value, where the normal case |
<> | 144:ef7eb2e8f9f7 | 962 | * would be that this function call has been triggered by the CALRDY |
<> | 144:ef7eb2e8f9f7 | 963 | * interrupt flag. |
<> | 144:ef7eb2e8f9f7 | 964 | * @return |
<> | 144:ef7eb2e8f9f7 | 965 | * Calibration count, the number of UPSEL clocks (see CMU_CalibrateConfig) |
<> | 144:ef7eb2e8f9f7 | 966 | * in the period of DOWNSEL oscillator clock cycles configured by a previous |
<> | 144:ef7eb2e8f9f7 | 967 | * write operation to CMU->CALCNT |
<> | 144:ef7eb2e8f9f7 | 968 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 969 | uint32_t CMU_CalibrateCountGet(void) |
<> | 144:ef7eb2e8f9f7 | 970 | { |
<> | 144:ef7eb2e8f9f7 | 971 | /* Wait until calibration completes, UNLESS continuous calibration mode is */ |
<> | 144:ef7eb2e8f9f7 | 972 | /* active */ |
<> | 144:ef7eb2e8f9f7 | 973 | #if defined( CMU_CALCTRL_CONT ) |
<> | 144:ef7eb2e8f9f7 | 974 | if (!BUS_RegBitRead(&CMU->CALCTRL, _CMU_CALCTRL_CONT_SHIFT)) |
<> | 144:ef7eb2e8f9f7 | 975 | { |
<> | 144:ef7eb2e8f9f7 | 976 | #if defined( CMU_STATUS_CALRDY ) |
<> | 144:ef7eb2e8f9f7 | 977 | /* Wait until calibration completes */ |
<> | 144:ef7eb2e8f9f7 | 978 | while (!BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALRDY_SHIFT)) |
<> | 144:ef7eb2e8f9f7 | 979 | { |
<> | 144:ef7eb2e8f9f7 | 980 | } |
<> | 144:ef7eb2e8f9f7 | 981 | #else |
<> | 144:ef7eb2e8f9f7 | 982 | /* Wait until calibration completes */ |
<> | 144:ef7eb2e8f9f7 | 983 | while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALBSY_SHIFT)) |
<> | 144:ef7eb2e8f9f7 | 984 | { |
<> | 144:ef7eb2e8f9f7 | 985 | } |
<> | 144:ef7eb2e8f9f7 | 986 | #endif |
<> | 144:ef7eb2e8f9f7 | 987 | } |
<> | 144:ef7eb2e8f9f7 | 988 | #else |
<> | 144:ef7eb2e8f9f7 | 989 | while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALBSY_SHIFT)) |
<> | 144:ef7eb2e8f9f7 | 990 | { |
<> | 144:ef7eb2e8f9f7 | 991 | } |
<> | 144:ef7eb2e8f9f7 | 992 | #endif |
<> | 144:ef7eb2e8f9f7 | 993 | return CMU->CALCNT; |
<> | 144:ef7eb2e8f9f7 | 994 | } |
<> | 144:ef7eb2e8f9f7 | 995 | |
<> | 144:ef7eb2e8f9f7 | 996 | |
<> | 144:ef7eb2e8f9f7 | 997 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 998 | * @brief |
<> | 144:ef7eb2e8f9f7 | 999 | * Get clock divisor/prescaler. |
<> | 144:ef7eb2e8f9f7 | 1000 | * |
<> | 144:ef7eb2e8f9f7 | 1001 | * @param[in] clock |
<> | 144:ef7eb2e8f9f7 | 1002 | * Clock point to get divisor/prescaler for. Notice that not all clock points |
<> | 144:ef7eb2e8f9f7 | 1003 | * have a divisor/prescaler. Please refer to CMU overview in reference manual. |
<> | 144:ef7eb2e8f9f7 | 1004 | * |
<> | 144:ef7eb2e8f9f7 | 1005 | * @return |
<> | 144:ef7eb2e8f9f7 | 1006 | * The current clock point divisor/prescaler. 1 is returned |
<> | 144:ef7eb2e8f9f7 | 1007 | * if @p clock specifies a clock point without a divisor/prescaler. |
<> | 144:ef7eb2e8f9f7 | 1008 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 1009 | CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock) |
<> | 144:ef7eb2e8f9f7 | 1010 | { |
<> | 144:ef7eb2e8f9f7 | 1011 | #if defined( _SILICON_LABS_32B_PLATFORM_2 ) |
<> | 144:ef7eb2e8f9f7 | 1012 | return 1 + (uint32_t)CMU_ClockPrescGet(clock); |
<> | 144:ef7eb2e8f9f7 | 1013 | |
<> | 144:ef7eb2e8f9f7 | 1014 | #elif defined( _SILICON_LABS_32B_PLATFORM_1 ) |
<> | 144:ef7eb2e8f9f7 | 1015 | uint32_t divReg; |
<> | 144:ef7eb2e8f9f7 | 1016 | CMU_ClkDiv_TypeDef ret; |
<> | 144:ef7eb2e8f9f7 | 1017 | |
<> | 144:ef7eb2e8f9f7 | 1018 | /* Get divisor reg id */ |
<> | 144:ef7eb2e8f9f7 | 1019 | divReg = (clock >> CMU_DIV_REG_POS) & CMU_DIV_REG_MASK; |
<> | 144:ef7eb2e8f9f7 | 1020 | |
<> | 144:ef7eb2e8f9f7 | 1021 | switch (divReg) |
<> | 144:ef7eb2e8f9f7 | 1022 | { |
<> | 144:ef7eb2e8f9f7 | 1023 | #if defined( _CMU_CTRL_HFCLKDIV_MASK ) |
<> | 144:ef7eb2e8f9f7 | 1024 | case CMU_HFCLKDIV_REG: |
<> | 144:ef7eb2e8f9f7 | 1025 | ret = 1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK) |
<> | 144:ef7eb2e8f9f7 | 1026 | >> _CMU_CTRL_HFCLKDIV_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1027 | break; |
<> | 144:ef7eb2e8f9f7 | 1028 | #endif |
<> | 144:ef7eb2e8f9f7 | 1029 | |
<> | 144:ef7eb2e8f9f7 | 1030 | case CMU_HFPERCLKDIV_REG: |
<> | 144:ef7eb2e8f9f7 | 1031 | ret = (CMU_ClkDiv_TypeDef)((CMU->HFPERCLKDIV |
<> | 144:ef7eb2e8f9f7 | 1032 | & _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK) |
<> | 144:ef7eb2e8f9f7 | 1033 | >> _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1034 | ret = CMU_Log2ToDiv(ret); |
<> | 144:ef7eb2e8f9f7 | 1035 | break; |
<> | 144:ef7eb2e8f9f7 | 1036 | |
<> | 144:ef7eb2e8f9f7 | 1037 | case CMU_HFCORECLKDIV_REG: |
<> | 144:ef7eb2e8f9f7 | 1038 | ret = (CMU_ClkDiv_TypeDef)((CMU->HFCORECLKDIV |
<> | 144:ef7eb2e8f9f7 | 1039 | & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) |
<> | 144:ef7eb2e8f9f7 | 1040 | >> _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1041 | ret = CMU_Log2ToDiv(ret); |
<> | 144:ef7eb2e8f9f7 | 1042 | break; |
<> | 144:ef7eb2e8f9f7 | 1043 | |
<> | 144:ef7eb2e8f9f7 | 1044 | case CMU_LFAPRESC0_REG: |
<> | 144:ef7eb2e8f9f7 | 1045 | switch (clock) |
<> | 144:ef7eb2e8f9f7 | 1046 | { |
<> | 144:ef7eb2e8f9f7 | 1047 | case cmuClock_RTC: |
<> | 144:ef7eb2e8f9f7 | 1048 | ret = (CMU_ClkDiv_TypeDef)((CMU->LFAPRESC0 & _CMU_LFAPRESC0_RTC_MASK) |
<> | 144:ef7eb2e8f9f7 | 1049 | >> _CMU_LFAPRESC0_RTC_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1050 | ret = CMU_Log2ToDiv(ret); |
<> | 144:ef7eb2e8f9f7 | 1051 | break; |
<> | 144:ef7eb2e8f9f7 | 1052 | |
<> | 144:ef7eb2e8f9f7 | 1053 | #if defined(_CMU_LFAPRESC0_LETIMER0_MASK) |
<> | 144:ef7eb2e8f9f7 | 1054 | case cmuClock_LETIMER0: |
<> | 144:ef7eb2e8f9f7 | 1055 | ret = (CMU_ClkDiv_TypeDef)((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK) |
<> | 144:ef7eb2e8f9f7 | 1056 | >> _CMU_LFAPRESC0_LETIMER0_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1057 | ret = CMU_Log2ToDiv(ret); |
<> | 144:ef7eb2e8f9f7 | 1058 | break; |
<> | 144:ef7eb2e8f9f7 | 1059 | #endif |
<> | 144:ef7eb2e8f9f7 | 1060 | |
<> | 144:ef7eb2e8f9f7 | 1061 | #if defined(_CMU_LFAPRESC0_LCD_MASK) |
<> | 144:ef7eb2e8f9f7 | 1062 | case cmuClock_LCDpre: |
<> | 144:ef7eb2e8f9f7 | 1063 | ret = (CMU_ClkDiv_TypeDef)(((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK) |
<> | 144:ef7eb2e8f9f7 | 1064 | >> _CMU_LFAPRESC0_LCD_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 1065 | + CMU_DivToLog2(cmuClkDiv_16)); |
<> | 144:ef7eb2e8f9f7 | 1066 | ret = CMU_Log2ToDiv(ret); |
<> | 144:ef7eb2e8f9f7 | 1067 | break; |
<> | 144:ef7eb2e8f9f7 | 1068 | #endif |
<> | 144:ef7eb2e8f9f7 | 1069 | |
<> | 144:ef7eb2e8f9f7 | 1070 | #if defined(_CMU_LFAPRESC0_LESENSE_MASK) |
<> | 144:ef7eb2e8f9f7 | 1071 | case cmuClock_LESENSE: |
<> | 144:ef7eb2e8f9f7 | 1072 | ret = (CMU_ClkDiv_TypeDef)((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LESENSE_MASK) |
<> | 144:ef7eb2e8f9f7 | 1073 | >> _CMU_LFAPRESC0_LESENSE_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1074 | ret = CMU_Log2ToDiv(ret); |
<> | 144:ef7eb2e8f9f7 | 1075 | break; |
<> | 144:ef7eb2e8f9f7 | 1076 | #endif |
<> | 144:ef7eb2e8f9f7 | 1077 | |
<> | 144:ef7eb2e8f9f7 | 1078 | default: |
<> | 144:ef7eb2e8f9f7 | 1079 | EFM_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 1080 | ret = cmuClkDiv_1; |
<> | 144:ef7eb2e8f9f7 | 1081 | break; |
<> | 144:ef7eb2e8f9f7 | 1082 | } |
<> | 144:ef7eb2e8f9f7 | 1083 | break; |
<> | 144:ef7eb2e8f9f7 | 1084 | |
<> | 144:ef7eb2e8f9f7 | 1085 | case CMU_LFBPRESC0_REG: |
<> | 144:ef7eb2e8f9f7 | 1086 | switch (clock) |
<> | 144:ef7eb2e8f9f7 | 1087 | { |
<> | 144:ef7eb2e8f9f7 | 1088 | #if defined(_CMU_LFBPRESC0_LEUART0_MASK) |
<> | 144:ef7eb2e8f9f7 | 1089 | case cmuClock_LEUART0: |
<> | 144:ef7eb2e8f9f7 | 1090 | ret = (CMU_ClkDiv_TypeDef)((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK) |
<> | 144:ef7eb2e8f9f7 | 1091 | >> _CMU_LFBPRESC0_LEUART0_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1092 | ret = CMU_Log2ToDiv(ret); |
<> | 144:ef7eb2e8f9f7 | 1093 | break; |
<> | 144:ef7eb2e8f9f7 | 1094 | #endif |
<> | 144:ef7eb2e8f9f7 | 1095 | |
<> | 144:ef7eb2e8f9f7 | 1096 | #if defined(_CMU_LFBPRESC0_LEUART1_MASK) |
<> | 144:ef7eb2e8f9f7 | 1097 | case cmuClock_LEUART1: |
<> | 144:ef7eb2e8f9f7 | 1098 | ret = (CMU_ClkDiv_TypeDef)((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK) |
<> | 144:ef7eb2e8f9f7 | 1099 | >> _CMU_LFBPRESC0_LEUART1_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1100 | ret = CMU_Log2ToDiv(ret); |
<> | 144:ef7eb2e8f9f7 | 1101 | break; |
<> | 144:ef7eb2e8f9f7 | 1102 | #endif |
<> | 144:ef7eb2e8f9f7 | 1103 | |
<> | 144:ef7eb2e8f9f7 | 1104 | default: |
<> | 144:ef7eb2e8f9f7 | 1105 | EFM_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 1106 | ret = cmuClkDiv_1; |
<> | 144:ef7eb2e8f9f7 | 1107 | break; |
<> | 144:ef7eb2e8f9f7 | 1108 | } |
<> | 144:ef7eb2e8f9f7 | 1109 | break; |
<> | 144:ef7eb2e8f9f7 | 1110 | |
<> | 144:ef7eb2e8f9f7 | 1111 | default: |
<> | 144:ef7eb2e8f9f7 | 1112 | EFM_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 1113 | ret = cmuClkDiv_1; |
<> | 144:ef7eb2e8f9f7 | 1114 | break; |
<> | 144:ef7eb2e8f9f7 | 1115 | } |
<> | 144:ef7eb2e8f9f7 | 1116 | |
<> | 144:ef7eb2e8f9f7 | 1117 | return ret; |
<> | 144:ef7eb2e8f9f7 | 1118 | #endif |
<> | 144:ef7eb2e8f9f7 | 1119 | } |
<> | 144:ef7eb2e8f9f7 | 1120 | |
<> | 144:ef7eb2e8f9f7 | 1121 | |
<> | 144:ef7eb2e8f9f7 | 1122 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 1123 | * @brief |
<> | 144:ef7eb2e8f9f7 | 1124 | * Set clock divisor/prescaler. |
<> | 144:ef7eb2e8f9f7 | 1125 | * |
<> | 144:ef7eb2e8f9f7 | 1126 | * @note |
<> | 144:ef7eb2e8f9f7 | 1127 | * If setting a LF clock prescaler, synchronization into the low frequency |
<> | 144:ef7eb2e8f9f7 | 1128 | * domain is required. If the same register is modified before a previous |
<> | 144:ef7eb2e8f9f7 | 1129 | * update has completed, this function will stall until the previous |
<> | 144:ef7eb2e8f9f7 | 1130 | * synchronization has completed. Please refer to CMU_FreezeEnable() for |
<> | 144:ef7eb2e8f9f7 | 1131 | * a suggestion on how to reduce stalling time in some use cases. |
<> | 144:ef7eb2e8f9f7 | 1132 | * |
<> | 144:ef7eb2e8f9f7 | 1133 | * @param[in] clock |
<> | 144:ef7eb2e8f9f7 | 1134 | * Clock point to set divisor/prescaler for. Notice that not all clock points |
<> | 144:ef7eb2e8f9f7 | 1135 | * have a divisor/prescaler, please refer to CMU overview in the reference |
<> | 144:ef7eb2e8f9f7 | 1136 | * manual. |
<> | 144:ef7eb2e8f9f7 | 1137 | * |
<> | 144:ef7eb2e8f9f7 | 1138 | * @param[in] div |
<> | 144:ef7eb2e8f9f7 | 1139 | * The clock divisor to use (<= cmuClkDiv_512). |
<> | 144:ef7eb2e8f9f7 | 1140 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 1141 | void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div) |
<> | 144:ef7eb2e8f9f7 | 1142 | { |
<> | 144:ef7eb2e8f9f7 | 1143 | #if defined( _SILICON_LABS_32B_PLATFORM_2 ) |
<> | 144:ef7eb2e8f9f7 | 1144 | CMU_ClockPrescSet(clock, (CMU_ClkPresc_TypeDef)(div - 1)); |
<> | 144:ef7eb2e8f9f7 | 1145 | |
<> | 144:ef7eb2e8f9f7 | 1146 | #elif defined( _SILICON_LABS_32B_PLATFORM_1 ) |
<> | 144:ef7eb2e8f9f7 | 1147 | uint32_t freq; |
<> | 144:ef7eb2e8f9f7 | 1148 | uint32_t divReg; |
<> | 144:ef7eb2e8f9f7 | 1149 | |
<> | 144:ef7eb2e8f9f7 | 1150 | /* Get divisor reg id */ |
<> | 144:ef7eb2e8f9f7 | 1151 | divReg = (clock >> CMU_DIV_REG_POS) & CMU_DIV_REG_MASK; |
<> | 144:ef7eb2e8f9f7 | 1152 | |
<> | 144:ef7eb2e8f9f7 | 1153 | switch (divReg) |
<> | 144:ef7eb2e8f9f7 | 1154 | { |
<> | 144:ef7eb2e8f9f7 | 1155 | #if defined( _CMU_CTRL_HFCLKDIV_MASK ) |
<> | 144:ef7eb2e8f9f7 | 1156 | case CMU_HFCLKDIV_REG: |
<> | 144:ef7eb2e8f9f7 | 1157 | EFM_ASSERT((div>=cmuClkDiv_1) && (div<=cmuClkDiv_8)); |
<> | 144:ef7eb2e8f9f7 | 1158 | |
<> | 144:ef7eb2e8f9f7 | 1159 | /* Configure worst case wait states for flash access before setting divisor */ |
<> | 144:ef7eb2e8f9f7 | 1160 | flashWaitStateMax(); |
<> | 144:ef7eb2e8f9f7 | 1161 | |
<> | 144:ef7eb2e8f9f7 | 1162 | /* Set divider */ |
<> | 144:ef7eb2e8f9f7 | 1163 | CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFCLKDIV_MASK) |
<> | 144:ef7eb2e8f9f7 | 1164 | | ((div-1) << _CMU_CTRL_HFCLKDIV_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1165 | |
<> | 144:ef7eb2e8f9f7 | 1166 | /* Update CMSIS core clock variable */ |
<> | 144:ef7eb2e8f9f7 | 1167 | /* (The function will update the global variable) */ |
<> | 144:ef7eb2e8f9f7 | 1168 | freq = SystemCoreClockGet(); |
<> | 144:ef7eb2e8f9f7 | 1169 | |
<> | 144:ef7eb2e8f9f7 | 1170 | /* Optimize flash access wait state setting for current core clk */ |
<> | 144:ef7eb2e8f9f7 | 1171 | flashWaitStateControl(freq); |
<> | 144:ef7eb2e8f9f7 | 1172 | break; |
<> | 144:ef7eb2e8f9f7 | 1173 | #endif |
<> | 144:ef7eb2e8f9f7 | 1174 | |
<> | 144:ef7eb2e8f9f7 | 1175 | case CMU_HFPERCLKDIV_REG: |
<> | 144:ef7eb2e8f9f7 | 1176 | EFM_ASSERT((div >= cmuClkDiv_1) && (div <= cmuClkDiv_512)); |
<> | 144:ef7eb2e8f9f7 | 1177 | /* Convert to correct scale */ |
<> | 144:ef7eb2e8f9f7 | 1178 | div = CMU_DivToLog2(div); |
<> | 144:ef7eb2e8f9f7 | 1179 | CMU->HFPERCLKDIV = (CMU->HFPERCLKDIV & ~_CMU_HFPERCLKDIV_HFPERCLKDIV_MASK) |
<> | 144:ef7eb2e8f9f7 | 1180 | | (div << _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1181 | break; |
<> | 144:ef7eb2e8f9f7 | 1182 | |
<> | 144:ef7eb2e8f9f7 | 1183 | case CMU_HFCORECLKDIV_REG: |
<> | 144:ef7eb2e8f9f7 | 1184 | EFM_ASSERT(div <= cmuClkDiv_512); |
<> | 144:ef7eb2e8f9f7 | 1185 | |
<> | 144:ef7eb2e8f9f7 | 1186 | /* Configure worst case wait states for flash access before setting divisor */ |
<> | 144:ef7eb2e8f9f7 | 1187 | flashWaitStateMax(); |
<> | 144:ef7eb2e8f9f7 | 1188 | |
<> | 144:ef7eb2e8f9f7 | 1189 | #if defined( CMU_CTRL_HFLE ) |
<> | 144:ef7eb2e8f9f7 | 1190 | /* Clear HFLE and set DIV2 factor for peripheral clock |
<> | 144:ef7eb2e8f9f7 | 1191 | when running at frequencies lower than or equal to CMU_MAX_FREQ_HFLE. */ |
<> | 144:ef7eb2e8f9f7 | 1192 | if ((CMU_ClockFreqGet(cmuClock_HF) / div) <= CMU_MAX_FREQ_HFLE()) |
<> | 144:ef7eb2e8f9f7 | 1193 | { |
<> | 144:ef7eb2e8f9f7 | 1194 | /* Clear CMU HFLE */ |
<> | 144:ef7eb2e8f9f7 | 1195 | BUS_RegBitWrite(&CMU->CTRL, _CMU_CTRL_HFLE_SHIFT, 0); |
<> | 144:ef7eb2e8f9f7 | 1196 | |
<> | 144:ef7eb2e8f9f7 | 1197 | /* Set DIV2 factor for peripheral clock */ |
<> | 144:ef7eb2e8f9f7 | 1198 | BUS_RegBitWrite(&CMU->HFCORECLKDIV, |
<> | 144:ef7eb2e8f9f7 | 1199 | _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 0); |
<> | 144:ef7eb2e8f9f7 | 1200 | } |
<> | 144:ef7eb2e8f9f7 | 1201 | else |
<> | 144:ef7eb2e8f9f7 | 1202 | { |
<> | 144:ef7eb2e8f9f7 | 1203 | /* Set CMU HFLE */ |
<> | 144:ef7eb2e8f9f7 | 1204 | BUS_RegBitWrite(&CMU->CTRL, _CMU_CTRL_HFLE_SHIFT, 1); |
<> | 144:ef7eb2e8f9f7 | 1205 | |
<> | 144:ef7eb2e8f9f7 | 1206 | /* Set DIV4 factor for peripheral clock */ |
<> | 144:ef7eb2e8f9f7 | 1207 | BUS_RegBitWrite(&CMU->HFCORECLKDIV, |
<> | 144:ef7eb2e8f9f7 | 1208 | _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 1); |
<> | 144:ef7eb2e8f9f7 | 1209 | } |
<> | 144:ef7eb2e8f9f7 | 1210 | #endif |
<> | 144:ef7eb2e8f9f7 | 1211 | |
<> | 144:ef7eb2e8f9f7 | 1212 | /* Convert to correct scale */ |
<> | 144:ef7eb2e8f9f7 | 1213 | div = CMU_DivToLog2(div); |
<> | 144:ef7eb2e8f9f7 | 1214 | |
<> | 144:ef7eb2e8f9f7 | 1215 | CMU->HFCORECLKDIV = (CMU->HFCORECLKDIV |
<> | 144:ef7eb2e8f9f7 | 1216 | & ~_CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) |
<> | 144:ef7eb2e8f9f7 | 1217 | | (div << _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1218 | |
<> | 144:ef7eb2e8f9f7 | 1219 | /* Update CMSIS core clock variable */ |
<> | 144:ef7eb2e8f9f7 | 1220 | /* (The function will update the global variable) */ |
<> | 144:ef7eb2e8f9f7 | 1221 | freq = SystemCoreClockGet(); |
<> | 144:ef7eb2e8f9f7 | 1222 | |
<> | 144:ef7eb2e8f9f7 | 1223 | /* Optimize flash access wait state setting for current core clk */ |
<> | 144:ef7eb2e8f9f7 | 1224 | flashWaitStateControl(freq); |
<> | 144:ef7eb2e8f9f7 | 1225 | break; |
<> | 144:ef7eb2e8f9f7 | 1226 | |
<> | 144:ef7eb2e8f9f7 | 1227 | case CMU_LFAPRESC0_REG: |
<> | 144:ef7eb2e8f9f7 | 1228 | switch (clock) |
<> | 144:ef7eb2e8f9f7 | 1229 | { |
<> | 144:ef7eb2e8f9f7 | 1230 | case cmuClock_RTC: |
<> | 144:ef7eb2e8f9f7 | 1231 | EFM_ASSERT(div <= cmuClkDiv_32768); |
<> | 144:ef7eb2e8f9f7 | 1232 | |
<> | 144:ef7eb2e8f9f7 | 1233 | /* LF register about to be modified require sync. busy check */ |
<> | 144:ef7eb2e8f9f7 | 1234 | syncReg(CMU_SYNCBUSY_LFAPRESC0); |
<> | 144:ef7eb2e8f9f7 | 1235 | |
<> | 144:ef7eb2e8f9f7 | 1236 | /* Convert to correct scale */ |
<> | 144:ef7eb2e8f9f7 | 1237 | div = CMU_DivToLog2(div); |
<> | 144:ef7eb2e8f9f7 | 1238 | |
<> | 144:ef7eb2e8f9f7 | 1239 | CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTC_MASK) |
<> | 144:ef7eb2e8f9f7 | 1240 | | (div << _CMU_LFAPRESC0_RTC_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1241 | break; |
<> | 144:ef7eb2e8f9f7 | 1242 | |
<> | 144:ef7eb2e8f9f7 | 1243 | #if defined(_CMU_LFAPRESC0_LETIMER0_MASK) |
<> | 144:ef7eb2e8f9f7 | 1244 | case cmuClock_LETIMER0: |
<> | 144:ef7eb2e8f9f7 | 1245 | EFM_ASSERT(div <= cmuClkDiv_32768); |
<> | 144:ef7eb2e8f9f7 | 1246 | |
<> | 144:ef7eb2e8f9f7 | 1247 | /* LF register about to be modified require sync. busy check */ |
<> | 144:ef7eb2e8f9f7 | 1248 | syncReg(CMU_SYNCBUSY_LFAPRESC0); |
<> | 144:ef7eb2e8f9f7 | 1249 | |
<> | 144:ef7eb2e8f9f7 | 1250 | /* Convert to correct scale */ |
<> | 144:ef7eb2e8f9f7 | 1251 | div = CMU_DivToLog2(div); |
<> | 144:ef7eb2e8f9f7 | 1252 | |
<> | 144:ef7eb2e8f9f7 | 1253 | CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LETIMER0_MASK) |
<> | 144:ef7eb2e8f9f7 | 1254 | | (div << _CMU_LFAPRESC0_LETIMER0_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1255 | break; |
<> | 144:ef7eb2e8f9f7 | 1256 | #endif |
<> | 144:ef7eb2e8f9f7 | 1257 | |
<> | 144:ef7eb2e8f9f7 | 1258 | #if defined(LCD_PRESENT) |
<> | 144:ef7eb2e8f9f7 | 1259 | case cmuClock_LCDpre: |
<> | 144:ef7eb2e8f9f7 | 1260 | EFM_ASSERT((div >= cmuClkDiv_16) && (div <= cmuClkDiv_128)); |
<> | 144:ef7eb2e8f9f7 | 1261 | |
<> | 144:ef7eb2e8f9f7 | 1262 | /* LF register about to be modified require sync. busy check */ |
<> | 144:ef7eb2e8f9f7 | 1263 | syncReg(CMU_SYNCBUSY_LFAPRESC0); |
<> | 144:ef7eb2e8f9f7 | 1264 | |
<> | 144:ef7eb2e8f9f7 | 1265 | /* Convert to correct scale */ |
<> | 144:ef7eb2e8f9f7 | 1266 | div = CMU_DivToLog2(div); |
<> | 144:ef7eb2e8f9f7 | 1267 | |
<> | 144:ef7eb2e8f9f7 | 1268 | CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LCD_MASK) |
<> | 144:ef7eb2e8f9f7 | 1269 | | ((div - CMU_DivToLog2(cmuClkDiv_16)) |
<> | 144:ef7eb2e8f9f7 | 1270 | << _CMU_LFAPRESC0_LCD_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1271 | break; |
<> | 144:ef7eb2e8f9f7 | 1272 | #endif /* defined(LCD_PRESENT) */ |
<> | 144:ef7eb2e8f9f7 | 1273 | |
<> | 144:ef7eb2e8f9f7 | 1274 | #if defined(LESENSE_PRESENT) |
<> | 144:ef7eb2e8f9f7 | 1275 | case cmuClock_LESENSE: |
<> | 144:ef7eb2e8f9f7 | 1276 | EFM_ASSERT(div <= cmuClkDiv_8); |
<> | 144:ef7eb2e8f9f7 | 1277 | |
<> | 144:ef7eb2e8f9f7 | 1278 | /* LF register about to be modified require sync. busy check */ |
<> | 144:ef7eb2e8f9f7 | 1279 | syncReg(CMU_SYNCBUSY_LFAPRESC0); |
<> | 144:ef7eb2e8f9f7 | 1280 | |
<> | 144:ef7eb2e8f9f7 | 1281 | /* Convert to correct scale */ |
<> | 144:ef7eb2e8f9f7 | 1282 | div = CMU_DivToLog2(div); |
<> | 144:ef7eb2e8f9f7 | 1283 | |
<> | 144:ef7eb2e8f9f7 | 1284 | CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LESENSE_MASK) |
<> | 144:ef7eb2e8f9f7 | 1285 | | (div << _CMU_LFAPRESC0_LESENSE_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1286 | break; |
<> | 144:ef7eb2e8f9f7 | 1287 | #endif /* defined(LESENSE_PRESENT) */ |
<> | 144:ef7eb2e8f9f7 | 1288 | |
<> | 144:ef7eb2e8f9f7 | 1289 | default: |
<> | 144:ef7eb2e8f9f7 | 1290 | EFM_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 1291 | break; |
<> | 144:ef7eb2e8f9f7 | 1292 | } |
<> | 144:ef7eb2e8f9f7 | 1293 | break; |
<> | 144:ef7eb2e8f9f7 | 1294 | |
<> | 144:ef7eb2e8f9f7 | 1295 | case CMU_LFBPRESC0_REG: |
<> | 144:ef7eb2e8f9f7 | 1296 | switch (clock) |
<> | 144:ef7eb2e8f9f7 | 1297 | { |
<> | 144:ef7eb2e8f9f7 | 1298 | #if defined(_CMU_LFBPRESC0_LEUART0_MASK) |
<> | 144:ef7eb2e8f9f7 | 1299 | case cmuClock_LEUART0: |
<> | 144:ef7eb2e8f9f7 | 1300 | EFM_ASSERT(div <= cmuClkDiv_8); |
<> | 144:ef7eb2e8f9f7 | 1301 | |
<> | 144:ef7eb2e8f9f7 | 1302 | /* LF register about to be modified require sync. busy check */ |
<> | 144:ef7eb2e8f9f7 | 1303 | syncReg(CMU_SYNCBUSY_LFBPRESC0); |
<> | 144:ef7eb2e8f9f7 | 1304 | |
<> | 144:ef7eb2e8f9f7 | 1305 | /* Convert to correct scale */ |
<> | 144:ef7eb2e8f9f7 | 1306 | div = CMU_DivToLog2(div); |
<> | 144:ef7eb2e8f9f7 | 1307 | |
<> | 144:ef7eb2e8f9f7 | 1308 | CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART0_MASK) |
<> | 144:ef7eb2e8f9f7 | 1309 | | (((uint32_t)div) << _CMU_LFBPRESC0_LEUART0_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1310 | break; |
<> | 144:ef7eb2e8f9f7 | 1311 | #endif |
<> | 144:ef7eb2e8f9f7 | 1312 | |
<> | 144:ef7eb2e8f9f7 | 1313 | #if defined(_CMU_LFBPRESC0_LEUART1_MASK) |
<> | 144:ef7eb2e8f9f7 | 1314 | case cmuClock_LEUART1: |
<> | 144:ef7eb2e8f9f7 | 1315 | EFM_ASSERT(div <= cmuClkDiv_8); |
<> | 144:ef7eb2e8f9f7 | 1316 | |
<> | 144:ef7eb2e8f9f7 | 1317 | /* LF register about to be modified require sync. busy check */ |
<> | 144:ef7eb2e8f9f7 | 1318 | syncReg(CMU_SYNCBUSY_LFBPRESC0); |
<> | 144:ef7eb2e8f9f7 | 1319 | |
<> | 144:ef7eb2e8f9f7 | 1320 | /* Convert to correct scale */ |
<> | 144:ef7eb2e8f9f7 | 1321 | div = CMU_DivToLog2(div); |
<> | 144:ef7eb2e8f9f7 | 1322 | |
<> | 144:ef7eb2e8f9f7 | 1323 | CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART1_MASK) |
<> | 144:ef7eb2e8f9f7 | 1324 | | (((uint32_t)div) << _CMU_LFBPRESC0_LEUART1_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1325 | break; |
<> | 144:ef7eb2e8f9f7 | 1326 | #endif |
<> | 144:ef7eb2e8f9f7 | 1327 | |
<> | 144:ef7eb2e8f9f7 | 1328 | default: |
<> | 144:ef7eb2e8f9f7 | 1329 | EFM_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 1330 | break; |
<> | 144:ef7eb2e8f9f7 | 1331 | } |
<> | 144:ef7eb2e8f9f7 | 1332 | break; |
<> | 144:ef7eb2e8f9f7 | 1333 | |
<> | 144:ef7eb2e8f9f7 | 1334 | default: |
<> | 144:ef7eb2e8f9f7 | 1335 | EFM_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 1336 | break; |
<> | 144:ef7eb2e8f9f7 | 1337 | } |
<> | 144:ef7eb2e8f9f7 | 1338 | #endif |
<> | 144:ef7eb2e8f9f7 | 1339 | } |
<> | 144:ef7eb2e8f9f7 | 1340 | |
<> | 144:ef7eb2e8f9f7 | 1341 | |
<> | 144:ef7eb2e8f9f7 | 1342 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 1343 | * @brief |
<> | 144:ef7eb2e8f9f7 | 1344 | * Enable/disable a clock. |
<> | 144:ef7eb2e8f9f7 | 1345 | * |
<> | 144:ef7eb2e8f9f7 | 1346 | * @details |
<> | 144:ef7eb2e8f9f7 | 1347 | * In general, module clocking is disabled after a reset. If a module |
<> | 144:ef7eb2e8f9f7 | 1348 | * clock is disabled, the registers of that module are not accessible and |
<> | 144:ef7eb2e8f9f7 | 1349 | * reading from such registers may return undefined values. Writing to |
<> | 144:ef7eb2e8f9f7 | 1350 | * registers of clock disabled modules have no effect. One should normally |
<> | 144:ef7eb2e8f9f7 | 1351 | * avoid accessing module registers of a module with a disabled clock. |
<> | 144:ef7eb2e8f9f7 | 1352 | * |
<> | 144:ef7eb2e8f9f7 | 1353 | * @note |
<> | 144:ef7eb2e8f9f7 | 1354 | * If enabling/disabling a LF clock, synchronization into the low frequency |
<> | 144:ef7eb2e8f9f7 | 1355 | * domain is required. If the same register is modified before a previous |
<> | 144:ef7eb2e8f9f7 | 1356 | * update has completed, this function will stall until the previous |
<> | 144:ef7eb2e8f9f7 | 1357 | * synchronization has completed. Please refer to CMU_FreezeEnable() for |
<> | 144:ef7eb2e8f9f7 | 1358 | * a suggestion on how to reduce stalling time in some use cases. |
<> | 144:ef7eb2e8f9f7 | 1359 | * |
<> | 144:ef7eb2e8f9f7 | 1360 | * @param[in] clock |
<> | 144:ef7eb2e8f9f7 | 1361 | * The clock to enable/disable. Notice that not all defined clock |
<> | 144:ef7eb2e8f9f7 | 1362 | * points have separate enable/disable control, please refer to CMU overview |
<> | 144:ef7eb2e8f9f7 | 1363 | * in reference manual. |
<> | 144:ef7eb2e8f9f7 | 1364 | * |
<> | 144:ef7eb2e8f9f7 | 1365 | * @param[in] enable |
<> | 144:ef7eb2e8f9f7 | 1366 | * @li true - enable specified clock. |
<> | 144:ef7eb2e8f9f7 | 1367 | * @li false - disable specified clock. |
<> | 144:ef7eb2e8f9f7 | 1368 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 1369 | void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable) |
<> | 144:ef7eb2e8f9f7 | 1370 | { |
<> | 144:ef7eb2e8f9f7 | 1371 | volatile uint32_t *reg; |
<> | 144:ef7eb2e8f9f7 | 1372 | uint32_t bit; |
<> | 144:ef7eb2e8f9f7 | 1373 | uint32_t sync = 0; |
<> | 144:ef7eb2e8f9f7 | 1374 | |
<> | 144:ef7eb2e8f9f7 | 1375 | /* Identify enable register */ |
<> | 144:ef7eb2e8f9f7 | 1376 | switch ((clock >> CMU_EN_REG_POS) & CMU_EN_REG_MASK) |
<> | 144:ef7eb2e8f9f7 | 1377 | { |
<> | 144:ef7eb2e8f9f7 | 1378 | #if defined( _SILICON_LABS_32B_PLATFORM_2 ) |
<> | 144:ef7eb2e8f9f7 | 1379 | case CMU_CTRL_EN_REG: |
<> | 144:ef7eb2e8f9f7 | 1380 | reg = &CMU->CTRL; |
<> | 144:ef7eb2e8f9f7 | 1381 | break; |
<> | 144:ef7eb2e8f9f7 | 1382 | #endif |
<> | 144:ef7eb2e8f9f7 | 1383 | |
<> | 144:ef7eb2e8f9f7 | 1384 | #if defined( _SILICON_LABS_32B_PLATFORM_1 ) |
<> | 144:ef7eb2e8f9f7 | 1385 | case CMU_HFCORECLKEN0_EN_REG: |
<> | 144:ef7eb2e8f9f7 | 1386 | reg = &CMU->HFCORECLKEN0; |
<> | 144:ef7eb2e8f9f7 | 1387 | #if defined( CMU_CTRL_HFLE ) |
<> | 144:ef7eb2e8f9f7 | 1388 | /* Set HFLE and DIV4 factor for peripheral clock when |
<> | 144:ef7eb2e8f9f7 | 1389 | running at frequencies higher than or equal to CMU_MAX_FREQ_HFLE. */ |
<> | 144:ef7eb2e8f9f7 | 1390 | if ( CMU_ClockFreqGet(cmuClock_CORE) > CMU_MAX_FREQ_HFLE()) |
<> | 144:ef7eb2e8f9f7 | 1391 | { |
<> | 144:ef7eb2e8f9f7 | 1392 | /* Enable CMU HFLE */ |
<> | 144:ef7eb2e8f9f7 | 1393 | BUS_RegBitWrite(&CMU->CTRL, _CMU_CTRL_HFLE_SHIFT, 1); |
<> | 144:ef7eb2e8f9f7 | 1394 | |
<> | 144:ef7eb2e8f9f7 | 1395 | /* Set DIV4 factor for peripheral clock */ |
<> | 144:ef7eb2e8f9f7 | 1396 | BUS_RegBitWrite(&CMU->HFCORECLKDIV, |
<> | 144:ef7eb2e8f9f7 | 1397 | _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 1); |
<> | 144:ef7eb2e8f9f7 | 1398 | } |
<> | 144:ef7eb2e8f9f7 | 1399 | #endif |
<> | 144:ef7eb2e8f9f7 | 1400 | break; |
<> | 144:ef7eb2e8f9f7 | 1401 | #endif |
<> | 144:ef7eb2e8f9f7 | 1402 | |
<> | 144:ef7eb2e8f9f7 | 1403 | #if defined( _CMU_HFBUSCLKEN0_MASK ) |
<> | 144:ef7eb2e8f9f7 | 1404 | case CMU_HFBUSCLKEN0_EN_REG: |
<> | 144:ef7eb2e8f9f7 | 1405 | reg = &CMU->HFBUSCLKEN0; |
<> | 144:ef7eb2e8f9f7 | 1406 | break; |
<> | 144:ef7eb2e8f9f7 | 1407 | #endif |
<> | 144:ef7eb2e8f9f7 | 1408 | |
<> | 144:ef7eb2e8f9f7 | 1409 | #if defined( _CMU_HFRADIOCLKEN0_MASK ) |
<> | 144:ef7eb2e8f9f7 | 1410 | case CMU_HFRADIOCLKEN0_EN_REG: |
<> | 144:ef7eb2e8f9f7 | 1411 | reg = &CMU->HFRADIOCLKEN0; |
<> | 144:ef7eb2e8f9f7 | 1412 | break; |
<> | 144:ef7eb2e8f9f7 | 1413 | #endif |
<> | 144:ef7eb2e8f9f7 | 1414 | |
<> | 144:ef7eb2e8f9f7 | 1415 | #if defined( _CMU_HFPERCLKDIV_MASK ) |
<> | 144:ef7eb2e8f9f7 | 1416 | case CMU_HFPERCLKDIV_EN_REG: |
<> | 144:ef7eb2e8f9f7 | 1417 | reg = &CMU->HFPERCLKDIV; |
<> | 144:ef7eb2e8f9f7 | 1418 | break; |
<> | 144:ef7eb2e8f9f7 | 1419 | #endif |
<> | 144:ef7eb2e8f9f7 | 1420 | |
<> | 144:ef7eb2e8f9f7 | 1421 | case CMU_HFPERCLKEN0_EN_REG: |
<> | 144:ef7eb2e8f9f7 | 1422 | reg = &CMU->HFPERCLKEN0; |
<> | 144:ef7eb2e8f9f7 | 1423 | break; |
<> | 144:ef7eb2e8f9f7 | 1424 | |
<> | 144:ef7eb2e8f9f7 | 1425 | case CMU_LFACLKEN0_EN_REG: |
<> | 144:ef7eb2e8f9f7 | 1426 | reg = &CMU->LFACLKEN0; |
<> | 144:ef7eb2e8f9f7 | 1427 | sync = CMU_SYNCBUSY_LFACLKEN0; |
<> | 144:ef7eb2e8f9f7 | 1428 | break; |
<> | 144:ef7eb2e8f9f7 | 1429 | |
<> | 144:ef7eb2e8f9f7 | 1430 | case CMU_LFBCLKEN0_EN_REG: |
<> | 144:ef7eb2e8f9f7 | 1431 | reg = &CMU->LFBCLKEN0; |
<> | 144:ef7eb2e8f9f7 | 1432 | sync = CMU_SYNCBUSY_LFBCLKEN0; |
<> | 144:ef7eb2e8f9f7 | 1433 | break; |
<> | 144:ef7eb2e8f9f7 | 1434 | |
<> | 144:ef7eb2e8f9f7 | 1435 | #if defined( _CMU_LFCCLKEN0_MASK ) |
<> | 144:ef7eb2e8f9f7 | 1436 | case CMU_LFCCLKEN0_EN_REG: |
<> | 144:ef7eb2e8f9f7 | 1437 | reg = &CMU->LFCCLKEN0; |
<> | 144:ef7eb2e8f9f7 | 1438 | sync = CMU_SYNCBUSY_LFCCLKEN0; |
<> | 144:ef7eb2e8f9f7 | 1439 | break; |
<> | 144:ef7eb2e8f9f7 | 1440 | #endif |
<> | 144:ef7eb2e8f9f7 | 1441 | |
<> | 144:ef7eb2e8f9f7 | 1442 | #if defined( _CMU_LFECLKEN0_MASK ) |
<> | 144:ef7eb2e8f9f7 | 1443 | case CMU_LFECLKEN0_EN_REG: |
<> | 144:ef7eb2e8f9f7 | 1444 | reg = &CMU->LFECLKEN0; |
<> | 144:ef7eb2e8f9f7 | 1445 | sync = CMU_SYNCBUSY_LFECLKEN0; |
<> | 144:ef7eb2e8f9f7 | 1446 | break; |
<> | 144:ef7eb2e8f9f7 | 1447 | #endif |
<> | 144:ef7eb2e8f9f7 | 1448 | |
<> | 144:ef7eb2e8f9f7 | 1449 | case CMU_PCNT_EN_REG: |
<> | 144:ef7eb2e8f9f7 | 1450 | reg = &CMU->PCNTCTRL; |
<> | 144:ef7eb2e8f9f7 | 1451 | break; |
<> | 144:ef7eb2e8f9f7 | 1452 | |
<> | 144:ef7eb2e8f9f7 | 1453 | default: /* Cannot enable/disable clock point */ |
<> | 144:ef7eb2e8f9f7 | 1454 | EFM_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 1455 | return; |
<> | 144:ef7eb2e8f9f7 | 1456 | } |
<> | 144:ef7eb2e8f9f7 | 1457 | |
<> | 144:ef7eb2e8f9f7 | 1458 | /* Get bit position used to enable/disable */ |
<> | 144:ef7eb2e8f9f7 | 1459 | bit = (clock >> CMU_EN_BIT_POS) & CMU_EN_BIT_MASK; |
<> | 144:ef7eb2e8f9f7 | 1460 | |
<> | 144:ef7eb2e8f9f7 | 1461 | /* LF synchronization required? */ |
<> | 144:ef7eb2e8f9f7 | 1462 | if (sync) |
<> | 144:ef7eb2e8f9f7 | 1463 | { |
<> | 144:ef7eb2e8f9f7 | 1464 | syncReg(sync); |
<> | 144:ef7eb2e8f9f7 | 1465 | } |
<> | 144:ef7eb2e8f9f7 | 1466 | |
<> | 144:ef7eb2e8f9f7 | 1467 | /* Set/clear bit as requested */ |
<> | 144:ef7eb2e8f9f7 | 1468 | BUS_RegBitWrite(reg, bit, enable); |
<> | 144:ef7eb2e8f9f7 | 1469 | } |
<> | 144:ef7eb2e8f9f7 | 1470 | |
<> | 144:ef7eb2e8f9f7 | 1471 | |
<> | 144:ef7eb2e8f9f7 | 1472 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 1473 | * @brief |
<> | 144:ef7eb2e8f9f7 | 1474 | * Get clock frequency for a clock point. |
<> | 144:ef7eb2e8f9f7 | 1475 | * |
<> | 144:ef7eb2e8f9f7 | 1476 | * @param[in] clock |
<> | 144:ef7eb2e8f9f7 | 1477 | * Clock point to fetch frequency for. |
<> | 144:ef7eb2e8f9f7 | 1478 | * |
<> | 144:ef7eb2e8f9f7 | 1479 | * @return |
<> | 144:ef7eb2e8f9f7 | 1480 | * The current frequency in Hz. |
<> | 144:ef7eb2e8f9f7 | 1481 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 1482 | uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock) |
<> | 144:ef7eb2e8f9f7 | 1483 | { |
<> | 144:ef7eb2e8f9f7 | 1484 | uint32_t ret; |
<> | 144:ef7eb2e8f9f7 | 1485 | |
<> | 144:ef7eb2e8f9f7 | 1486 | switch(clock & (CMU_CLK_BRANCH_MASK << CMU_CLK_BRANCH_POS)) |
<> | 144:ef7eb2e8f9f7 | 1487 | { |
<> | 144:ef7eb2e8f9f7 | 1488 | case (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS): |
<> | 144:ef7eb2e8f9f7 | 1489 | ret = SystemHFClockGet(); |
<> | 144:ef7eb2e8f9f7 | 1490 | #if defined( _CMU_CTRL_HFCLKDIV_MASK ) |
<> | 144:ef7eb2e8f9f7 | 1491 | /* Family with an additional divider. */ |
<> | 144:ef7eb2e8f9f7 | 1492 | ret = ret / (1U + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK) |
<> | 144:ef7eb2e8f9f7 | 1493 | >> _CMU_CTRL_HFCLKDIV_SHIFT)); |
<> | 144:ef7eb2e8f9f7 | 1494 | #endif |
<> | 144:ef7eb2e8f9f7 | 1495 | #if defined( _CMU_HFPRESC_MASK ) |
<> | 144:ef7eb2e8f9f7 | 1496 | ret = ret / (1U + ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK) |
<> | 144:ef7eb2e8f9f7 | 1497 | >> _CMU_HFPRESC_PRESC_SHIFT)); |
<> | 144:ef7eb2e8f9f7 | 1498 | #endif |
<> | 144:ef7eb2e8f9f7 | 1499 | break; |
<> | 144:ef7eb2e8f9f7 | 1500 | |
<> | 144:ef7eb2e8f9f7 | 1501 | case (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS): |
<> | 144:ef7eb2e8f9f7 | 1502 | ret = SystemHFClockGet(); |
<> | 144:ef7eb2e8f9f7 | 1503 | #if defined( _SILICON_LABS_32B_PLATFORM_1 ) |
<> | 144:ef7eb2e8f9f7 | 1504 | #if defined( _CMU_CTRL_HFCLKDIV_MASK ) |
<> | 144:ef7eb2e8f9f7 | 1505 | /* Family with an additional divider. */ |
<> | 144:ef7eb2e8f9f7 | 1506 | ret = ret / (1U + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK) |
<> | 144:ef7eb2e8f9f7 | 1507 | >> _CMU_CTRL_HFCLKDIV_SHIFT)); |
<> | 144:ef7eb2e8f9f7 | 1508 | #endif |
<> | 144:ef7eb2e8f9f7 | 1509 | ret >>= (CMU->HFPERCLKDIV & _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK) |
<> | 144:ef7eb2e8f9f7 | 1510 | >> _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 1511 | #elif defined( _SILICON_LABS_32B_PLATFORM_2 ) |
<> | 144:ef7eb2e8f9f7 | 1512 | ret /= 1U + ((CMU->HFPERPRESC & _CMU_HFPERPRESC_PRESC_MASK) |
<> | 144:ef7eb2e8f9f7 | 1513 | >> _CMU_HFPERPRESC_PRESC_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1514 | #endif |
<> | 144:ef7eb2e8f9f7 | 1515 | break; |
<> | 144:ef7eb2e8f9f7 | 1516 | |
<> | 144:ef7eb2e8f9f7 | 1517 | #if defined( _SILICON_LABS_32B_PLATFORM_2 ) |
<> | 144:ef7eb2e8f9f7 | 1518 | #if defined( _CMU_HFRADIOPRESC_PRESC_MASK ) |
<> | 144:ef7eb2e8f9f7 | 1519 | case (CMU_HFRADIO_CLK_BRANCH << CMU_CLK_BRANCH_POS): |
<> | 144:ef7eb2e8f9f7 | 1520 | ret = SystemHFClockGet(); |
<> | 144:ef7eb2e8f9f7 | 1521 | ret /= 1U + ((CMU->HFRADIOPRESC & _CMU_HFRADIOPRESC_PRESC_MASK) |
<> | 144:ef7eb2e8f9f7 | 1522 | >> _CMU_HFRADIOPRESC_PRESC_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1523 | break; |
<> | 144:ef7eb2e8f9f7 | 1524 | #endif |
<> | 144:ef7eb2e8f9f7 | 1525 | |
<> | 144:ef7eb2e8f9f7 | 1526 | #if defined( CRYPTO_PRESENT ) \ |
<> | 144:ef7eb2e8f9f7 | 1527 | || defined( LDMA_PRESENT ) \ |
<> | 144:ef7eb2e8f9f7 | 1528 | || defined( GPCRC_PRESENT ) \ |
<> | 144:ef7eb2e8f9f7 | 1529 | || defined( PRS_PRESENT ) \ |
<> | 144:ef7eb2e8f9f7 | 1530 | || defined( GPIO_PRESENT ) |
<> | 144:ef7eb2e8f9f7 | 1531 | case (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS): |
<> | 144:ef7eb2e8f9f7 | 1532 | ret = SystemHFClockGet(); |
<> | 144:ef7eb2e8f9f7 | 1533 | break; |
<> | 144:ef7eb2e8f9f7 | 1534 | #endif |
<> | 144:ef7eb2e8f9f7 | 1535 | |
<> | 144:ef7eb2e8f9f7 | 1536 | case (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS): |
<> | 144:ef7eb2e8f9f7 | 1537 | ret = SystemHFClockGet(); |
<> | 144:ef7eb2e8f9f7 | 1538 | ret /= 1U + ((CMU->HFCOREPRESC & _CMU_HFCOREPRESC_PRESC_MASK) |
<> | 144:ef7eb2e8f9f7 | 1539 | >> _CMU_HFCOREPRESC_PRESC_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1540 | break; |
<> | 144:ef7eb2e8f9f7 | 1541 | |
<> | 144:ef7eb2e8f9f7 | 1542 | case (CMU_HFEXP_CLK_BRANCH << CMU_CLK_BRANCH_POS): |
<> | 144:ef7eb2e8f9f7 | 1543 | ret = SystemHFClockGet(); |
<> | 144:ef7eb2e8f9f7 | 1544 | ret /= 1U + ((CMU->HFEXPPRESC & _CMU_HFEXPPRESC_PRESC_MASK) |
<> | 144:ef7eb2e8f9f7 | 1545 | >> _CMU_HFEXPPRESC_PRESC_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1546 | break; |
<> | 144:ef7eb2e8f9f7 | 1547 | #endif |
<> | 144:ef7eb2e8f9f7 | 1548 | |
<> | 144:ef7eb2e8f9f7 | 1549 | #if defined( _SILICON_LABS_32B_PLATFORM_1 ) |
<> | 144:ef7eb2e8f9f7 | 1550 | #if defined(AES_PRESENT) \ |
<> | 144:ef7eb2e8f9f7 | 1551 | || defined(DMA_PRESENT) \ |
<> | 144:ef7eb2e8f9f7 | 1552 | || defined(EBI_PRESENT) \ |
<> | 144:ef7eb2e8f9f7 | 1553 | || defined(USB_PRESENT) |
<> | 144:ef7eb2e8f9f7 | 1554 | case (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS): |
<> | 144:ef7eb2e8f9f7 | 1555 | { |
<> | 144:ef7eb2e8f9f7 | 1556 | ret = SystemCoreClockGet(); |
<> | 144:ef7eb2e8f9f7 | 1557 | } break; |
<> | 144:ef7eb2e8f9f7 | 1558 | #endif |
<> | 144:ef7eb2e8f9f7 | 1559 | #endif |
<> | 144:ef7eb2e8f9f7 | 1560 | |
<> | 144:ef7eb2e8f9f7 | 1561 | case (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS): |
<> | 144:ef7eb2e8f9f7 | 1562 | ret = lfClkGet(cmuClock_LFA); |
<> | 144:ef7eb2e8f9f7 | 1563 | break; |
<> | 144:ef7eb2e8f9f7 | 1564 | |
<> | 144:ef7eb2e8f9f7 | 1565 | #if defined( _CMU_LFACLKEN0_RTC_MASK ) |
<> | 144:ef7eb2e8f9f7 | 1566 | case (CMU_RTC_CLK_BRANCH << CMU_CLK_BRANCH_POS): |
<> | 144:ef7eb2e8f9f7 | 1567 | ret = lfClkGet(cmuClock_LFA); |
<> | 144:ef7eb2e8f9f7 | 1568 | ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_RTC_MASK) |
<> | 144:ef7eb2e8f9f7 | 1569 | >> _CMU_LFAPRESC0_RTC_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 1570 | break; |
<> | 144:ef7eb2e8f9f7 | 1571 | #endif |
<> | 144:ef7eb2e8f9f7 | 1572 | |
<> | 144:ef7eb2e8f9f7 | 1573 | #if defined( _CMU_LFECLKEN0_RTCC_MASK ) |
<> | 144:ef7eb2e8f9f7 | 1574 | case (CMU_RTCC_CLK_BRANCH << CMU_CLK_BRANCH_POS): |
<> | 144:ef7eb2e8f9f7 | 1575 | ret = lfClkGet(cmuClock_LFE); |
<> | 144:ef7eb2e8f9f7 | 1576 | break; |
<> | 144:ef7eb2e8f9f7 | 1577 | #endif |
<> | 144:ef7eb2e8f9f7 | 1578 | |
<> | 144:ef7eb2e8f9f7 | 1579 | #if defined( _CMU_LFACLKEN0_LETIMER0_MASK ) |
<> | 144:ef7eb2e8f9f7 | 1580 | case (CMU_LETIMER0_CLK_BRANCH << CMU_CLK_BRANCH_POS): |
<> | 144:ef7eb2e8f9f7 | 1581 | ret = lfClkGet(cmuClock_LFA); |
<> | 144:ef7eb2e8f9f7 | 1582 | #if defined( _SILICON_LABS_32B_PLATFORM_1 ) |
<> | 144:ef7eb2e8f9f7 | 1583 | ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK) |
<> | 144:ef7eb2e8f9f7 | 1584 | >> _CMU_LFAPRESC0_LETIMER0_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 1585 | #elif defined( _SILICON_LABS_32B_PLATFORM_2 ) |
<> | 144:ef7eb2e8f9f7 | 1586 | ret /= CMU_Log2ToDiv((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK) |
<> | 144:ef7eb2e8f9f7 | 1587 | >> _CMU_LFAPRESC0_LETIMER0_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1588 | #endif |
<> | 144:ef7eb2e8f9f7 | 1589 | break; |
<> | 144:ef7eb2e8f9f7 | 1590 | #endif |
<> | 144:ef7eb2e8f9f7 | 1591 | |
<> | 144:ef7eb2e8f9f7 | 1592 | #if defined(_CMU_LFACLKEN0_LCD_MASK) |
<> | 144:ef7eb2e8f9f7 | 1593 | case (CMU_LCDPRE_CLK_BRANCH << CMU_CLK_BRANCH_POS): |
<> | 144:ef7eb2e8f9f7 | 1594 | ret = lfClkGet(cmuClock_LFA); |
<> | 144:ef7eb2e8f9f7 | 1595 | ret >>= ((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK) |
<> | 144:ef7eb2e8f9f7 | 1596 | >> _CMU_LFAPRESC0_LCD_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 1597 | + CMU_DivToLog2(cmuClkDiv_16); |
<> | 144:ef7eb2e8f9f7 | 1598 | break; |
<> | 144:ef7eb2e8f9f7 | 1599 | |
<> | 144:ef7eb2e8f9f7 | 1600 | case (CMU_LCD_CLK_BRANCH << CMU_CLK_BRANCH_POS): |
<> | 144:ef7eb2e8f9f7 | 1601 | ret = lfClkGet(cmuClock_LFA); |
<> | 144:ef7eb2e8f9f7 | 1602 | ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK) |
<> | 144:ef7eb2e8f9f7 | 1603 | >> _CMU_LFAPRESC0_LCD_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 1604 | ret /= 1U + ((CMU->LCDCTRL & _CMU_LCDCTRL_FDIV_MASK) |
<> | 144:ef7eb2e8f9f7 | 1605 | >> _CMU_LCDCTRL_FDIV_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1606 | break; |
<> | 144:ef7eb2e8f9f7 | 1607 | #endif |
<> | 144:ef7eb2e8f9f7 | 1608 | |
<> | 144:ef7eb2e8f9f7 | 1609 | #if defined(_CMU_LFACLKEN0_LESENSE_MASK) |
<> | 144:ef7eb2e8f9f7 | 1610 | case (CMU_LESENSE_CLK_BRANCH << CMU_CLK_BRANCH_POS): |
<> | 144:ef7eb2e8f9f7 | 1611 | ret = lfClkGet(cmuClock_LFA); |
<> | 144:ef7eb2e8f9f7 | 1612 | ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LESENSE_MASK) |
<> | 144:ef7eb2e8f9f7 | 1613 | >> _CMU_LFAPRESC0_LESENSE_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 1614 | break; |
<> | 144:ef7eb2e8f9f7 | 1615 | #endif |
<> | 144:ef7eb2e8f9f7 | 1616 | |
<> | 144:ef7eb2e8f9f7 | 1617 | case (CMU_LFB_CLK_BRANCH << CMU_CLK_BRANCH_POS): |
<> | 144:ef7eb2e8f9f7 | 1618 | ret = lfClkGet(cmuClock_LFB); |
<> | 144:ef7eb2e8f9f7 | 1619 | break; |
<> | 144:ef7eb2e8f9f7 | 1620 | |
<> | 144:ef7eb2e8f9f7 | 1621 | #if defined( _CMU_LFBCLKEN0_LEUART0_MASK ) |
<> | 144:ef7eb2e8f9f7 | 1622 | case (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS): |
<> | 144:ef7eb2e8f9f7 | 1623 | ret = lfClkGet(cmuClock_LFB); |
<> | 144:ef7eb2e8f9f7 | 1624 | #if defined( _SILICON_LABS_32B_PLATFORM_1 ) |
<> | 144:ef7eb2e8f9f7 | 1625 | ret >>= (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK) |
<> | 144:ef7eb2e8f9f7 | 1626 | >> _CMU_LFBPRESC0_LEUART0_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 1627 | #elif defined( _SILICON_LABS_32B_PLATFORM_2 ) |
<> | 144:ef7eb2e8f9f7 | 1628 | ret /= CMU_Log2ToDiv((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK) |
<> | 144:ef7eb2e8f9f7 | 1629 | >> _CMU_LFBPRESC0_LEUART0_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1630 | #endif |
<> | 144:ef7eb2e8f9f7 | 1631 | break; |
<> | 144:ef7eb2e8f9f7 | 1632 | #endif |
<> | 144:ef7eb2e8f9f7 | 1633 | |
<> | 144:ef7eb2e8f9f7 | 1634 | #if defined( _CMU_LFBCLKEN0_LEUART1_MASK ) |
<> | 144:ef7eb2e8f9f7 | 1635 | case (CMU_LEUART1_CLK_BRANCH << CMU_CLK_BRANCH_POS): |
<> | 144:ef7eb2e8f9f7 | 1636 | ret = lfClkGet(cmuClock_LFB); |
<> | 144:ef7eb2e8f9f7 | 1637 | #if defined( _SILICON_LABS_32B_PLATFORM_1 ) |
<> | 144:ef7eb2e8f9f7 | 1638 | ret >>= (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK) |
<> | 144:ef7eb2e8f9f7 | 1639 | >> _CMU_LFBPRESC0_LEUART1_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 1640 | #elif defined( _SILICON_LABS_32B_PLATFORM_2 ) |
<> | 144:ef7eb2e8f9f7 | 1641 | ret /= CMU_Log2ToDiv((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK) |
<> | 144:ef7eb2e8f9f7 | 1642 | >> _CMU_LFBPRESC0_LEUART1_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1643 | #endif |
<> | 144:ef7eb2e8f9f7 | 1644 | break; |
<> | 144:ef7eb2e8f9f7 | 1645 | #endif |
<> | 144:ef7eb2e8f9f7 | 1646 | |
<> | 144:ef7eb2e8f9f7 | 1647 | #if defined( _SILICON_LABS_32B_PLATFORM_2 ) |
<> | 144:ef7eb2e8f9f7 | 1648 | case (CMU_LFE_CLK_BRANCH << CMU_CLK_BRANCH_POS): |
<> | 144:ef7eb2e8f9f7 | 1649 | ret = lfClkGet(cmuClock_LFE); |
<> | 144:ef7eb2e8f9f7 | 1650 | break; |
<> | 144:ef7eb2e8f9f7 | 1651 | #endif |
<> | 144:ef7eb2e8f9f7 | 1652 | |
<> | 144:ef7eb2e8f9f7 | 1653 | case (CMU_DBG_CLK_BRANCH << CMU_CLK_BRANCH_POS): |
<> | 144:ef7eb2e8f9f7 | 1654 | ret = dbgClkGet(); |
<> | 144:ef7eb2e8f9f7 | 1655 | break; |
<> | 144:ef7eb2e8f9f7 | 1656 | |
<> | 144:ef7eb2e8f9f7 | 1657 | case (CMU_AUX_CLK_BRANCH << CMU_CLK_BRANCH_POS): |
<> | 144:ef7eb2e8f9f7 | 1658 | ret = auxClkGet(); |
<> | 144:ef7eb2e8f9f7 | 1659 | break; |
<> | 144:ef7eb2e8f9f7 | 1660 | |
<> | 144:ef7eb2e8f9f7 | 1661 | #if defined(USB_PRESENT) |
<> | 144:ef7eb2e8f9f7 | 1662 | case (CMU_USBC_CLK_BRANCH << CMU_CLK_BRANCH_POS): |
<> | 144:ef7eb2e8f9f7 | 1663 | ret = usbCClkGet(); |
<> | 144:ef7eb2e8f9f7 | 1664 | break; |
<> | 144:ef7eb2e8f9f7 | 1665 | #endif |
<> | 144:ef7eb2e8f9f7 | 1666 | |
<> | 144:ef7eb2e8f9f7 | 1667 | default: |
<> | 144:ef7eb2e8f9f7 | 1668 | EFM_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 1669 | ret = 0; |
<> | 144:ef7eb2e8f9f7 | 1670 | break; |
<> | 144:ef7eb2e8f9f7 | 1671 | } |
<> | 144:ef7eb2e8f9f7 | 1672 | |
<> | 144:ef7eb2e8f9f7 | 1673 | return ret; |
<> | 144:ef7eb2e8f9f7 | 1674 | } |
<> | 144:ef7eb2e8f9f7 | 1675 | |
<> | 144:ef7eb2e8f9f7 | 1676 | |
<> | 144:ef7eb2e8f9f7 | 1677 | #if defined( _SILICON_LABS_32B_PLATFORM_2 ) |
<> | 144:ef7eb2e8f9f7 | 1678 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 1679 | * @brief |
<> | 144:ef7eb2e8f9f7 | 1680 | * Get clock prescaler. |
<> | 144:ef7eb2e8f9f7 | 1681 | * |
<> | 144:ef7eb2e8f9f7 | 1682 | * @param[in] clock |
<> | 144:ef7eb2e8f9f7 | 1683 | * Clock point to get the prescaler for. Notice that not all clock points |
<> | 144:ef7eb2e8f9f7 | 1684 | * have a prescaler. Please refer to CMU overview in reference manual. |
<> | 144:ef7eb2e8f9f7 | 1685 | * |
<> | 144:ef7eb2e8f9f7 | 1686 | * @return |
<> | 144:ef7eb2e8f9f7 | 1687 | * The prescaler value of the current clock point. 0 is returned |
<> | 144:ef7eb2e8f9f7 | 1688 | * if @p clock specifies a clock point without a prescaler. |
<> | 144:ef7eb2e8f9f7 | 1689 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 1690 | uint32_t CMU_ClockPrescGet(CMU_Clock_TypeDef clock) |
<> | 144:ef7eb2e8f9f7 | 1691 | { |
<> | 144:ef7eb2e8f9f7 | 1692 | uint32_t prescReg; |
<> | 144:ef7eb2e8f9f7 | 1693 | uint32_t ret; |
<> | 144:ef7eb2e8f9f7 | 1694 | |
<> | 144:ef7eb2e8f9f7 | 1695 | /* Get prescaler register id. */ |
<> | 144:ef7eb2e8f9f7 | 1696 | prescReg = (clock >> CMU_PRESC_REG_POS) & CMU_PRESC_REG_MASK; |
<> | 144:ef7eb2e8f9f7 | 1697 | |
<> | 144:ef7eb2e8f9f7 | 1698 | switch (prescReg) |
<> | 144:ef7eb2e8f9f7 | 1699 | { |
<> | 144:ef7eb2e8f9f7 | 1700 | case CMU_HFPRESC_REG: |
<> | 144:ef7eb2e8f9f7 | 1701 | ret = ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK) |
<> | 144:ef7eb2e8f9f7 | 1702 | >> _CMU_HFPRESC_PRESC_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1703 | break; |
<> | 144:ef7eb2e8f9f7 | 1704 | |
<> | 144:ef7eb2e8f9f7 | 1705 | case CMU_HFEXPPRESC_REG: |
<> | 144:ef7eb2e8f9f7 | 1706 | ret = ((CMU->HFEXPPRESC & _CMU_HFEXPPRESC_PRESC_MASK) |
<> | 144:ef7eb2e8f9f7 | 1707 | >> _CMU_HFEXPPRESC_PRESC_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1708 | break; |
<> | 144:ef7eb2e8f9f7 | 1709 | |
<> | 144:ef7eb2e8f9f7 | 1710 | case CMU_HFCLKLEPRESC_REG: |
<> | 144:ef7eb2e8f9f7 | 1711 | ret = ((CMU->HFPRESC & _CMU_HFPRESC_HFCLKLEPRESC_MASK) |
<> | 144:ef7eb2e8f9f7 | 1712 | >> _CMU_HFPRESC_HFCLKLEPRESC_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1713 | break; |
<> | 144:ef7eb2e8f9f7 | 1714 | |
<> | 144:ef7eb2e8f9f7 | 1715 | case CMU_HFPERPRESC_REG: |
<> | 144:ef7eb2e8f9f7 | 1716 | ret = ((CMU->HFPERPRESC & _CMU_HFPERPRESC_PRESC_MASK) |
<> | 144:ef7eb2e8f9f7 | 1717 | >> _CMU_HFPERPRESC_PRESC_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1718 | break; |
<> | 144:ef7eb2e8f9f7 | 1719 | |
<> | 144:ef7eb2e8f9f7 | 1720 | #if defined( _CMU_HFRADIOPRESC_PRESC_MASK ) |
<> | 144:ef7eb2e8f9f7 | 1721 | case CMU_HFRADIOPRESC_REG: |
<> | 144:ef7eb2e8f9f7 | 1722 | ret = ((CMU->HFRADIOPRESC & _CMU_HFRADIOPRESC_PRESC_MASK) |
<> | 144:ef7eb2e8f9f7 | 1723 | >> _CMU_HFRADIOPRESC_PRESC_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1724 | break; |
<> | 144:ef7eb2e8f9f7 | 1725 | #endif |
<> | 144:ef7eb2e8f9f7 | 1726 | |
<> | 144:ef7eb2e8f9f7 | 1727 | case CMU_HFCOREPRESC_REG: |
<> | 144:ef7eb2e8f9f7 | 1728 | ret = ((CMU->HFCOREPRESC & _CMU_HFCOREPRESC_PRESC_MASK) |
<> | 144:ef7eb2e8f9f7 | 1729 | >> _CMU_HFCOREPRESC_PRESC_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1730 | break; |
<> | 144:ef7eb2e8f9f7 | 1731 | |
<> | 144:ef7eb2e8f9f7 | 1732 | case CMU_LFAPRESC0_REG: |
<> | 144:ef7eb2e8f9f7 | 1733 | switch (clock) |
<> | 144:ef7eb2e8f9f7 | 1734 | { |
<> | 144:ef7eb2e8f9f7 | 1735 | #if defined( _CMU_LFAPRESC0_LETIMER0_MASK ) |
<> | 144:ef7eb2e8f9f7 | 1736 | case cmuClock_LETIMER0: |
<> | 144:ef7eb2e8f9f7 | 1737 | ret = (((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK) |
<> | 144:ef7eb2e8f9f7 | 1738 | >> _CMU_LFAPRESC0_LETIMER0_SHIFT)); |
<> | 144:ef7eb2e8f9f7 | 1739 | /* Convert the exponent to prescaler value. */ |
<> | 144:ef7eb2e8f9f7 | 1740 | ret = CMU_Log2ToDiv(ret) - 1U; |
<> | 144:ef7eb2e8f9f7 | 1741 | break; |
<> | 144:ef7eb2e8f9f7 | 1742 | #endif |
<> | 144:ef7eb2e8f9f7 | 1743 | |
<> | 144:ef7eb2e8f9f7 | 1744 | default: |
<> | 144:ef7eb2e8f9f7 | 1745 | EFM_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 1746 | ret = 0U; |
<> | 144:ef7eb2e8f9f7 | 1747 | break; |
<> | 144:ef7eb2e8f9f7 | 1748 | } |
<> | 144:ef7eb2e8f9f7 | 1749 | break; |
<> | 144:ef7eb2e8f9f7 | 1750 | |
<> | 144:ef7eb2e8f9f7 | 1751 | case CMU_LFBPRESC0_REG: |
<> | 144:ef7eb2e8f9f7 | 1752 | switch (clock) |
<> | 144:ef7eb2e8f9f7 | 1753 | { |
<> | 144:ef7eb2e8f9f7 | 1754 | #if defined( _CMU_LFBPRESC0_LEUART0_MASK ) |
<> | 144:ef7eb2e8f9f7 | 1755 | case cmuClock_LEUART0: |
<> | 144:ef7eb2e8f9f7 | 1756 | ret = (((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK) |
<> | 144:ef7eb2e8f9f7 | 1757 | >> _CMU_LFBPRESC0_LEUART0_SHIFT)); |
<> | 144:ef7eb2e8f9f7 | 1758 | /* Convert the exponent to prescaler value. */ |
<> | 144:ef7eb2e8f9f7 | 1759 | ret = CMU_Log2ToDiv(ret) - 1U; |
<> | 144:ef7eb2e8f9f7 | 1760 | break; |
<> | 144:ef7eb2e8f9f7 | 1761 | #endif |
<> | 144:ef7eb2e8f9f7 | 1762 | |
<> | 144:ef7eb2e8f9f7 | 1763 | #if defined( _CMU_LFBPRESC0_LEUART1_MASK ) |
<> | 144:ef7eb2e8f9f7 | 1764 | case cmuClock_LEUART1: |
<> | 144:ef7eb2e8f9f7 | 1765 | ret = (((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK) |
<> | 144:ef7eb2e8f9f7 | 1766 | >> _CMU_LFBPRESC0_LEUART1_SHIFT)); |
<> | 144:ef7eb2e8f9f7 | 1767 | /* Convert the exponent to prescaler value. */ |
<> | 144:ef7eb2e8f9f7 | 1768 | ret = CMU_Log2ToDiv(ret) - 1U; |
<> | 144:ef7eb2e8f9f7 | 1769 | break; |
<> | 144:ef7eb2e8f9f7 | 1770 | #endif |
<> | 144:ef7eb2e8f9f7 | 1771 | |
<> | 144:ef7eb2e8f9f7 | 1772 | default: |
<> | 144:ef7eb2e8f9f7 | 1773 | EFM_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 1774 | ret = 0U; |
<> | 144:ef7eb2e8f9f7 | 1775 | break; |
<> | 144:ef7eb2e8f9f7 | 1776 | } |
<> | 144:ef7eb2e8f9f7 | 1777 | break; |
<> | 144:ef7eb2e8f9f7 | 1778 | |
<> | 144:ef7eb2e8f9f7 | 1779 | case CMU_LFEPRESC0_REG: |
<> | 144:ef7eb2e8f9f7 | 1780 | switch (clock) |
<> | 144:ef7eb2e8f9f7 | 1781 | { |
<> | 144:ef7eb2e8f9f7 | 1782 | #if defined( RTCC_PRESENT ) |
<> | 144:ef7eb2e8f9f7 | 1783 | case cmuClock_RTCC: |
<> | 144:ef7eb2e8f9f7 | 1784 | /* No need to compute with LFEPRESC0_RTCC - DIV1 is the only */ |
<> | 144:ef7eb2e8f9f7 | 1785 | /* allowed value. Convert the exponent to prescaler value. */ |
<> | 144:ef7eb2e8f9f7 | 1786 | ret = _CMU_LFEPRESC0_RTCC_DIV1; |
<> | 144:ef7eb2e8f9f7 | 1787 | break; |
<> | 144:ef7eb2e8f9f7 | 1788 | |
<> | 144:ef7eb2e8f9f7 | 1789 | default: |
<> | 144:ef7eb2e8f9f7 | 1790 | EFM_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 1791 | ret = 0U; |
<> | 144:ef7eb2e8f9f7 | 1792 | break; |
<> | 144:ef7eb2e8f9f7 | 1793 | #endif |
<> | 144:ef7eb2e8f9f7 | 1794 | } |
<> | 144:ef7eb2e8f9f7 | 1795 | break; |
<> | 144:ef7eb2e8f9f7 | 1796 | |
<> | 144:ef7eb2e8f9f7 | 1797 | default: |
<> | 144:ef7eb2e8f9f7 | 1798 | EFM_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 1799 | ret = 0U; |
<> | 144:ef7eb2e8f9f7 | 1800 | break; |
<> | 144:ef7eb2e8f9f7 | 1801 | } |
<> | 144:ef7eb2e8f9f7 | 1802 | |
<> | 144:ef7eb2e8f9f7 | 1803 | return ret; |
<> | 144:ef7eb2e8f9f7 | 1804 | } |
<> | 144:ef7eb2e8f9f7 | 1805 | #endif |
<> | 144:ef7eb2e8f9f7 | 1806 | |
<> | 144:ef7eb2e8f9f7 | 1807 | |
<> | 144:ef7eb2e8f9f7 | 1808 | #if defined( _SILICON_LABS_32B_PLATFORM_2 ) |
<> | 144:ef7eb2e8f9f7 | 1809 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 1810 | * @brief |
<> | 144:ef7eb2e8f9f7 | 1811 | * Set clock prescaler. |
<> | 144:ef7eb2e8f9f7 | 1812 | * |
<> | 144:ef7eb2e8f9f7 | 1813 | * @note |
<> | 144:ef7eb2e8f9f7 | 1814 | * If setting a LF clock prescaler, synchronization into the low frequency |
<> | 144:ef7eb2e8f9f7 | 1815 | * domain is required. If the same register is modified before a previous |
<> | 144:ef7eb2e8f9f7 | 1816 | * update has completed, this function will stall until the previous |
<> | 144:ef7eb2e8f9f7 | 1817 | * synchronization has completed. Please refer to CMU_FreezeEnable() for |
<> | 144:ef7eb2e8f9f7 | 1818 | * a suggestion on how to reduce stalling time in some use cases. |
<> | 144:ef7eb2e8f9f7 | 1819 | * |
<> | 144:ef7eb2e8f9f7 | 1820 | * @param[in] clock |
<> | 144:ef7eb2e8f9f7 | 1821 | * Clock point to set prescaler for. Notice that not all clock points |
<> | 144:ef7eb2e8f9f7 | 1822 | * have a prescaler, please refer to CMU overview in the reference manual. |
<> | 144:ef7eb2e8f9f7 | 1823 | * |
<> | 144:ef7eb2e8f9f7 | 1824 | * @param[in] presc |
<> | 144:ef7eb2e8f9f7 | 1825 | * The clock prescaler to use. |
<> | 144:ef7eb2e8f9f7 | 1826 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 1827 | void CMU_ClockPrescSet(CMU_Clock_TypeDef clock, CMU_ClkPresc_TypeDef presc) |
<> | 144:ef7eb2e8f9f7 | 1828 | { |
<> | 144:ef7eb2e8f9f7 | 1829 | uint32_t freq; |
<> | 144:ef7eb2e8f9f7 | 1830 | uint32_t prescReg; |
<> | 144:ef7eb2e8f9f7 | 1831 | |
<> | 144:ef7eb2e8f9f7 | 1832 | /* Get divisor reg id */ |
<> | 144:ef7eb2e8f9f7 | 1833 | prescReg = (clock >> CMU_PRESC_REG_POS) & CMU_PRESC_REG_MASK; |
<> | 144:ef7eb2e8f9f7 | 1834 | |
<> | 144:ef7eb2e8f9f7 | 1835 | switch (prescReg) |
<> | 144:ef7eb2e8f9f7 | 1836 | { |
<> | 144:ef7eb2e8f9f7 | 1837 | case CMU_HFPRESC_REG: |
<> | 144:ef7eb2e8f9f7 | 1838 | EFM_ASSERT(presc < 32U); |
<> | 144:ef7eb2e8f9f7 | 1839 | |
<> | 144:ef7eb2e8f9f7 | 1840 | CMU->HFPRESC = (CMU->HFPRESC & ~_CMU_HFPRESC_PRESC_MASK) |
<> | 144:ef7eb2e8f9f7 | 1841 | | (presc << _CMU_HFPRESC_PRESC_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1842 | break; |
<> | 144:ef7eb2e8f9f7 | 1843 | |
<> | 144:ef7eb2e8f9f7 | 1844 | case CMU_HFEXPPRESC_REG: |
<> | 144:ef7eb2e8f9f7 | 1845 | EFM_ASSERT(presc < 32U); |
<> | 144:ef7eb2e8f9f7 | 1846 | |
<> | 144:ef7eb2e8f9f7 | 1847 | CMU->HFEXPPRESC = (CMU->HFEXPPRESC & ~_CMU_HFEXPPRESC_PRESC_MASK) |
<> | 144:ef7eb2e8f9f7 | 1848 | | (presc << _CMU_HFEXPPRESC_PRESC_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1849 | break; |
<> | 144:ef7eb2e8f9f7 | 1850 | |
<> | 144:ef7eb2e8f9f7 | 1851 | case CMU_HFCLKLEPRESC_REG: |
<> | 144:ef7eb2e8f9f7 | 1852 | EFM_ASSERT(presc < 2U); |
<> | 144:ef7eb2e8f9f7 | 1853 | |
<> | 144:ef7eb2e8f9f7 | 1854 | /* Specifies the clock divider for HFCLKLE. When running at frequencies |
<> | 144:ef7eb2e8f9f7 | 1855 | * higher than 32 MHz, this must be set to DIV4. */ |
<> | 144:ef7eb2e8f9f7 | 1856 | CMU->HFPRESC = (CMU->HFPRESC & ~_CMU_HFPRESC_HFCLKLEPRESC_MASK) |
<> | 144:ef7eb2e8f9f7 | 1857 | | (presc << _CMU_HFPRESC_HFCLKLEPRESC_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1858 | break; |
<> | 144:ef7eb2e8f9f7 | 1859 | |
<> | 144:ef7eb2e8f9f7 | 1860 | case CMU_HFPERPRESC_REG: |
<> | 144:ef7eb2e8f9f7 | 1861 | EFM_ASSERT(presc < 512U); |
<> | 144:ef7eb2e8f9f7 | 1862 | |
<> | 144:ef7eb2e8f9f7 | 1863 | CMU->HFPERPRESC = (CMU->HFPERPRESC & ~_CMU_HFPERPRESC_PRESC_MASK) |
<> | 144:ef7eb2e8f9f7 | 1864 | | (presc << _CMU_HFPERPRESC_PRESC_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1865 | break; |
<> | 144:ef7eb2e8f9f7 | 1866 | |
<> | 144:ef7eb2e8f9f7 | 1867 | #if defined( _CMU_HFRADIOPRESC_PRESC_MASK ) |
<> | 144:ef7eb2e8f9f7 | 1868 | case CMU_HFRADIOPRESC_REG: |
<> | 144:ef7eb2e8f9f7 | 1869 | EFM_ASSERT(presc < 512U); |
<> | 144:ef7eb2e8f9f7 | 1870 | |
<> | 144:ef7eb2e8f9f7 | 1871 | CMU->HFRADIOPRESC = (CMU->HFRADIOPRESC & ~_CMU_HFRADIOPRESC_PRESC_MASK) |
<> | 144:ef7eb2e8f9f7 | 1872 | | (presc << _CMU_HFRADIOPRESC_PRESC_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1873 | break; |
<> | 144:ef7eb2e8f9f7 | 1874 | #endif |
<> | 144:ef7eb2e8f9f7 | 1875 | |
<> | 144:ef7eb2e8f9f7 | 1876 | case CMU_HFCOREPRESC_REG: |
<> | 144:ef7eb2e8f9f7 | 1877 | EFM_ASSERT(presc < 512U); |
<> | 144:ef7eb2e8f9f7 | 1878 | |
<> | 144:ef7eb2e8f9f7 | 1879 | /* Configure worst case wait states for flash access before setting |
<> | 144:ef7eb2e8f9f7 | 1880 | * the prescaler. */ |
<> | 144:ef7eb2e8f9f7 | 1881 | flashWaitStateControl(CMU_MAX_FREQ_0WS + 1); |
<> | 144:ef7eb2e8f9f7 | 1882 | |
<> | 144:ef7eb2e8f9f7 | 1883 | CMU->HFCOREPRESC = (CMU->HFCOREPRESC & ~_CMU_HFCOREPRESC_PRESC_MASK) |
<> | 144:ef7eb2e8f9f7 | 1884 | | (presc << _CMU_HFCOREPRESC_PRESC_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1885 | |
<> | 144:ef7eb2e8f9f7 | 1886 | /* Update CMSIS core clock variable */ |
<> | 144:ef7eb2e8f9f7 | 1887 | /* (The function will update the global variable) */ |
<> | 144:ef7eb2e8f9f7 | 1888 | freq = SystemCoreClockGet(); |
<> | 144:ef7eb2e8f9f7 | 1889 | |
<> | 144:ef7eb2e8f9f7 | 1890 | /* Optimize flash access wait state setting for current core clk */ |
<> | 144:ef7eb2e8f9f7 | 1891 | flashWaitStateControl(freq); |
<> | 144:ef7eb2e8f9f7 | 1892 | break; |
<> | 144:ef7eb2e8f9f7 | 1893 | |
<> | 144:ef7eb2e8f9f7 | 1894 | case CMU_LFAPRESC0_REG: |
<> | 144:ef7eb2e8f9f7 | 1895 | switch (clock) |
<> | 144:ef7eb2e8f9f7 | 1896 | { |
<> | 144:ef7eb2e8f9f7 | 1897 | #if defined( RTC_PRESENT ) |
<> | 144:ef7eb2e8f9f7 | 1898 | case cmuClock_RTC: |
<> | 144:ef7eb2e8f9f7 | 1899 | EFM_ASSERT(presc <= 32768U); |
<> | 144:ef7eb2e8f9f7 | 1900 | |
<> | 144:ef7eb2e8f9f7 | 1901 | /* Convert prescaler value to DIV exponent scale. */ |
<> | 144:ef7eb2e8f9f7 | 1902 | presc = CMU_PrescToLog2(presc); |
<> | 144:ef7eb2e8f9f7 | 1903 | |
<> | 144:ef7eb2e8f9f7 | 1904 | /* LF register about to be modified require sync. Busy check. */ |
<> | 144:ef7eb2e8f9f7 | 1905 | syncReg(CMU_SYNCBUSY_LFAPRESC0); |
<> | 144:ef7eb2e8f9f7 | 1906 | |
<> | 144:ef7eb2e8f9f7 | 1907 | CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTC_MASK) |
<> | 144:ef7eb2e8f9f7 | 1908 | | (presc << _CMU_LFAPRESC0_RTC_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1909 | break; |
<> | 144:ef7eb2e8f9f7 | 1910 | #endif |
<> | 144:ef7eb2e8f9f7 | 1911 | |
<> | 144:ef7eb2e8f9f7 | 1912 | #if defined( RTCC_PRESENT ) |
<> | 144:ef7eb2e8f9f7 | 1913 | case cmuClock_RTCC: |
<> | 144:ef7eb2e8f9f7 | 1914 | #if defined( _CMU_LFEPRESC0_RTCC_MASK ) |
<> | 144:ef7eb2e8f9f7 | 1915 | /* DIV1 is the only accepted value. */ |
<> | 144:ef7eb2e8f9f7 | 1916 | EFM_ASSERT(presc <= 0U); |
<> | 144:ef7eb2e8f9f7 | 1917 | |
<> | 144:ef7eb2e8f9f7 | 1918 | /* LF register about to be modified require sync. Busy check.. */ |
<> | 144:ef7eb2e8f9f7 | 1919 | syncReg(CMU_SYNCBUSY_LFEPRESC0); |
<> | 144:ef7eb2e8f9f7 | 1920 | |
<> | 144:ef7eb2e8f9f7 | 1921 | CMU->LFEPRESC0 = (CMU->LFEPRESC0 & ~_CMU_LFEPRESC0_RTCC_MASK) |
<> | 144:ef7eb2e8f9f7 | 1922 | | (presc << _CMU_LFEPRESC0_RTCC_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1923 | #else |
<> | 144:ef7eb2e8f9f7 | 1924 | EFM_ASSERT(presc <= 32768U); |
<> | 144:ef7eb2e8f9f7 | 1925 | |
<> | 144:ef7eb2e8f9f7 | 1926 | /* Convert prescaler value to DIV exponent scale. */ |
<> | 144:ef7eb2e8f9f7 | 1927 | presc = CMU_PrescToLog2(presc); |
<> | 144:ef7eb2e8f9f7 | 1928 | |
<> | 144:ef7eb2e8f9f7 | 1929 | /* LF register about to be modified require sync. Busy check. */ |
<> | 144:ef7eb2e8f9f7 | 1930 | syncReg(CMU_SYNCBUSY_LFAPRESC0); |
<> | 144:ef7eb2e8f9f7 | 1931 | |
<> | 144:ef7eb2e8f9f7 | 1932 | CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTCC_MASK) |
<> | 144:ef7eb2e8f9f7 | 1933 | | (presc << _CMU_LFAPRESC0_RTCC_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1934 | #endif |
<> | 144:ef7eb2e8f9f7 | 1935 | break; |
<> | 144:ef7eb2e8f9f7 | 1936 | #endif |
<> | 144:ef7eb2e8f9f7 | 1937 | |
<> | 144:ef7eb2e8f9f7 | 1938 | #if defined( _CMU_LFAPRESC0_LETIMER0_MASK ) |
<> | 144:ef7eb2e8f9f7 | 1939 | case cmuClock_LETIMER0: |
<> | 144:ef7eb2e8f9f7 | 1940 | EFM_ASSERT(presc <= 32768U); |
<> | 144:ef7eb2e8f9f7 | 1941 | |
<> | 144:ef7eb2e8f9f7 | 1942 | /* Convert prescaler value to DIV exponent scale. */ |
<> | 144:ef7eb2e8f9f7 | 1943 | presc = CMU_PrescToLog2(presc); |
<> | 144:ef7eb2e8f9f7 | 1944 | |
<> | 144:ef7eb2e8f9f7 | 1945 | /* LF register about to be modified require sync. Busy check. */ |
<> | 144:ef7eb2e8f9f7 | 1946 | syncReg(CMU_SYNCBUSY_LFAPRESC0); |
<> | 144:ef7eb2e8f9f7 | 1947 | |
<> | 144:ef7eb2e8f9f7 | 1948 | CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LETIMER0_MASK) |
<> | 144:ef7eb2e8f9f7 | 1949 | | (presc << _CMU_LFAPRESC0_LETIMER0_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1950 | break; |
<> | 144:ef7eb2e8f9f7 | 1951 | #endif |
<> | 144:ef7eb2e8f9f7 | 1952 | |
<> | 144:ef7eb2e8f9f7 | 1953 | default: |
<> | 144:ef7eb2e8f9f7 | 1954 | EFM_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 1955 | break; |
<> | 144:ef7eb2e8f9f7 | 1956 | } |
<> | 144:ef7eb2e8f9f7 | 1957 | break; |
<> | 144:ef7eb2e8f9f7 | 1958 | |
<> | 144:ef7eb2e8f9f7 | 1959 | case CMU_LFBPRESC0_REG: |
<> | 144:ef7eb2e8f9f7 | 1960 | switch (clock) |
<> | 144:ef7eb2e8f9f7 | 1961 | { |
<> | 144:ef7eb2e8f9f7 | 1962 | #if defined( _CMU_LFBPRESC0_LEUART0_MASK ) |
<> | 144:ef7eb2e8f9f7 | 1963 | case cmuClock_LEUART0: |
<> | 144:ef7eb2e8f9f7 | 1964 | EFM_ASSERT(presc <= 8U); |
<> | 144:ef7eb2e8f9f7 | 1965 | |
<> | 144:ef7eb2e8f9f7 | 1966 | /* Convert prescaler value to DIV exponent scale. */ |
<> | 144:ef7eb2e8f9f7 | 1967 | presc = CMU_PrescToLog2(presc); |
<> | 144:ef7eb2e8f9f7 | 1968 | |
<> | 144:ef7eb2e8f9f7 | 1969 | /* LF register about to be modified require sync. Busy check. */ |
<> | 144:ef7eb2e8f9f7 | 1970 | syncReg(CMU_SYNCBUSY_LFBPRESC0); |
<> | 144:ef7eb2e8f9f7 | 1971 | |
<> | 144:ef7eb2e8f9f7 | 1972 | CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART0_MASK) |
<> | 144:ef7eb2e8f9f7 | 1973 | | (presc << _CMU_LFBPRESC0_LEUART0_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1974 | break; |
<> | 144:ef7eb2e8f9f7 | 1975 | #endif |
<> | 144:ef7eb2e8f9f7 | 1976 | |
<> | 144:ef7eb2e8f9f7 | 1977 | #if defined( _CMU_LFBPRESC0_LEUART1_MASK ) |
<> | 144:ef7eb2e8f9f7 | 1978 | case cmuClock_LEUART1: |
<> | 144:ef7eb2e8f9f7 | 1979 | EFM_ASSERT(presc <= 8U); |
<> | 144:ef7eb2e8f9f7 | 1980 | |
<> | 144:ef7eb2e8f9f7 | 1981 | /* Convert prescaler value to DIV exponent scale. */ |
<> | 144:ef7eb2e8f9f7 | 1982 | presc = CMU_PrescToLog2(presc); |
<> | 144:ef7eb2e8f9f7 | 1983 | |
<> | 144:ef7eb2e8f9f7 | 1984 | /* LF register about to be modified require sync. Busy check. */ |
<> | 144:ef7eb2e8f9f7 | 1985 | syncReg(CMU_SYNCBUSY_LFBPRESC0); |
<> | 144:ef7eb2e8f9f7 | 1986 | |
<> | 144:ef7eb2e8f9f7 | 1987 | CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART1_MASK) |
<> | 144:ef7eb2e8f9f7 | 1988 | | (presc << _CMU_LFBPRESC0_LEUART1_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 1989 | break; |
<> | 144:ef7eb2e8f9f7 | 1990 | #endif |
<> | 144:ef7eb2e8f9f7 | 1991 | |
<> | 144:ef7eb2e8f9f7 | 1992 | default: |
<> | 144:ef7eb2e8f9f7 | 1993 | EFM_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 1994 | break; |
<> | 144:ef7eb2e8f9f7 | 1995 | } |
<> | 144:ef7eb2e8f9f7 | 1996 | break; |
<> | 144:ef7eb2e8f9f7 | 1997 | |
<> | 144:ef7eb2e8f9f7 | 1998 | case CMU_LFEPRESC0_REG: |
<> | 144:ef7eb2e8f9f7 | 1999 | switch (clock) |
<> | 144:ef7eb2e8f9f7 | 2000 | { |
<> | 144:ef7eb2e8f9f7 | 2001 | #if defined( _CMU_LFEPRESC0_RTCC_MASK ) |
<> | 144:ef7eb2e8f9f7 | 2002 | case cmuClock_RTCC: |
<> | 144:ef7eb2e8f9f7 | 2003 | EFM_ASSERT(presc <= 0U); |
<> | 144:ef7eb2e8f9f7 | 2004 | |
<> | 144:ef7eb2e8f9f7 | 2005 | /* LF register about to be modified require sync. Busy check. */ |
<> | 144:ef7eb2e8f9f7 | 2006 | syncReg(CMU_SYNCBUSY_LFEPRESC0); |
<> | 144:ef7eb2e8f9f7 | 2007 | |
<> | 144:ef7eb2e8f9f7 | 2008 | CMU->LFEPRESC0 = (CMU->LFEPRESC0 & ~_CMU_LFEPRESC0_RTCC_MASK) |
<> | 144:ef7eb2e8f9f7 | 2009 | | (presc << _CMU_LFEPRESC0_RTCC_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 2010 | break; |
<> | 144:ef7eb2e8f9f7 | 2011 | #endif |
<> | 144:ef7eb2e8f9f7 | 2012 | |
<> | 144:ef7eb2e8f9f7 | 2013 | default: |
<> | 144:ef7eb2e8f9f7 | 2014 | EFM_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 2015 | break; |
<> | 144:ef7eb2e8f9f7 | 2016 | } |
<> | 144:ef7eb2e8f9f7 | 2017 | break; |
<> | 144:ef7eb2e8f9f7 | 2018 | |
<> | 144:ef7eb2e8f9f7 | 2019 | default: |
<> | 144:ef7eb2e8f9f7 | 2020 | EFM_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 2021 | break; |
<> | 144:ef7eb2e8f9f7 | 2022 | } |
<> | 144:ef7eb2e8f9f7 | 2023 | } |
<> | 144:ef7eb2e8f9f7 | 2024 | #endif |
<> | 144:ef7eb2e8f9f7 | 2025 | |
<> | 144:ef7eb2e8f9f7 | 2026 | |
<> | 144:ef7eb2e8f9f7 | 2027 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 2028 | * @brief |
<> | 144:ef7eb2e8f9f7 | 2029 | * Get currently selected reference clock used for a clock branch. |
<> | 144:ef7eb2e8f9f7 | 2030 | * |
<> | 144:ef7eb2e8f9f7 | 2031 | * @param[in] clock |
<> | 144:ef7eb2e8f9f7 | 2032 | * Clock branch to fetch selected ref. clock for. One of: |
<> | 144:ef7eb2e8f9f7 | 2033 | * @li #cmuClock_HF |
<> | 144:ef7eb2e8f9f7 | 2034 | * @li #cmuClock_LFA |
<> | 144:ef7eb2e8f9f7 | 2035 | * @li #cmuClock_LFB @if _CMU_LFCLKSEL_LFAE_ULFRCO |
<> | 144:ef7eb2e8f9f7 | 2036 | * @li #cmuClock_LFC |
<> | 144:ef7eb2e8f9f7 | 2037 | * @endif @if _SILICON_LABS_32B_PLATFORM_2 |
<> | 144:ef7eb2e8f9f7 | 2038 | * @li #cmuClock_LFE |
<> | 144:ef7eb2e8f9f7 | 2039 | * @endif |
<> | 144:ef7eb2e8f9f7 | 2040 | * @li #cmuClock_DBG @if DOXYDOC_USB_PRESENT |
<> | 144:ef7eb2e8f9f7 | 2041 | * @li #cmuClock_USBC |
<> | 144:ef7eb2e8f9f7 | 2042 | * @endif |
<> | 144:ef7eb2e8f9f7 | 2043 | * |
<> | 144:ef7eb2e8f9f7 | 2044 | * @return |
<> | 144:ef7eb2e8f9f7 | 2045 | * Reference clock used for clocking selected branch, #cmuSelect_Error if |
<> | 144:ef7eb2e8f9f7 | 2046 | * invalid @p clock provided. |
<> | 144:ef7eb2e8f9f7 | 2047 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 2048 | CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock) |
<> | 144:ef7eb2e8f9f7 | 2049 | { |
<> | 144:ef7eb2e8f9f7 | 2050 | CMU_Select_TypeDef ret = cmuSelect_Disabled; |
<> | 144:ef7eb2e8f9f7 | 2051 | uint32_t selReg; |
<> | 144:ef7eb2e8f9f7 | 2052 | |
<> | 144:ef7eb2e8f9f7 | 2053 | selReg = (clock >> CMU_SEL_REG_POS) & CMU_SEL_REG_MASK; |
<> | 144:ef7eb2e8f9f7 | 2054 | |
<> | 144:ef7eb2e8f9f7 | 2055 | switch (selReg) |
<> | 144:ef7eb2e8f9f7 | 2056 | { |
<> | 144:ef7eb2e8f9f7 | 2057 | case CMU_HFCLKSEL_REG: |
<> | 144:ef7eb2e8f9f7 | 2058 | #if defined( _CMU_HFCLKSEL_HF_MASK ) |
<> | 144:ef7eb2e8f9f7 | 2059 | switch (CMU->HFCLKSEL & _CMU_HFCLKSEL_HF_MASK) |
<> | 144:ef7eb2e8f9f7 | 2060 | { |
<> | 144:ef7eb2e8f9f7 | 2061 | case CMU_HFCLKSEL_HF_LFXO: |
<> | 144:ef7eb2e8f9f7 | 2062 | ret = cmuSelect_LFXO; |
<> | 144:ef7eb2e8f9f7 | 2063 | break; |
<> | 144:ef7eb2e8f9f7 | 2064 | |
<> | 144:ef7eb2e8f9f7 | 2065 | case CMU_HFCLKSEL_HF_LFRCO: |
<> | 144:ef7eb2e8f9f7 | 2066 | ret = cmuSelect_LFRCO; |
<> | 144:ef7eb2e8f9f7 | 2067 | break; |
<> | 144:ef7eb2e8f9f7 | 2068 | |
<> | 144:ef7eb2e8f9f7 | 2069 | case CMU_HFCLKSEL_HF_HFXO: |
<> | 144:ef7eb2e8f9f7 | 2070 | ret = cmuSelect_HFXO; |
<> | 144:ef7eb2e8f9f7 | 2071 | break; |
<> | 144:ef7eb2e8f9f7 | 2072 | |
<> | 144:ef7eb2e8f9f7 | 2073 | default: |
<> | 144:ef7eb2e8f9f7 | 2074 | ret = cmuSelect_HFRCO; |
<> | 144:ef7eb2e8f9f7 | 2075 | break; |
<> | 144:ef7eb2e8f9f7 | 2076 | } |
<> | 144:ef7eb2e8f9f7 | 2077 | #else |
<> | 144:ef7eb2e8f9f7 | 2078 | switch (CMU->STATUS |
<> | 144:ef7eb2e8f9f7 | 2079 | & (CMU_STATUS_HFRCOSEL |
<> | 144:ef7eb2e8f9f7 | 2080 | | CMU_STATUS_HFXOSEL |
<> | 144:ef7eb2e8f9f7 | 2081 | | CMU_STATUS_LFRCOSEL |
<> | 144:ef7eb2e8f9f7 | 2082 | #if defined( CMU_STATUS_USHFRCODIV2SEL ) |
<> | 144:ef7eb2e8f9f7 | 2083 | | CMU_STATUS_USHFRCODIV2SEL |
<> | 144:ef7eb2e8f9f7 | 2084 | #endif |
<> | 144:ef7eb2e8f9f7 | 2085 | | CMU_STATUS_LFXOSEL)) |
<> | 144:ef7eb2e8f9f7 | 2086 | { |
<> | 144:ef7eb2e8f9f7 | 2087 | case CMU_STATUS_LFXOSEL: |
<> | 144:ef7eb2e8f9f7 | 2088 | ret = cmuSelect_LFXO; |
<> | 144:ef7eb2e8f9f7 | 2089 | break; |
<> | 144:ef7eb2e8f9f7 | 2090 | |
<> | 144:ef7eb2e8f9f7 | 2091 | case CMU_STATUS_LFRCOSEL: |
<> | 144:ef7eb2e8f9f7 | 2092 | ret = cmuSelect_LFRCO; |
<> | 144:ef7eb2e8f9f7 | 2093 | break; |
<> | 144:ef7eb2e8f9f7 | 2094 | |
<> | 144:ef7eb2e8f9f7 | 2095 | case CMU_STATUS_HFXOSEL: |
<> | 144:ef7eb2e8f9f7 | 2096 | ret = cmuSelect_HFXO; |
<> | 144:ef7eb2e8f9f7 | 2097 | break; |
<> | 144:ef7eb2e8f9f7 | 2098 | |
<> | 144:ef7eb2e8f9f7 | 2099 | #if defined( CMU_STATUS_USHFRCODIV2SEL ) |
<> | 144:ef7eb2e8f9f7 | 2100 | case CMU_STATUS_USHFRCODIV2SEL: |
<> | 144:ef7eb2e8f9f7 | 2101 | ret = cmuSelect_USHFRCODIV2; |
<> | 144:ef7eb2e8f9f7 | 2102 | break; |
<> | 144:ef7eb2e8f9f7 | 2103 | #endif |
<> | 144:ef7eb2e8f9f7 | 2104 | |
<> | 144:ef7eb2e8f9f7 | 2105 | default: |
<> | 144:ef7eb2e8f9f7 | 2106 | ret = cmuSelect_HFRCO; |
<> | 144:ef7eb2e8f9f7 | 2107 | break; |
<> | 144:ef7eb2e8f9f7 | 2108 | } |
<> | 144:ef7eb2e8f9f7 | 2109 | #endif |
<> | 144:ef7eb2e8f9f7 | 2110 | break; |
<> | 144:ef7eb2e8f9f7 | 2111 | |
<> | 144:ef7eb2e8f9f7 | 2112 | case CMU_LFACLKSEL_REG: |
<> | 144:ef7eb2e8f9f7 | 2113 | #if defined( _CMU_LFCLKSEL_MASK ) |
<> | 144:ef7eb2e8f9f7 | 2114 | switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFA_MASK) |
<> | 144:ef7eb2e8f9f7 | 2115 | { |
<> | 144:ef7eb2e8f9f7 | 2116 | case CMU_LFCLKSEL_LFA_LFRCO: |
<> | 144:ef7eb2e8f9f7 | 2117 | ret = cmuSelect_LFRCO; |
<> | 144:ef7eb2e8f9f7 | 2118 | break; |
<> | 144:ef7eb2e8f9f7 | 2119 | |
<> | 144:ef7eb2e8f9f7 | 2120 | case CMU_LFCLKSEL_LFA_LFXO: |
<> | 144:ef7eb2e8f9f7 | 2121 | ret = cmuSelect_LFXO; |
<> | 144:ef7eb2e8f9f7 | 2122 | break; |
<> | 144:ef7eb2e8f9f7 | 2123 | |
<> | 144:ef7eb2e8f9f7 | 2124 | #if defined( CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 ) |
<> | 144:ef7eb2e8f9f7 | 2125 | case CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2: |
<> | 144:ef7eb2e8f9f7 | 2126 | ret = cmuSelect_CORELEDIV2; |
<> | 144:ef7eb2e8f9f7 | 2127 | break; |
<> | 144:ef7eb2e8f9f7 | 2128 | #endif |
<> | 144:ef7eb2e8f9f7 | 2129 | |
<> | 144:ef7eb2e8f9f7 | 2130 | default: |
<> | 144:ef7eb2e8f9f7 | 2131 | #if defined( CMU_LFCLKSEL_LFAE ) |
<> | 144:ef7eb2e8f9f7 | 2132 | if (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFAE_MASK) |
<> | 144:ef7eb2e8f9f7 | 2133 | { |
<> | 144:ef7eb2e8f9f7 | 2134 | ret = cmuSelect_ULFRCO; |
<> | 144:ef7eb2e8f9f7 | 2135 | break; |
<> | 144:ef7eb2e8f9f7 | 2136 | } |
<> | 144:ef7eb2e8f9f7 | 2137 | #else |
<> | 144:ef7eb2e8f9f7 | 2138 | ret = cmuSelect_Disabled; |
<> | 144:ef7eb2e8f9f7 | 2139 | #endif |
<> | 144:ef7eb2e8f9f7 | 2140 | break; |
<> | 144:ef7eb2e8f9f7 | 2141 | } |
<> | 144:ef7eb2e8f9f7 | 2142 | #endif /* _CMU_LFCLKSEL_MASK */ |
<> | 144:ef7eb2e8f9f7 | 2143 | |
<> | 144:ef7eb2e8f9f7 | 2144 | #if defined( _CMU_LFACLKSEL_MASK ) |
<> | 144:ef7eb2e8f9f7 | 2145 | switch (CMU->LFACLKSEL & _CMU_LFACLKSEL_LFA_MASK) |
<> | 144:ef7eb2e8f9f7 | 2146 | { |
<> | 144:ef7eb2e8f9f7 | 2147 | case CMU_LFACLKSEL_LFA_LFRCO: |
<> | 144:ef7eb2e8f9f7 | 2148 | ret = cmuSelect_LFRCO; |
<> | 144:ef7eb2e8f9f7 | 2149 | break; |
<> | 144:ef7eb2e8f9f7 | 2150 | |
<> | 144:ef7eb2e8f9f7 | 2151 | case CMU_LFACLKSEL_LFA_LFXO: |
<> | 144:ef7eb2e8f9f7 | 2152 | ret = cmuSelect_LFXO; |
<> | 144:ef7eb2e8f9f7 | 2153 | break; |
<> | 144:ef7eb2e8f9f7 | 2154 | |
<> | 144:ef7eb2e8f9f7 | 2155 | case CMU_LFACLKSEL_LFA_ULFRCO: |
<> | 144:ef7eb2e8f9f7 | 2156 | ret = cmuSelect_ULFRCO; |
<> | 144:ef7eb2e8f9f7 | 2157 | break; |
<> | 144:ef7eb2e8f9f7 | 2158 | |
<> | 144:ef7eb2e8f9f7 | 2159 | #if defined( _CMU_LFACLKSEL_LFA_HFCLKLE ) |
<> | 144:ef7eb2e8f9f7 | 2160 | case CMU_LFACLKSEL_LFA_HFCLKLE: |
<> | 144:ef7eb2e8f9f7 | 2161 | ret = cmuSelect_HFCLKLE; |
<> | 144:ef7eb2e8f9f7 | 2162 | break; |
<> | 144:ef7eb2e8f9f7 | 2163 | #endif |
<> | 144:ef7eb2e8f9f7 | 2164 | |
<> | 144:ef7eb2e8f9f7 | 2165 | default: |
<> | 144:ef7eb2e8f9f7 | 2166 | ret = cmuSelect_Disabled; |
<> | 144:ef7eb2e8f9f7 | 2167 | break; |
<> | 144:ef7eb2e8f9f7 | 2168 | } |
<> | 144:ef7eb2e8f9f7 | 2169 | #endif |
<> | 144:ef7eb2e8f9f7 | 2170 | break; |
<> | 144:ef7eb2e8f9f7 | 2171 | |
<> | 144:ef7eb2e8f9f7 | 2172 | case CMU_LFBCLKSEL_REG: |
<> | 144:ef7eb2e8f9f7 | 2173 | #if defined( _CMU_LFCLKSEL_MASK ) |
<> | 144:ef7eb2e8f9f7 | 2174 | switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFB_MASK) |
<> | 144:ef7eb2e8f9f7 | 2175 | { |
<> | 144:ef7eb2e8f9f7 | 2176 | case CMU_LFCLKSEL_LFB_LFRCO: |
<> | 144:ef7eb2e8f9f7 | 2177 | ret = cmuSelect_LFRCO; |
<> | 144:ef7eb2e8f9f7 | 2178 | break; |
<> | 144:ef7eb2e8f9f7 | 2179 | |
<> | 144:ef7eb2e8f9f7 | 2180 | case CMU_LFCLKSEL_LFB_LFXO: |
<> | 144:ef7eb2e8f9f7 | 2181 | ret = cmuSelect_LFXO; |
<> | 144:ef7eb2e8f9f7 | 2182 | break; |
<> | 144:ef7eb2e8f9f7 | 2183 | |
<> | 144:ef7eb2e8f9f7 | 2184 | #if defined( CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 ) |
<> | 144:ef7eb2e8f9f7 | 2185 | case CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2: |
<> | 144:ef7eb2e8f9f7 | 2186 | ret = cmuSelect_CORELEDIV2; |
<> | 144:ef7eb2e8f9f7 | 2187 | break; |
<> | 144:ef7eb2e8f9f7 | 2188 | #endif |
<> | 144:ef7eb2e8f9f7 | 2189 | |
<> | 144:ef7eb2e8f9f7 | 2190 | #if defined( CMU_LFCLKSEL_LFB_HFCLKLE ) |
<> | 144:ef7eb2e8f9f7 | 2191 | case CMU_LFCLKSEL_LFB_HFCLKLE: |
<> | 144:ef7eb2e8f9f7 | 2192 | ret = cmuSelect_HFCLKLE; |
<> | 144:ef7eb2e8f9f7 | 2193 | break; |
<> | 144:ef7eb2e8f9f7 | 2194 | #endif |
<> | 144:ef7eb2e8f9f7 | 2195 | |
<> | 144:ef7eb2e8f9f7 | 2196 | default: |
<> | 144:ef7eb2e8f9f7 | 2197 | #if defined( CMU_LFCLKSEL_LFBE ) |
<> | 144:ef7eb2e8f9f7 | 2198 | if (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFBE_MASK) |
<> | 144:ef7eb2e8f9f7 | 2199 | { |
<> | 144:ef7eb2e8f9f7 | 2200 | ret = cmuSelect_ULFRCO; |
<> | 144:ef7eb2e8f9f7 | 2201 | break; |
<> | 144:ef7eb2e8f9f7 | 2202 | } |
<> | 144:ef7eb2e8f9f7 | 2203 | #else |
<> | 144:ef7eb2e8f9f7 | 2204 | ret = cmuSelect_Disabled; |
<> | 144:ef7eb2e8f9f7 | 2205 | #endif |
<> | 144:ef7eb2e8f9f7 | 2206 | break; |
<> | 144:ef7eb2e8f9f7 | 2207 | } |
<> | 144:ef7eb2e8f9f7 | 2208 | #endif /* _CMU_LFCLKSEL_MASK */ |
<> | 144:ef7eb2e8f9f7 | 2209 | |
<> | 144:ef7eb2e8f9f7 | 2210 | #if defined( _CMU_LFBCLKSEL_MASK ) |
<> | 144:ef7eb2e8f9f7 | 2211 | switch (CMU->LFBCLKSEL & _CMU_LFBCLKSEL_LFB_MASK) |
<> | 144:ef7eb2e8f9f7 | 2212 | { |
<> | 144:ef7eb2e8f9f7 | 2213 | case CMU_LFBCLKSEL_LFB_LFRCO: |
<> | 144:ef7eb2e8f9f7 | 2214 | ret = cmuSelect_LFRCO; |
<> | 144:ef7eb2e8f9f7 | 2215 | break; |
<> | 144:ef7eb2e8f9f7 | 2216 | |
<> | 144:ef7eb2e8f9f7 | 2217 | case CMU_LFBCLKSEL_LFB_LFXO: |
<> | 144:ef7eb2e8f9f7 | 2218 | ret = cmuSelect_LFXO; |
<> | 144:ef7eb2e8f9f7 | 2219 | break; |
<> | 144:ef7eb2e8f9f7 | 2220 | |
<> | 144:ef7eb2e8f9f7 | 2221 | case CMU_LFBCLKSEL_LFB_ULFRCO: |
<> | 144:ef7eb2e8f9f7 | 2222 | ret = cmuSelect_ULFRCO; |
<> | 144:ef7eb2e8f9f7 | 2223 | break; |
<> | 144:ef7eb2e8f9f7 | 2224 | |
<> | 144:ef7eb2e8f9f7 | 2225 | case CMU_LFBCLKSEL_LFB_HFCLKLE: |
<> | 144:ef7eb2e8f9f7 | 2226 | ret = cmuSelect_HFCLKLE; |
<> | 144:ef7eb2e8f9f7 | 2227 | break; |
<> | 144:ef7eb2e8f9f7 | 2228 | |
<> | 144:ef7eb2e8f9f7 | 2229 | default: |
<> | 144:ef7eb2e8f9f7 | 2230 | ret = cmuSelect_Disabled; |
<> | 144:ef7eb2e8f9f7 | 2231 | break; |
<> | 144:ef7eb2e8f9f7 | 2232 | } |
<> | 144:ef7eb2e8f9f7 | 2233 | #endif |
<> | 144:ef7eb2e8f9f7 | 2234 | break; |
<> | 144:ef7eb2e8f9f7 | 2235 | |
<> | 144:ef7eb2e8f9f7 | 2236 | #if defined( _CMU_LFCLKSEL_LFC_MASK ) |
<> | 144:ef7eb2e8f9f7 | 2237 | case CMU_LFCCLKSEL_REG: |
<> | 144:ef7eb2e8f9f7 | 2238 | switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFC_MASK) |
<> | 144:ef7eb2e8f9f7 | 2239 | { |
<> | 144:ef7eb2e8f9f7 | 2240 | case CMU_LFCLKSEL_LFC_LFRCO: |
<> | 144:ef7eb2e8f9f7 | 2241 | ret = cmuSelect_LFRCO; |
<> | 144:ef7eb2e8f9f7 | 2242 | break; |
<> | 144:ef7eb2e8f9f7 | 2243 | |
<> | 144:ef7eb2e8f9f7 | 2244 | case CMU_LFCLKSEL_LFC_LFXO: |
<> | 144:ef7eb2e8f9f7 | 2245 | ret = cmuSelect_LFXO; |
<> | 144:ef7eb2e8f9f7 | 2246 | break; |
<> | 144:ef7eb2e8f9f7 | 2247 | |
<> | 144:ef7eb2e8f9f7 | 2248 | default: |
<> | 144:ef7eb2e8f9f7 | 2249 | ret = cmuSelect_Disabled; |
<> | 144:ef7eb2e8f9f7 | 2250 | break; |
<> | 144:ef7eb2e8f9f7 | 2251 | } |
<> | 144:ef7eb2e8f9f7 | 2252 | break; |
<> | 144:ef7eb2e8f9f7 | 2253 | #endif |
<> | 144:ef7eb2e8f9f7 | 2254 | |
<> | 144:ef7eb2e8f9f7 | 2255 | #if defined( _CMU_LFECLKSEL_LFE_MASK ) |
<> | 144:ef7eb2e8f9f7 | 2256 | case CMU_LFECLKSEL_REG: |
<> | 144:ef7eb2e8f9f7 | 2257 | switch (CMU->LFECLKSEL & _CMU_LFECLKSEL_LFE_MASK) |
<> | 144:ef7eb2e8f9f7 | 2258 | { |
<> | 144:ef7eb2e8f9f7 | 2259 | case CMU_LFECLKSEL_LFE_LFRCO: |
<> | 144:ef7eb2e8f9f7 | 2260 | ret = cmuSelect_LFRCO; |
<> | 144:ef7eb2e8f9f7 | 2261 | break; |
<> | 144:ef7eb2e8f9f7 | 2262 | |
<> | 144:ef7eb2e8f9f7 | 2263 | case CMU_LFECLKSEL_LFE_LFXO: |
<> | 144:ef7eb2e8f9f7 | 2264 | ret = cmuSelect_LFXO; |
<> | 144:ef7eb2e8f9f7 | 2265 | break; |
<> | 144:ef7eb2e8f9f7 | 2266 | |
<> | 144:ef7eb2e8f9f7 | 2267 | case CMU_LFECLKSEL_LFE_ULFRCO: |
<> | 144:ef7eb2e8f9f7 | 2268 | ret = cmuSelect_ULFRCO; |
<> | 144:ef7eb2e8f9f7 | 2269 | break; |
<> | 144:ef7eb2e8f9f7 | 2270 | |
<> | 144:ef7eb2e8f9f7 | 2271 | #if defined ( _CMU_LFECLKSEL_LFE_HFCLKLE ) |
<> | 144:ef7eb2e8f9f7 | 2272 | case CMU_LFECLKSEL_LFE_HFCLKLE: |
<> | 144:ef7eb2e8f9f7 | 2273 | ret = cmuSelect_HFCLKLE; |
<> | 144:ef7eb2e8f9f7 | 2274 | break; |
<> | 144:ef7eb2e8f9f7 | 2275 | #endif |
<> | 144:ef7eb2e8f9f7 | 2276 | |
<> | 144:ef7eb2e8f9f7 | 2277 | default: |
<> | 144:ef7eb2e8f9f7 | 2278 | ret = cmuSelect_Disabled; |
<> | 144:ef7eb2e8f9f7 | 2279 | break; |
<> | 144:ef7eb2e8f9f7 | 2280 | } |
<> | 144:ef7eb2e8f9f7 | 2281 | break; |
<> | 144:ef7eb2e8f9f7 | 2282 | #endif /* CMU_LFECLKSEL_REG */ |
<> | 144:ef7eb2e8f9f7 | 2283 | |
<> | 144:ef7eb2e8f9f7 | 2284 | case CMU_DBGCLKSEL_REG: |
<> | 144:ef7eb2e8f9f7 | 2285 | #if defined( _CMU_DBGCLKSEL_DBG_MASK ) |
<> | 144:ef7eb2e8f9f7 | 2286 | switch (CMU->DBGCLKSEL & _CMU_DBGCLKSEL_DBG_MASK) |
<> | 144:ef7eb2e8f9f7 | 2287 | { |
<> | 144:ef7eb2e8f9f7 | 2288 | case CMU_DBGCLKSEL_DBG_HFCLK: |
<> | 144:ef7eb2e8f9f7 | 2289 | ret = cmuSelect_HFCLK; |
<> | 144:ef7eb2e8f9f7 | 2290 | break; |
<> | 144:ef7eb2e8f9f7 | 2291 | |
<> | 144:ef7eb2e8f9f7 | 2292 | case CMU_DBGCLKSEL_DBG_AUXHFRCO: |
<> | 144:ef7eb2e8f9f7 | 2293 | ret = cmuSelect_AUXHFRCO; |
<> | 144:ef7eb2e8f9f7 | 2294 | break; |
<> | 144:ef7eb2e8f9f7 | 2295 | } |
<> | 144:ef7eb2e8f9f7 | 2296 | #else |
<> | 144:ef7eb2e8f9f7 | 2297 | ret = cmuSelect_AUXHFRCO; |
<> | 144:ef7eb2e8f9f7 | 2298 | #endif /* CMU_DBGCLKSEL_DBG */ |
<> | 144:ef7eb2e8f9f7 | 2299 | |
<> | 144:ef7eb2e8f9f7 | 2300 | #if defined( _CMU_CTRL_DBGCLK_MASK ) |
<> | 144:ef7eb2e8f9f7 | 2301 | switch(CMU->CTRL & _CMU_CTRL_DBGCLK_MASK) |
<> | 144:ef7eb2e8f9f7 | 2302 | { |
<> | 144:ef7eb2e8f9f7 | 2303 | case CMU_CTRL_DBGCLK_AUXHFRCO: |
<> | 144:ef7eb2e8f9f7 | 2304 | ret = cmuSelect_AUXHFRCO; |
<> | 144:ef7eb2e8f9f7 | 2305 | break; |
<> | 144:ef7eb2e8f9f7 | 2306 | |
<> | 144:ef7eb2e8f9f7 | 2307 | case CMU_CTRL_DBGCLK_HFCLK: |
<> | 144:ef7eb2e8f9f7 | 2308 | ret = cmuSelect_HFCLK; |
<> | 144:ef7eb2e8f9f7 | 2309 | break; |
<> | 144:ef7eb2e8f9f7 | 2310 | } |
<> | 144:ef7eb2e8f9f7 | 2311 | #else |
<> | 144:ef7eb2e8f9f7 | 2312 | ret = cmuSelect_AUXHFRCO; |
<> | 144:ef7eb2e8f9f7 | 2313 | #endif |
<> | 144:ef7eb2e8f9f7 | 2314 | break; |
<> | 144:ef7eb2e8f9f7 | 2315 | |
<> | 144:ef7eb2e8f9f7 | 2316 | |
<> | 144:ef7eb2e8f9f7 | 2317 | #if defined( USB_PRESENT ) |
<> | 144:ef7eb2e8f9f7 | 2318 | case CMU_USBCCLKSEL_REG: |
<> | 144:ef7eb2e8f9f7 | 2319 | switch (CMU->STATUS |
<> | 144:ef7eb2e8f9f7 | 2320 | & (CMU_STATUS_USBCLFXOSEL |
<> | 144:ef7eb2e8f9f7 | 2321 | #if defined(_CMU_STATUS_USBCHFCLKSEL_MASK) |
<> | 144:ef7eb2e8f9f7 | 2322 | | CMU_STATUS_USBCHFCLKSEL |
<> | 144:ef7eb2e8f9f7 | 2323 | #endif |
<> | 144:ef7eb2e8f9f7 | 2324 | #if defined(_CMU_STATUS_USBCUSHFRCOSEL_MASK) |
<> | 144:ef7eb2e8f9f7 | 2325 | | CMU_STATUS_USBCUSHFRCOSEL |
<> | 144:ef7eb2e8f9f7 | 2326 | #endif |
<> | 144:ef7eb2e8f9f7 | 2327 | | CMU_STATUS_USBCLFRCOSEL)) |
<> | 144:ef7eb2e8f9f7 | 2328 | { |
<> | 144:ef7eb2e8f9f7 | 2329 | #if defined(_CMU_STATUS_USBCHFCLKSEL_MASK) |
<> | 144:ef7eb2e8f9f7 | 2330 | case CMU_STATUS_USBCHFCLKSEL: |
<> | 144:ef7eb2e8f9f7 | 2331 | ret = cmuSelect_HFCLK; |
<> | 144:ef7eb2e8f9f7 | 2332 | break; |
<> | 144:ef7eb2e8f9f7 | 2333 | #endif |
<> | 144:ef7eb2e8f9f7 | 2334 | |
<> | 144:ef7eb2e8f9f7 | 2335 | #if defined(_CMU_STATUS_USBCUSHFRCOSEL_MASK) |
<> | 144:ef7eb2e8f9f7 | 2336 | case CMU_STATUS_USBCUSHFRCOSEL: |
<> | 144:ef7eb2e8f9f7 | 2337 | ret = cmuSelect_USHFRCO; |
<> | 144:ef7eb2e8f9f7 | 2338 | break; |
<> | 144:ef7eb2e8f9f7 | 2339 | #endif |
<> | 144:ef7eb2e8f9f7 | 2340 | |
<> | 144:ef7eb2e8f9f7 | 2341 | case CMU_STATUS_USBCLFXOSEL: |
<> | 144:ef7eb2e8f9f7 | 2342 | ret = cmuSelect_LFXO; |
<> | 144:ef7eb2e8f9f7 | 2343 | break; |
<> | 144:ef7eb2e8f9f7 | 2344 | |
<> | 144:ef7eb2e8f9f7 | 2345 | case CMU_STATUS_USBCLFRCOSEL: |
<> | 144:ef7eb2e8f9f7 | 2346 | ret = cmuSelect_LFRCO; |
<> | 144:ef7eb2e8f9f7 | 2347 | break; |
<> | 144:ef7eb2e8f9f7 | 2348 | |
<> | 144:ef7eb2e8f9f7 | 2349 | default: |
<> | 144:ef7eb2e8f9f7 | 2350 | ret = cmuSelect_Disabled; |
<> | 144:ef7eb2e8f9f7 | 2351 | break; |
<> | 144:ef7eb2e8f9f7 | 2352 | } |
<> | 144:ef7eb2e8f9f7 | 2353 | break; |
<> | 144:ef7eb2e8f9f7 | 2354 | #endif |
<> | 144:ef7eb2e8f9f7 | 2355 | |
<> | 144:ef7eb2e8f9f7 | 2356 | default: |
<> | 144:ef7eb2e8f9f7 | 2357 | EFM_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 2358 | ret = cmuSelect_Error; |
<> | 144:ef7eb2e8f9f7 | 2359 | break; |
<> | 144:ef7eb2e8f9f7 | 2360 | } |
<> | 144:ef7eb2e8f9f7 | 2361 | |
<> | 144:ef7eb2e8f9f7 | 2362 | return ret; |
<> | 144:ef7eb2e8f9f7 | 2363 | } |
<> | 144:ef7eb2e8f9f7 | 2364 | |
<> | 144:ef7eb2e8f9f7 | 2365 | |
<> | 144:ef7eb2e8f9f7 | 2366 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 2367 | * @brief |
<> | 144:ef7eb2e8f9f7 | 2368 | * Select reference clock/oscillator used for a clock branch. |
<> | 144:ef7eb2e8f9f7 | 2369 | * |
<> | 144:ef7eb2e8f9f7 | 2370 | * @details |
<> | 144:ef7eb2e8f9f7 | 2371 | * Notice that if a selected reference is not enabled prior to selecting its |
<> | 144:ef7eb2e8f9f7 | 2372 | * use, it will be enabled, and this function will wait for the selected |
<> | 144:ef7eb2e8f9f7 | 2373 | * oscillator to be stable. It will however NOT be disabled if another |
<> | 144:ef7eb2e8f9f7 | 2374 | * reference clock is selected later. |
<> | 144:ef7eb2e8f9f7 | 2375 | * |
<> | 144:ef7eb2e8f9f7 | 2376 | * This feature is particularly important if selecting a new reference |
<> | 144:ef7eb2e8f9f7 | 2377 | * clock for the clock branch clocking the core, otherwise the system |
<> | 144:ef7eb2e8f9f7 | 2378 | * may halt. |
<> | 144:ef7eb2e8f9f7 | 2379 | * |
<> | 144:ef7eb2e8f9f7 | 2380 | * @param[in] clock |
<> | 144:ef7eb2e8f9f7 | 2381 | * Clock branch to select reference clock for. One of: |
<> | 144:ef7eb2e8f9f7 | 2382 | * @li #cmuClock_HF |
<> | 144:ef7eb2e8f9f7 | 2383 | * @li #cmuClock_LFA |
<> | 144:ef7eb2e8f9f7 | 2384 | * @li #cmuClock_LFB @if _CMU_LFCLKSEL_LFAE_ULFRCO |
<> | 144:ef7eb2e8f9f7 | 2385 | * @li #cmuClock_LFC |
<> | 144:ef7eb2e8f9f7 | 2386 | * @endif @if _SILICON_LABS_32B_PLATFORM_2 |
<> | 144:ef7eb2e8f9f7 | 2387 | * @li #cmuClock_LFE |
<> | 144:ef7eb2e8f9f7 | 2388 | * @endif |
<> | 144:ef7eb2e8f9f7 | 2389 | * @li #cmuClock_DBG @if DOXYDOC_USB_PRESENT |
<> | 144:ef7eb2e8f9f7 | 2390 | * @li #cmuClock_USBC |
<> | 144:ef7eb2e8f9f7 | 2391 | * @endif |
<> | 144:ef7eb2e8f9f7 | 2392 | * |
<> | 144:ef7eb2e8f9f7 | 2393 | * @param[in] ref |
<> | 144:ef7eb2e8f9f7 | 2394 | * Reference selected for clocking, please refer to reference manual for |
<> | 144:ef7eb2e8f9f7 | 2395 | * for details on which reference is available for a specific clock branch. |
<> | 144:ef7eb2e8f9f7 | 2396 | * @li #cmuSelect_HFRCO |
<> | 144:ef7eb2e8f9f7 | 2397 | * @li #cmuSelect_LFRCO |
<> | 144:ef7eb2e8f9f7 | 2398 | * @li #cmuSelect_HFXO |
<> | 144:ef7eb2e8f9f7 | 2399 | * @li #cmuSelect_LFXO |
<> | 144:ef7eb2e8f9f7 | 2400 | * @li #cmuSelect_CORELEDIV2 |
<> | 144:ef7eb2e8f9f7 | 2401 | * @li #cmuSelect_AUXHFRCO |
<> | 144:ef7eb2e8f9f7 | 2402 | * @li #cmuSelect_HFCLK @ifnot DOXYDOC_EFM32_GECKO_FAMILY |
<> | 144:ef7eb2e8f9f7 | 2403 | * @li #cmuSelect_ULFRCO |
<> | 144:ef7eb2e8f9f7 | 2404 | * @endif |
<> | 144:ef7eb2e8f9f7 | 2405 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 2406 | void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref) |
<> | 144:ef7eb2e8f9f7 | 2407 | { |
<> | 144:ef7eb2e8f9f7 | 2408 | uint32_t select = cmuOsc_HFRCO; |
<> | 144:ef7eb2e8f9f7 | 2409 | CMU_Osc_TypeDef osc = cmuOsc_HFRCO; |
<> | 144:ef7eb2e8f9f7 | 2410 | uint32_t freq; |
<> | 144:ef7eb2e8f9f7 | 2411 | uint32_t tmp; |
<> | 144:ef7eb2e8f9f7 | 2412 | uint32_t selRegId; |
<> | 144:ef7eb2e8f9f7 | 2413 | #if defined( _SILICON_LABS_32B_PLATFORM_2 ) |
<> | 144:ef7eb2e8f9f7 | 2414 | volatile uint32_t *selReg = NULL; |
<> | 144:ef7eb2e8f9f7 | 2415 | #endif |
<> | 144:ef7eb2e8f9f7 | 2416 | #if defined( CMU_LFCLKSEL_LFAE_ULFRCO ) |
<> | 144:ef7eb2e8f9f7 | 2417 | uint32_t lfExtended = 0; |
<> | 144:ef7eb2e8f9f7 | 2418 | #endif |
<> | 144:ef7eb2e8f9f7 | 2419 | |
<> | 144:ef7eb2e8f9f7 | 2420 | selRegId = (clock >> CMU_SEL_REG_POS) & CMU_SEL_REG_MASK; |
<> | 144:ef7eb2e8f9f7 | 2421 | |
<> | 144:ef7eb2e8f9f7 | 2422 | switch (selRegId) |
<> | 144:ef7eb2e8f9f7 | 2423 | { |
<> | 144:ef7eb2e8f9f7 | 2424 | case CMU_HFCLKSEL_REG: |
<> | 144:ef7eb2e8f9f7 | 2425 | switch (ref) |
<> | 144:ef7eb2e8f9f7 | 2426 | { |
<> | 144:ef7eb2e8f9f7 | 2427 | case cmuSelect_LFXO: |
<> | 144:ef7eb2e8f9f7 | 2428 | #if defined( _SILICON_LABS_32B_PLATFORM_2 ) |
<> | 144:ef7eb2e8f9f7 | 2429 | select = CMU_HFCLKSEL_HF_LFXO; |
<> | 144:ef7eb2e8f9f7 | 2430 | #elif defined( _SILICON_LABS_32B_PLATFORM_1 ) |
<> | 144:ef7eb2e8f9f7 | 2431 | select = CMU_CMD_HFCLKSEL_LFXO; |
<> | 144:ef7eb2e8f9f7 | 2432 | #endif |
<> | 144:ef7eb2e8f9f7 | 2433 | osc = cmuOsc_LFXO; |
<> | 144:ef7eb2e8f9f7 | 2434 | break; |
<> | 144:ef7eb2e8f9f7 | 2435 | |
<> | 144:ef7eb2e8f9f7 | 2436 | case cmuSelect_LFRCO: |
<> | 144:ef7eb2e8f9f7 | 2437 | #if defined( _SILICON_LABS_32B_PLATFORM_2 ) |
<> | 144:ef7eb2e8f9f7 | 2438 | select = CMU_HFCLKSEL_HF_LFRCO; |
<> | 144:ef7eb2e8f9f7 | 2439 | #elif defined( _SILICON_LABS_32B_PLATFORM_1 ) |
<> | 144:ef7eb2e8f9f7 | 2440 | select = CMU_CMD_HFCLKSEL_LFRCO; |
<> | 144:ef7eb2e8f9f7 | 2441 | #endif |
<> | 144:ef7eb2e8f9f7 | 2442 | osc = cmuOsc_LFRCO; |
<> | 144:ef7eb2e8f9f7 | 2443 | break; |
<> | 144:ef7eb2e8f9f7 | 2444 | |
<> | 144:ef7eb2e8f9f7 | 2445 | case cmuSelect_HFXO: |
<> | 144:ef7eb2e8f9f7 | 2446 | osc = cmuOsc_HFXO; |
<> | 144:ef7eb2e8f9f7 | 2447 | #if defined( _SILICON_LABS_32B_PLATFORM_2 ) |
<> | 144:ef7eb2e8f9f7 | 2448 | select = CMU_HFCLKSEL_HF_HFXO; |
<> | 144:ef7eb2e8f9f7 | 2449 | /* Adjust HFXO buffer current for high frequencies, */ |
<> | 144:ef7eb2e8f9f7 | 2450 | /* enable WSHFLE for frequencies above 32MHz. */ |
<> | 144:ef7eb2e8f9f7 | 2451 | if (SystemHFXOClockGet() > 32000000) |
<> | 144:ef7eb2e8f9f7 | 2452 | { |
<> | 144:ef7eb2e8f9f7 | 2453 | CMU->CTRL |= CMU_CTRL_WSHFLE; |
<> | 144:ef7eb2e8f9f7 | 2454 | } |
<> | 144:ef7eb2e8f9f7 | 2455 | #elif defined( _SILICON_LABS_32B_PLATFORM_1 ) |
<> | 144:ef7eb2e8f9f7 | 2456 | select = CMU_CMD_HFCLKSEL_HFXO; |
<> | 144:ef7eb2e8f9f7 | 2457 | #if defined( CMU_CTRL_HFLE ) |
<> | 144:ef7eb2e8f9f7 | 2458 | /* Adjust HFXO buffer current for high frequencies, */ |
<> | 144:ef7eb2e8f9f7 | 2459 | /* enable HFLE for frequencies above CMU_MAX_FREQ_HFLE. */ |
<> | 144:ef7eb2e8f9f7 | 2460 | if(SystemHFXOClockGet() > CMU_MAX_FREQ_HFLE()) |
<> | 144:ef7eb2e8f9f7 | 2461 | { |
<> | 144:ef7eb2e8f9f7 | 2462 | CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK) |
<> | 144:ef7eb2e8f9f7 | 2463 | | CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ |
<> | 144:ef7eb2e8f9f7 | 2464 | /* Must have HFLE enabled to access some LE peripherals >=32MHz */ |
<> | 144:ef7eb2e8f9f7 | 2465 | | CMU_CTRL_HFLE; |
<> | 144:ef7eb2e8f9f7 | 2466 | |
<> | 144:ef7eb2e8f9f7 | 2467 | /* Set HFLE and DIV4 factor for peripheral clock if HFCORE */ |
<> | 144:ef7eb2e8f9f7 | 2468 | /* clock for LE is enabled. */ |
<> | 144:ef7eb2e8f9f7 | 2469 | if (CMU->HFCORECLKEN0 & CMU_HFCORECLKEN0_LE) |
<> | 144:ef7eb2e8f9f7 | 2470 | { |
<> | 144:ef7eb2e8f9f7 | 2471 | BUS_RegBitWrite(&CMU->HFCORECLKDIV, |
<> | 144:ef7eb2e8f9f7 | 2472 | _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 1); |
<> | 144:ef7eb2e8f9f7 | 2473 | } |
<> | 144:ef7eb2e8f9f7 | 2474 | } |
<> | 144:ef7eb2e8f9f7 | 2475 | else |
<> | 144:ef7eb2e8f9f7 | 2476 | { |
<> | 144:ef7eb2e8f9f7 | 2477 | /* This can happen if the user configures the EFM32_HFXO_FREQ to */ |
<> | 144:ef7eb2e8f9f7 | 2478 | /* use another oscillator frequency */ |
<> | 144:ef7eb2e8f9f7 | 2479 | CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK) |
<> | 144:ef7eb2e8f9f7 | 2480 | | CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ; |
<> | 144:ef7eb2e8f9f7 | 2481 | } |
<> | 144:ef7eb2e8f9f7 | 2482 | #endif |
<> | 144:ef7eb2e8f9f7 | 2483 | #endif |
<> | 144:ef7eb2e8f9f7 | 2484 | break; |
<> | 144:ef7eb2e8f9f7 | 2485 | |
<> | 144:ef7eb2e8f9f7 | 2486 | case cmuSelect_HFRCO: |
<> | 144:ef7eb2e8f9f7 | 2487 | #if defined( _SILICON_LABS_32B_PLATFORM_2 ) |
<> | 144:ef7eb2e8f9f7 | 2488 | select = CMU_HFCLKSEL_HF_HFRCO; |
<> | 144:ef7eb2e8f9f7 | 2489 | #elif defined( _SILICON_LABS_32B_PLATFORM_1 ) |
<> | 144:ef7eb2e8f9f7 | 2490 | select = CMU_CMD_HFCLKSEL_HFRCO; |
<> | 144:ef7eb2e8f9f7 | 2491 | #endif |
<> | 144:ef7eb2e8f9f7 | 2492 | osc = cmuOsc_HFRCO; |
<> | 144:ef7eb2e8f9f7 | 2493 | break; |
<> | 144:ef7eb2e8f9f7 | 2494 | |
<> | 144:ef7eb2e8f9f7 | 2495 | #if defined( CMU_CMD_HFCLKSEL_USHFRCODIV2 ) |
<> | 144:ef7eb2e8f9f7 | 2496 | case cmuSelect_USHFRCODIV2: |
<> | 144:ef7eb2e8f9f7 | 2497 | select = CMU_CMD_HFCLKSEL_USHFRCODIV2; |
<> | 144:ef7eb2e8f9f7 | 2498 | osc = cmuOsc_USHFRCO; |
<> | 144:ef7eb2e8f9f7 | 2499 | break; |
<> | 144:ef7eb2e8f9f7 | 2500 | #endif |
<> | 144:ef7eb2e8f9f7 | 2501 | |
<> | 144:ef7eb2e8f9f7 | 2502 | #if defined( CMU_LFCLKSEL_LFAE_ULFRCO ) || defined( CMU_LFACLKSEL_LFA_ULFRCO ) |
<> | 144:ef7eb2e8f9f7 | 2503 | case cmuSelect_ULFRCO: |
<> | 144:ef7eb2e8f9f7 | 2504 | /* ULFRCO cannot be used as HFCLK */ |
<> | 144:ef7eb2e8f9f7 | 2505 | EFM_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 2506 | return; |
<> | 144:ef7eb2e8f9f7 | 2507 | #endif |
<> | 144:ef7eb2e8f9f7 | 2508 | |
<> | 144:ef7eb2e8f9f7 | 2509 | default: |
<> | 144:ef7eb2e8f9f7 | 2510 | EFM_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 2511 | return; |
<> | 144:ef7eb2e8f9f7 | 2512 | } |
<> | 144:ef7eb2e8f9f7 | 2513 | |
<> | 144:ef7eb2e8f9f7 | 2514 | /* Ensure selected oscillator is enabled, waiting for it to stabilize */ |
<> | 144:ef7eb2e8f9f7 | 2515 | CMU_OscillatorEnable(osc, true, true); |
<> | 144:ef7eb2e8f9f7 | 2516 | |
<> | 144:ef7eb2e8f9f7 | 2517 | /* Configure worst case wait states for flash access before selecting */ |
<> | 144:ef7eb2e8f9f7 | 2518 | flashWaitStateMax(); |
<> | 144:ef7eb2e8f9f7 | 2519 | |
<> | 144:ef7eb2e8f9f7 | 2520 | /* Switch to selected oscillator */ |
<> | 144:ef7eb2e8f9f7 | 2521 | #if defined( _SILICON_LABS_32B_PLATFORM_2 ) |
<> | 144:ef7eb2e8f9f7 | 2522 | CMU->HFCLKSEL = select; |
<> | 144:ef7eb2e8f9f7 | 2523 | #elif defined( _SILICON_LABS_32B_PLATFORM_1 ) |
<> | 144:ef7eb2e8f9f7 | 2524 | CMU->CMD = select; |
<> | 144:ef7eb2e8f9f7 | 2525 | #endif |
<> | 144:ef7eb2e8f9f7 | 2526 | |
<> | 144:ef7eb2e8f9f7 | 2527 | /* Keep EMU module informed */ |
<> | 144:ef7eb2e8f9f7 | 2528 | EMU_UpdateOscConfig(); |
<> | 144:ef7eb2e8f9f7 | 2529 | |
<> | 144:ef7eb2e8f9f7 | 2530 | /* Update CMSIS core clock variable */ |
<> | 144:ef7eb2e8f9f7 | 2531 | /* (The function will update the global variable) */ |
<> | 144:ef7eb2e8f9f7 | 2532 | freq = SystemCoreClockGet(); |
<> | 144:ef7eb2e8f9f7 | 2533 | |
<> | 144:ef7eb2e8f9f7 | 2534 | /* Optimize flash access wait state setting for currently selected core clk */ |
<> | 144:ef7eb2e8f9f7 | 2535 | flashWaitStateControl(freq); |
<> | 144:ef7eb2e8f9f7 | 2536 | break; |
<> | 144:ef7eb2e8f9f7 | 2537 | |
<> | 144:ef7eb2e8f9f7 | 2538 | #if defined( _SILICON_LABS_32B_PLATFORM_2 ) |
<> | 144:ef7eb2e8f9f7 | 2539 | case CMU_LFACLKSEL_REG: |
<> | 144:ef7eb2e8f9f7 | 2540 | selReg = (selReg == NULL) ? &CMU->LFACLKSEL : selReg; |
<> | 144:ef7eb2e8f9f7 | 2541 | #if !defined( _CMU_LFACLKSEL_LFA_HFCLKLE ) |
<> | 144:ef7eb2e8f9f7 | 2542 | /* HFCLKCLE can not be used as LFACLK */ |
<> | 144:ef7eb2e8f9f7 | 2543 | EFM_ASSERT(ref != cmuSelect_HFCLKLE); |
<> | 144:ef7eb2e8f9f7 | 2544 | #endif |
<> | 144:ef7eb2e8f9f7 | 2545 | case CMU_LFECLKSEL_REG: |
<> | 144:ef7eb2e8f9f7 | 2546 | selReg = (selReg == NULL) ? &CMU->LFECLKSEL : selReg; |
<> | 144:ef7eb2e8f9f7 | 2547 | #if !defined( _CMU_LFECLKSEL_LFE_HFCLKLE ) |
<> | 144:ef7eb2e8f9f7 | 2548 | /* HFCLKCLE can not be used as LFECLK */ |
<> | 144:ef7eb2e8f9f7 | 2549 | EFM_ASSERT(ref != cmuSelect_HFCLKLE); |
<> | 144:ef7eb2e8f9f7 | 2550 | #endif |
<> | 144:ef7eb2e8f9f7 | 2551 | case CMU_LFBCLKSEL_REG: |
<> | 144:ef7eb2e8f9f7 | 2552 | selReg = (selReg == NULL) ? &CMU->LFBCLKSEL : selReg; |
<> | 144:ef7eb2e8f9f7 | 2553 | switch (ref) |
<> | 144:ef7eb2e8f9f7 | 2554 | { |
<> | 144:ef7eb2e8f9f7 | 2555 | case cmuSelect_Disabled: |
<> | 144:ef7eb2e8f9f7 | 2556 | tmp = _CMU_LFACLKSEL_LFA_DISABLED; |
<> | 144:ef7eb2e8f9f7 | 2557 | break; |
<> | 144:ef7eb2e8f9f7 | 2558 | |
<> | 144:ef7eb2e8f9f7 | 2559 | case cmuSelect_LFXO: |
<> | 144:ef7eb2e8f9f7 | 2560 | /* Ensure selected oscillator is enabled, waiting for it to stabilize */ |
<> | 144:ef7eb2e8f9f7 | 2561 | CMU_OscillatorEnable(cmuOsc_LFXO, true, true); |
<> | 144:ef7eb2e8f9f7 | 2562 | tmp = _CMU_LFACLKSEL_LFA_LFXO; |
<> | 144:ef7eb2e8f9f7 | 2563 | break; |
<> | 144:ef7eb2e8f9f7 | 2564 | |
<> | 144:ef7eb2e8f9f7 | 2565 | case cmuSelect_LFRCO: |
<> | 144:ef7eb2e8f9f7 | 2566 | /* Ensure selected oscillator is enabled, waiting for it to stabilize */ |
<> | 144:ef7eb2e8f9f7 | 2567 | CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); |
<> | 144:ef7eb2e8f9f7 | 2568 | tmp = _CMU_LFACLKSEL_LFA_LFRCO; |
<> | 144:ef7eb2e8f9f7 | 2569 | break; |
<> | 144:ef7eb2e8f9f7 | 2570 | |
<> | 144:ef7eb2e8f9f7 | 2571 | case cmuSelect_HFCLKLE: |
<> | 144:ef7eb2e8f9f7 | 2572 | /* Ensure HFCORE to LE clocking is enabled */ |
<> | 144:ef7eb2e8f9f7 | 2573 | BUS_RegBitWrite(&CMU->HFBUSCLKEN0, _CMU_HFBUSCLKEN0_LE_SHIFT, 1); |
<> | 144:ef7eb2e8f9f7 | 2574 | tmp = _CMU_LFBCLKSEL_LFB_HFCLKLE; |
<> | 144:ef7eb2e8f9f7 | 2575 | |
<> | 144:ef7eb2e8f9f7 | 2576 | /* If core frequency is > 32MHz enable WSHFLE */ |
<> | 144:ef7eb2e8f9f7 | 2577 | freq = SystemCoreClockGet(); |
<> | 144:ef7eb2e8f9f7 | 2578 | if (freq > 32000000U) |
<> | 144:ef7eb2e8f9f7 | 2579 | { |
<> | 144:ef7eb2e8f9f7 | 2580 | /* Enable CMU HFLE */ |
<> | 144:ef7eb2e8f9f7 | 2581 | BUS_RegBitWrite(&CMU->CTRL, _CMU_CTRL_WSHFLE_SHIFT, 1); |
<> | 144:ef7eb2e8f9f7 | 2582 | |
<> | 144:ef7eb2e8f9f7 | 2583 | /* Enable DIV4 factor for peripheral clock */ |
<> | 144:ef7eb2e8f9f7 | 2584 | BUS_RegBitWrite(&CMU->HFPRESC, _CMU_HFPRESC_HFCLKLEPRESC_SHIFT, 1); |
<> | 144:ef7eb2e8f9f7 | 2585 | } |
<> | 144:ef7eb2e8f9f7 | 2586 | break; |
<> | 144:ef7eb2e8f9f7 | 2587 | |
<> | 144:ef7eb2e8f9f7 | 2588 | case cmuSelect_ULFRCO: |
<> | 144:ef7eb2e8f9f7 | 2589 | /* ULFRCO is always on, there is no need to enable it. */ |
<> | 144:ef7eb2e8f9f7 | 2590 | tmp = _CMU_LFACLKSEL_LFA_ULFRCO; |
<> | 144:ef7eb2e8f9f7 | 2591 | break; |
<> | 144:ef7eb2e8f9f7 | 2592 | |
<> | 144:ef7eb2e8f9f7 | 2593 | default: |
<> | 144:ef7eb2e8f9f7 | 2594 | EFM_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 2595 | return; |
<> | 144:ef7eb2e8f9f7 | 2596 | } |
<> | 144:ef7eb2e8f9f7 | 2597 | *selReg = tmp; |
<> | 144:ef7eb2e8f9f7 | 2598 | break; |
<> | 144:ef7eb2e8f9f7 | 2599 | |
<> | 144:ef7eb2e8f9f7 | 2600 | #elif defined( _SILICON_LABS_32B_PLATFORM_1 ) |
<> | 144:ef7eb2e8f9f7 | 2601 | case CMU_LFACLKSEL_REG: |
<> | 144:ef7eb2e8f9f7 | 2602 | case CMU_LFBCLKSEL_REG: |
<> | 144:ef7eb2e8f9f7 | 2603 | switch (ref) |
<> | 144:ef7eb2e8f9f7 | 2604 | { |
<> | 144:ef7eb2e8f9f7 | 2605 | case cmuSelect_Disabled: |
<> | 144:ef7eb2e8f9f7 | 2606 | tmp = _CMU_LFCLKSEL_LFA_DISABLED; |
<> | 144:ef7eb2e8f9f7 | 2607 | break; |
<> | 144:ef7eb2e8f9f7 | 2608 | |
<> | 144:ef7eb2e8f9f7 | 2609 | case cmuSelect_LFXO: |
<> | 144:ef7eb2e8f9f7 | 2610 | /* Ensure selected oscillator is enabled, waiting for it to stabilize */ |
<> | 144:ef7eb2e8f9f7 | 2611 | CMU_OscillatorEnable(cmuOsc_LFXO, true, true); |
<> | 144:ef7eb2e8f9f7 | 2612 | tmp = _CMU_LFCLKSEL_LFA_LFXO; |
<> | 144:ef7eb2e8f9f7 | 2613 | break; |
<> | 144:ef7eb2e8f9f7 | 2614 | |
<> | 144:ef7eb2e8f9f7 | 2615 | case cmuSelect_LFRCO: |
<> | 144:ef7eb2e8f9f7 | 2616 | /* Ensure selected oscillator is enabled, waiting for it to stabilize */ |
<> | 144:ef7eb2e8f9f7 | 2617 | CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); |
<> | 144:ef7eb2e8f9f7 | 2618 | tmp = _CMU_LFCLKSEL_LFA_LFRCO; |
<> | 144:ef7eb2e8f9f7 | 2619 | break; |
<> | 144:ef7eb2e8f9f7 | 2620 | |
<> | 144:ef7eb2e8f9f7 | 2621 | case cmuSelect_CORELEDIV2: |
<> | 144:ef7eb2e8f9f7 | 2622 | /* Ensure HFCORE to LE clocking is enabled */ |
<> | 144:ef7eb2e8f9f7 | 2623 | BUS_RegBitWrite(&(CMU->HFCORECLKEN0), _CMU_HFCORECLKEN0_LE_SHIFT, 1); |
<> | 144:ef7eb2e8f9f7 | 2624 | tmp = _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2; |
<> | 144:ef7eb2e8f9f7 | 2625 | #if defined( CMU_CTRL_HFLE ) |
<> | 144:ef7eb2e8f9f7 | 2626 | /* If core frequency is higher than CMU_MAX_FREQ_HFLE on |
<> | 144:ef7eb2e8f9f7 | 2627 | Giant/Leopard/Wonder, enable HFLE and DIV4. */ |
<> | 144:ef7eb2e8f9f7 | 2628 | freq = SystemCoreClockGet(); |
<> | 144:ef7eb2e8f9f7 | 2629 | if(freq > CMU_MAX_FREQ_HFLE()) |
<> | 144:ef7eb2e8f9f7 | 2630 | { |
<> | 144:ef7eb2e8f9f7 | 2631 | /* Enable CMU HFLE */ |
<> | 144:ef7eb2e8f9f7 | 2632 | BUS_RegBitWrite(&CMU->CTRL, _CMU_CTRL_HFLE_SHIFT, 1); |
<> | 144:ef7eb2e8f9f7 | 2633 | |
<> | 144:ef7eb2e8f9f7 | 2634 | /* Enable DIV4 factor for peripheral clock */ |
<> | 144:ef7eb2e8f9f7 | 2635 | BUS_RegBitWrite(&CMU->HFCORECLKDIV, |
<> | 144:ef7eb2e8f9f7 | 2636 | _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 1); |
<> | 144:ef7eb2e8f9f7 | 2637 | } |
<> | 144:ef7eb2e8f9f7 | 2638 | #endif |
<> | 144:ef7eb2e8f9f7 | 2639 | break; |
<> | 144:ef7eb2e8f9f7 | 2640 | |
<> | 144:ef7eb2e8f9f7 | 2641 | #if defined( CMU_LFCLKSEL_LFAE_ULFRCO ) |
<> | 144:ef7eb2e8f9f7 | 2642 | case cmuSelect_ULFRCO: |
<> | 144:ef7eb2e8f9f7 | 2643 | /* ULFRCO is always enabled */ |
<> | 144:ef7eb2e8f9f7 | 2644 | tmp = _CMU_LFCLKSEL_LFA_DISABLED; |
<> | 144:ef7eb2e8f9f7 | 2645 | lfExtended = 1; |
<> | 144:ef7eb2e8f9f7 | 2646 | break; |
<> | 144:ef7eb2e8f9f7 | 2647 | #endif |
<> | 144:ef7eb2e8f9f7 | 2648 | |
<> | 144:ef7eb2e8f9f7 | 2649 | default: |
<> | 144:ef7eb2e8f9f7 | 2650 | /* Illegal clock source for LFA/LFB selected */ |
<> | 144:ef7eb2e8f9f7 | 2651 | EFM_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 2652 | return; |
<> | 144:ef7eb2e8f9f7 | 2653 | } |
<> | 144:ef7eb2e8f9f7 | 2654 | |
<> | 144:ef7eb2e8f9f7 | 2655 | /* Apply select */ |
<> | 144:ef7eb2e8f9f7 | 2656 | if (selRegId == CMU_LFACLKSEL_REG) |
<> | 144:ef7eb2e8f9f7 | 2657 | { |
<> | 144:ef7eb2e8f9f7 | 2658 | #if defined( _CMU_LFCLKSEL_LFAE_MASK ) |
<> | 144:ef7eb2e8f9f7 | 2659 | CMU->LFCLKSEL = (CMU->LFCLKSEL |
<> | 144:ef7eb2e8f9f7 | 2660 | & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK)) |
<> | 144:ef7eb2e8f9f7 | 2661 | | (tmp << _CMU_LFCLKSEL_LFA_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 2662 | | (lfExtended << _CMU_LFCLKSEL_LFAE_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 2663 | #else |
<> | 144:ef7eb2e8f9f7 | 2664 | CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK) |
<> | 144:ef7eb2e8f9f7 | 2665 | | (tmp << _CMU_LFCLKSEL_LFA_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 2666 | #endif |
<> | 144:ef7eb2e8f9f7 | 2667 | } |
<> | 144:ef7eb2e8f9f7 | 2668 | else |
<> | 144:ef7eb2e8f9f7 | 2669 | { |
<> | 144:ef7eb2e8f9f7 | 2670 | #if defined( _CMU_LFCLKSEL_LFBE_MASK ) |
<> | 144:ef7eb2e8f9f7 | 2671 | CMU->LFCLKSEL = (CMU->LFCLKSEL |
<> | 144:ef7eb2e8f9f7 | 2672 | & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK)) |
<> | 144:ef7eb2e8f9f7 | 2673 | | (tmp << _CMU_LFCLKSEL_LFB_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 2674 | | (lfExtended << _CMU_LFCLKSEL_LFBE_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 2675 | #else |
<> | 144:ef7eb2e8f9f7 | 2676 | CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK) |
<> | 144:ef7eb2e8f9f7 | 2677 | | (tmp << _CMU_LFCLKSEL_LFB_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 2678 | #endif |
<> | 144:ef7eb2e8f9f7 | 2679 | } |
<> | 144:ef7eb2e8f9f7 | 2680 | break; |
<> | 144:ef7eb2e8f9f7 | 2681 | |
<> | 144:ef7eb2e8f9f7 | 2682 | #if defined( _CMU_LFCLKSEL_LFC_MASK ) |
<> | 144:ef7eb2e8f9f7 | 2683 | case CMU_LFCCLKSEL_REG: |
<> | 144:ef7eb2e8f9f7 | 2684 | switch(ref) |
<> | 144:ef7eb2e8f9f7 | 2685 | { |
<> | 144:ef7eb2e8f9f7 | 2686 | case cmuSelect_Disabled: |
<> | 144:ef7eb2e8f9f7 | 2687 | tmp = _CMU_LFCLKSEL_LFA_DISABLED; |
<> | 144:ef7eb2e8f9f7 | 2688 | break; |
<> | 144:ef7eb2e8f9f7 | 2689 | |
<> | 144:ef7eb2e8f9f7 | 2690 | case cmuSelect_LFXO: |
<> | 144:ef7eb2e8f9f7 | 2691 | /* Ensure selected oscillator is enabled, waiting for it to stabilize */ |
<> | 144:ef7eb2e8f9f7 | 2692 | CMU_OscillatorEnable(cmuOsc_LFXO, true, true); |
<> | 144:ef7eb2e8f9f7 | 2693 | tmp = _CMU_LFCLKSEL_LFC_LFXO; |
<> | 144:ef7eb2e8f9f7 | 2694 | break; |
<> | 144:ef7eb2e8f9f7 | 2695 | |
<> | 144:ef7eb2e8f9f7 | 2696 | case cmuSelect_LFRCO: |
<> | 144:ef7eb2e8f9f7 | 2697 | /* Ensure selected oscillator is enabled, waiting for it to stabilize */ |
<> | 144:ef7eb2e8f9f7 | 2698 | CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); |
<> | 144:ef7eb2e8f9f7 | 2699 | tmp = _CMU_LFCLKSEL_LFC_LFRCO; |
<> | 144:ef7eb2e8f9f7 | 2700 | break; |
<> | 144:ef7eb2e8f9f7 | 2701 | |
<> | 144:ef7eb2e8f9f7 | 2702 | default: |
<> | 144:ef7eb2e8f9f7 | 2703 | /* Illegal clock source for LFC selected */ |
<> | 144:ef7eb2e8f9f7 | 2704 | EFM_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 2705 | return; |
<> | 144:ef7eb2e8f9f7 | 2706 | } |
<> | 144:ef7eb2e8f9f7 | 2707 | |
<> | 144:ef7eb2e8f9f7 | 2708 | /* Apply select */ |
<> | 144:ef7eb2e8f9f7 | 2709 | CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFC_MASK) |
<> | 144:ef7eb2e8f9f7 | 2710 | | (tmp << _CMU_LFCLKSEL_LFC_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 2711 | break; |
<> | 144:ef7eb2e8f9f7 | 2712 | #endif |
<> | 144:ef7eb2e8f9f7 | 2713 | #endif |
<> | 144:ef7eb2e8f9f7 | 2714 | |
<> | 144:ef7eb2e8f9f7 | 2715 | #if defined( CMU_DBGCLKSEL_DBG ) || defined( CMU_CTRL_DBGCLK ) |
<> | 144:ef7eb2e8f9f7 | 2716 | case CMU_DBGCLKSEL_REG: |
<> | 144:ef7eb2e8f9f7 | 2717 | switch(ref) |
<> | 144:ef7eb2e8f9f7 | 2718 | { |
<> | 144:ef7eb2e8f9f7 | 2719 | #if defined( CMU_DBGCLKSEL_DBG ) |
<> | 144:ef7eb2e8f9f7 | 2720 | case cmuSelect_AUXHFRCO: |
<> | 144:ef7eb2e8f9f7 | 2721 | /* Select AUXHFRCO as debug clock */ |
<> | 144:ef7eb2e8f9f7 | 2722 | CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_AUXHFRCO; |
<> | 144:ef7eb2e8f9f7 | 2723 | break; |
<> | 144:ef7eb2e8f9f7 | 2724 | |
<> | 144:ef7eb2e8f9f7 | 2725 | case cmuSelect_HFCLK: |
<> | 144:ef7eb2e8f9f7 | 2726 | /* Select divided HFCLK as debug clock */ |
<> | 144:ef7eb2e8f9f7 | 2727 | CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_HFCLK; |
<> | 144:ef7eb2e8f9f7 | 2728 | break; |
<> | 144:ef7eb2e8f9f7 | 2729 | #endif |
<> | 144:ef7eb2e8f9f7 | 2730 | |
<> | 144:ef7eb2e8f9f7 | 2731 | #if defined( CMU_CTRL_DBGCLK ) |
<> | 144:ef7eb2e8f9f7 | 2732 | case cmuSelect_AUXHFRCO: |
<> | 144:ef7eb2e8f9f7 | 2733 | /* Select AUXHFRCO as debug clock */ |
<> | 144:ef7eb2e8f9f7 | 2734 | CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK)) |
<> | 144:ef7eb2e8f9f7 | 2735 | | CMU_CTRL_DBGCLK_AUXHFRCO; |
<> | 144:ef7eb2e8f9f7 | 2736 | break; |
<> | 144:ef7eb2e8f9f7 | 2737 | |
<> | 144:ef7eb2e8f9f7 | 2738 | case cmuSelect_HFCLK: |
<> | 144:ef7eb2e8f9f7 | 2739 | /* Select divided HFCLK as debug clock */ |
<> | 144:ef7eb2e8f9f7 | 2740 | CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK)) |
<> | 144:ef7eb2e8f9f7 | 2741 | | CMU_CTRL_DBGCLK_HFCLK; |
<> | 144:ef7eb2e8f9f7 | 2742 | break; |
<> | 144:ef7eb2e8f9f7 | 2743 | #endif |
<> | 144:ef7eb2e8f9f7 | 2744 | |
<> | 144:ef7eb2e8f9f7 | 2745 | default: |
<> | 144:ef7eb2e8f9f7 | 2746 | /* Illegal clock source for debug selected */ |
<> | 144:ef7eb2e8f9f7 | 2747 | EFM_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 2748 | return; |
<> | 144:ef7eb2e8f9f7 | 2749 | } |
<> | 144:ef7eb2e8f9f7 | 2750 | break; |
<> | 144:ef7eb2e8f9f7 | 2751 | #endif |
<> | 144:ef7eb2e8f9f7 | 2752 | |
<> | 144:ef7eb2e8f9f7 | 2753 | #if defined(USB_PRESENT) |
<> | 144:ef7eb2e8f9f7 | 2754 | case CMU_USBCCLKSEL_REG: |
<> | 144:ef7eb2e8f9f7 | 2755 | switch(ref) |
<> | 144:ef7eb2e8f9f7 | 2756 | { |
<> | 144:ef7eb2e8f9f7 | 2757 | case cmuSelect_LFXO: |
<> | 144:ef7eb2e8f9f7 | 2758 | /* Select LFXO as clock source for USB, can only be used in sleep mode */ |
<> | 144:ef7eb2e8f9f7 | 2759 | /* Ensure selected oscillator is enabled, waiting for it to stabilize */ |
<> | 144:ef7eb2e8f9f7 | 2760 | CMU_OscillatorEnable(cmuOsc_LFXO, true, true); |
<> | 144:ef7eb2e8f9f7 | 2761 | |
<> | 144:ef7eb2e8f9f7 | 2762 | /* Switch oscillator */ |
<> | 144:ef7eb2e8f9f7 | 2763 | CMU->CMD = CMU_CMD_USBCCLKSEL_LFXO; |
<> | 144:ef7eb2e8f9f7 | 2764 | |
<> | 144:ef7eb2e8f9f7 | 2765 | /* Wait until clock is activated */ |
<> | 144:ef7eb2e8f9f7 | 2766 | while((CMU->STATUS & CMU_STATUS_USBCLFXOSEL)==0) |
<> | 144:ef7eb2e8f9f7 | 2767 | { |
<> | 144:ef7eb2e8f9f7 | 2768 | } |
<> | 144:ef7eb2e8f9f7 | 2769 | break; |
<> | 144:ef7eb2e8f9f7 | 2770 | |
<> | 144:ef7eb2e8f9f7 | 2771 | case cmuSelect_LFRCO: |
<> | 144:ef7eb2e8f9f7 | 2772 | /* Select LFRCO as clock source for USB, can only be used in sleep mode */ |
<> | 144:ef7eb2e8f9f7 | 2773 | /* Ensure selected oscillator is enabled, waiting for it to stabilize */ |
<> | 144:ef7eb2e8f9f7 | 2774 | CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); |
<> | 144:ef7eb2e8f9f7 | 2775 | |
<> | 144:ef7eb2e8f9f7 | 2776 | /* Switch oscillator */ |
<> | 144:ef7eb2e8f9f7 | 2777 | CMU->CMD = CMU_CMD_USBCCLKSEL_LFRCO; |
<> | 144:ef7eb2e8f9f7 | 2778 | |
<> | 144:ef7eb2e8f9f7 | 2779 | /* Wait until clock is activated */ |
<> | 144:ef7eb2e8f9f7 | 2780 | while((CMU->STATUS & CMU_STATUS_USBCLFRCOSEL)==0) |
<> | 144:ef7eb2e8f9f7 | 2781 | { |
<> | 144:ef7eb2e8f9f7 | 2782 | } |
<> | 144:ef7eb2e8f9f7 | 2783 | break; |
<> | 144:ef7eb2e8f9f7 | 2784 | |
<> | 144:ef7eb2e8f9f7 | 2785 | #if defined( CMU_STATUS_USBCHFCLKSEL ) |
<> | 144:ef7eb2e8f9f7 | 2786 | case cmuSelect_HFCLK: |
<> | 144:ef7eb2e8f9f7 | 2787 | /* Select undivided HFCLK as clock source for USB */ |
<> | 144:ef7eb2e8f9f7 | 2788 | /* Oscillator must already be enabled to avoid a core lockup */ |
<> | 144:ef7eb2e8f9f7 | 2789 | CMU->CMD = CMU_CMD_USBCCLKSEL_HFCLKNODIV; |
<> | 144:ef7eb2e8f9f7 | 2790 | /* Wait until clock is activated */ |
<> | 144:ef7eb2e8f9f7 | 2791 | while((CMU->STATUS & CMU_STATUS_USBCHFCLKSEL)==0) |
<> | 144:ef7eb2e8f9f7 | 2792 | { |
<> | 144:ef7eb2e8f9f7 | 2793 | } |
<> | 144:ef7eb2e8f9f7 | 2794 | break; |
<> | 144:ef7eb2e8f9f7 | 2795 | #endif |
<> | 144:ef7eb2e8f9f7 | 2796 | |
<> | 144:ef7eb2e8f9f7 | 2797 | #if defined( CMU_CMD_USBCCLKSEL_USHFRCO ) |
<> | 144:ef7eb2e8f9f7 | 2798 | case cmuSelect_USHFRCO: |
<> | 144:ef7eb2e8f9f7 | 2799 | /* Select USHFRCO as clock source for USB */ |
<> | 144:ef7eb2e8f9f7 | 2800 | /* Ensure selected oscillator is enabled, waiting for it to stabilize */ |
<> | 144:ef7eb2e8f9f7 | 2801 | CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); |
<> | 144:ef7eb2e8f9f7 | 2802 | |
<> | 144:ef7eb2e8f9f7 | 2803 | /* Switch oscillator */ |
<> | 144:ef7eb2e8f9f7 | 2804 | CMU->CMD = CMU_CMD_USBCCLKSEL_USHFRCO; |
<> | 144:ef7eb2e8f9f7 | 2805 | |
<> | 144:ef7eb2e8f9f7 | 2806 | /* Wait until clock is activated */ |
<> | 144:ef7eb2e8f9f7 | 2807 | while((CMU->STATUS & CMU_STATUS_USBCUSHFRCOSEL)==0) |
<> | 144:ef7eb2e8f9f7 | 2808 | { |
<> | 144:ef7eb2e8f9f7 | 2809 | } |
<> | 144:ef7eb2e8f9f7 | 2810 | break; |
<> | 144:ef7eb2e8f9f7 | 2811 | #endif |
<> | 144:ef7eb2e8f9f7 | 2812 | |
<> | 144:ef7eb2e8f9f7 | 2813 | default: |
<> | 144:ef7eb2e8f9f7 | 2814 | /* Illegal clock source for USB */ |
<> | 144:ef7eb2e8f9f7 | 2815 | EFM_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 2816 | return; |
<> | 144:ef7eb2e8f9f7 | 2817 | } |
<> | 144:ef7eb2e8f9f7 | 2818 | break; |
<> | 144:ef7eb2e8f9f7 | 2819 | #endif |
<> | 144:ef7eb2e8f9f7 | 2820 | |
<> | 144:ef7eb2e8f9f7 | 2821 | default: |
<> | 144:ef7eb2e8f9f7 | 2822 | EFM_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 2823 | break; |
<> | 144:ef7eb2e8f9f7 | 2824 | } |
<> | 144:ef7eb2e8f9f7 | 2825 | } |
<> | 144:ef7eb2e8f9f7 | 2826 | |
<> | 144:ef7eb2e8f9f7 | 2827 | |
<> | 144:ef7eb2e8f9f7 | 2828 | /**************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 2829 | * @brief |
<> | 144:ef7eb2e8f9f7 | 2830 | * CMU low frequency register synchronization freeze control. |
<> | 144:ef7eb2e8f9f7 | 2831 | * |
<> | 144:ef7eb2e8f9f7 | 2832 | * @details |
<> | 144:ef7eb2e8f9f7 | 2833 | * Some CMU registers requires synchronization into the low frequency (LF) |
<> | 144:ef7eb2e8f9f7 | 2834 | * domain. The freeze feature allows for several such registers to be |
<> | 144:ef7eb2e8f9f7 | 2835 | * modified before passing them to the LF domain simultaneously (which |
<> | 144:ef7eb2e8f9f7 | 2836 | * takes place when the freeze mode is disabled). |
<> | 144:ef7eb2e8f9f7 | 2837 | * |
<> | 144:ef7eb2e8f9f7 | 2838 | * Another usage scenario of this feature, is when using an API (such |
<> | 144:ef7eb2e8f9f7 | 2839 | * as the CMU API) for modifying several bit fields consecutively in the |
<> | 144:ef7eb2e8f9f7 | 2840 | * same register. If freeze mode is enabled during this sequence, stalling |
<> | 144:ef7eb2e8f9f7 | 2841 | * can be avoided. |
<> | 144:ef7eb2e8f9f7 | 2842 | * |
<> | 144:ef7eb2e8f9f7 | 2843 | * @note |
<> | 144:ef7eb2e8f9f7 | 2844 | * When enabling freeze mode, this function will wait for all current |
<> | 144:ef7eb2e8f9f7 | 2845 | * ongoing CMU synchronization to LF domain to complete (Normally |
<> | 144:ef7eb2e8f9f7 | 2846 | * synchronization will not be in progress.) However for this reason, when |
<> | 144:ef7eb2e8f9f7 | 2847 | * using freeze mode, modifications of registers requiring LF synchronization |
<> | 144:ef7eb2e8f9f7 | 2848 | * should be done within one freeze enable/disable block to avoid unecessary |
<> | 144:ef7eb2e8f9f7 | 2849 | * stalling. |
<> | 144:ef7eb2e8f9f7 | 2850 | * |
<> | 144:ef7eb2e8f9f7 | 2851 | * @param[in] enable |
<> | 144:ef7eb2e8f9f7 | 2852 | * @li true - enable freeze, modified registers are not propagated to the |
<> | 144:ef7eb2e8f9f7 | 2853 | * LF domain |
<> | 144:ef7eb2e8f9f7 | 2854 | * @li false - disable freeze, modified registers are propagated to LF |
<> | 144:ef7eb2e8f9f7 | 2855 | * domain |
<> | 144:ef7eb2e8f9f7 | 2856 | *****************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 2857 | void CMU_FreezeEnable(bool enable) |
<> | 144:ef7eb2e8f9f7 | 2858 | { |
<> | 144:ef7eb2e8f9f7 | 2859 | if (enable) |
<> | 144:ef7eb2e8f9f7 | 2860 | { |
<> | 144:ef7eb2e8f9f7 | 2861 | /* Wait for any ongoing LF synchronization to complete. This is just to */ |
<> | 144:ef7eb2e8f9f7 | 2862 | /* protect against the rare case when a user */ |
<> | 144:ef7eb2e8f9f7 | 2863 | /* - modifies a register requiring LF sync */ |
<> | 144:ef7eb2e8f9f7 | 2864 | /* - then enables freeze before LF sync completed */ |
<> | 144:ef7eb2e8f9f7 | 2865 | /* - then modifies the same register again */ |
<> | 144:ef7eb2e8f9f7 | 2866 | /* since modifying a register while it is in sync progress should be */ |
<> | 144:ef7eb2e8f9f7 | 2867 | /* avoided. */ |
<> | 144:ef7eb2e8f9f7 | 2868 | while (CMU->SYNCBUSY) |
<> | 144:ef7eb2e8f9f7 | 2869 | { |
<> | 144:ef7eb2e8f9f7 | 2870 | } |
<> | 144:ef7eb2e8f9f7 | 2871 | |
<> | 144:ef7eb2e8f9f7 | 2872 | CMU->FREEZE = CMU_FREEZE_REGFREEZE; |
<> | 144:ef7eb2e8f9f7 | 2873 | } |
<> | 144:ef7eb2e8f9f7 | 2874 | else |
<> | 144:ef7eb2e8f9f7 | 2875 | { |
<> | 144:ef7eb2e8f9f7 | 2876 | CMU->FREEZE = 0; |
<> | 144:ef7eb2e8f9f7 | 2877 | } |
<> | 144:ef7eb2e8f9f7 | 2878 | } |
<> | 144:ef7eb2e8f9f7 | 2879 | |
<> | 144:ef7eb2e8f9f7 | 2880 | |
<> | 144:ef7eb2e8f9f7 | 2881 | #if defined( _CMU_HFRCOCTRL_BAND_MASK ) |
<> | 144:ef7eb2e8f9f7 | 2882 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 2883 | * @brief |
<> | 144:ef7eb2e8f9f7 | 2884 | * Get HFRCO band in use. |
<> | 144:ef7eb2e8f9f7 | 2885 | * |
<> | 144:ef7eb2e8f9f7 | 2886 | * @return |
<> | 144:ef7eb2e8f9f7 | 2887 | * HFRCO band in use. |
<> | 144:ef7eb2e8f9f7 | 2888 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 2889 | CMU_HFRCOBand_TypeDef CMU_HFRCOBandGet(void) |
<> | 144:ef7eb2e8f9f7 | 2890 | { |
<> | 144:ef7eb2e8f9f7 | 2891 | return (CMU_HFRCOBand_TypeDef)((CMU->HFRCOCTRL & _CMU_HFRCOCTRL_BAND_MASK) |
<> | 144:ef7eb2e8f9f7 | 2892 | >> _CMU_HFRCOCTRL_BAND_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 2893 | } |
<> | 144:ef7eb2e8f9f7 | 2894 | #endif /* _CMU_HFRCOCTRL_BAND_MASK */ |
<> | 144:ef7eb2e8f9f7 | 2895 | |
<> | 144:ef7eb2e8f9f7 | 2896 | |
<> | 144:ef7eb2e8f9f7 | 2897 | #if defined( _CMU_HFRCOCTRL_BAND_MASK ) |
<> | 144:ef7eb2e8f9f7 | 2898 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 2899 | * @brief |
<> | 144:ef7eb2e8f9f7 | 2900 | * Set HFRCO band and the tuning value based on the value in the calibration |
<> | 144:ef7eb2e8f9f7 | 2901 | * table made during production. |
<> | 144:ef7eb2e8f9f7 | 2902 | * |
<> | 144:ef7eb2e8f9f7 | 2903 | * @param[in] band |
<> | 144:ef7eb2e8f9f7 | 2904 | * HFRCO band to activate. |
<> | 144:ef7eb2e8f9f7 | 2905 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 2906 | void CMU_HFRCOBandSet(CMU_HFRCOBand_TypeDef band) |
<> | 144:ef7eb2e8f9f7 | 2907 | { |
<> | 144:ef7eb2e8f9f7 | 2908 | uint32_t tuning; |
<> | 144:ef7eb2e8f9f7 | 2909 | uint32_t freq; |
<> | 144:ef7eb2e8f9f7 | 2910 | CMU_Select_TypeDef osc; |
<> | 144:ef7eb2e8f9f7 | 2911 | |
<> | 144:ef7eb2e8f9f7 | 2912 | /* Read tuning value from calibration table */ |
<> | 144:ef7eb2e8f9f7 | 2913 | switch (band) |
<> | 144:ef7eb2e8f9f7 | 2914 | { |
<> | 144:ef7eb2e8f9f7 | 2915 | case cmuHFRCOBand_1MHz: |
<> | 144:ef7eb2e8f9f7 | 2916 | tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND1_MASK) |
<> | 144:ef7eb2e8f9f7 | 2917 | >> _DEVINFO_HFRCOCAL0_BAND1_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 2918 | break; |
<> | 144:ef7eb2e8f9f7 | 2919 | |
<> | 144:ef7eb2e8f9f7 | 2920 | case cmuHFRCOBand_7MHz: |
<> | 144:ef7eb2e8f9f7 | 2921 | tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND7_MASK) |
<> | 144:ef7eb2e8f9f7 | 2922 | >> _DEVINFO_HFRCOCAL0_BAND7_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 2923 | break; |
<> | 144:ef7eb2e8f9f7 | 2924 | |
<> | 144:ef7eb2e8f9f7 | 2925 | case cmuHFRCOBand_11MHz: |
<> | 144:ef7eb2e8f9f7 | 2926 | tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND11_MASK) |
<> | 144:ef7eb2e8f9f7 | 2927 | >> _DEVINFO_HFRCOCAL0_BAND11_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 2928 | break; |
<> | 144:ef7eb2e8f9f7 | 2929 | |
<> | 144:ef7eb2e8f9f7 | 2930 | case cmuHFRCOBand_14MHz: |
<> | 144:ef7eb2e8f9f7 | 2931 | tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND14_MASK) |
<> | 144:ef7eb2e8f9f7 | 2932 | >> _DEVINFO_HFRCOCAL0_BAND14_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 2933 | break; |
<> | 144:ef7eb2e8f9f7 | 2934 | |
<> | 144:ef7eb2e8f9f7 | 2935 | case cmuHFRCOBand_21MHz: |
<> | 144:ef7eb2e8f9f7 | 2936 | tuning = (DEVINFO->HFRCOCAL1 & _DEVINFO_HFRCOCAL1_BAND21_MASK) |
<> | 144:ef7eb2e8f9f7 | 2937 | >> _DEVINFO_HFRCOCAL1_BAND21_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 2938 | break; |
<> | 144:ef7eb2e8f9f7 | 2939 | |
<> | 144:ef7eb2e8f9f7 | 2940 | #if defined( _CMU_HFRCOCTRL_BAND_28MHZ ) |
<> | 144:ef7eb2e8f9f7 | 2941 | case cmuHFRCOBand_28MHz: |
<> | 144:ef7eb2e8f9f7 | 2942 | tuning = (DEVINFO->HFRCOCAL1 & _DEVINFO_HFRCOCAL1_BAND28_MASK) |
<> | 144:ef7eb2e8f9f7 | 2943 | >> _DEVINFO_HFRCOCAL1_BAND28_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 2944 | break; |
<> | 144:ef7eb2e8f9f7 | 2945 | #endif |
<> | 144:ef7eb2e8f9f7 | 2946 | |
<> | 144:ef7eb2e8f9f7 | 2947 | default: |
<> | 144:ef7eb2e8f9f7 | 2948 | EFM_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 2949 | return; |
<> | 144:ef7eb2e8f9f7 | 2950 | } |
<> | 144:ef7eb2e8f9f7 | 2951 | |
<> | 144:ef7eb2e8f9f7 | 2952 | /* If HFRCO is used for core clock, we have to consider flash access WS. */ |
<> | 144:ef7eb2e8f9f7 | 2953 | osc = CMU_ClockSelectGet(cmuClock_HF); |
<> | 144:ef7eb2e8f9f7 | 2954 | if (osc == cmuSelect_HFRCO) |
<> | 144:ef7eb2e8f9f7 | 2955 | { |
<> | 144:ef7eb2e8f9f7 | 2956 | /* Configure worst case wait states for flash access before setting divider */ |
<> | 144:ef7eb2e8f9f7 | 2957 | flashWaitStateMax(); |
<> | 144:ef7eb2e8f9f7 | 2958 | } |
<> | 144:ef7eb2e8f9f7 | 2959 | |
<> | 144:ef7eb2e8f9f7 | 2960 | /* Set band/tuning */ |
<> | 144:ef7eb2e8f9f7 | 2961 | CMU->HFRCOCTRL = (CMU->HFRCOCTRL & |
<> | 144:ef7eb2e8f9f7 | 2962 | ~(_CMU_HFRCOCTRL_BAND_MASK | _CMU_HFRCOCTRL_TUNING_MASK)) |
<> | 144:ef7eb2e8f9f7 | 2963 | | (band << _CMU_HFRCOCTRL_BAND_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 2964 | | (tuning << _CMU_HFRCOCTRL_TUNING_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 2965 | |
<> | 144:ef7eb2e8f9f7 | 2966 | /* If HFRCO is used for core clock, optimize flash WS */ |
<> | 144:ef7eb2e8f9f7 | 2967 | if (osc == cmuSelect_HFRCO) |
<> | 144:ef7eb2e8f9f7 | 2968 | { |
<> | 144:ef7eb2e8f9f7 | 2969 | /* Update CMSIS core clock variable and get current core clock */ |
<> | 144:ef7eb2e8f9f7 | 2970 | /* (The function will update the global variable) */ |
<> | 144:ef7eb2e8f9f7 | 2971 | /* NOTE! We need at least 21 cycles before setting zero wait state to flash */ |
<> | 144:ef7eb2e8f9f7 | 2972 | /* (i.e. WS0) when going from the 28MHz to 1MHz in the HFRCO band */ |
<> | 144:ef7eb2e8f9f7 | 2973 | freq = SystemCoreClockGet(); |
<> | 144:ef7eb2e8f9f7 | 2974 | |
<> | 144:ef7eb2e8f9f7 | 2975 | /* Optimize flash access wait state setting for current core clk */ |
<> | 144:ef7eb2e8f9f7 | 2976 | flashWaitStateControl(freq); |
<> | 144:ef7eb2e8f9f7 | 2977 | } |
<> | 144:ef7eb2e8f9f7 | 2978 | } |
<> | 144:ef7eb2e8f9f7 | 2979 | #endif /* _CMU_HFRCOCTRL_BAND_MASK */ |
<> | 144:ef7eb2e8f9f7 | 2980 | |
<> | 144:ef7eb2e8f9f7 | 2981 | |
<> | 144:ef7eb2e8f9f7 | 2982 | #if defined( _CMU_HFRCOCTRL_FREQRANGE_MASK ) |
<> | 144:ef7eb2e8f9f7 | 2983 | /**************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 2984 | * @brief |
<> | 144:ef7eb2e8f9f7 | 2985 | * Get a pointer to the HFRCO frequency calibration word in DEVINFO |
<> | 144:ef7eb2e8f9f7 | 2986 | * |
<> | 144:ef7eb2e8f9f7 | 2987 | * @param[in] freq |
<> | 144:ef7eb2e8f9f7 | 2988 | * Frequency in Hz |
<> | 144:ef7eb2e8f9f7 | 2989 | * |
<> | 144:ef7eb2e8f9f7 | 2990 | * @return |
<> | 144:ef7eb2e8f9f7 | 2991 | * HFRCO calibration word for a given frequency |
<> | 144:ef7eb2e8f9f7 | 2992 | *****************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 2993 | static uint32_t CMU_HFRCODevinfoGet(CMU_HFRCOFreq_TypeDef freq) |
<> | 144:ef7eb2e8f9f7 | 2994 | { |
<> | 144:ef7eb2e8f9f7 | 2995 | switch (freq) |
<> | 144:ef7eb2e8f9f7 | 2996 | { |
<> | 144:ef7eb2e8f9f7 | 2997 | /* 1, 2 and 4MHz share the same calibration word */ |
<> | 144:ef7eb2e8f9f7 | 2998 | case cmuHFRCOFreq_1M0Hz: |
<> | 144:ef7eb2e8f9f7 | 2999 | case cmuHFRCOFreq_2M0Hz: |
<> | 144:ef7eb2e8f9f7 | 3000 | case cmuHFRCOFreq_4M0Hz: |
<> | 144:ef7eb2e8f9f7 | 3001 | return DEVINFO->HFRCOCAL0; |
<> | 144:ef7eb2e8f9f7 | 3002 | |
<> | 144:ef7eb2e8f9f7 | 3003 | case cmuHFRCOFreq_7M0Hz: |
<> | 144:ef7eb2e8f9f7 | 3004 | return DEVINFO->HFRCOCAL3; |
<> | 144:ef7eb2e8f9f7 | 3005 | |
<> | 144:ef7eb2e8f9f7 | 3006 | case cmuHFRCOFreq_13M0Hz: |
<> | 144:ef7eb2e8f9f7 | 3007 | return DEVINFO->HFRCOCAL6; |
<> | 144:ef7eb2e8f9f7 | 3008 | |
<> | 144:ef7eb2e8f9f7 | 3009 | case cmuHFRCOFreq_16M0Hz: |
<> | 144:ef7eb2e8f9f7 | 3010 | return DEVINFO->HFRCOCAL7; |
<> | 144:ef7eb2e8f9f7 | 3011 | |
<> | 144:ef7eb2e8f9f7 | 3012 | case cmuHFRCOFreq_19M0Hz: |
<> | 144:ef7eb2e8f9f7 | 3013 | return DEVINFO->HFRCOCAL8; |
<> | 144:ef7eb2e8f9f7 | 3014 | |
<> | 144:ef7eb2e8f9f7 | 3015 | case cmuHFRCOFreq_26M0Hz: |
<> | 144:ef7eb2e8f9f7 | 3016 | return DEVINFO->HFRCOCAL10; |
<> | 144:ef7eb2e8f9f7 | 3017 | |
<> | 144:ef7eb2e8f9f7 | 3018 | case cmuHFRCOFreq_32M0Hz: |
<> | 144:ef7eb2e8f9f7 | 3019 | return DEVINFO->HFRCOCAL11; |
<> | 144:ef7eb2e8f9f7 | 3020 | |
<> | 144:ef7eb2e8f9f7 | 3021 | case cmuHFRCOFreq_38M0Hz: |
<> | 144:ef7eb2e8f9f7 | 3022 | return DEVINFO->HFRCOCAL12; |
<> | 144:ef7eb2e8f9f7 | 3023 | |
<> | 144:ef7eb2e8f9f7 | 3024 | default: /* cmuHFRCOFreq_UserDefined */ |
<> | 144:ef7eb2e8f9f7 | 3025 | return 0; |
<> | 144:ef7eb2e8f9f7 | 3026 | } |
<> | 144:ef7eb2e8f9f7 | 3027 | } |
<> | 144:ef7eb2e8f9f7 | 3028 | |
<> | 144:ef7eb2e8f9f7 | 3029 | |
<> | 144:ef7eb2e8f9f7 | 3030 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 3031 | * @brief |
<> | 144:ef7eb2e8f9f7 | 3032 | * Get HFRCO frequency enumeration in use |
<> | 144:ef7eb2e8f9f7 | 3033 | * |
<> | 144:ef7eb2e8f9f7 | 3034 | * @return |
<> | 144:ef7eb2e8f9f7 | 3035 | * HFRCO frequency enumeration in use |
<> | 144:ef7eb2e8f9f7 | 3036 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 3037 | CMU_HFRCOFreq_TypeDef CMU_HFRCOFreqGet(void) |
<> | 144:ef7eb2e8f9f7 | 3038 | { |
<> | 144:ef7eb2e8f9f7 | 3039 | return (CMU_HFRCOFreq_TypeDef)SystemHfrcoFreq; |
<> | 144:ef7eb2e8f9f7 | 3040 | } |
<> | 144:ef7eb2e8f9f7 | 3041 | |
<> | 144:ef7eb2e8f9f7 | 3042 | |
<> | 144:ef7eb2e8f9f7 | 3043 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 3044 | * @brief |
<> | 144:ef7eb2e8f9f7 | 3045 | * Set HFRCO calibration for the selected target frequency |
<> | 144:ef7eb2e8f9f7 | 3046 | * |
<> | 144:ef7eb2e8f9f7 | 3047 | * @param[in] freq |
<> | 144:ef7eb2e8f9f7 | 3048 | * HFRCO frequency band to set |
<> | 144:ef7eb2e8f9f7 | 3049 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 3050 | void CMU_HFRCOFreqSet(CMU_HFRCOFreq_TypeDef freq) |
<> | 144:ef7eb2e8f9f7 | 3051 | { |
<> | 144:ef7eb2e8f9f7 | 3052 | uint32_t freqCal; |
<> | 144:ef7eb2e8f9f7 | 3053 | |
<> | 144:ef7eb2e8f9f7 | 3054 | /* Get DEVINFO index, set CMSIS frequency SystemHfrcoFreq */ |
<> | 144:ef7eb2e8f9f7 | 3055 | freqCal = CMU_HFRCODevinfoGet(freq); |
<> | 144:ef7eb2e8f9f7 | 3056 | EFM_ASSERT((freqCal != 0) && (freqCal != UINT_MAX)); |
<> | 144:ef7eb2e8f9f7 | 3057 | SystemHfrcoFreq = (uint32_t)freq; |
<> | 144:ef7eb2e8f9f7 | 3058 | |
<> | 144:ef7eb2e8f9f7 | 3059 | /* Set max wait-states while changing core clock */ |
<> | 144:ef7eb2e8f9f7 | 3060 | if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) |
<> | 144:ef7eb2e8f9f7 | 3061 | { |
<> | 144:ef7eb2e8f9f7 | 3062 | flashWaitStateMax(); |
<> | 144:ef7eb2e8f9f7 | 3063 | } |
<> | 144:ef7eb2e8f9f7 | 3064 | |
<> | 144:ef7eb2e8f9f7 | 3065 | /* Wait for any previous sync to complete, and then set calibration data |
<> | 144:ef7eb2e8f9f7 | 3066 | for the selected frequency. */ |
<> | 144:ef7eb2e8f9f7 | 3067 | while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_HFRCOBSY_SHIFT)); |
<> | 144:ef7eb2e8f9f7 | 3068 | |
<> | 144:ef7eb2e8f9f7 | 3069 | /* Check for valid calibration data */ |
<> | 144:ef7eb2e8f9f7 | 3070 | EFM_ASSERT(freqCal != UINT_MAX); |
<> | 144:ef7eb2e8f9f7 | 3071 | |
<> | 144:ef7eb2e8f9f7 | 3072 | /* Set divider in HFRCOCTRL for 1, 2 and 4MHz */ |
<> | 144:ef7eb2e8f9f7 | 3073 | switch(freq) |
<> | 144:ef7eb2e8f9f7 | 3074 | { |
<> | 144:ef7eb2e8f9f7 | 3075 | case cmuHFRCOFreq_1M0Hz: |
<> | 144:ef7eb2e8f9f7 | 3076 | freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK) |
<> | 144:ef7eb2e8f9f7 | 3077 | | CMU_HFRCOCTRL_CLKDIV_DIV4; |
<> | 144:ef7eb2e8f9f7 | 3078 | break; |
<> | 144:ef7eb2e8f9f7 | 3079 | |
<> | 144:ef7eb2e8f9f7 | 3080 | case cmuHFRCOFreq_2M0Hz: |
<> | 144:ef7eb2e8f9f7 | 3081 | freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK) |
<> | 144:ef7eb2e8f9f7 | 3082 | | CMU_HFRCOCTRL_CLKDIV_DIV2; |
<> | 144:ef7eb2e8f9f7 | 3083 | break; |
<> | 144:ef7eb2e8f9f7 | 3084 | |
<> | 144:ef7eb2e8f9f7 | 3085 | case cmuHFRCOFreq_4M0Hz: |
<> | 144:ef7eb2e8f9f7 | 3086 | freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK) |
<> | 144:ef7eb2e8f9f7 | 3087 | | CMU_HFRCOCTRL_CLKDIV_DIV1; |
<> | 144:ef7eb2e8f9f7 | 3088 | break; |
<> | 144:ef7eb2e8f9f7 | 3089 | |
<> | 144:ef7eb2e8f9f7 | 3090 | default: |
<> | 144:ef7eb2e8f9f7 | 3091 | break; |
<> | 144:ef7eb2e8f9f7 | 3092 | } |
<> | 144:ef7eb2e8f9f7 | 3093 | CMU->HFRCOCTRL = freqCal; |
<> | 144:ef7eb2e8f9f7 | 3094 | |
<> | 144:ef7eb2e8f9f7 | 3095 | /* Optimize flash access wait-state configuration for this frequency, */ |
<> | 144:ef7eb2e8f9f7 | 3096 | /* if HFRCO is reference for core clock. */ |
<> | 144:ef7eb2e8f9f7 | 3097 | if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) |
<> | 144:ef7eb2e8f9f7 | 3098 | { |
<> | 144:ef7eb2e8f9f7 | 3099 | flashWaitStateControl((uint32_t)freq); |
<> | 144:ef7eb2e8f9f7 | 3100 | } |
<> | 144:ef7eb2e8f9f7 | 3101 | } |
<> | 144:ef7eb2e8f9f7 | 3102 | #endif /* _CMU_HFRCOCTRL_FREQRANGE_MASK */ |
<> | 144:ef7eb2e8f9f7 | 3103 | |
<> | 144:ef7eb2e8f9f7 | 3104 | #if defined( _CMU_HFRCOCTRL_SUDELAY_MASK ) |
<> | 144:ef7eb2e8f9f7 | 3105 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 3106 | * @brief |
<> | 144:ef7eb2e8f9f7 | 3107 | * Get the HFRCO startup delay. |
<> | 144:ef7eb2e8f9f7 | 3108 | * |
<> | 144:ef7eb2e8f9f7 | 3109 | * @details |
<> | 144:ef7eb2e8f9f7 | 3110 | * Please refer to the reference manual for further details. |
<> | 144:ef7eb2e8f9f7 | 3111 | * |
<> | 144:ef7eb2e8f9f7 | 3112 | * @return |
<> | 144:ef7eb2e8f9f7 | 3113 | * The startup delay in use. |
<> | 144:ef7eb2e8f9f7 | 3114 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 3115 | uint32_t CMU_HFRCOStartupDelayGet(void) |
<> | 144:ef7eb2e8f9f7 | 3116 | { |
<> | 144:ef7eb2e8f9f7 | 3117 | return (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_SUDELAY_MASK) |
<> | 144:ef7eb2e8f9f7 | 3118 | >> _CMU_HFRCOCTRL_SUDELAY_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 3119 | } |
<> | 144:ef7eb2e8f9f7 | 3120 | |
<> | 144:ef7eb2e8f9f7 | 3121 | |
<> | 144:ef7eb2e8f9f7 | 3122 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 3123 | * @brief |
<> | 144:ef7eb2e8f9f7 | 3124 | * Set the HFRCO startup delay. |
<> | 144:ef7eb2e8f9f7 | 3125 | * |
<> | 144:ef7eb2e8f9f7 | 3126 | * @details |
<> | 144:ef7eb2e8f9f7 | 3127 | * Please refer to the reference manual for further details. |
<> | 144:ef7eb2e8f9f7 | 3128 | * |
<> | 144:ef7eb2e8f9f7 | 3129 | * @param[in] delay |
<> | 144:ef7eb2e8f9f7 | 3130 | * The startup delay to set (<= 31). |
<> | 144:ef7eb2e8f9f7 | 3131 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 3132 | void CMU_HFRCOStartupDelaySet(uint32_t delay) |
<> | 144:ef7eb2e8f9f7 | 3133 | { |
<> | 144:ef7eb2e8f9f7 | 3134 | EFM_ASSERT(delay <= 31); |
<> | 144:ef7eb2e8f9f7 | 3135 | |
<> | 144:ef7eb2e8f9f7 | 3136 | delay &= _CMU_HFRCOCTRL_SUDELAY_MASK >> _CMU_HFRCOCTRL_SUDELAY_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 3137 | CMU->HFRCOCTRL = (CMU->HFRCOCTRL & ~(_CMU_HFRCOCTRL_SUDELAY_MASK)) |
<> | 144:ef7eb2e8f9f7 | 3138 | | (delay << _CMU_HFRCOCTRL_SUDELAY_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 3139 | } |
<> | 144:ef7eb2e8f9f7 | 3140 | #endif |
<> | 144:ef7eb2e8f9f7 | 3141 | |
<> | 144:ef7eb2e8f9f7 | 3142 | |
<> | 144:ef7eb2e8f9f7 | 3143 | #if defined( _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK ) |
<> | 144:ef7eb2e8f9f7 | 3144 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 3145 | * @brief |
<> | 144:ef7eb2e8f9f7 | 3146 | * Enable or disable HFXO autostart |
<> | 144:ef7eb2e8f9f7 | 3147 | * |
<> | 144:ef7eb2e8f9f7 | 3148 | * @param[in] enRACStartSel |
<> | 144:ef7eb2e8f9f7 | 3149 | * If true, HFXO is automatically started and selected upon RAC wakeup. |
<> | 144:ef7eb2e8f9f7 | 3150 | * If false, HFXO is not started or selected automatically upon RAC wakeup. |
<> | 144:ef7eb2e8f9f7 | 3151 | * |
<> | 144:ef7eb2e8f9f7 | 3152 | * @param[in] enEM0EM1Start |
<> | 144:ef7eb2e8f9f7 | 3153 | * If true, HFXO is automatically started upon entering EM0/EM1 entry from |
<> | 144:ef7eb2e8f9f7 | 3154 | * EM2/EM3. HFXO selection has to be handled by the user. |
<> | 144:ef7eb2e8f9f7 | 3155 | * If false, HFXO is not started automatically when entering EM0/EM1. |
<> | 144:ef7eb2e8f9f7 | 3156 | * |
<> | 144:ef7eb2e8f9f7 | 3157 | * @param[in] enEM0EM1StartSel |
<> | 144:ef7eb2e8f9f7 | 3158 | * If true, HFXO is automatically started and immediately selected upon |
<> | 144:ef7eb2e8f9f7 | 3159 | * entering EM0/EM1 entry from EM2/EM3. Note that this option stalls the use of |
<> | 144:ef7eb2e8f9f7 | 3160 | * HFSRCCLK until HFXO becomes ready. |
<> | 144:ef7eb2e8f9f7 | 3161 | * If false, HFXO is not started or selected automatically when entering |
<> | 144:ef7eb2e8f9f7 | 3162 | * EM0/EM1. |
<> | 144:ef7eb2e8f9f7 | 3163 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 3164 | void CMU_HFXOAutostartEnable(bool enRACStartSel, |
<> | 144:ef7eb2e8f9f7 | 3165 | bool enEM0EM1Start, |
<> | 144:ef7eb2e8f9f7 | 3166 | bool enEM0EM1StartSel) |
<> | 144:ef7eb2e8f9f7 | 3167 | { |
<> | 144:ef7eb2e8f9f7 | 3168 | uint32_t hfxoCtrl; |
<> | 144:ef7eb2e8f9f7 | 3169 | hfxoCtrl = CMU->HFXOCTRL & ~(_CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK |
<> | 144:ef7eb2e8f9f7 | 3170 | | _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK |
<> | 144:ef7eb2e8f9f7 | 3171 | | _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK); |
<> | 144:ef7eb2e8f9f7 | 3172 | |
<> | 144:ef7eb2e8f9f7 | 3173 | hfxoCtrl |= (enRACStartSel ? CMU_HFXOCTRL_AUTOSTARTRDYSELRAC : 0) |
<> | 144:ef7eb2e8f9f7 | 3174 | | (enEM0EM1Start ? CMU_HFXOCTRL_AUTOSTARTEM0EM1 : 0) |
<> | 144:ef7eb2e8f9f7 | 3175 | | (enEM0EM1StartSel ? CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 : 0); |
<> | 144:ef7eb2e8f9f7 | 3176 | |
<> | 144:ef7eb2e8f9f7 | 3177 | CMU->HFXOCTRL = hfxoCtrl; |
<> | 144:ef7eb2e8f9f7 | 3178 | } |
<> | 144:ef7eb2e8f9f7 | 3179 | #endif /* _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK */ |
<> | 144:ef7eb2e8f9f7 | 3180 | |
<> | 144:ef7eb2e8f9f7 | 3181 | |
<> | 144:ef7eb2e8f9f7 | 3182 | #if defined( _CMU_HFXOCTRL_MASK ) |
<> | 144:ef7eb2e8f9f7 | 3183 | /**************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 3184 | * @brief |
<> | 144:ef7eb2e8f9f7 | 3185 | * Set HFXO control registers |
<> | 144:ef7eb2e8f9f7 | 3186 | * |
<> | 144:ef7eb2e8f9f7 | 3187 | * @note |
<> | 144:ef7eb2e8f9f7 | 3188 | * HFXO configuration should be obtained from a configuration tool, |
<> | 144:ef7eb2e8f9f7 | 3189 | * app note or xtal datasheet. This function disables the HFXO to ensure |
<> | 144:ef7eb2e8f9f7 | 3190 | * a valid state before update. |
<> | 144:ef7eb2e8f9f7 | 3191 | * |
<> | 144:ef7eb2e8f9f7 | 3192 | * @param[in] hfxoInit |
<> | 144:ef7eb2e8f9f7 | 3193 | * HFXO setup parameters |
<> | 144:ef7eb2e8f9f7 | 3194 | *****************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 3195 | void CMU_HFXOInit(CMU_HFXOInit_TypeDef *hfxoInit) |
<> | 144:ef7eb2e8f9f7 | 3196 | { |
<> | 144:ef7eb2e8f9f7 | 3197 | uint32_t ishReg; |
<> | 144:ef7eb2e8f9f7 | 3198 | uint32_t ishMax; |
<> | 144:ef7eb2e8f9f7 | 3199 | |
<> | 144:ef7eb2e8f9f7 | 3200 | /* Do not disable HFXO if it is currently selected as HF/Core clock */ |
<> | 144:ef7eb2e8f9f7 | 3201 | EFM_ASSERT(CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_HFXO); |
<> | 144:ef7eb2e8f9f7 | 3202 | |
<> | 144:ef7eb2e8f9f7 | 3203 | /* HFXO must be disabled before reconfiguration */ |
<> | 144:ef7eb2e8f9f7 | 3204 | CMU_OscillatorEnable(cmuOsc_HFXO, false, false); |
<> | 144:ef7eb2e8f9f7 | 3205 | |
<> | 144:ef7eb2e8f9f7 | 3206 | /* Apply control settings */ |
<> | 144:ef7eb2e8f9f7 | 3207 | BUS_RegMaskedWrite(&CMU->HFXOCTRL, |
<> | 144:ef7eb2e8f9f7 | 3208 | _CMU_HFXOCTRL_LOWPOWER_MASK |
<> | 144:ef7eb2e8f9f7 | 3209 | #if defined( _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK ) |
<> | 144:ef7eb2e8f9f7 | 3210 | | _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK |
<> | 144:ef7eb2e8f9f7 | 3211 | #endif |
<> | 144:ef7eb2e8f9f7 | 3212 | | _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK |
<> | 144:ef7eb2e8f9f7 | 3213 | | _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK, |
<> | 144:ef7eb2e8f9f7 | 3214 | (hfxoInit->lowPowerMode |
<> | 144:ef7eb2e8f9f7 | 3215 | ? CMU_HFXOCTRL_LOWPOWER : 0) |
<> | 144:ef7eb2e8f9f7 | 3216 | #if defined( _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK ) |
<> | 144:ef7eb2e8f9f7 | 3217 | | (hfxoInit->autoStartSelOnRacWakeup |
<> | 144:ef7eb2e8f9f7 | 3218 | ? CMU_HFXOCTRL_AUTOSTARTRDYSELRAC : 0) |
<> | 144:ef7eb2e8f9f7 | 3219 | #endif |
<> | 144:ef7eb2e8f9f7 | 3220 | | (hfxoInit->autoStartEm01 |
<> | 144:ef7eb2e8f9f7 | 3221 | ? CMU_HFXOCTRL_AUTOSTARTEM0EM1 : 0) |
<> | 144:ef7eb2e8f9f7 | 3222 | | (hfxoInit->autoSelEm01 |
<> | 144:ef7eb2e8f9f7 | 3223 | ? CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 : 0)); |
<> | 144:ef7eb2e8f9f7 | 3224 | |
<> | 144:ef7eb2e8f9f7 | 3225 | /* Set XTAL tuning parameters */ |
<> | 144:ef7eb2e8f9f7 | 3226 | |
<> | 144:ef7eb2e8f9f7 | 3227 | /* Set peak detection threshold in CMU_HFXOCTRL1_PEAKDETTHR[2:0] (hidden). */ |
<> | 144:ef7eb2e8f9f7 | 3228 | BUS_RegMaskedWrite((volatile uint32_t *)0x400E4028, 0x7, hfxoInit->thresholdPeakDetect); |
<> | 144:ef7eb2e8f9f7 | 3229 | |
<> | 144:ef7eb2e8f9f7 | 3230 | /* Set tuning for startup and steady state */ |
<> | 144:ef7eb2e8f9f7 | 3231 | BUS_RegMaskedWrite(&CMU->HFXOSTARTUPCTRL, |
<> | 144:ef7eb2e8f9f7 | 3232 | _CMU_HFXOSTARTUPCTRL_CTUNE_MASK |
<> | 144:ef7eb2e8f9f7 | 3233 | | _CMU_HFXOSTARTUPCTRL_REGISHWARM_MASK |
<> | 144:ef7eb2e8f9f7 | 3234 | | _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK |
<> | 144:ef7eb2e8f9f7 | 3235 | | _CMU_HFXOSTARTUPCTRL_IBTRIMXOCOREWARM_MASK, |
<> | 144:ef7eb2e8f9f7 | 3236 | (hfxoInit->ctuneStartup |
<> | 144:ef7eb2e8f9f7 | 3237 | << _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 3238 | | (hfxoInit->regIshStartup |
<> | 144:ef7eb2e8f9f7 | 3239 | << _CMU_HFXOSTARTUPCTRL_REGISHWARM_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 3240 | | (hfxoInit->xoCoreBiasTrimStartup |
<> | 144:ef7eb2e8f9f7 | 3241 | << _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 3242 | | 0x4 /* Recommended tuning */ |
<> | 144:ef7eb2e8f9f7 | 3243 | << _CMU_HFXOSTARTUPCTRL_IBTRIMXOCOREWARM_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 3244 | |
<> | 144:ef7eb2e8f9f7 | 3245 | /* Adjust CMU_HFXOSTEADYSTATECTRL_REGISHUPPER according to regIshSteadyState. |
<> | 144:ef7eb2e8f9f7 | 3246 | Saturate at max value. Please see the reference manual page 433 and Section |
<> | 144:ef7eb2e8f9f7 | 3247 | 12.5.10 CMU_HFXOSTEADYSTATECTRL for more details. */ |
<> | 144:ef7eb2e8f9f7 | 3248 | ishReg = hfxoInit->regIshSteadyState + 3; |
<> | 144:ef7eb2e8f9f7 | 3249 | ishMax = _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK |
<> | 144:ef7eb2e8f9f7 | 3250 | >> _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 3251 | ishReg = ishReg > ishMax ? ishMax : ishReg; |
<> | 144:ef7eb2e8f9f7 | 3252 | ishReg <<= _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 3253 | |
<> | 144:ef7eb2e8f9f7 | 3254 | BUS_RegMaskedWrite(&CMU->HFXOSTEADYSTATECTRL, |
<> | 144:ef7eb2e8f9f7 | 3255 | _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK |
<> | 144:ef7eb2e8f9f7 | 3256 | | _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK |
<> | 144:ef7eb2e8f9f7 | 3257 | | _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK |
<> | 144:ef7eb2e8f9f7 | 3258 | | _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK, |
<> | 144:ef7eb2e8f9f7 | 3259 | (hfxoInit->ctuneSteadyState |
<> | 144:ef7eb2e8f9f7 | 3260 | << _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 3261 | | (hfxoInit->regIshSteadyState |
<> | 144:ef7eb2e8f9f7 | 3262 | << _CMU_HFXOSTEADYSTATECTRL_REGISH_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 3263 | | (hfxoInit->xoCoreBiasTrimSteadyState |
<> | 144:ef7eb2e8f9f7 | 3264 | << _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 3265 | | ishReg); |
<> | 144:ef7eb2e8f9f7 | 3266 | |
<> | 144:ef7eb2e8f9f7 | 3267 | /* Set timeouts */ |
<> | 144:ef7eb2e8f9f7 | 3268 | BUS_RegMaskedWrite(&CMU->HFXOTIMEOUTCTRL, |
<> | 144:ef7eb2e8f9f7 | 3269 | _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_MASK |
<> | 144:ef7eb2e8f9f7 | 3270 | | _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK |
<> | 144:ef7eb2e8f9f7 | 3271 | | _CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_MASK |
<> | 144:ef7eb2e8f9f7 | 3272 | | _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK |
<> | 144:ef7eb2e8f9f7 | 3273 | | _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK, |
<> | 144:ef7eb2e8f9f7 | 3274 | (hfxoInit->timeoutShuntOptimization |
<> | 144:ef7eb2e8f9f7 | 3275 | << _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 3276 | | (hfxoInit->timeoutPeakDetect |
<> | 144:ef7eb2e8f9f7 | 3277 | << _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 3278 | | (hfxoInit->timeoutWarmSteady |
<> | 144:ef7eb2e8f9f7 | 3279 | << _CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 3280 | | (hfxoInit->timeoutSteady |
<> | 144:ef7eb2e8f9f7 | 3281 | << _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 3282 | | (hfxoInit->timeoutStartup |
<> | 144:ef7eb2e8f9f7 | 3283 | << _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT)); |
<> | 144:ef7eb2e8f9f7 | 3284 | } |
<> | 144:ef7eb2e8f9f7 | 3285 | #endif |
<> | 144:ef7eb2e8f9f7 | 3286 | |
<> | 144:ef7eb2e8f9f7 | 3287 | |
<> | 144:ef7eb2e8f9f7 | 3288 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 3289 | * @brief |
<> | 144:ef7eb2e8f9f7 | 3290 | * Get the LCD framerate divisor (FDIV) setting. |
<> | 144:ef7eb2e8f9f7 | 3291 | * |
<> | 144:ef7eb2e8f9f7 | 3292 | * @return |
<> | 144:ef7eb2e8f9f7 | 3293 | * The LCD framerate divisor. |
<> | 144:ef7eb2e8f9f7 | 3294 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 3295 | uint32_t CMU_LCDClkFDIVGet(void) |
<> | 144:ef7eb2e8f9f7 | 3296 | { |
<> | 144:ef7eb2e8f9f7 | 3297 | #if defined( LCD_PRESENT ) |
<> | 144:ef7eb2e8f9f7 | 3298 | return (CMU->LCDCTRL & _CMU_LCDCTRL_FDIV_MASK) >> _CMU_LCDCTRL_FDIV_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 3299 | #else |
<> | 144:ef7eb2e8f9f7 | 3300 | return 0; |
<> | 144:ef7eb2e8f9f7 | 3301 | #endif /* defined(LCD_PRESENT) */ |
<> | 144:ef7eb2e8f9f7 | 3302 | } |
<> | 144:ef7eb2e8f9f7 | 3303 | |
<> | 144:ef7eb2e8f9f7 | 3304 | |
<> | 144:ef7eb2e8f9f7 | 3305 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 3306 | * @brief |
<> | 144:ef7eb2e8f9f7 | 3307 | * Set the LCD framerate divisor (FDIV) setting. |
<> | 144:ef7eb2e8f9f7 | 3308 | * |
<> | 144:ef7eb2e8f9f7 | 3309 | * @note |
<> | 144:ef7eb2e8f9f7 | 3310 | * The FDIV field (CMU LCDCTRL register) should only be modified while the |
<> | 144:ef7eb2e8f9f7 | 3311 | * LCD module is clock disabled (CMU LFACLKEN0.LCD bit is 0). This function |
<> | 144:ef7eb2e8f9f7 | 3312 | * will NOT modify FDIV if the LCD module clock is enabled. Please refer to |
<> | 144:ef7eb2e8f9f7 | 3313 | * CMU_ClockEnable() for disabling/enabling LCD clock. |
<> | 144:ef7eb2e8f9f7 | 3314 | * |
<> | 144:ef7eb2e8f9f7 | 3315 | * @param[in] div |
<> | 144:ef7eb2e8f9f7 | 3316 | * The FDIV setting to use. |
<> | 144:ef7eb2e8f9f7 | 3317 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 3318 | void CMU_LCDClkFDIVSet(uint32_t div) |
<> | 144:ef7eb2e8f9f7 | 3319 | { |
<> | 144:ef7eb2e8f9f7 | 3320 | #if defined( LCD_PRESENT ) |
<> | 144:ef7eb2e8f9f7 | 3321 | EFM_ASSERT(div <= cmuClkDiv_128); |
<> | 144:ef7eb2e8f9f7 | 3322 | |
<> | 144:ef7eb2e8f9f7 | 3323 | /* Do not allow modification if LCD clock enabled */ |
<> | 144:ef7eb2e8f9f7 | 3324 | if (CMU->LFACLKEN0 & CMU_LFACLKEN0_LCD) |
<> | 144:ef7eb2e8f9f7 | 3325 | { |
<> | 144:ef7eb2e8f9f7 | 3326 | return; |
<> | 144:ef7eb2e8f9f7 | 3327 | } |
<> | 144:ef7eb2e8f9f7 | 3328 | |
<> | 144:ef7eb2e8f9f7 | 3329 | div <<= _CMU_LCDCTRL_FDIV_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 3330 | div &= _CMU_LCDCTRL_FDIV_MASK; |
<> | 144:ef7eb2e8f9f7 | 3331 | CMU->LCDCTRL = (CMU->LCDCTRL & ~_CMU_LCDCTRL_FDIV_MASK) | div; |
<> | 144:ef7eb2e8f9f7 | 3332 | #else |
<> | 144:ef7eb2e8f9f7 | 3333 | (void)div; /* Unused parameter */ |
<> | 144:ef7eb2e8f9f7 | 3334 | #endif /* defined(LCD_PRESENT) */ |
<> | 144:ef7eb2e8f9f7 | 3335 | } |
<> | 144:ef7eb2e8f9f7 | 3336 | |
<> | 144:ef7eb2e8f9f7 | 3337 | |
<> | 144:ef7eb2e8f9f7 | 3338 | #if defined( _CMU_LFXOCTRL_MASK ) |
<> | 144:ef7eb2e8f9f7 | 3339 | /**************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 3340 | * @brief |
<> | 144:ef7eb2e8f9f7 | 3341 | * Set LFXO control registers |
<> | 144:ef7eb2e8f9f7 | 3342 | * |
<> | 144:ef7eb2e8f9f7 | 3343 | * @note |
<> | 144:ef7eb2e8f9f7 | 3344 | * LFXO configuration should be obtained from a configuration tool, |
<> | 144:ef7eb2e8f9f7 | 3345 | * app note or xtal datasheet. This function disables the LFXO to ensure |
<> | 144:ef7eb2e8f9f7 | 3346 | * a valid state before update. |
<> | 144:ef7eb2e8f9f7 | 3347 | * |
<> | 144:ef7eb2e8f9f7 | 3348 | * @param[in] lfxoInit |
<> | 144:ef7eb2e8f9f7 | 3349 | * LFXO setup parameters |
<> | 144:ef7eb2e8f9f7 | 3350 | *****************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 3351 | void CMU_LFXOInit(CMU_LFXOInit_TypeDef *lfxoInit) |
<> | 144:ef7eb2e8f9f7 | 3352 | { |
<> | 144:ef7eb2e8f9f7 | 3353 | /* Do not disable LFXO if it is currently selected as HF/Core clock */ |
<> | 144:ef7eb2e8f9f7 | 3354 | EFM_ASSERT(CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_LFXO); |
<> | 144:ef7eb2e8f9f7 | 3355 | |
<> | 144:ef7eb2e8f9f7 | 3356 | /* LFXO must be disabled before reconfiguration */ |
<> | 144:ef7eb2e8f9f7 | 3357 | CMU_OscillatorEnable(cmuOsc_LFXO, false, false); |
<> | 144:ef7eb2e8f9f7 | 3358 | |
<> | 144:ef7eb2e8f9f7 | 3359 | BUS_RegMaskedWrite(&CMU->LFXOCTRL, |
<> | 144:ef7eb2e8f9f7 | 3360 | _CMU_LFXOCTRL_TUNING_MASK |
<> | 144:ef7eb2e8f9f7 | 3361 | | _CMU_LFXOCTRL_GAIN_MASK |
<> | 144:ef7eb2e8f9f7 | 3362 | | _CMU_LFXOCTRL_TIMEOUT_MASK, |
<> | 144:ef7eb2e8f9f7 | 3363 | (lfxoInit->ctune << _CMU_LFXOCTRL_TUNING_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 3364 | | (lfxoInit->gain << _CMU_LFXOCTRL_GAIN_SHIFT) |
<> | 144:ef7eb2e8f9f7 | 3365 | | (lfxoInit->timeout << _CMU_LFXOCTRL_TIMEOUT_SHIFT)); |
<> | 144:ef7eb2e8f9f7 | 3366 | } |
<> | 144:ef7eb2e8f9f7 | 3367 | #endif |
<> | 144:ef7eb2e8f9f7 | 3368 | |
<> | 144:ef7eb2e8f9f7 | 3369 | |
<> | 144:ef7eb2e8f9f7 | 3370 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 3371 | * @brief |
<> | 144:ef7eb2e8f9f7 | 3372 | * Enable/disable oscillator. |
<> | 144:ef7eb2e8f9f7 | 3373 | * |
<> | 144:ef7eb2e8f9f7 | 3374 | * @note |
<> | 144:ef7eb2e8f9f7 | 3375 | * WARNING: When this function is called to disable either cmuOsc_LFXO or |
<> | 144:ef7eb2e8f9f7 | 3376 | * cmuOsc_HFXO the LFXOMODE or HFXOMODE fields of the CMU_CTRL register |
<> | 144:ef7eb2e8f9f7 | 3377 | * are reset to the reset value. I.e. if external clock sources are selected |
<> | 144:ef7eb2e8f9f7 | 3378 | * in either LFXOMODE or HFXOMODE fields, the configuration will be cleared |
<> | 144:ef7eb2e8f9f7 | 3379 | * and needs to be reconfigured if needed later. |
<> | 144:ef7eb2e8f9f7 | 3380 | * |
<> | 144:ef7eb2e8f9f7 | 3381 | * @param[in] osc |
<> | 144:ef7eb2e8f9f7 | 3382 | * The oscillator to enable/disable. |
<> | 144:ef7eb2e8f9f7 | 3383 | * |
<> | 144:ef7eb2e8f9f7 | 3384 | * @param[in] enable |
<> | 144:ef7eb2e8f9f7 | 3385 | * @li true - enable specified oscillator. |
<> | 144:ef7eb2e8f9f7 | 3386 | * @li false - disable specified oscillator. |
<> | 144:ef7eb2e8f9f7 | 3387 | * |
<> | 144:ef7eb2e8f9f7 | 3388 | * @param[in] wait |
<> | 144:ef7eb2e8f9f7 | 3389 | * Only used if @p enable is true. |
<> | 144:ef7eb2e8f9f7 | 3390 | * @li true - wait for oscillator start-up time to timeout before returning. |
<> | 144:ef7eb2e8f9f7 | 3391 | * @li false - do not wait for oscillator start-up time to timeout before |
<> | 144:ef7eb2e8f9f7 | 3392 | * returning. |
<> | 144:ef7eb2e8f9f7 | 3393 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 3394 | void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait) |
<> | 144:ef7eb2e8f9f7 | 3395 | { |
<> | 144:ef7eb2e8f9f7 | 3396 | uint32_t rdyBitPos; |
<> | 144:ef7eb2e8f9f7 | 3397 | #if defined( _SILICON_LABS_32B_PLATFORM_2 ) |
<> | 144:ef7eb2e8f9f7 | 3398 | uint32_t ensBitPos; |
<> | 144:ef7eb2e8f9f7 | 3399 | #endif |
<> | 144:ef7eb2e8f9f7 | 3400 | uint32_t enBit; |
<> | 144:ef7eb2e8f9f7 | 3401 | uint32_t disBit; |
<> | 144:ef7eb2e8f9f7 | 3402 | |
<> | 144:ef7eb2e8f9f7 | 3403 | switch (osc) |
<> | 144:ef7eb2e8f9f7 | 3404 | { |
<> | 144:ef7eb2e8f9f7 | 3405 | case cmuOsc_HFRCO: |
<> | 144:ef7eb2e8f9f7 | 3406 | enBit = CMU_OSCENCMD_HFRCOEN; |
<> | 144:ef7eb2e8f9f7 | 3407 | disBit = CMU_OSCENCMD_HFRCODIS; |
<> | 144:ef7eb2e8f9f7 | 3408 | rdyBitPos = _CMU_STATUS_HFRCORDY_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 3409 | #if defined( _SILICON_LABS_32B_PLATFORM_2 ) |
<> | 144:ef7eb2e8f9f7 | 3410 | ensBitPos = _CMU_STATUS_HFRCOENS_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 3411 | #endif |
<> | 144:ef7eb2e8f9f7 | 3412 | break; |
<> | 144:ef7eb2e8f9f7 | 3413 | |
<> | 144:ef7eb2e8f9f7 | 3414 | case cmuOsc_HFXO: |
<> | 144:ef7eb2e8f9f7 | 3415 | enBit = CMU_OSCENCMD_HFXOEN; |
<> | 144:ef7eb2e8f9f7 | 3416 | disBit = CMU_OSCENCMD_HFXODIS; |
<> | 144:ef7eb2e8f9f7 | 3417 | rdyBitPos = _CMU_STATUS_HFXORDY_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 3418 | #if defined( _SILICON_LABS_32B_PLATFORM_2 ) |
<> | 144:ef7eb2e8f9f7 | 3419 | ensBitPos = _CMU_STATUS_HFXOENS_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 3420 | #endif |
<> | 144:ef7eb2e8f9f7 | 3421 | break; |
<> | 144:ef7eb2e8f9f7 | 3422 | |
<> | 144:ef7eb2e8f9f7 | 3423 | case cmuOsc_AUXHFRCO: |
<> | 144:ef7eb2e8f9f7 | 3424 | enBit = CMU_OSCENCMD_AUXHFRCOEN; |
<> | 144:ef7eb2e8f9f7 | 3425 | disBit = CMU_OSCENCMD_AUXHFRCODIS; |
<> | 144:ef7eb2e8f9f7 | 3426 | rdyBitPos = _CMU_STATUS_AUXHFRCORDY_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 3427 | #if defined( _SILICON_LABS_32B_PLATFORM_2 ) |
<> | 144:ef7eb2e8f9f7 | 3428 | ensBitPos = _CMU_STATUS_AUXHFRCOENS_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 3429 | #endif |
<> | 144:ef7eb2e8f9f7 | 3430 | break; |
<> | 144:ef7eb2e8f9f7 | 3431 | |
<> | 144:ef7eb2e8f9f7 | 3432 | case cmuOsc_LFRCO: |
<> | 144:ef7eb2e8f9f7 | 3433 | enBit = CMU_OSCENCMD_LFRCOEN; |
<> | 144:ef7eb2e8f9f7 | 3434 | disBit = CMU_OSCENCMD_LFRCODIS; |
<> | 144:ef7eb2e8f9f7 | 3435 | rdyBitPos = _CMU_STATUS_LFRCORDY_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 3436 | #if defined( _SILICON_LABS_32B_PLATFORM_2 ) |
<> | 144:ef7eb2e8f9f7 | 3437 | ensBitPos = _CMU_STATUS_LFRCOENS_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 3438 | #endif |
<> | 144:ef7eb2e8f9f7 | 3439 | break; |
<> | 144:ef7eb2e8f9f7 | 3440 | |
<> | 144:ef7eb2e8f9f7 | 3441 | case cmuOsc_LFXO: |
<> | 144:ef7eb2e8f9f7 | 3442 | enBit = CMU_OSCENCMD_LFXOEN; |
<> | 144:ef7eb2e8f9f7 | 3443 | disBit = CMU_OSCENCMD_LFXODIS; |
<> | 144:ef7eb2e8f9f7 | 3444 | rdyBitPos = _CMU_STATUS_LFXORDY_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 3445 | #if defined( _SILICON_LABS_32B_PLATFORM_2 ) |
<> | 144:ef7eb2e8f9f7 | 3446 | ensBitPos = _CMU_STATUS_LFXOENS_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 3447 | #endif |
<> | 144:ef7eb2e8f9f7 | 3448 | break; |
<> | 144:ef7eb2e8f9f7 | 3449 | |
<> | 144:ef7eb2e8f9f7 | 3450 | #if defined( _CMU_STATUS_USHFRCOENS_MASK ) |
<> | 144:ef7eb2e8f9f7 | 3451 | case cmuOsc_USHFRCO: |
<> | 144:ef7eb2e8f9f7 | 3452 | enBit = CMU_OSCENCMD_USHFRCOEN; |
<> | 144:ef7eb2e8f9f7 | 3453 | disBit = CMU_OSCENCMD_USHFRCODIS; |
<> | 144:ef7eb2e8f9f7 | 3454 | rdyBitPos = _CMU_STATUS_USHFRCORDY_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 3455 | #if defined( _SILICON_LABS_32B_PLATFORM_2 ) |
<> | 144:ef7eb2e8f9f7 | 3456 | ensBitPos = _CMU_STATUS_USHFRCOENS_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 3457 | #endif |
<> | 144:ef7eb2e8f9f7 | 3458 | break; |
<> | 144:ef7eb2e8f9f7 | 3459 | #endif |
<> | 144:ef7eb2e8f9f7 | 3460 | |
<> | 144:ef7eb2e8f9f7 | 3461 | #if defined( CMU_LFCLKSEL_LFAE_ULFRCO ) |
<> | 144:ef7eb2e8f9f7 | 3462 | case cmuOsc_ULFRCO: |
<> | 144:ef7eb2e8f9f7 | 3463 | /* ULFRCO is always enabled, and cannot be turned off */ |
<> | 144:ef7eb2e8f9f7 | 3464 | return; |
<> | 144:ef7eb2e8f9f7 | 3465 | #endif |
<> | 144:ef7eb2e8f9f7 | 3466 | |
<> | 144:ef7eb2e8f9f7 | 3467 | default: |
<> | 144:ef7eb2e8f9f7 | 3468 | /* Undefined clock source */ |
<> | 144:ef7eb2e8f9f7 | 3469 | EFM_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 3470 | return; |
<> | 144:ef7eb2e8f9f7 | 3471 | } |
<> | 144:ef7eb2e8f9f7 | 3472 | |
<> | 144:ef7eb2e8f9f7 | 3473 | if (enable) |
<> | 144:ef7eb2e8f9f7 | 3474 | { |
<> | 144:ef7eb2e8f9f7 | 3475 | CMU->OSCENCMD = enBit; |
<> | 144:ef7eb2e8f9f7 | 3476 | |
<> | 144:ef7eb2e8f9f7 | 3477 | #if defined( _SILICON_LABS_32B_PLATFORM_2 ) |
<> | 144:ef7eb2e8f9f7 | 3478 | /* Always wait for ENS to go high */ |
<> | 144:ef7eb2e8f9f7 | 3479 | while (!BUS_RegBitRead(&CMU->STATUS, ensBitPos)) |
<> | 144:ef7eb2e8f9f7 | 3480 | { |
<> | 144:ef7eb2e8f9f7 | 3481 | } |
<> | 144:ef7eb2e8f9f7 | 3482 | #endif |
<> | 144:ef7eb2e8f9f7 | 3483 | |
<> | 144:ef7eb2e8f9f7 | 3484 | /* Wait for clock to become ready after enable */ |
<> | 144:ef7eb2e8f9f7 | 3485 | if (wait) |
<> | 144:ef7eb2e8f9f7 | 3486 | { |
<> | 144:ef7eb2e8f9f7 | 3487 | while (!BUS_RegBitRead(&CMU->STATUS, rdyBitPos)); |
<> | 144:ef7eb2e8f9f7 | 3488 | #if defined( _CMU_STATUS_HFXOSHUNTOPTRDY_MASK ) |
<> | 144:ef7eb2e8f9f7 | 3489 | /* Wait for shunt current optimization to complete */ |
<> | 144:ef7eb2e8f9f7 | 3490 | if ((osc == cmuOsc_HFXO) |
<> | 144:ef7eb2e8f9f7 | 3491 | && (BUS_RegMaskedRead(&CMU->HFXOCTRL, |
<> | 144:ef7eb2e8f9f7 | 3492 | _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) |
<> | 144:ef7eb2e8f9f7 | 3493 | == CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD)) |
<> | 144:ef7eb2e8f9f7 | 3494 | { |
<> | 144:ef7eb2e8f9f7 | 3495 | while (!BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_HFXOSHUNTOPTRDY_SHIFT)) |
<> | 144:ef7eb2e8f9f7 | 3496 | { |
<> | 144:ef7eb2e8f9f7 | 3497 | } |
<> | 144:ef7eb2e8f9f7 | 3498 | /* Assert on failed peak detection. Incorrect HFXO initialization parameters |
<> | 144:ef7eb2e8f9f7 | 3499 | caused startup to fail. Please review parameters. */ |
<> | 144:ef7eb2e8f9f7 | 3500 | EFM_ASSERT(BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_HFXOPEAKDETRDY_SHIFT)); |
<> | 144:ef7eb2e8f9f7 | 3501 | } |
<> | 144:ef7eb2e8f9f7 | 3502 | #endif |
<> | 144:ef7eb2e8f9f7 | 3503 | } |
<> | 144:ef7eb2e8f9f7 | 3504 | } |
<> | 144:ef7eb2e8f9f7 | 3505 | else |
<> | 144:ef7eb2e8f9f7 | 3506 | { |
<> | 144:ef7eb2e8f9f7 | 3507 | CMU->OSCENCMD = disBit; |
<> | 144:ef7eb2e8f9f7 | 3508 | |
<> | 144:ef7eb2e8f9f7 | 3509 | #if defined( _SILICON_LABS_32B_PLATFORM_2 ) |
<> | 144:ef7eb2e8f9f7 | 3510 | /* Always wait for ENS to go low */ |
<> | 144:ef7eb2e8f9f7 | 3511 | while (BUS_RegBitRead(&CMU->STATUS, ensBitPos)) |
<> | 144:ef7eb2e8f9f7 | 3512 | { |
<> | 144:ef7eb2e8f9f7 | 3513 | } |
<> | 144:ef7eb2e8f9f7 | 3514 | #endif |
<> | 144:ef7eb2e8f9f7 | 3515 | } |
<> | 144:ef7eb2e8f9f7 | 3516 | |
<> | 144:ef7eb2e8f9f7 | 3517 | /* Keep EMU module informed */ |
<> | 144:ef7eb2e8f9f7 | 3518 | EMU_UpdateOscConfig(); |
<> | 144:ef7eb2e8f9f7 | 3519 | } |
<> | 144:ef7eb2e8f9f7 | 3520 | |
<> | 144:ef7eb2e8f9f7 | 3521 | |
<> | 144:ef7eb2e8f9f7 | 3522 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 3523 | * @brief |
<> | 144:ef7eb2e8f9f7 | 3524 | * Get oscillator frequency tuning setting. |
<> | 144:ef7eb2e8f9f7 | 3525 | * |
<> | 144:ef7eb2e8f9f7 | 3526 | * @param[in] osc |
<> | 144:ef7eb2e8f9f7 | 3527 | * Oscillator to get tuning value for, one of: |
<> | 144:ef7eb2e8f9f7 | 3528 | * @li #cmuOsc_LFRCO |
<> | 144:ef7eb2e8f9f7 | 3529 | * @li #cmuOsc_HFRCO |
<> | 144:ef7eb2e8f9f7 | 3530 | * @li #cmuOsc_AUXHFRCO |
<> | 144:ef7eb2e8f9f7 | 3531 | * |
<> | 144:ef7eb2e8f9f7 | 3532 | * @return |
<> | 144:ef7eb2e8f9f7 | 3533 | * The oscillator frequency tuning setting in use. |
<> | 144:ef7eb2e8f9f7 | 3534 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 3535 | uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc) |
<> | 144:ef7eb2e8f9f7 | 3536 | { |
<> | 144:ef7eb2e8f9f7 | 3537 | uint32_t ret; |
<> | 144:ef7eb2e8f9f7 | 3538 | |
<> | 144:ef7eb2e8f9f7 | 3539 | switch (osc) |
<> | 144:ef7eb2e8f9f7 | 3540 | { |
<> | 144:ef7eb2e8f9f7 | 3541 | case cmuOsc_LFRCO: |
<> | 144:ef7eb2e8f9f7 | 3542 | ret = (CMU->LFRCOCTRL & _CMU_LFRCOCTRL_TUNING_MASK) |
<> | 144:ef7eb2e8f9f7 | 3543 | >> _CMU_LFRCOCTRL_TUNING_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 3544 | break; |
<> | 144:ef7eb2e8f9f7 | 3545 | |
<> | 144:ef7eb2e8f9f7 | 3546 | case cmuOsc_HFRCO: |
<> | 144:ef7eb2e8f9f7 | 3547 | ret = (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_TUNING_MASK) |
<> | 144:ef7eb2e8f9f7 | 3548 | >> _CMU_HFRCOCTRL_TUNING_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 3549 | break; |
<> | 144:ef7eb2e8f9f7 | 3550 | |
<> | 144:ef7eb2e8f9f7 | 3551 | case cmuOsc_AUXHFRCO: |
<> | 144:ef7eb2e8f9f7 | 3552 | ret = (CMU->AUXHFRCOCTRL & _CMU_AUXHFRCOCTRL_TUNING_MASK) |
<> | 144:ef7eb2e8f9f7 | 3553 | >> _CMU_AUXHFRCOCTRL_TUNING_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 3554 | break; |
<> | 144:ef7eb2e8f9f7 | 3555 | |
<> | 144:ef7eb2e8f9f7 | 3556 | default: |
<> | 144:ef7eb2e8f9f7 | 3557 | EFM_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 3558 | ret = 0; |
<> | 144:ef7eb2e8f9f7 | 3559 | break; |
<> | 144:ef7eb2e8f9f7 | 3560 | } |
<> | 144:ef7eb2e8f9f7 | 3561 | |
<> | 144:ef7eb2e8f9f7 | 3562 | return ret; |
<> | 144:ef7eb2e8f9f7 | 3563 | } |
<> | 144:ef7eb2e8f9f7 | 3564 | |
<> | 144:ef7eb2e8f9f7 | 3565 | |
<> | 144:ef7eb2e8f9f7 | 3566 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 3567 | * @brief |
<> | 144:ef7eb2e8f9f7 | 3568 | * Set the oscillator frequency tuning control. |
<> | 144:ef7eb2e8f9f7 | 3569 | * |
<> | 144:ef7eb2e8f9f7 | 3570 | * @note |
<> | 144:ef7eb2e8f9f7 | 3571 | * Oscillator tuning is done during production, and the tuning value is |
<> | 144:ef7eb2e8f9f7 | 3572 | * automatically loaded after a reset. Changing the tuning value from the |
<> | 144:ef7eb2e8f9f7 | 3573 | * calibrated value is for more advanced use. |
<> | 144:ef7eb2e8f9f7 | 3574 | * |
<> | 144:ef7eb2e8f9f7 | 3575 | * @param[in] osc |
<> | 144:ef7eb2e8f9f7 | 3576 | * Oscillator to set tuning value for, one of: |
<> | 144:ef7eb2e8f9f7 | 3577 | * @li #cmuOsc_LFRCO |
<> | 144:ef7eb2e8f9f7 | 3578 | * @li #cmuOsc_HFRCO |
<> | 144:ef7eb2e8f9f7 | 3579 | * @li #cmuOsc_AUXHFRCO |
<> | 144:ef7eb2e8f9f7 | 3580 | * |
<> | 144:ef7eb2e8f9f7 | 3581 | * @param[in] val |
<> | 144:ef7eb2e8f9f7 | 3582 | * The oscillator frequency tuning setting to use. |
<> | 144:ef7eb2e8f9f7 | 3583 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 3584 | void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val) |
<> | 144:ef7eb2e8f9f7 | 3585 | { |
<> | 144:ef7eb2e8f9f7 | 3586 | switch (osc) |
<> | 144:ef7eb2e8f9f7 | 3587 | { |
<> | 144:ef7eb2e8f9f7 | 3588 | case cmuOsc_LFRCO: |
<> | 144:ef7eb2e8f9f7 | 3589 | EFM_ASSERT(val <= (_CMU_LFRCOCTRL_TUNING_MASK |
<> | 144:ef7eb2e8f9f7 | 3590 | >> _CMU_LFRCOCTRL_TUNING_SHIFT)); |
<> | 144:ef7eb2e8f9f7 | 3591 | val &= (_CMU_LFRCOCTRL_TUNING_MASK >> _CMU_LFRCOCTRL_TUNING_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 3592 | #if defined( _SILICON_LABS_32B_PLATFORM_2 ) |
<> | 144:ef7eb2e8f9f7 | 3593 | while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_LFRCOBSY_SHIFT)); |
<> | 144:ef7eb2e8f9f7 | 3594 | #endif |
<> | 144:ef7eb2e8f9f7 | 3595 | CMU->LFRCOCTRL = (CMU->LFRCOCTRL & ~(_CMU_LFRCOCTRL_TUNING_MASK)) |
<> | 144:ef7eb2e8f9f7 | 3596 | | (val << _CMU_LFRCOCTRL_TUNING_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 3597 | break; |
<> | 144:ef7eb2e8f9f7 | 3598 | |
<> | 144:ef7eb2e8f9f7 | 3599 | case cmuOsc_HFRCO: |
<> | 144:ef7eb2e8f9f7 | 3600 | EFM_ASSERT(val <= (_CMU_HFRCOCTRL_TUNING_MASK |
<> | 144:ef7eb2e8f9f7 | 3601 | >> _CMU_HFRCOCTRL_TUNING_SHIFT)); |
<> | 144:ef7eb2e8f9f7 | 3602 | val &= (_CMU_HFRCOCTRL_TUNING_MASK >> _CMU_HFRCOCTRL_TUNING_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 3603 | #if defined( _SILICON_LABS_32B_PLATFORM_2 ) |
<> | 144:ef7eb2e8f9f7 | 3604 | while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_HFRCOBSY_SHIFT)) |
<> | 144:ef7eb2e8f9f7 | 3605 | { |
<> | 144:ef7eb2e8f9f7 | 3606 | } |
<> | 144:ef7eb2e8f9f7 | 3607 | #endif |
<> | 144:ef7eb2e8f9f7 | 3608 | CMU->HFRCOCTRL = (CMU->HFRCOCTRL & ~(_CMU_HFRCOCTRL_TUNING_MASK)) |
<> | 144:ef7eb2e8f9f7 | 3609 | | (val << _CMU_HFRCOCTRL_TUNING_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 3610 | break; |
<> | 144:ef7eb2e8f9f7 | 3611 | |
<> | 144:ef7eb2e8f9f7 | 3612 | case cmuOsc_AUXHFRCO: |
<> | 144:ef7eb2e8f9f7 | 3613 | EFM_ASSERT(val <= (_CMU_AUXHFRCOCTRL_TUNING_MASK |
<> | 144:ef7eb2e8f9f7 | 3614 | >> _CMU_AUXHFRCOCTRL_TUNING_SHIFT)); |
<> | 144:ef7eb2e8f9f7 | 3615 | val &= (_CMU_AUXHFRCOCTRL_TUNING_MASK >> _CMU_AUXHFRCOCTRL_TUNING_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 3616 | #if defined( _SILICON_LABS_32B_PLATFORM_2 ) |
<> | 144:ef7eb2e8f9f7 | 3617 | while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT)) |
<> | 144:ef7eb2e8f9f7 | 3618 | { |
<> | 144:ef7eb2e8f9f7 | 3619 | } |
<> | 144:ef7eb2e8f9f7 | 3620 | #endif |
<> | 144:ef7eb2e8f9f7 | 3621 | CMU->AUXHFRCOCTRL = (CMU->AUXHFRCOCTRL & ~(_CMU_AUXHFRCOCTRL_TUNING_MASK)) |
<> | 144:ef7eb2e8f9f7 | 3622 | | (val << _CMU_AUXHFRCOCTRL_TUNING_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 3623 | break; |
<> | 144:ef7eb2e8f9f7 | 3624 | |
<> | 144:ef7eb2e8f9f7 | 3625 | default: |
<> | 144:ef7eb2e8f9f7 | 3626 | EFM_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 3627 | break; |
<> | 144:ef7eb2e8f9f7 | 3628 | } |
<> | 144:ef7eb2e8f9f7 | 3629 | } |
<> | 144:ef7eb2e8f9f7 | 3630 | |
<> | 144:ef7eb2e8f9f7 | 3631 | |
<> | 144:ef7eb2e8f9f7 | 3632 | /**************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 3633 | * @brief |
<> | 144:ef7eb2e8f9f7 | 3634 | * Determine if currently selected PCNTn clock used is external or LFBCLK. |
<> | 144:ef7eb2e8f9f7 | 3635 | * |
<> | 144:ef7eb2e8f9f7 | 3636 | * @param[in] instance |
<> | 144:ef7eb2e8f9f7 | 3637 | * PCNT instance number to get currently selected clock source for. |
<> | 144:ef7eb2e8f9f7 | 3638 | * |
<> | 144:ef7eb2e8f9f7 | 3639 | * @return |
<> | 144:ef7eb2e8f9f7 | 3640 | * @li true - selected clock is external clock. |
<> | 144:ef7eb2e8f9f7 | 3641 | * @li false - selected clock is LFBCLK. |
<> | 144:ef7eb2e8f9f7 | 3642 | *****************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 3643 | bool CMU_PCNTClockExternalGet(unsigned int instance) |
<> | 144:ef7eb2e8f9f7 | 3644 | { |
<> | 144:ef7eb2e8f9f7 | 3645 | uint32_t setting; |
<> | 144:ef7eb2e8f9f7 | 3646 | |
<> | 144:ef7eb2e8f9f7 | 3647 | switch (instance) |
<> | 144:ef7eb2e8f9f7 | 3648 | { |
<> | 144:ef7eb2e8f9f7 | 3649 | #if defined( _CMU_PCNTCTRL_PCNT0CLKEN_MASK ) |
<> | 144:ef7eb2e8f9f7 | 3650 | case 0: |
<> | 144:ef7eb2e8f9f7 | 3651 | setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0; |
<> | 144:ef7eb2e8f9f7 | 3652 | break; |
<> | 144:ef7eb2e8f9f7 | 3653 | |
<> | 144:ef7eb2e8f9f7 | 3654 | #if defined( _CMU_PCNTCTRL_PCNT1CLKEN_MASK ) |
<> | 144:ef7eb2e8f9f7 | 3655 | case 1: |
<> | 144:ef7eb2e8f9f7 | 3656 | setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0; |
<> | 144:ef7eb2e8f9f7 | 3657 | break; |
<> | 144:ef7eb2e8f9f7 | 3658 | |
<> | 144:ef7eb2e8f9f7 | 3659 | #if defined( _CMU_PCNTCTRL_PCNT2CLKEN_MASK ) |
<> | 144:ef7eb2e8f9f7 | 3660 | case 2: |
<> | 144:ef7eb2e8f9f7 | 3661 | setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0; |
<> | 144:ef7eb2e8f9f7 | 3662 | break; |
<> | 144:ef7eb2e8f9f7 | 3663 | #endif |
<> | 144:ef7eb2e8f9f7 | 3664 | #endif |
<> | 144:ef7eb2e8f9f7 | 3665 | #endif |
<> | 144:ef7eb2e8f9f7 | 3666 | |
<> | 144:ef7eb2e8f9f7 | 3667 | default: |
<> | 144:ef7eb2e8f9f7 | 3668 | setting = 0; |
<> | 144:ef7eb2e8f9f7 | 3669 | break; |
<> | 144:ef7eb2e8f9f7 | 3670 | } |
<> | 144:ef7eb2e8f9f7 | 3671 | return (setting ? true : false); |
<> | 144:ef7eb2e8f9f7 | 3672 | } |
<> | 144:ef7eb2e8f9f7 | 3673 | |
<> | 144:ef7eb2e8f9f7 | 3674 | |
<> | 144:ef7eb2e8f9f7 | 3675 | /**************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 3676 | * @brief |
<> | 144:ef7eb2e8f9f7 | 3677 | * Select PCNTn clock. |
<> | 144:ef7eb2e8f9f7 | 3678 | * |
<> | 144:ef7eb2e8f9f7 | 3679 | * @param[in] instance |
<> | 144:ef7eb2e8f9f7 | 3680 | * PCNT instance number to set selected clock source for. |
<> | 144:ef7eb2e8f9f7 | 3681 | * |
<> | 144:ef7eb2e8f9f7 | 3682 | * @param[in] external |
<> | 144:ef7eb2e8f9f7 | 3683 | * Set to true to select external clock, false to select LFBCLK. |
<> | 144:ef7eb2e8f9f7 | 3684 | *****************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 3685 | void CMU_PCNTClockExternalSet(unsigned int instance, bool external) |
<> | 144:ef7eb2e8f9f7 | 3686 | { |
<> | 144:ef7eb2e8f9f7 | 3687 | #if defined( PCNT_PRESENT ) |
<> | 144:ef7eb2e8f9f7 | 3688 | uint32_t setting = 0; |
<> | 144:ef7eb2e8f9f7 | 3689 | |
<> | 144:ef7eb2e8f9f7 | 3690 | EFM_ASSERT(instance < PCNT_COUNT); |
<> | 144:ef7eb2e8f9f7 | 3691 | |
<> | 144:ef7eb2e8f9f7 | 3692 | if (external) |
<> | 144:ef7eb2e8f9f7 | 3693 | { |
<> | 144:ef7eb2e8f9f7 | 3694 | setting = 1; |
<> | 144:ef7eb2e8f9f7 | 3695 | } |
<> | 144:ef7eb2e8f9f7 | 3696 | |
<> | 144:ef7eb2e8f9f7 | 3697 | BUS_RegBitWrite(&(CMU->PCNTCTRL), (instance * 2) + 1, setting); |
<> | 144:ef7eb2e8f9f7 | 3698 | |
<> | 144:ef7eb2e8f9f7 | 3699 | #else |
<> | 144:ef7eb2e8f9f7 | 3700 | (void)instance; /* Unused parameter */ |
<> | 144:ef7eb2e8f9f7 | 3701 | (void)external; /* Unused parameter */ |
<> | 144:ef7eb2e8f9f7 | 3702 | #endif |
<> | 144:ef7eb2e8f9f7 | 3703 | } |
<> | 144:ef7eb2e8f9f7 | 3704 | |
<> | 144:ef7eb2e8f9f7 | 3705 | |
<> | 144:ef7eb2e8f9f7 | 3706 | #if defined( _CMU_USHFRCOCONF_BAND_MASK ) |
<> | 144:ef7eb2e8f9f7 | 3707 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 3708 | * @brief |
<> | 144:ef7eb2e8f9f7 | 3709 | * Get USHFRCO band in use. |
<> | 144:ef7eb2e8f9f7 | 3710 | * |
<> | 144:ef7eb2e8f9f7 | 3711 | * @return |
<> | 144:ef7eb2e8f9f7 | 3712 | * USHFRCO band in use. |
<> | 144:ef7eb2e8f9f7 | 3713 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 3714 | CMU_USHFRCOBand_TypeDef CMU_USHFRCOBandGet(void) |
<> | 144:ef7eb2e8f9f7 | 3715 | { |
<> | 144:ef7eb2e8f9f7 | 3716 | return (CMU_USHFRCOBand_TypeDef)((CMU->USHFRCOCONF |
<> | 144:ef7eb2e8f9f7 | 3717 | & _CMU_USHFRCOCONF_BAND_MASK) |
<> | 144:ef7eb2e8f9f7 | 3718 | >> _CMU_USHFRCOCONF_BAND_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 3719 | } |
<> | 144:ef7eb2e8f9f7 | 3720 | #endif |
<> | 144:ef7eb2e8f9f7 | 3721 | |
<> | 144:ef7eb2e8f9f7 | 3722 | #if defined( _CMU_USHFRCOCONF_BAND_MASK ) |
<> | 144:ef7eb2e8f9f7 | 3723 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 3724 | * @brief |
<> | 144:ef7eb2e8f9f7 | 3725 | * Set USHFRCO band to use. |
<> | 144:ef7eb2e8f9f7 | 3726 | * |
<> | 144:ef7eb2e8f9f7 | 3727 | * @param[in] band |
<> | 144:ef7eb2e8f9f7 | 3728 | * USHFRCO band to activate. |
<> | 144:ef7eb2e8f9f7 | 3729 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 3730 | void CMU_USHFRCOBandSet(CMU_USHFRCOBand_TypeDef band) |
<> | 144:ef7eb2e8f9f7 | 3731 | { |
<> | 144:ef7eb2e8f9f7 | 3732 | uint32_t tuning; |
<> | 144:ef7eb2e8f9f7 | 3733 | uint32_t fineTuning; |
<> | 144:ef7eb2e8f9f7 | 3734 | CMU_Select_TypeDef osc; |
<> | 144:ef7eb2e8f9f7 | 3735 | |
<> | 144:ef7eb2e8f9f7 | 3736 | /* Cannot switch band if USHFRCO is already selected as HF clock. */ |
<> | 144:ef7eb2e8f9f7 | 3737 | osc = CMU_ClockSelectGet(cmuClock_HF); |
<> | 144:ef7eb2e8f9f7 | 3738 | EFM_ASSERT((CMU_USHFRCOBandGet() != band) && (osc != cmuSelect_USHFRCO)); |
<> | 144:ef7eb2e8f9f7 | 3739 | |
<> | 144:ef7eb2e8f9f7 | 3740 | /* Read tuning value from calibration table */ |
<> | 144:ef7eb2e8f9f7 | 3741 | switch (band) |
<> | 144:ef7eb2e8f9f7 | 3742 | { |
<> | 144:ef7eb2e8f9f7 | 3743 | case cmuUSHFRCOBand_24MHz: |
<> | 144:ef7eb2e8f9f7 | 3744 | tuning = (DEVINFO->USHFRCOCAL0 & _DEVINFO_USHFRCOCAL0_BAND24_TUNING_MASK) |
<> | 144:ef7eb2e8f9f7 | 3745 | >> _DEVINFO_USHFRCOCAL0_BAND24_TUNING_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 3746 | fineTuning = (DEVINFO->USHFRCOCAL0 |
<> | 144:ef7eb2e8f9f7 | 3747 | & _DEVINFO_USHFRCOCAL0_BAND24_FINETUNING_MASK) |
<> | 144:ef7eb2e8f9f7 | 3748 | >> _DEVINFO_USHFRCOCAL0_BAND24_FINETUNING_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 3749 | break; |
<> | 144:ef7eb2e8f9f7 | 3750 | |
<> | 144:ef7eb2e8f9f7 | 3751 | case cmuUSHFRCOBand_48MHz: |
<> | 144:ef7eb2e8f9f7 | 3752 | tuning = (DEVINFO->USHFRCOCAL0 & _DEVINFO_USHFRCOCAL0_BAND48_TUNING_MASK) |
<> | 144:ef7eb2e8f9f7 | 3753 | >> _DEVINFO_USHFRCOCAL0_BAND48_TUNING_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 3754 | fineTuning = (DEVINFO->USHFRCOCAL0 |
<> | 144:ef7eb2e8f9f7 | 3755 | & _DEVINFO_USHFRCOCAL0_BAND48_FINETUNING_MASK) |
<> | 144:ef7eb2e8f9f7 | 3756 | >> _DEVINFO_USHFRCOCAL0_BAND48_FINETUNING_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 3757 | /* Enable the clock divider before switching the band from 24 to 48MHz */ |
<> | 144:ef7eb2e8f9f7 | 3758 | BUS_RegBitWrite(&CMU->USHFRCOCONF, _CMU_USHFRCOCONF_USHFRCODIV2DIS_SHIFT, 0); |
<> | 144:ef7eb2e8f9f7 | 3759 | break; |
<> | 144:ef7eb2e8f9f7 | 3760 | |
<> | 144:ef7eb2e8f9f7 | 3761 | default: |
<> | 144:ef7eb2e8f9f7 | 3762 | EFM_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 3763 | return; |
<> | 144:ef7eb2e8f9f7 | 3764 | } |
<> | 144:ef7eb2e8f9f7 | 3765 | |
<> | 144:ef7eb2e8f9f7 | 3766 | /* Set band and tuning */ |
<> | 144:ef7eb2e8f9f7 | 3767 | CMU->USHFRCOCONF = (CMU->USHFRCOCONF & ~_CMU_USHFRCOCONF_BAND_MASK) |
<> | 144:ef7eb2e8f9f7 | 3768 | | (band << _CMU_USHFRCOCONF_BAND_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 3769 | CMU->USHFRCOCTRL = (CMU->USHFRCOCTRL & ~_CMU_USHFRCOCTRL_TUNING_MASK) |
<> | 144:ef7eb2e8f9f7 | 3770 | | (tuning << _CMU_USHFRCOCTRL_TUNING_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 3771 | CMU->USHFRCOTUNE = (CMU->USHFRCOTUNE & ~_CMU_USHFRCOTUNE_FINETUNING_MASK) |
<> | 144:ef7eb2e8f9f7 | 3772 | | (fineTuning << _CMU_USHFRCOTUNE_FINETUNING_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 3773 | |
<> | 144:ef7eb2e8f9f7 | 3774 | /* Disable the clock divider after switching the band from 48 to 24MHz */ |
<> | 144:ef7eb2e8f9f7 | 3775 | if (band == cmuUSHFRCOBand_24MHz) |
<> | 144:ef7eb2e8f9f7 | 3776 | { |
<> | 144:ef7eb2e8f9f7 | 3777 | BUS_RegBitWrite(&CMU->USHFRCOCONF, _CMU_USHFRCOCONF_USHFRCODIV2DIS_SHIFT, 1); |
<> | 144:ef7eb2e8f9f7 | 3778 | } |
<> | 144:ef7eb2e8f9f7 | 3779 | } |
<> | 144:ef7eb2e8f9f7 | 3780 | #endif |
<> | 144:ef7eb2e8f9f7 | 3781 | |
<> | 144:ef7eb2e8f9f7 | 3782 | |
<> | 144:ef7eb2e8f9f7 | 3783 | |
<> | 144:ef7eb2e8f9f7 | 3784 | /** @} (end addtogroup CMU) */ |
<> | 144:ef7eb2e8f9f7 | 3785 | /** @} (end addtogroup EM_Library) */ |
<> | 144:ef7eb2e8f9f7 | 3786 | #endif /* __EM_CMU_H */ |