added prescaler for 16 bit pwm in LPC1347 target
Fork of mbed-dev by
targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_MCU_K64F/serial_api.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)
- Committer:
- <>
- Date:
- Fri Sep 02 15:07:44 2016 +0100
- Revision:
- 144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /* mbed Microcontroller Library |
<> | 144:ef7eb2e8f9f7 | 2 | * Copyright (c) 2006-2013 ARM Limited |
<> | 144:ef7eb2e8f9f7 | 3 | * |
<> | 144:ef7eb2e8f9f7 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
<> | 144:ef7eb2e8f9f7 | 5 | * you may not use this file except in compliance with the License. |
<> | 144:ef7eb2e8f9f7 | 6 | * You may obtain a copy of the License at |
<> | 144:ef7eb2e8f9f7 | 7 | * |
<> | 144:ef7eb2e8f9f7 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
<> | 144:ef7eb2e8f9f7 | 9 | * |
<> | 144:ef7eb2e8f9f7 | 10 | * Unless required by applicable law or agreed to in writing, software |
<> | 144:ef7eb2e8f9f7 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
<> | 144:ef7eb2e8f9f7 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
<> | 144:ef7eb2e8f9f7 | 13 | * See the License for the specific language governing permissions and |
<> | 144:ef7eb2e8f9f7 | 14 | * limitations under the License. |
<> | 144:ef7eb2e8f9f7 | 15 | */ |
<> | 144:ef7eb2e8f9f7 | 16 | #include "serial_api.h" |
<> | 144:ef7eb2e8f9f7 | 17 | |
<> | 144:ef7eb2e8f9f7 | 18 | #if DEVICE_SERIAL |
<> | 144:ef7eb2e8f9f7 | 19 | |
<> | 144:ef7eb2e8f9f7 | 20 | // math.h required for floating point operations for baud rate calculation |
<> | 144:ef7eb2e8f9f7 | 21 | #include <math.h> |
<> | 144:ef7eb2e8f9f7 | 22 | #include "mbed_assert.h" |
<> | 144:ef7eb2e8f9f7 | 23 | |
<> | 144:ef7eb2e8f9f7 | 24 | #include <string.h> |
<> | 144:ef7eb2e8f9f7 | 25 | |
<> | 144:ef7eb2e8f9f7 | 26 | #include "cmsis.h" |
<> | 144:ef7eb2e8f9f7 | 27 | #include "pinmap.h" |
<> | 144:ef7eb2e8f9f7 | 28 | #include "fsl_uart.h" |
<> | 144:ef7eb2e8f9f7 | 29 | #include "peripheral_clock_defines.h" |
<> | 144:ef7eb2e8f9f7 | 30 | #include "PeripheralPins.h" |
<> | 144:ef7eb2e8f9f7 | 31 | #include "fsl_clock_config.h" |
<> | 144:ef7eb2e8f9f7 | 32 | |
<> | 144:ef7eb2e8f9f7 | 33 | static uint32_t serial_irq_ids[FSL_FEATURE_SOC_UART_COUNT] = {0}; |
<> | 144:ef7eb2e8f9f7 | 34 | static uart_irq_handler irq_handler; |
<> | 144:ef7eb2e8f9f7 | 35 | /* Array of UART peripheral base address. */ |
<> | 144:ef7eb2e8f9f7 | 36 | static UART_Type *const uart_addrs[] = UART_BASE_PTRS; |
<> | 144:ef7eb2e8f9f7 | 37 | /* Array of UART bus clock frequencies */ |
<> | 144:ef7eb2e8f9f7 | 38 | static clock_name_t const uart_clocks[] = UART_CLOCK_FREQS; |
<> | 144:ef7eb2e8f9f7 | 39 | |
<> | 144:ef7eb2e8f9f7 | 40 | |
<> | 144:ef7eb2e8f9f7 | 41 | int stdio_uart_inited = 0; |
<> | 144:ef7eb2e8f9f7 | 42 | serial_t stdio_uart; |
<> | 144:ef7eb2e8f9f7 | 43 | |
<> | 144:ef7eb2e8f9f7 | 44 | void serial_init(serial_t *obj, PinName tx, PinName rx) { |
<> | 144:ef7eb2e8f9f7 | 45 | uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX); |
<> | 144:ef7eb2e8f9f7 | 46 | uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX); |
<> | 144:ef7eb2e8f9f7 | 47 | obj->index = pinmap_merge(uart_tx, uart_rx); |
<> | 144:ef7eb2e8f9f7 | 48 | MBED_ASSERT((int)obj->index != NC); |
<> | 144:ef7eb2e8f9f7 | 49 | |
<> | 144:ef7eb2e8f9f7 | 50 | // Need to initialize the clocks here as ticker init gets called before mbed_sdk_init |
<> | 144:ef7eb2e8f9f7 | 51 | if (SystemCoreClock == DEFAULT_SYSTEM_CLOCK) |
<> | 144:ef7eb2e8f9f7 | 52 | BOARD_BootClockRUN(); |
<> | 144:ef7eb2e8f9f7 | 53 | |
<> | 144:ef7eb2e8f9f7 | 54 | uart_config_t config; |
<> | 144:ef7eb2e8f9f7 | 55 | |
<> | 144:ef7eb2e8f9f7 | 56 | UART_GetDefaultConfig(&config); |
<> | 144:ef7eb2e8f9f7 | 57 | config.baudRate_Bps = 9600; |
<> | 144:ef7eb2e8f9f7 | 58 | config.enableTx = false; |
<> | 144:ef7eb2e8f9f7 | 59 | config.enableRx = false; |
<> | 144:ef7eb2e8f9f7 | 60 | |
<> | 144:ef7eb2e8f9f7 | 61 | UART_Init(uart_addrs[obj->index], &config, CLOCK_GetFreq(uart_clocks[obj->index])); |
<> | 144:ef7eb2e8f9f7 | 62 | |
<> | 144:ef7eb2e8f9f7 | 63 | pinmap_pinout(tx, PinMap_UART_TX); |
<> | 144:ef7eb2e8f9f7 | 64 | pinmap_pinout(rx, PinMap_UART_RX); |
<> | 144:ef7eb2e8f9f7 | 65 | |
<> | 144:ef7eb2e8f9f7 | 66 | if (tx != NC) { |
<> | 144:ef7eb2e8f9f7 | 67 | UART_EnableTx(uart_addrs[obj->index], true); |
<> | 144:ef7eb2e8f9f7 | 68 | pin_mode(tx, PullUp); |
<> | 144:ef7eb2e8f9f7 | 69 | } |
<> | 144:ef7eb2e8f9f7 | 70 | if (rx != NC) { |
<> | 144:ef7eb2e8f9f7 | 71 | UART_EnableRx(uart_addrs[obj->index], true); |
<> | 144:ef7eb2e8f9f7 | 72 | pin_mode(rx, PullUp); |
<> | 144:ef7eb2e8f9f7 | 73 | } |
<> | 144:ef7eb2e8f9f7 | 74 | |
<> | 144:ef7eb2e8f9f7 | 75 | if (obj->index == STDIO_UART) { |
<> | 144:ef7eb2e8f9f7 | 76 | stdio_uart_inited = 1; |
<> | 144:ef7eb2e8f9f7 | 77 | memcpy(&stdio_uart, obj, sizeof(serial_t)); |
<> | 144:ef7eb2e8f9f7 | 78 | } |
<> | 144:ef7eb2e8f9f7 | 79 | } |
<> | 144:ef7eb2e8f9f7 | 80 | |
<> | 144:ef7eb2e8f9f7 | 81 | void serial_free(serial_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 82 | UART_Deinit(uart_addrs[obj->index]); |
<> | 144:ef7eb2e8f9f7 | 83 | serial_irq_ids[obj->index] = 0; |
<> | 144:ef7eb2e8f9f7 | 84 | } |
<> | 144:ef7eb2e8f9f7 | 85 | |
<> | 144:ef7eb2e8f9f7 | 86 | void serial_baud(serial_t *obj, int baudrate) { |
<> | 144:ef7eb2e8f9f7 | 87 | UART_SetBaudRate(uart_addrs[obj->index], (uint32_t)baudrate, CLOCK_GetFreq(uart_clocks[obj->index])); |
<> | 144:ef7eb2e8f9f7 | 88 | } |
<> | 144:ef7eb2e8f9f7 | 89 | |
<> | 144:ef7eb2e8f9f7 | 90 | void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) { |
<> | 144:ef7eb2e8f9f7 | 91 | UART_Type *base = uart_addrs[obj->index]; |
<> | 144:ef7eb2e8f9f7 | 92 | uint8_t temp; |
<> | 144:ef7eb2e8f9f7 | 93 | /* Set bit count and parity mode. */ |
<> | 144:ef7eb2e8f9f7 | 94 | temp = base->C1 & ~(UART_C1_PE_MASK | UART_C1_PT_MASK | UART_C1_M_MASK); |
<> | 144:ef7eb2e8f9f7 | 95 | if (parity != ParityNone) |
<> | 144:ef7eb2e8f9f7 | 96 | { |
<> | 144:ef7eb2e8f9f7 | 97 | /* Enable Parity */ |
<> | 144:ef7eb2e8f9f7 | 98 | temp |= (UART_C1_PE_MASK | UART_C1_M_MASK); |
<> | 144:ef7eb2e8f9f7 | 99 | if (parity == ParityOdd) { |
<> | 144:ef7eb2e8f9f7 | 100 | temp |= UART_C1_PT_MASK; |
<> | 144:ef7eb2e8f9f7 | 101 | } else if (parity == ParityEven) { |
<> | 144:ef7eb2e8f9f7 | 102 | // PT=0 so nothing more to do |
<> | 144:ef7eb2e8f9f7 | 103 | } else { |
<> | 144:ef7eb2e8f9f7 | 104 | // Hardware does not support forced parity |
<> | 144:ef7eb2e8f9f7 | 105 | MBED_ASSERT(0); |
<> | 144:ef7eb2e8f9f7 | 106 | } |
<> | 144:ef7eb2e8f9f7 | 107 | } |
<> | 144:ef7eb2e8f9f7 | 108 | base->C1 = temp; |
<> | 144:ef7eb2e8f9f7 | 109 | #if defined(FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT |
<> | 144:ef7eb2e8f9f7 | 110 | /* Set stop bit per char */ |
<> | 144:ef7eb2e8f9f7 | 111 | base->BDH = (base->BDH & ~UART_BDH_SBNS_MASK) | UART_BDH_SBNS((uint8_t)--stop_bits); |
<> | 144:ef7eb2e8f9f7 | 112 | #endif |
<> | 144:ef7eb2e8f9f7 | 113 | } |
<> | 144:ef7eb2e8f9f7 | 114 | |
<> | 144:ef7eb2e8f9f7 | 115 | /****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 116 | * INTERRUPTS HANDLING |
<> | 144:ef7eb2e8f9f7 | 117 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 118 | static inline void uart_irq(uint32_t transmit_empty, uint32_t receive_full, uint32_t index) { |
<> | 144:ef7eb2e8f9f7 | 119 | UART_Type *base = uart_addrs[index]; |
<> | 144:ef7eb2e8f9f7 | 120 | |
<> | 144:ef7eb2e8f9f7 | 121 | /* If RX overrun. */ |
<> | 144:ef7eb2e8f9f7 | 122 | if (UART_S1_OR_MASK & base->S1) |
<> | 144:ef7eb2e8f9f7 | 123 | { |
<> | 144:ef7eb2e8f9f7 | 124 | /* Read base->D, otherwise the RX does not work. */ |
<> | 144:ef7eb2e8f9f7 | 125 | (void)base->D; |
<> | 144:ef7eb2e8f9f7 | 126 | } |
<> | 144:ef7eb2e8f9f7 | 127 | |
<> | 144:ef7eb2e8f9f7 | 128 | if (serial_irq_ids[index] != 0) { |
<> | 144:ef7eb2e8f9f7 | 129 | if (transmit_empty) |
<> | 144:ef7eb2e8f9f7 | 130 | irq_handler(serial_irq_ids[index], TxIrq); |
<> | 144:ef7eb2e8f9f7 | 131 | |
<> | 144:ef7eb2e8f9f7 | 132 | if (receive_full) |
<> | 144:ef7eb2e8f9f7 | 133 | irq_handler(serial_irq_ids[index], RxIrq); |
<> | 144:ef7eb2e8f9f7 | 134 | } |
<> | 144:ef7eb2e8f9f7 | 135 | } |
<> | 144:ef7eb2e8f9f7 | 136 | |
<> | 144:ef7eb2e8f9f7 | 137 | void uart0_irq() { |
<> | 144:ef7eb2e8f9f7 | 138 | uint32_t status_flags = UART0->S1; |
<> | 144:ef7eb2e8f9f7 | 139 | uart_irq((status_flags & kUART_TxDataRegEmptyFlag), (status_flags & kUART_RxDataRegFullFlag), 0); |
<> | 144:ef7eb2e8f9f7 | 140 | } |
<> | 144:ef7eb2e8f9f7 | 141 | |
<> | 144:ef7eb2e8f9f7 | 142 | void uart1_irq() { |
<> | 144:ef7eb2e8f9f7 | 143 | uint32_t status_flags = UART1->S1; |
<> | 144:ef7eb2e8f9f7 | 144 | uart_irq((status_flags & UART_S1_TDRE_MASK), (status_flags & UART_S1_RDRF_MASK), 1); |
<> | 144:ef7eb2e8f9f7 | 145 | } |
<> | 144:ef7eb2e8f9f7 | 146 | |
<> | 144:ef7eb2e8f9f7 | 147 | void uart2_irq() { |
<> | 144:ef7eb2e8f9f7 | 148 | uint32_t status_flags = UART2->S1; |
<> | 144:ef7eb2e8f9f7 | 149 | uart_irq((status_flags & UART_S1_TDRE_MASK), (status_flags & UART_S1_RDRF_MASK), 2); |
<> | 144:ef7eb2e8f9f7 | 150 | } |
<> | 144:ef7eb2e8f9f7 | 151 | |
<> | 144:ef7eb2e8f9f7 | 152 | void uart3_irq() { |
<> | 144:ef7eb2e8f9f7 | 153 | uint32_t status_flags = UART3->S1; |
<> | 144:ef7eb2e8f9f7 | 154 | uart_irq((status_flags & UART_S1_TDRE_MASK), (status_flags & UART_S1_RDRF_MASK), 3); |
<> | 144:ef7eb2e8f9f7 | 155 | } |
<> | 144:ef7eb2e8f9f7 | 156 | |
<> | 144:ef7eb2e8f9f7 | 157 | void uart4_irq() { |
<> | 144:ef7eb2e8f9f7 | 158 | uint32_t status_flags = UART4->S1; |
<> | 144:ef7eb2e8f9f7 | 159 | uart_irq((status_flags & UART_S1_TDRE_MASK), (status_flags & UART_S1_RDRF_MASK), 4); |
<> | 144:ef7eb2e8f9f7 | 160 | } |
<> | 144:ef7eb2e8f9f7 | 161 | |
<> | 144:ef7eb2e8f9f7 | 162 | void uart5_irq() { |
<> | 144:ef7eb2e8f9f7 | 163 | uint32_t status_flags = UART5->S1; |
<> | 144:ef7eb2e8f9f7 | 164 | uart_irq((status_flags & UART_S1_TDRE_MASK), (status_flags & UART_S1_RDRF_MASK), 5); |
<> | 144:ef7eb2e8f9f7 | 165 | } |
<> | 144:ef7eb2e8f9f7 | 166 | |
<> | 144:ef7eb2e8f9f7 | 167 | void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { |
<> | 144:ef7eb2e8f9f7 | 168 | irq_handler = handler; |
<> | 144:ef7eb2e8f9f7 | 169 | serial_irq_ids[obj->index] = id; |
<> | 144:ef7eb2e8f9f7 | 170 | } |
<> | 144:ef7eb2e8f9f7 | 171 | |
<> | 144:ef7eb2e8f9f7 | 172 | void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { |
<> | 144:ef7eb2e8f9f7 | 173 | IRQn_Type uart_irqs[] = UART_RX_TX_IRQS; |
<> | 144:ef7eb2e8f9f7 | 174 | uint32_t vector = 0; |
<> | 144:ef7eb2e8f9f7 | 175 | |
<> | 144:ef7eb2e8f9f7 | 176 | switch (obj->index) { |
<> | 144:ef7eb2e8f9f7 | 177 | case 0: |
<> | 144:ef7eb2e8f9f7 | 178 | vector = (uint32_t)&uart0_irq; |
<> | 144:ef7eb2e8f9f7 | 179 | break; |
<> | 144:ef7eb2e8f9f7 | 180 | case 1: |
<> | 144:ef7eb2e8f9f7 | 181 | vector = (uint32_t)&uart1_irq; |
<> | 144:ef7eb2e8f9f7 | 182 | break; |
<> | 144:ef7eb2e8f9f7 | 183 | case 2: |
<> | 144:ef7eb2e8f9f7 | 184 | vector = (uint32_t)&uart2_irq; |
<> | 144:ef7eb2e8f9f7 | 185 | break; |
<> | 144:ef7eb2e8f9f7 | 186 | case 3: |
<> | 144:ef7eb2e8f9f7 | 187 | vector = (uint32_t)&uart3_irq; |
<> | 144:ef7eb2e8f9f7 | 188 | break; |
<> | 144:ef7eb2e8f9f7 | 189 | case 4: |
<> | 144:ef7eb2e8f9f7 | 190 | vector = (uint32_t)&uart4_irq; |
<> | 144:ef7eb2e8f9f7 | 191 | break; |
<> | 144:ef7eb2e8f9f7 | 192 | case 5: |
<> | 144:ef7eb2e8f9f7 | 193 | vector = (uint32_t)&uart5_irq; |
<> | 144:ef7eb2e8f9f7 | 194 | break; |
<> | 144:ef7eb2e8f9f7 | 195 | default: |
<> | 144:ef7eb2e8f9f7 | 196 | break; |
<> | 144:ef7eb2e8f9f7 | 197 | } |
<> | 144:ef7eb2e8f9f7 | 198 | |
<> | 144:ef7eb2e8f9f7 | 199 | if (enable) { |
<> | 144:ef7eb2e8f9f7 | 200 | switch (irq) { |
<> | 144:ef7eb2e8f9f7 | 201 | case RxIrq: |
<> | 144:ef7eb2e8f9f7 | 202 | UART_EnableInterrupts(uart_addrs[obj->index], kUART_RxDataRegFullInterruptEnable); |
<> | 144:ef7eb2e8f9f7 | 203 | break; |
<> | 144:ef7eb2e8f9f7 | 204 | case TxIrq: |
<> | 144:ef7eb2e8f9f7 | 205 | UART_EnableInterrupts(uart_addrs[obj->index], kUART_TxDataRegEmptyInterruptEnable); |
<> | 144:ef7eb2e8f9f7 | 206 | break; |
<> | 144:ef7eb2e8f9f7 | 207 | default: |
<> | 144:ef7eb2e8f9f7 | 208 | break; |
<> | 144:ef7eb2e8f9f7 | 209 | } |
<> | 144:ef7eb2e8f9f7 | 210 | NVIC_SetVector(uart_irqs[obj->index], vector); |
<> | 144:ef7eb2e8f9f7 | 211 | NVIC_EnableIRQ(uart_irqs[obj->index]); |
<> | 144:ef7eb2e8f9f7 | 212 | |
<> | 144:ef7eb2e8f9f7 | 213 | } else { // disable |
<> | 144:ef7eb2e8f9f7 | 214 | int all_disabled = 0; |
<> | 144:ef7eb2e8f9f7 | 215 | SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq); |
<> | 144:ef7eb2e8f9f7 | 216 | switch (irq) { |
<> | 144:ef7eb2e8f9f7 | 217 | case RxIrq: |
<> | 144:ef7eb2e8f9f7 | 218 | UART_DisableInterrupts(uart_addrs[obj->index], kUART_RxDataRegFullInterruptEnable); |
<> | 144:ef7eb2e8f9f7 | 219 | break; |
<> | 144:ef7eb2e8f9f7 | 220 | case TxIrq: |
<> | 144:ef7eb2e8f9f7 | 221 | UART_DisableInterrupts(uart_addrs[obj->index], kUART_TxDataRegEmptyInterruptEnable); |
<> | 144:ef7eb2e8f9f7 | 222 | break; |
<> | 144:ef7eb2e8f9f7 | 223 | default: |
<> | 144:ef7eb2e8f9f7 | 224 | break; |
<> | 144:ef7eb2e8f9f7 | 225 | } |
<> | 144:ef7eb2e8f9f7 | 226 | switch (other_irq) { |
<> | 144:ef7eb2e8f9f7 | 227 | case RxIrq: |
<> | 144:ef7eb2e8f9f7 | 228 | all_disabled = ((UART_GetEnabledInterrupts(uart_addrs[obj->index]) & kUART_RxDataRegFullInterruptEnable) == 0); |
<> | 144:ef7eb2e8f9f7 | 229 | break; |
<> | 144:ef7eb2e8f9f7 | 230 | case TxIrq: |
<> | 144:ef7eb2e8f9f7 | 231 | all_disabled = ((UART_GetEnabledInterrupts(uart_addrs[obj->index]) & kUART_TxDataRegEmptyInterruptEnable) == 0); |
<> | 144:ef7eb2e8f9f7 | 232 | break; |
<> | 144:ef7eb2e8f9f7 | 233 | default: |
<> | 144:ef7eb2e8f9f7 | 234 | break; |
<> | 144:ef7eb2e8f9f7 | 235 | } |
<> | 144:ef7eb2e8f9f7 | 236 | if (all_disabled) |
<> | 144:ef7eb2e8f9f7 | 237 | NVIC_DisableIRQ(uart_irqs[obj->index]); |
<> | 144:ef7eb2e8f9f7 | 238 | } |
<> | 144:ef7eb2e8f9f7 | 239 | } |
<> | 144:ef7eb2e8f9f7 | 240 | |
<> | 144:ef7eb2e8f9f7 | 241 | int serial_getc(serial_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 242 | while (!serial_readable(obj)); |
<> | 144:ef7eb2e8f9f7 | 243 | uint8_t data; |
<> | 144:ef7eb2e8f9f7 | 244 | data = UART_ReadByte(uart_addrs[obj->index]); |
<> | 144:ef7eb2e8f9f7 | 245 | |
<> | 144:ef7eb2e8f9f7 | 246 | return data; |
<> | 144:ef7eb2e8f9f7 | 247 | } |
<> | 144:ef7eb2e8f9f7 | 248 | |
<> | 144:ef7eb2e8f9f7 | 249 | void serial_putc(serial_t *obj, int c) { |
<> | 144:ef7eb2e8f9f7 | 250 | while (!serial_writable(obj)); |
<> | 144:ef7eb2e8f9f7 | 251 | UART_WriteByte(uart_addrs[obj->index], (uint8_t)c); |
<> | 144:ef7eb2e8f9f7 | 252 | } |
<> | 144:ef7eb2e8f9f7 | 253 | |
<> | 144:ef7eb2e8f9f7 | 254 | int serial_readable(serial_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 255 | uint32_t status_flags = UART_GetStatusFlags(uart_addrs[obj->index]); |
<> | 144:ef7eb2e8f9f7 | 256 | if (status_flags & kUART_RxOverrunFlag) |
<> | 144:ef7eb2e8f9f7 | 257 | UART_ClearStatusFlags(uart_addrs[obj->index], kUART_RxOverrunFlag); |
<> | 144:ef7eb2e8f9f7 | 258 | return (status_flags & kUART_RxDataRegFullFlag); |
<> | 144:ef7eb2e8f9f7 | 259 | } |
<> | 144:ef7eb2e8f9f7 | 260 | |
<> | 144:ef7eb2e8f9f7 | 261 | int serial_writable(serial_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 262 | uint32_t status_flags = UART_GetStatusFlags(uart_addrs[obj->index]); |
<> | 144:ef7eb2e8f9f7 | 263 | if (status_flags & kUART_RxOverrunFlag) |
<> | 144:ef7eb2e8f9f7 | 264 | UART_ClearStatusFlags(uart_addrs[obj->index], kUART_RxOverrunFlag); |
<> | 144:ef7eb2e8f9f7 | 265 | return (status_flags & kUART_TxDataRegEmptyFlag); |
<> | 144:ef7eb2e8f9f7 | 266 | } |
<> | 144:ef7eb2e8f9f7 | 267 | |
<> | 144:ef7eb2e8f9f7 | 268 | void serial_clear(serial_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 269 | } |
<> | 144:ef7eb2e8f9f7 | 270 | |
<> | 144:ef7eb2e8f9f7 | 271 | void serial_pinout_tx(PinName tx) { |
<> | 144:ef7eb2e8f9f7 | 272 | pinmap_pinout(tx, PinMap_UART_TX); |
<> | 144:ef7eb2e8f9f7 | 273 | } |
<> | 144:ef7eb2e8f9f7 | 274 | |
<> | 144:ef7eb2e8f9f7 | 275 | void serial_break_set(serial_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 276 | uart_addrs[obj->index]->C2 |= UART_C2_SBK_MASK; |
<> | 144:ef7eb2e8f9f7 | 277 | } |
<> | 144:ef7eb2e8f9f7 | 278 | |
<> | 144:ef7eb2e8f9f7 | 279 | void serial_break_clear(serial_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 280 | uart_addrs[obj->index]->C2 &= ~UART_C2_SBK_MASK; |
<> | 144:ef7eb2e8f9f7 | 281 | } |
<> | 144:ef7eb2e8f9f7 | 282 | |
<> | 144:ef7eb2e8f9f7 | 283 | #if DEVICE_SERIAL_FC |
<> | 144:ef7eb2e8f9f7 | 284 | |
<> | 144:ef7eb2e8f9f7 | 285 | /* |
<> | 144:ef7eb2e8f9f7 | 286 | * Only hardware flow control is implemented in this API. |
<> | 144:ef7eb2e8f9f7 | 287 | */ |
<> | 144:ef7eb2e8f9f7 | 288 | void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) |
<> | 144:ef7eb2e8f9f7 | 289 | { |
<> | 144:ef7eb2e8f9f7 | 290 | switch(type) { |
<> | 144:ef7eb2e8f9f7 | 291 | case FlowControlRTS: |
<> | 144:ef7eb2e8f9f7 | 292 | pinmap_pinout(rxflow, PinMap_UART_RTS); |
<> | 144:ef7eb2e8f9f7 | 293 | uart_addrs[obj->index]->MODEM &= ~UART_MODEM_TXCTSE_MASK; |
<> | 144:ef7eb2e8f9f7 | 294 | uart_addrs[obj->index]->MODEM |= UART_MODEM_RXRTSE_MASK; |
<> | 144:ef7eb2e8f9f7 | 295 | break; |
<> | 144:ef7eb2e8f9f7 | 296 | |
<> | 144:ef7eb2e8f9f7 | 297 | case FlowControlCTS: |
<> | 144:ef7eb2e8f9f7 | 298 | pinmap_pinout(txflow, PinMap_UART_CTS); |
<> | 144:ef7eb2e8f9f7 | 299 | uart_addrs[obj->index]->MODEM &= ~UART_MODEM_RXRTSE_MASK; |
<> | 144:ef7eb2e8f9f7 | 300 | uart_addrs[obj->index]->MODEM |= UART_MODEM_TXCTSE_MASK; |
<> | 144:ef7eb2e8f9f7 | 301 | break; |
<> | 144:ef7eb2e8f9f7 | 302 | |
<> | 144:ef7eb2e8f9f7 | 303 | case FlowControlRTSCTS: |
<> | 144:ef7eb2e8f9f7 | 304 | pinmap_pinout(rxflow, PinMap_UART_RTS); |
<> | 144:ef7eb2e8f9f7 | 305 | pinmap_pinout(txflow, PinMap_UART_CTS); |
<> | 144:ef7eb2e8f9f7 | 306 | uart_addrs[obj->index]->MODEM |= UART_MODEM_TXCTSE_MASK | UART_MODEM_RXRTSE_MASK; |
<> | 144:ef7eb2e8f9f7 | 307 | break; |
<> | 144:ef7eb2e8f9f7 | 308 | |
<> | 144:ef7eb2e8f9f7 | 309 | case FlowControlNone: |
<> | 144:ef7eb2e8f9f7 | 310 | uart_addrs[obj->index]->MODEM &= ~(UART_MODEM_TXCTSE_MASK | UART_MODEM_RXRTSE_MASK); |
<> | 144:ef7eb2e8f9f7 | 311 | break; |
<> | 144:ef7eb2e8f9f7 | 312 | |
<> | 144:ef7eb2e8f9f7 | 313 | default: |
<> | 144:ef7eb2e8f9f7 | 314 | break; |
<> | 144:ef7eb2e8f9f7 | 315 | } |
<> | 144:ef7eb2e8f9f7 | 316 | } |
<> | 144:ef7eb2e8f9f7 | 317 | |
<> | 144:ef7eb2e8f9f7 | 318 | #endif |
<> | 144:ef7eb2e8f9f7 | 319 | |
<> | 144:ef7eb2e8f9f7 | 320 | #endif |