added prescaler for 16 bit pwm in LPC1347 target
Fork of mbed-dev by
targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/drivers/fsl_spi.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)
- Committer:
- <>
- Date:
- Fri Sep 02 15:07:44 2016 +0100
- Revision:
- 144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /* |
<> | 144:ef7eb2e8f9f7 | 2 | * Copyright (c) 2015, Freescale Semiconductor, Inc. |
<> | 144:ef7eb2e8f9f7 | 3 | * All rights reserved. |
<> | 144:ef7eb2e8f9f7 | 4 | * |
<> | 144:ef7eb2e8f9f7 | 5 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 144:ef7eb2e8f9f7 | 6 | * are permitted provided that the following conditions are met: |
<> | 144:ef7eb2e8f9f7 | 7 | * |
<> | 144:ef7eb2e8f9f7 | 8 | * o Redistributions of source code must retain the above copyright notice, this list |
<> | 144:ef7eb2e8f9f7 | 9 | * of conditions and the following disclaimer. |
<> | 144:ef7eb2e8f9f7 | 10 | * |
<> | 144:ef7eb2e8f9f7 | 11 | * o Redistributions in binary form must reproduce the above copyright notice, this |
<> | 144:ef7eb2e8f9f7 | 12 | * list of conditions and the following disclaimer in the documentation and/or |
<> | 144:ef7eb2e8f9f7 | 13 | * other materials provided with the distribution. |
<> | 144:ef7eb2e8f9f7 | 14 | * |
<> | 144:ef7eb2e8f9f7 | 15 | * o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
<> | 144:ef7eb2e8f9f7 | 16 | * contributors may be used to endorse or promote products derived from this |
<> | 144:ef7eb2e8f9f7 | 17 | * software without specific prior written permission. |
<> | 144:ef7eb2e8f9f7 | 18 | * |
<> | 144:ef7eb2e8f9f7 | 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
<> | 144:ef7eb2e8f9f7 | 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
<> | 144:ef7eb2e8f9f7 | 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 144:ef7eb2e8f9f7 | 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
<> | 144:ef7eb2e8f9f7 | 23 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
<> | 144:ef7eb2e8f9f7 | 24 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
<> | 144:ef7eb2e8f9f7 | 25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
<> | 144:ef7eb2e8f9f7 | 26 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
<> | 144:ef7eb2e8f9f7 | 27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
<> | 144:ef7eb2e8f9f7 | 28 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 144:ef7eb2e8f9f7 | 29 | */ |
<> | 144:ef7eb2e8f9f7 | 30 | |
<> | 144:ef7eb2e8f9f7 | 31 | #include "fsl_spi.h" |
<> | 144:ef7eb2e8f9f7 | 32 | |
<> | 144:ef7eb2e8f9f7 | 33 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 34 | * Definitons |
<> | 144:ef7eb2e8f9f7 | 35 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 36 | /*! @brief SPI transfer state, which is used for SPI transactiaonl APIs' internal state. */ |
<> | 144:ef7eb2e8f9f7 | 37 | enum _spi_transfer_states_t |
<> | 144:ef7eb2e8f9f7 | 38 | { |
<> | 144:ef7eb2e8f9f7 | 39 | kSPI_Idle = 0x0, /*!< SPI is idle state */ |
<> | 144:ef7eb2e8f9f7 | 40 | kSPI_Busy /*!< SPI is busy tranferring data. */ |
<> | 144:ef7eb2e8f9f7 | 41 | }; |
<> | 144:ef7eb2e8f9f7 | 42 | |
<> | 144:ef7eb2e8f9f7 | 43 | /*! @brief Typedef for spi master interrupt handler. spi master and slave handle is the same. */ |
<> | 144:ef7eb2e8f9f7 | 44 | typedef void (*spi_isr_t)(SPI_Type *base, spi_master_handle_t *spiHandle); |
<> | 144:ef7eb2e8f9f7 | 45 | |
<> | 144:ef7eb2e8f9f7 | 46 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 47 | * Prototypes |
<> | 144:ef7eb2e8f9f7 | 48 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 49 | /*! |
<> | 144:ef7eb2e8f9f7 | 50 | * @brief Get the instance for SPI module. |
<> | 144:ef7eb2e8f9f7 | 51 | * |
<> | 144:ef7eb2e8f9f7 | 52 | * @param base SPI base address |
<> | 144:ef7eb2e8f9f7 | 53 | */ |
<> | 144:ef7eb2e8f9f7 | 54 | uint32_t SPI_GetInstance(SPI_Type *base); |
<> | 144:ef7eb2e8f9f7 | 55 | |
<> | 144:ef7eb2e8f9f7 | 56 | /*! |
<> | 144:ef7eb2e8f9f7 | 57 | * @brief Sends a buffer of data bytes in non-blocking way. |
<> | 144:ef7eb2e8f9f7 | 58 | * |
<> | 144:ef7eb2e8f9f7 | 59 | * @param base SPI base pointer |
<> | 144:ef7eb2e8f9f7 | 60 | * @param buffer The data bytes to send |
<> | 144:ef7eb2e8f9f7 | 61 | * @param size The number of data bytes to send |
<> | 144:ef7eb2e8f9f7 | 62 | */ |
<> | 144:ef7eb2e8f9f7 | 63 | static void SPI_WriteNonBlocking(SPI_Type *base, uint8_t *buffer, size_t size); |
<> | 144:ef7eb2e8f9f7 | 64 | |
<> | 144:ef7eb2e8f9f7 | 65 | /*! |
<> | 144:ef7eb2e8f9f7 | 66 | * @brief Receive a buffer of data bytes in non-blocking way. |
<> | 144:ef7eb2e8f9f7 | 67 | * |
<> | 144:ef7eb2e8f9f7 | 68 | * @param base SPI base pointer |
<> | 144:ef7eb2e8f9f7 | 69 | * @param buffer The data bytes to send |
<> | 144:ef7eb2e8f9f7 | 70 | * @param size The number of data bytes to send |
<> | 144:ef7eb2e8f9f7 | 71 | */ |
<> | 144:ef7eb2e8f9f7 | 72 | static void SPI_ReadNonBlocking(SPI_Type *base, uint8_t *buffer, size_t size); |
<> | 144:ef7eb2e8f9f7 | 73 | |
<> | 144:ef7eb2e8f9f7 | 74 | /*! |
<> | 144:ef7eb2e8f9f7 | 75 | * @brief Send a piece of data for SPI. |
<> | 144:ef7eb2e8f9f7 | 76 | * |
<> | 144:ef7eb2e8f9f7 | 77 | * This function computes the number of data to be written into D register or Tx FIFO, |
<> | 144:ef7eb2e8f9f7 | 78 | * and write the data into it. At the same time, this function updates the values in |
<> | 144:ef7eb2e8f9f7 | 79 | * master handle structure. |
<> | 144:ef7eb2e8f9f7 | 80 | * |
<> | 144:ef7eb2e8f9f7 | 81 | * @param handle Pointer to SPI master handle structure. |
<> | 144:ef7eb2e8f9f7 | 82 | */ |
<> | 144:ef7eb2e8f9f7 | 83 | static void SPI_SendTransfer(SPI_Type *base, spi_master_handle_t *handle); |
<> | 144:ef7eb2e8f9f7 | 84 | |
<> | 144:ef7eb2e8f9f7 | 85 | /*! |
<> | 144:ef7eb2e8f9f7 | 86 | * @brief Receive a piece of data for SPI master. |
<> | 144:ef7eb2e8f9f7 | 87 | * |
<> | 144:ef7eb2e8f9f7 | 88 | * This function computes the number of data to receive from D register or Rx FIFO, |
<> | 144:ef7eb2e8f9f7 | 89 | * and write the data to destination address. At the same time, this function updates |
<> | 144:ef7eb2e8f9f7 | 90 | * the values in master handle structure. |
<> | 144:ef7eb2e8f9f7 | 91 | * |
<> | 144:ef7eb2e8f9f7 | 92 | * @param handle Pointer to SPI master handle structure. |
<> | 144:ef7eb2e8f9f7 | 93 | */ |
<> | 144:ef7eb2e8f9f7 | 94 | static void SPI_ReceiveTransfer(SPI_Type *base, spi_master_handle_t *handle); |
<> | 144:ef7eb2e8f9f7 | 95 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 96 | * Variables |
<> | 144:ef7eb2e8f9f7 | 97 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 98 | /*! @brief SPI internal handle pointer array */ |
<> | 144:ef7eb2e8f9f7 | 99 | static spi_master_handle_t *s_spiHandle[FSL_FEATURE_SOC_SPI_COUNT]; |
<> | 144:ef7eb2e8f9f7 | 100 | /*! @brief Base pointer array */ |
<> | 144:ef7eb2e8f9f7 | 101 | static SPI_Type *const s_spiBases[] = SPI_BASE_PTRS; |
<> | 144:ef7eb2e8f9f7 | 102 | /*! @brief IRQ name array */ |
<> | 144:ef7eb2e8f9f7 | 103 | static const IRQn_Type s_spiIRQ[] = SPI_IRQS; |
<> | 144:ef7eb2e8f9f7 | 104 | /*! @brief Clock array name */ |
<> | 144:ef7eb2e8f9f7 | 105 | static const clock_ip_name_t s_spiClock[] = SPI_CLOCKS; |
<> | 144:ef7eb2e8f9f7 | 106 | |
<> | 144:ef7eb2e8f9f7 | 107 | /*! @brief Pointer to master IRQ handler for each instance. */ |
<> | 144:ef7eb2e8f9f7 | 108 | static spi_isr_t s_spiIsr; |
<> | 144:ef7eb2e8f9f7 | 109 | |
<> | 144:ef7eb2e8f9f7 | 110 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 111 | * Code |
<> | 144:ef7eb2e8f9f7 | 112 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 113 | uint32_t SPI_GetInstance(SPI_Type *base) |
<> | 144:ef7eb2e8f9f7 | 114 | { |
<> | 144:ef7eb2e8f9f7 | 115 | uint32_t instance; |
<> | 144:ef7eb2e8f9f7 | 116 | |
<> | 144:ef7eb2e8f9f7 | 117 | /* Find the instance index from base address mappings. */ |
<> | 144:ef7eb2e8f9f7 | 118 | for (instance = 0; instance < FSL_FEATURE_SOC_SPI_COUNT; instance++) |
<> | 144:ef7eb2e8f9f7 | 119 | { |
<> | 144:ef7eb2e8f9f7 | 120 | if (s_spiBases[instance] == base) |
<> | 144:ef7eb2e8f9f7 | 121 | { |
<> | 144:ef7eb2e8f9f7 | 122 | break; |
<> | 144:ef7eb2e8f9f7 | 123 | } |
<> | 144:ef7eb2e8f9f7 | 124 | } |
<> | 144:ef7eb2e8f9f7 | 125 | |
<> | 144:ef7eb2e8f9f7 | 126 | assert(instance < FSL_FEATURE_SOC_SPI_COUNT); |
<> | 144:ef7eb2e8f9f7 | 127 | |
<> | 144:ef7eb2e8f9f7 | 128 | return instance; |
<> | 144:ef7eb2e8f9f7 | 129 | } |
<> | 144:ef7eb2e8f9f7 | 130 | |
<> | 144:ef7eb2e8f9f7 | 131 | static void SPI_WriteNonBlocking(SPI_Type *base, uint8_t *buffer, size_t size) |
<> | 144:ef7eb2e8f9f7 | 132 | { |
<> | 144:ef7eb2e8f9f7 | 133 | uint32_t i = 0; |
<> | 144:ef7eb2e8f9f7 | 134 | uint8_t bytesPerFrame = 1U; |
<> | 144:ef7eb2e8f9f7 | 135 | |
<> | 144:ef7eb2e8f9f7 | 136 | #if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS |
<> | 144:ef7eb2e8f9f7 | 137 | /* Check if 16 bits or 8 bits */ |
<> | 144:ef7eb2e8f9f7 | 138 | bytesPerFrame = ((base->C2 & SPI_C2_SPIMODE_MASK) >> SPI_C2_SPIMODE_SHIFT) + 1U; |
<> | 144:ef7eb2e8f9f7 | 139 | #endif |
<> | 144:ef7eb2e8f9f7 | 140 | |
<> | 144:ef7eb2e8f9f7 | 141 | while (i < size) |
<> | 144:ef7eb2e8f9f7 | 142 | { |
<> | 144:ef7eb2e8f9f7 | 143 | if (buffer != NULL) |
<> | 144:ef7eb2e8f9f7 | 144 | { |
<> | 144:ef7eb2e8f9f7 | 145 | #if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS |
<> | 144:ef7eb2e8f9f7 | 146 | /*16 bit mode*/ |
<> | 144:ef7eb2e8f9f7 | 147 | if (base->C2 & SPI_C2_SPIMODE_MASK) |
<> | 144:ef7eb2e8f9f7 | 148 | { |
<> | 144:ef7eb2e8f9f7 | 149 | base->DL = *buffer++; |
<> | 144:ef7eb2e8f9f7 | 150 | base->DH = *buffer++; |
<> | 144:ef7eb2e8f9f7 | 151 | } |
<> | 144:ef7eb2e8f9f7 | 152 | /* 8 bit mode */ |
<> | 144:ef7eb2e8f9f7 | 153 | else |
<> | 144:ef7eb2e8f9f7 | 154 | { |
<> | 144:ef7eb2e8f9f7 | 155 | base->DL = *buffer++; |
<> | 144:ef7eb2e8f9f7 | 156 | } |
<> | 144:ef7eb2e8f9f7 | 157 | #else |
<> | 144:ef7eb2e8f9f7 | 158 | base->D = *buffer++; |
<> | 144:ef7eb2e8f9f7 | 159 | #endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */ |
<> | 144:ef7eb2e8f9f7 | 160 | } |
<> | 144:ef7eb2e8f9f7 | 161 | /* Send dummy data */ |
<> | 144:ef7eb2e8f9f7 | 162 | else |
<> | 144:ef7eb2e8f9f7 | 163 | { |
<> | 144:ef7eb2e8f9f7 | 164 | SPI_WriteData(base, SPI_DUMMYDATA); |
<> | 144:ef7eb2e8f9f7 | 165 | } |
<> | 144:ef7eb2e8f9f7 | 166 | i += bytesPerFrame; |
<> | 144:ef7eb2e8f9f7 | 167 | } |
<> | 144:ef7eb2e8f9f7 | 168 | } |
<> | 144:ef7eb2e8f9f7 | 169 | |
<> | 144:ef7eb2e8f9f7 | 170 | static void SPI_ReadNonBlocking(SPI_Type *base, uint8_t *buffer, size_t size) |
<> | 144:ef7eb2e8f9f7 | 171 | { |
<> | 144:ef7eb2e8f9f7 | 172 | uint32_t i = 0; |
<> | 144:ef7eb2e8f9f7 | 173 | uint8_t bytesPerFrame = 1U; |
<> | 144:ef7eb2e8f9f7 | 174 | |
<> | 144:ef7eb2e8f9f7 | 175 | #if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS |
<> | 144:ef7eb2e8f9f7 | 176 | /* Check if 16 bits or 8 bits */ |
<> | 144:ef7eb2e8f9f7 | 177 | bytesPerFrame = ((base->C2 & SPI_C2_SPIMODE_MASK) >> SPI_C2_SPIMODE_SHIFT) + 1U; |
<> | 144:ef7eb2e8f9f7 | 178 | #endif |
<> | 144:ef7eb2e8f9f7 | 179 | |
<> | 144:ef7eb2e8f9f7 | 180 | while (i < size) |
<> | 144:ef7eb2e8f9f7 | 181 | { |
<> | 144:ef7eb2e8f9f7 | 182 | if (buffer != NULL) |
<> | 144:ef7eb2e8f9f7 | 183 | { |
<> | 144:ef7eb2e8f9f7 | 184 | #if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS |
<> | 144:ef7eb2e8f9f7 | 185 | /*16 bit mode*/ |
<> | 144:ef7eb2e8f9f7 | 186 | if (base->C2 & SPI_C2_SPIMODE_MASK) |
<> | 144:ef7eb2e8f9f7 | 187 | { |
<> | 144:ef7eb2e8f9f7 | 188 | *buffer++ = base->DL; |
<> | 144:ef7eb2e8f9f7 | 189 | *buffer++ = base->DH; |
<> | 144:ef7eb2e8f9f7 | 190 | } |
<> | 144:ef7eb2e8f9f7 | 191 | /* 8 bit mode */ |
<> | 144:ef7eb2e8f9f7 | 192 | else |
<> | 144:ef7eb2e8f9f7 | 193 | { |
<> | 144:ef7eb2e8f9f7 | 194 | *buffer++ = base->DL; |
<> | 144:ef7eb2e8f9f7 | 195 | } |
<> | 144:ef7eb2e8f9f7 | 196 | #else |
<> | 144:ef7eb2e8f9f7 | 197 | *buffer++ = base->D; |
<> | 144:ef7eb2e8f9f7 | 198 | #endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */ |
<> | 144:ef7eb2e8f9f7 | 199 | } |
<> | 144:ef7eb2e8f9f7 | 200 | else |
<> | 144:ef7eb2e8f9f7 | 201 | { |
<> | 144:ef7eb2e8f9f7 | 202 | SPI_ReadData(base); |
<> | 144:ef7eb2e8f9f7 | 203 | } |
<> | 144:ef7eb2e8f9f7 | 204 | i += bytesPerFrame; |
<> | 144:ef7eb2e8f9f7 | 205 | } |
<> | 144:ef7eb2e8f9f7 | 206 | } |
<> | 144:ef7eb2e8f9f7 | 207 | |
<> | 144:ef7eb2e8f9f7 | 208 | static void SPI_SendTransfer(SPI_Type *base, spi_master_handle_t *handle) |
<> | 144:ef7eb2e8f9f7 | 209 | { |
<> | 144:ef7eb2e8f9f7 | 210 | uint8_t bytes = MIN((handle->watermark * 2U), handle->txRemainingBytes); |
<> | 144:ef7eb2e8f9f7 | 211 | |
<> | 144:ef7eb2e8f9f7 | 212 | /* Read S register and ensure SPTEF is 1, otherwise the write would be ignored. */ |
<> | 144:ef7eb2e8f9f7 | 213 | if (handle->watermark == 1U) |
<> | 144:ef7eb2e8f9f7 | 214 | { |
<> | 144:ef7eb2e8f9f7 | 215 | if (bytes != 0U) |
<> | 144:ef7eb2e8f9f7 | 216 | { |
<> | 144:ef7eb2e8f9f7 | 217 | bytes = handle->bytePerFrame; |
<> | 144:ef7eb2e8f9f7 | 218 | } |
<> | 144:ef7eb2e8f9f7 | 219 | |
<> | 144:ef7eb2e8f9f7 | 220 | /* Send data */ |
<> | 144:ef7eb2e8f9f7 | 221 | if (base->C1 & SPI_C1_MSTR_MASK) |
<> | 144:ef7eb2e8f9f7 | 222 | { |
<> | 144:ef7eb2e8f9f7 | 223 | /* As a master, only write once */ |
<> | 144:ef7eb2e8f9f7 | 224 | if (base->S & SPI_S_SPTEF_MASK) |
<> | 144:ef7eb2e8f9f7 | 225 | { |
<> | 144:ef7eb2e8f9f7 | 226 | SPI_WriteNonBlocking(base, handle->txData, bytes); |
<> | 144:ef7eb2e8f9f7 | 227 | /* Update handle information */ |
<> | 144:ef7eb2e8f9f7 | 228 | if (handle->txData) |
<> | 144:ef7eb2e8f9f7 | 229 | { |
<> | 144:ef7eb2e8f9f7 | 230 | handle->txData += bytes; |
<> | 144:ef7eb2e8f9f7 | 231 | } |
<> | 144:ef7eb2e8f9f7 | 232 | handle->txRemainingBytes -= bytes; |
<> | 144:ef7eb2e8f9f7 | 233 | } |
<> | 144:ef7eb2e8f9f7 | 234 | } |
<> | 144:ef7eb2e8f9f7 | 235 | else |
<> | 144:ef7eb2e8f9f7 | 236 | { |
<> | 144:ef7eb2e8f9f7 | 237 | /* As a slave, send data until SPTEF cleared */ |
<> | 144:ef7eb2e8f9f7 | 238 | while ((base->S & SPI_S_SPTEF_MASK) && (handle->txRemainingBytes > 0)) |
<> | 144:ef7eb2e8f9f7 | 239 | { |
<> | 144:ef7eb2e8f9f7 | 240 | SPI_WriteNonBlocking(base, handle->txData, bytes); |
<> | 144:ef7eb2e8f9f7 | 241 | |
<> | 144:ef7eb2e8f9f7 | 242 | /* Update handle information */ |
<> | 144:ef7eb2e8f9f7 | 243 | if (handle->txData) |
<> | 144:ef7eb2e8f9f7 | 244 | { |
<> | 144:ef7eb2e8f9f7 | 245 | handle->txData += bytes; |
<> | 144:ef7eb2e8f9f7 | 246 | } |
<> | 144:ef7eb2e8f9f7 | 247 | handle->txRemainingBytes -= bytes; |
<> | 144:ef7eb2e8f9f7 | 248 | } |
<> | 144:ef7eb2e8f9f7 | 249 | } |
<> | 144:ef7eb2e8f9f7 | 250 | } |
<> | 144:ef7eb2e8f9f7 | 251 | |
<> | 144:ef7eb2e8f9f7 | 252 | #if defined(FSL_FEATURE_SPI_HAS_FIFO) && (FSL_FEATURE_SPI_HAS_FIFO) |
<> | 144:ef7eb2e8f9f7 | 253 | /* If use FIFO */ |
<> | 144:ef7eb2e8f9f7 | 254 | else |
<> | 144:ef7eb2e8f9f7 | 255 | { |
<> | 144:ef7eb2e8f9f7 | 256 | if (base->S & SPI_S_TNEAREF_MASK) |
<> | 144:ef7eb2e8f9f7 | 257 | { |
<> | 144:ef7eb2e8f9f7 | 258 | SPI_WriteNonBlocking(base, handle->txData, bytes); |
<> | 144:ef7eb2e8f9f7 | 259 | |
<> | 144:ef7eb2e8f9f7 | 260 | /* Update handle information */ |
<> | 144:ef7eb2e8f9f7 | 261 | if (handle->txData) |
<> | 144:ef7eb2e8f9f7 | 262 | { |
<> | 144:ef7eb2e8f9f7 | 263 | handle->txData += bytes; |
<> | 144:ef7eb2e8f9f7 | 264 | } |
<> | 144:ef7eb2e8f9f7 | 265 | handle->txRemainingBytes -= bytes; |
<> | 144:ef7eb2e8f9f7 | 266 | } |
<> | 144:ef7eb2e8f9f7 | 267 | } |
<> | 144:ef7eb2e8f9f7 | 268 | #endif |
<> | 144:ef7eb2e8f9f7 | 269 | } |
<> | 144:ef7eb2e8f9f7 | 270 | |
<> | 144:ef7eb2e8f9f7 | 271 | static void SPI_ReceiveTransfer(SPI_Type *base, spi_master_handle_t *handle) |
<> | 144:ef7eb2e8f9f7 | 272 | { |
<> | 144:ef7eb2e8f9f7 | 273 | uint8_t bytes = MIN((handle->watermark * 2U), handle->rxRemainingBytes); |
<> | 144:ef7eb2e8f9f7 | 274 | uint8_t val = 1U; |
<> | 144:ef7eb2e8f9f7 | 275 | |
<> | 144:ef7eb2e8f9f7 | 276 | /* Read S register and ensure SPRF is 1, otherwise the write would be ignored. */ |
<> | 144:ef7eb2e8f9f7 | 277 | if (handle->watermark == 1U) |
<> | 144:ef7eb2e8f9f7 | 278 | { |
<> | 144:ef7eb2e8f9f7 | 279 | val = base->S & SPI_S_SPRF_MASK; |
<> | 144:ef7eb2e8f9f7 | 280 | if (bytes != 0U) |
<> | 144:ef7eb2e8f9f7 | 281 | { |
<> | 144:ef7eb2e8f9f7 | 282 | bytes = handle->bytePerFrame; |
<> | 144:ef7eb2e8f9f7 | 283 | } |
<> | 144:ef7eb2e8f9f7 | 284 | } |
<> | 144:ef7eb2e8f9f7 | 285 | |
<> | 144:ef7eb2e8f9f7 | 286 | if (val) |
<> | 144:ef7eb2e8f9f7 | 287 | { |
<> | 144:ef7eb2e8f9f7 | 288 | SPI_ReadNonBlocking(base, handle->rxData, bytes); |
<> | 144:ef7eb2e8f9f7 | 289 | |
<> | 144:ef7eb2e8f9f7 | 290 | /* Update information in handle */ |
<> | 144:ef7eb2e8f9f7 | 291 | if (handle->rxData) |
<> | 144:ef7eb2e8f9f7 | 292 | { |
<> | 144:ef7eb2e8f9f7 | 293 | handle->rxData += bytes; |
<> | 144:ef7eb2e8f9f7 | 294 | } |
<> | 144:ef7eb2e8f9f7 | 295 | handle->rxRemainingBytes -= bytes; |
<> | 144:ef7eb2e8f9f7 | 296 | } |
<> | 144:ef7eb2e8f9f7 | 297 | } |
<> | 144:ef7eb2e8f9f7 | 298 | |
<> | 144:ef7eb2e8f9f7 | 299 | void SPI_MasterGetDefaultConfig(spi_master_config_t *config) |
<> | 144:ef7eb2e8f9f7 | 300 | { |
<> | 144:ef7eb2e8f9f7 | 301 | config->enableMaster = true; |
<> | 144:ef7eb2e8f9f7 | 302 | config->enableStopInWaitMode = false; |
<> | 144:ef7eb2e8f9f7 | 303 | config->polarity = kSPI_ClockPolarityActiveHigh; |
<> | 144:ef7eb2e8f9f7 | 304 | config->phase = kSPI_ClockPhaseFirstEdge; |
<> | 144:ef7eb2e8f9f7 | 305 | config->direction = kSPI_MsbFirst; |
<> | 144:ef7eb2e8f9f7 | 306 | |
<> | 144:ef7eb2e8f9f7 | 307 | #if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS |
<> | 144:ef7eb2e8f9f7 | 308 | config->dataMode = kSPI_8BitMode; |
<> | 144:ef7eb2e8f9f7 | 309 | #endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */ |
<> | 144:ef7eb2e8f9f7 | 310 | |
<> | 144:ef7eb2e8f9f7 | 311 | #if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO |
<> | 144:ef7eb2e8f9f7 | 312 | config->txWatermark = kSPI_TxFifoOneHalfEmpty; |
<> | 144:ef7eb2e8f9f7 | 313 | config->rxWatermark = kSPI_RxFifoOneHalfFull; |
<> | 144:ef7eb2e8f9f7 | 314 | #endif /* FSL_FEATURE_SPI_HAS_FIFO */ |
<> | 144:ef7eb2e8f9f7 | 315 | |
<> | 144:ef7eb2e8f9f7 | 316 | config->pinMode = kSPI_PinModeNormal; |
<> | 144:ef7eb2e8f9f7 | 317 | config->outputMode = kSPI_SlaveSelectAutomaticOutput; |
<> | 144:ef7eb2e8f9f7 | 318 | config->baudRate_Bps = 500000U; |
<> | 144:ef7eb2e8f9f7 | 319 | } |
<> | 144:ef7eb2e8f9f7 | 320 | |
<> | 144:ef7eb2e8f9f7 | 321 | void SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz) |
<> | 144:ef7eb2e8f9f7 | 322 | { |
<> | 144:ef7eb2e8f9f7 | 323 | assert(config && srcClock_Hz); |
<> | 144:ef7eb2e8f9f7 | 324 | |
<> | 144:ef7eb2e8f9f7 | 325 | /* Open clock gate for SPI and open interrupt */ |
<> | 144:ef7eb2e8f9f7 | 326 | CLOCK_EnableClock(s_spiClock[SPI_GetInstance(base)]); |
<> | 144:ef7eb2e8f9f7 | 327 | |
<> | 144:ef7eb2e8f9f7 | 328 | /* Disable SPI before configuration */ |
<> | 144:ef7eb2e8f9f7 | 329 | base->C1 &= ~SPI_C1_SPE_MASK; |
<> | 144:ef7eb2e8f9f7 | 330 | |
<> | 144:ef7eb2e8f9f7 | 331 | /* Configure clock polarity and phase, set SPI to master */ |
<> | 144:ef7eb2e8f9f7 | 332 | base->C1 = SPI_C1_MSTR(1U) | SPI_C1_CPOL(config->polarity) | SPI_C1_CPHA(config->phase) | |
<> | 144:ef7eb2e8f9f7 | 333 | SPI_C1_SSOE(config->outputMode & 1U) | SPI_C1_LSBFE(config->direction); |
<> | 144:ef7eb2e8f9f7 | 334 | |
<> | 144:ef7eb2e8f9f7 | 335 | /* Set data mode, and also pin mode and mode fault settings */ |
<> | 144:ef7eb2e8f9f7 | 336 | #if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS |
<> | 144:ef7eb2e8f9f7 | 337 | base->C2 = SPI_C2_MODFEN(config->outputMode >> 1U) | SPI_C2_BIDIROE(config->pinMode >> 1U) | |
<> | 144:ef7eb2e8f9f7 | 338 | SPI_C2_SPISWAI(config->enableStopInWaitMode) | SPI_C2_SPC0(config->pinMode & 1U) | |
<> | 144:ef7eb2e8f9f7 | 339 | SPI_C2_SPIMODE(config->dataMode); |
<> | 144:ef7eb2e8f9f7 | 340 | #else |
<> | 144:ef7eb2e8f9f7 | 341 | base->C2 = SPI_C2_MODFEN(config->outputMode >> 1U) | SPI_C2_BIDIROE(config->pinMode >> 1U) | |
<> | 144:ef7eb2e8f9f7 | 342 | SPI_C2_SPISWAI(config->enableStopInWaitMode) | SPI_C2_SPC0(config->pinMode & 1U); |
<> | 144:ef7eb2e8f9f7 | 343 | #endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */ |
<> | 144:ef7eb2e8f9f7 | 344 | |
<> | 144:ef7eb2e8f9f7 | 345 | /* Set watermark, FIFO is enabled */ |
<> | 144:ef7eb2e8f9f7 | 346 | #if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO |
<> | 144:ef7eb2e8f9f7 | 347 | if (FSL_FEATURE_SPI_FIFO_SIZEn(base) != 0) |
<> | 144:ef7eb2e8f9f7 | 348 | { |
<> | 144:ef7eb2e8f9f7 | 349 | base->C3 = SPI_C3_TNEAREF_MARK(config->txWatermark) | SPI_C3_RNFULLF_MARK(config->rxWatermark) | |
<> | 144:ef7eb2e8f9f7 | 350 | SPI_C3_INTCLR(0U) | SPI_C3_FIFOMODE(1U); |
<> | 144:ef7eb2e8f9f7 | 351 | } |
<> | 144:ef7eb2e8f9f7 | 352 | #endif /* FSL_FEATURE_SPI_HAS_FIFO */ |
<> | 144:ef7eb2e8f9f7 | 353 | |
<> | 144:ef7eb2e8f9f7 | 354 | /* Set baud rate */ |
<> | 144:ef7eb2e8f9f7 | 355 | SPI_MasterSetBaudRate(base, config->baudRate_Bps, srcClock_Hz); |
<> | 144:ef7eb2e8f9f7 | 356 | |
<> | 144:ef7eb2e8f9f7 | 357 | /* Enable SPI */ |
<> | 144:ef7eb2e8f9f7 | 358 | if (config->enableMaster) |
<> | 144:ef7eb2e8f9f7 | 359 | { |
<> | 144:ef7eb2e8f9f7 | 360 | base->C1 |= SPI_C1_SPE_MASK; |
<> | 144:ef7eb2e8f9f7 | 361 | } |
<> | 144:ef7eb2e8f9f7 | 362 | } |
<> | 144:ef7eb2e8f9f7 | 363 | |
<> | 144:ef7eb2e8f9f7 | 364 | void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config) |
<> | 144:ef7eb2e8f9f7 | 365 | { |
<> | 144:ef7eb2e8f9f7 | 366 | config->enableSlave = true; |
<> | 144:ef7eb2e8f9f7 | 367 | config->polarity = kSPI_ClockPolarityActiveHigh; |
<> | 144:ef7eb2e8f9f7 | 368 | config->phase = kSPI_ClockPhaseFirstEdge; |
<> | 144:ef7eb2e8f9f7 | 369 | config->direction = kSPI_MsbFirst; |
<> | 144:ef7eb2e8f9f7 | 370 | config->enableStopInWaitMode = false; |
<> | 144:ef7eb2e8f9f7 | 371 | |
<> | 144:ef7eb2e8f9f7 | 372 | #if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS |
<> | 144:ef7eb2e8f9f7 | 373 | config->dataMode = kSPI_8BitMode; |
<> | 144:ef7eb2e8f9f7 | 374 | #endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */ |
<> | 144:ef7eb2e8f9f7 | 375 | |
<> | 144:ef7eb2e8f9f7 | 376 | #if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO |
<> | 144:ef7eb2e8f9f7 | 377 | config->txWatermark = kSPI_TxFifoOneHalfEmpty; |
<> | 144:ef7eb2e8f9f7 | 378 | config->rxWatermark = kSPI_RxFifoOneHalfFull; |
<> | 144:ef7eb2e8f9f7 | 379 | #endif /* FSL_FEATURE_SPI_HAS_FIFO */ |
<> | 144:ef7eb2e8f9f7 | 380 | } |
<> | 144:ef7eb2e8f9f7 | 381 | |
<> | 144:ef7eb2e8f9f7 | 382 | void SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config) |
<> | 144:ef7eb2e8f9f7 | 383 | { |
<> | 144:ef7eb2e8f9f7 | 384 | assert(config); |
<> | 144:ef7eb2e8f9f7 | 385 | |
<> | 144:ef7eb2e8f9f7 | 386 | /* Open clock gate for SPI and open interrupt */ |
<> | 144:ef7eb2e8f9f7 | 387 | CLOCK_EnableClock(s_spiClock[SPI_GetInstance(base)]); |
<> | 144:ef7eb2e8f9f7 | 388 | |
<> | 144:ef7eb2e8f9f7 | 389 | /* Disable SPI before configuration */ |
<> | 144:ef7eb2e8f9f7 | 390 | base->C1 &= ~SPI_C1_SPE_MASK; |
<> | 144:ef7eb2e8f9f7 | 391 | |
<> | 144:ef7eb2e8f9f7 | 392 | /* Configure master and clock polarity and phase */ |
<> | 144:ef7eb2e8f9f7 | 393 | base->C1 = |
<> | 144:ef7eb2e8f9f7 | 394 | SPI_C1_MSTR(0U) | SPI_C1_CPOL(config->polarity) | SPI_C1_CPHA(config->phase) | SPI_C1_LSBFE(config->direction); |
<> | 144:ef7eb2e8f9f7 | 395 | |
<> | 144:ef7eb2e8f9f7 | 396 | /* Configure data mode if needed */ |
<> | 144:ef7eb2e8f9f7 | 397 | #if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS |
<> | 144:ef7eb2e8f9f7 | 398 | base->C2 = SPI_C2_SPIMODE(config->dataMode) | SPI_C2_SPISWAI(config->enableStopInWaitMode); |
<> | 144:ef7eb2e8f9f7 | 399 | #else |
<> | 144:ef7eb2e8f9f7 | 400 | base->C2 = SPI_C2_SPISWAI(config->enableStopInWaitMode); |
<> | 144:ef7eb2e8f9f7 | 401 | #endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */ |
<> | 144:ef7eb2e8f9f7 | 402 | |
<> | 144:ef7eb2e8f9f7 | 403 | /* Set watermark */ |
<> | 144:ef7eb2e8f9f7 | 404 | #if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO |
<> | 144:ef7eb2e8f9f7 | 405 | if (FSL_FEATURE_SPI_FIFO_SIZEn(base) != 0U) |
<> | 144:ef7eb2e8f9f7 | 406 | { |
<> | 144:ef7eb2e8f9f7 | 407 | base->C3 = SPI_C3_TNEAREF_MARK(config->txWatermark) | SPI_C3_RNFULLF_MARK(config->rxWatermark) | |
<> | 144:ef7eb2e8f9f7 | 408 | SPI_C3_INTCLR(0U) | SPI_C3_FIFOMODE(1U); |
<> | 144:ef7eb2e8f9f7 | 409 | } |
<> | 144:ef7eb2e8f9f7 | 410 | #endif /* FSL_FEATURE_SPI_HAS_FIFO */ |
<> | 144:ef7eb2e8f9f7 | 411 | |
<> | 144:ef7eb2e8f9f7 | 412 | /* Enable SPI */ |
<> | 144:ef7eb2e8f9f7 | 413 | if (config->enableSlave) |
<> | 144:ef7eb2e8f9f7 | 414 | { |
<> | 144:ef7eb2e8f9f7 | 415 | base->C1 |= SPI_C1_SPE_MASK; |
<> | 144:ef7eb2e8f9f7 | 416 | } |
<> | 144:ef7eb2e8f9f7 | 417 | } |
<> | 144:ef7eb2e8f9f7 | 418 | |
<> | 144:ef7eb2e8f9f7 | 419 | void SPI_Deinit(SPI_Type *base) |
<> | 144:ef7eb2e8f9f7 | 420 | { |
<> | 144:ef7eb2e8f9f7 | 421 | /* Disable SPI module before shutting down */ |
<> | 144:ef7eb2e8f9f7 | 422 | base->C1 &= ~SPI_C1_SPE_MASK; |
<> | 144:ef7eb2e8f9f7 | 423 | |
<> | 144:ef7eb2e8f9f7 | 424 | /* Gate the clock */ |
<> | 144:ef7eb2e8f9f7 | 425 | CLOCK_DisableClock(s_spiClock[SPI_GetInstance(base)]); |
<> | 144:ef7eb2e8f9f7 | 426 | } |
<> | 144:ef7eb2e8f9f7 | 427 | |
<> | 144:ef7eb2e8f9f7 | 428 | uint32_t SPI_GetStatusFlags(SPI_Type *base) |
<> | 144:ef7eb2e8f9f7 | 429 | { |
<> | 144:ef7eb2e8f9f7 | 430 | #if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO |
<> | 144:ef7eb2e8f9f7 | 431 | if (FSL_FEATURE_SPI_FIFO_SIZEn(base) != 0) |
<> | 144:ef7eb2e8f9f7 | 432 | { |
<> | 144:ef7eb2e8f9f7 | 433 | return ((base->S) | (((uint32_t)base->CI) << 8U)); |
<> | 144:ef7eb2e8f9f7 | 434 | } |
<> | 144:ef7eb2e8f9f7 | 435 | else |
<> | 144:ef7eb2e8f9f7 | 436 | { |
<> | 144:ef7eb2e8f9f7 | 437 | return (base->S); |
<> | 144:ef7eb2e8f9f7 | 438 | } |
<> | 144:ef7eb2e8f9f7 | 439 | #else |
<> | 144:ef7eb2e8f9f7 | 440 | return (base->S); |
<> | 144:ef7eb2e8f9f7 | 441 | #endif /* FSL_FEATURE_SPI_HAS_FIFO */ |
<> | 144:ef7eb2e8f9f7 | 442 | } |
<> | 144:ef7eb2e8f9f7 | 443 | |
<> | 144:ef7eb2e8f9f7 | 444 | void SPI_EnableInterrupts(SPI_Type *base, uint32_t mask) |
<> | 144:ef7eb2e8f9f7 | 445 | { |
<> | 144:ef7eb2e8f9f7 | 446 | /* Rx full interrupt */ |
<> | 144:ef7eb2e8f9f7 | 447 | if (mask & kSPI_RxFullAndModfInterruptEnable) |
<> | 144:ef7eb2e8f9f7 | 448 | { |
<> | 144:ef7eb2e8f9f7 | 449 | base->C1 |= SPI_C1_SPIE_MASK; |
<> | 144:ef7eb2e8f9f7 | 450 | } |
<> | 144:ef7eb2e8f9f7 | 451 | |
<> | 144:ef7eb2e8f9f7 | 452 | /* Tx empty interrupt */ |
<> | 144:ef7eb2e8f9f7 | 453 | if (mask & kSPI_TxEmptyInterruptEnable) |
<> | 144:ef7eb2e8f9f7 | 454 | { |
<> | 144:ef7eb2e8f9f7 | 455 | base->C1 |= SPI_C1_SPTIE_MASK; |
<> | 144:ef7eb2e8f9f7 | 456 | } |
<> | 144:ef7eb2e8f9f7 | 457 | |
<> | 144:ef7eb2e8f9f7 | 458 | /* Data match interrupt */ |
<> | 144:ef7eb2e8f9f7 | 459 | if (mask & kSPI_MatchInterruptEnable) |
<> | 144:ef7eb2e8f9f7 | 460 | { |
<> | 144:ef7eb2e8f9f7 | 461 | base->C2 |= SPI_C2_SPMIE_MASK; |
<> | 144:ef7eb2e8f9f7 | 462 | } |
<> | 144:ef7eb2e8f9f7 | 463 | |
<> | 144:ef7eb2e8f9f7 | 464 | /* FIFO related interrupts */ |
<> | 144:ef7eb2e8f9f7 | 465 | #if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO |
<> | 144:ef7eb2e8f9f7 | 466 | if (FSL_FEATURE_SPI_FIFO_SIZEn(base) != 0) |
<> | 144:ef7eb2e8f9f7 | 467 | { |
<> | 144:ef7eb2e8f9f7 | 468 | /* Rx FIFO near full interrupt */ |
<> | 144:ef7eb2e8f9f7 | 469 | if (mask & kSPI_RxFifoNearFullInterruptEnable) |
<> | 144:ef7eb2e8f9f7 | 470 | { |
<> | 144:ef7eb2e8f9f7 | 471 | base->C3 |= SPI_C3_RNFULLIEN_MASK; |
<> | 144:ef7eb2e8f9f7 | 472 | } |
<> | 144:ef7eb2e8f9f7 | 473 | |
<> | 144:ef7eb2e8f9f7 | 474 | /* Tx FIFO near empty interrupt */ |
<> | 144:ef7eb2e8f9f7 | 475 | if (mask & kSPI_TxFifoNearEmptyInterruptEnable) |
<> | 144:ef7eb2e8f9f7 | 476 | { |
<> | 144:ef7eb2e8f9f7 | 477 | base->C3 |= SPI_C3_TNEARIEN_MASK; |
<> | 144:ef7eb2e8f9f7 | 478 | } |
<> | 144:ef7eb2e8f9f7 | 479 | } |
<> | 144:ef7eb2e8f9f7 | 480 | #endif /* FSL_FEATURE_SPI_HAS_FIFO */ |
<> | 144:ef7eb2e8f9f7 | 481 | } |
<> | 144:ef7eb2e8f9f7 | 482 | |
<> | 144:ef7eb2e8f9f7 | 483 | void SPI_DisableInterrupts(SPI_Type *base, uint32_t mask) |
<> | 144:ef7eb2e8f9f7 | 484 | { |
<> | 144:ef7eb2e8f9f7 | 485 | /* Rx full interrupt */ |
<> | 144:ef7eb2e8f9f7 | 486 | if (mask & kSPI_RxFullAndModfInterruptEnable) |
<> | 144:ef7eb2e8f9f7 | 487 | { |
<> | 144:ef7eb2e8f9f7 | 488 | base->C1 &= (~SPI_C1_SPIE_MASK); |
<> | 144:ef7eb2e8f9f7 | 489 | } |
<> | 144:ef7eb2e8f9f7 | 490 | |
<> | 144:ef7eb2e8f9f7 | 491 | /* Tx empty interrupt */ |
<> | 144:ef7eb2e8f9f7 | 492 | if (mask & kSPI_TxEmptyInterruptEnable) |
<> | 144:ef7eb2e8f9f7 | 493 | { |
<> | 144:ef7eb2e8f9f7 | 494 | base->C1 &= (~SPI_C1_SPTIE_MASK); |
<> | 144:ef7eb2e8f9f7 | 495 | } |
<> | 144:ef7eb2e8f9f7 | 496 | |
<> | 144:ef7eb2e8f9f7 | 497 | /* Data match interrupt */ |
<> | 144:ef7eb2e8f9f7 | 498 | if (mask & kSPI_MatchInterruptEnable) |
<> | 144:ef7eb2e8f9f7 | 499 | { |
<> | 144:ef7eb2e8f9f7 | 500 | base->C2 &= (~SPI_C2_SPMIE_MASK); |
<> | 144:ef7eb2e8f9f7 | 501 | } |
<> | 144:ef7eb2e8f9f7 | 502 | |
<> | 144:ef7eb2e8f9f7 | 503 | #if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO |
<> | 144:ef7eb2e8f9f7 | 504 | if (FSL_FEATURE_SPI_FIFO_SIZEn(base) != 0) |
<> | 144:ef7eb2e8f9f7 | 505 | { |
<> | 144:ef7eb2e8f9f7 | 506 | /* Rx FIFO near full interrupt */ |
<> | 144:ef7eb2e8f9f7 | 507 | if (mask & kSPI_RxFifoNearFullInterruptEnable) |
<> | 144:ef7eb2e8f9f7 | 508 | { |
<> | 144:ef7eb2e8f9f7 | 509 | base->C3 &= ~SPI_C3_RNFULLIEN_MASK; |
<> | 144:ef7eb2e8f9f7 | 510 | } |
<> | 144:ef7eb2e8f9f7 | 511 | |
<> | 144:ef7eb2e8f9f7 | 512 | /* Tx FIFO near empty interrupt */ |
<> | 144:ef7eb2e8f9f7 | 513 | if (mask & kSPI_TxFifoNearEmptyInterruptEnable) |
<> | 144:ef7eb2e8f9f7 | 514 | { |
<> | 144:ef7eb2e8f9f7 | 515 | base->C3 &= ~SPI_C3_TNEARIEN_MASK; |
<> | 144:ef7eb2e8f9f7 | 516 | } |
<> | 144:ef7eb2e8f9f7 | 517 | } |
<> | 144:ef7eb2e8f9f7 | 518 | #endif /* FSL_FEATURE_SPI_HAS_FIFO */ |
<> | 144:ef7eb2e8f9f7 | 519 | } |
<> | 144:ef7eb2e8f9f7 | 520 | |
<> | 144:ef7eb2e8f9f7 | 521 | void SPI_MasterSetBaudRate(SPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) |
<> | 144:ef7eb2e8f9f7 | 522 | { |
<> | 144:ef7eb2e8f9f7 | 523 | uint32_t prescaler; |
<> | 144:ef7eb2e8f9f7 | 524 | uint32_t bestPrescaler; |
<> | 144:ef7eb2e8f9f7 | 525 | uint32_t rateDivisor; |
<> | 144:ef7eb2e8f9f7 | 526 | uint32_t bestDivisor; |
<> | 144:ef7eb2e8f9f7 | 527 | uint32_t rateDivisorValue; |
<> | 144:ef7eb2e8f9f7 | 528 | uint32_t realBaudrate; |
<> | 144:ef7eb2e8f9f7 | 529 | uint32_t diff; |
<> | 144:ef7eb2e8f9f7 | 530 | uint32_t min_diff; |
<> | 144:ef7eb2e8f9f7 | 531 | uint32_t freq = baudRate_Bps; |
<> | 144:ef7eb2e8f9f7 | 532 | |
<> | 144:ef7eb2e8f9f7 | 533 | /* Find combination of prescaler and scaler resulting in baudrate closest to the requested value */ |
<> | 144:ef7eb2e8f9f7 | 534 | min_diff = 0xFFFFFFFFU; |
<> | 144:ef7eb2e8f9f7 | 535 | |
<> | 144:ef7eb2e8f9f7 | 536 | /* Set the maximum divisor bit settings for each of the following divisors */ |
<> | 144:ef7eb2e8f9f7 | 537 | bestPrescaler = 7U; |
<> | 144:ef7eb2e8f9f7 | 538 | bestDivisor = 8U; |
<> | 144:ef7eb2e8f9f7 | 539 | |
<> | 144:ef7eb2e8f9f7 | 540 | /* In all for loops, if min_diff = 0, the exit for loop*/ |
<> | 144:ef7eb2e8f9f7 | 541 | for (prescaler = 0; (prescaler <= 7) && min_diff; prescaler++) |
<> | 144:ef7eb2e8f9f7 | 542 | { |
<> | 144:ef7eb2e8f9f7 | 543 | /* Initialize to div-by-2 */ |
<> | 144:ef7eb2e8f9f7 | 544 | rateDivisorValue = 2U; |
<> | 144:ef7eb2e8f9f7 | 545 | |
<> | 144:ef7eb2e8f9f7 | 546 | for (rateDivisor = 0; (rateDivisor <= 8U) && min_diff; rateDivisor++) |
<> | 144:ef7eb2e8f9f7 | 547 | { |
<> | 144:ef7eb2e8f9f7 | 548 | /* Calculate actual baud rate, note need to add 1 to prescaler */ |
<> | 144:ef7eb2e8f9f7 | 549 | realBaudrate = ((srcClock_Hz) / ((prescaler + 1) * rateDivisorValue)); |
<> | 144:ef7eb2e8f9f7 | 550 | |
<> | 144:ef7eb2e8f9f7 | 551 | /* Calculate the baud rate difference based on the conditional statement ,that states that the |
<> | 144:ef7eb2e8f9f7 | 552 | calculated baud rate must not exceed the desired baud rate */ |
<> | 144:ef7eb2e8f9f7 | 553 | if (freq >= realBaudrate) |
<> | 144:ef7eb2e8f9f7 | 554 | { |
<> | 144:ef7eb2e8f9f7 | 555 | diff = freq - realBaudrate; |
<> | 144:ef7eb2e8f9f7 | 556 | if (min_diff > diff) |
<> | 144:ef7eb2e8f9f7 | 557 | { |
<> | 144:ef7eb2e8f9f7 | 558 | /* A better match found */ |
<> | 144:ef7eb2e8f9f7 | 559 | min_diff = diff; |
<> | 144:ef7eb2e8f9f7 | 560 | bestPrescaler = prescaler; |
<> | 144:ef7eb2e8f9f7 | 561 | bestDivisor = rateDivisor; |
<> | 144:ef7eb2e8f9f7 | 562 | } |
<> | 144:ef7eb2e8f9f7 | 563 | } |
<> | 144:ef7eb2e8f9f7 | 564 | |
<> | 144:ef7eb2e8f9f7 | 565 | /* Multiply by 2 for each iteration, possible divisor values: 2, 4, 8, 16, ... 512 */ |
<> | 144:ef7eb2e8f9f7 | 566 | rateDivisorValue *= 2U; |
<> | 144:ef7eb2e8f9f7 | 567 | } |
<> | 144:ef7eb2e8f9f7 | 568 | } |
<> | 144:ef7eb2e8f9f7 | 569 | |
<> | 144:ef7eb2e8f9f7 | 570 | /* Write the best prescalar and baud rate scalar */ |
<> | 144:ef7eb2e8f9f7 | 571 | base->BR = SPI_BR_SPR(bestDivisor) | SPI_BR_SPPR(bestPrescaler); |
<> | 144:ef7eb2e8f9f7 | 572 | } |
<> | 144:ef7eb2e8f9f7 | 573 | |
<> | 144:ef7eb2e8f9f7 | 574 | void SPI_WriteBlocking(SPI_Type *base, uint8_t *buffer, size_t size) |
<> | 144:ef7eb2e8f9f7 | 575 | { |
<> | 144:ef7eb2e8f9f7 | 576 | uint32_t i = 0; |
<> | 144:ef7eb2e8f9f7 | 577 | uint8_t bytesPerFrame = 1U; |
<> | 144:ef7eb2e8f9f7 | 578 | |
<> | 144:ef7eb2e8f9f7 | 579 | #if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS |
<> | 144:ef7eb2e8f9f7 | 580 | /* Check if 16 bits or 8 bits */ |
<> | 144:ef7eb2e8f9f7 | 581 | bytesPerFrame = ((base->C2 & SPI_C2_SPIMODE_MASK) >> SPI_C2_SPIMODE_SHIFT) + 1U; |
<> | 144:ef7eb2e8f9f7 | 582 | #endif |
<> | 144:ef7eb2e8f9f7 | 583 | |
<> | 144:ef7eb2e8f9f7 | 584 | while (i < size) |
<> | 144:ef7eb2e8f9f7 | 585 | { |
<> | 144:ef7eb2e8f9f7 | 586 | while ((base->S & SPI_S_SPTEF_MASK) == 0) |
<> | 144:ef7eb2e8f9f7 | 587 | { |
<> | 144:ef7eb2e8f9f7 | 588 | } |
<> | 144:ef7eb2e8f9f7 | 589 | |
<> | 144:ef7eb2e8f9f7 | 590 | /* Send a frame of data */ |
<> | 144:ef7eb2e8f9f7 | 591 | SPI_WriteNonBlocking(base, buffer, bytesPerFrame); |
<> | 144:ef7eb2e8f9f7 | 592 | |
<> | 144:ef7eb2e8f9f7 | 593 | i += bytesPerFrame; |
<> | 144:ef7eb2e8f9f7 | 594 | buffer += bytesPerFrame; |
<> | 144:ef7eb2e8f9f7 | 595 | } |
<> | 144:ef7eb2e8f9f7 | 596 | } |
<> | 144:ef7eb2e8f9f7 | 597 | |
<> | 144:ef7eb2e8f9f7 | 598 | #if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO |
<> | 144:ef7eb2e8f9f7 | 599 | void SPI_EnableFIFO(SPI_Type *base, bool enable) |
<> | 144:ef7eb2e8f9f7 | 600 | { |
<> | 144:ef7eb2e8f9f7 | 601 | if (FSL_FEATURE_SPI_FIFO_SIZEn(base) != 0U) |
<> | 144:ef7eb2e8f9f7 | 602 | { |
<> | 144:ef7eb2e8f9f7 | 603 | if (enable) |
<> | 144:ef7eb2e8f9f7 | 604 | { |
<> | 144:ef7eb2e8f9f7 | 605 | base->C3 |= SPI_C3_FIFOMODE_MASK; |
<> | 144:ef7eb2e8f9f7 | 606 | } |
<> | 144:ef7eb2e8f9f7 | 607 | else |
<> | 144:ef7eb2e8f9f7 | 608 | { |
<> | 144:ef7eb2e8f9f7 | 609 | base->C3 &= ~SPI_C3_FIFOMODE_MASK; |
<> | 144:ef7eb2e8f9f7 | 610 | } |
<> | 144:ef7eb2e8f9f7 | 611 | } |
<> | 144:ef7eb2e8f9f7 | 612 | } |
<> | 144:ef7eb2e8f9f7 | 613 | #endif /* FSL_FEATURE_SPI_HAS_FIFO */ |
<> | 144:ef7eb2e8f9f7 | 614 | |
<> | 144:ef7eb2e8f9f7 | 615 | void SPI_WriteData(SPI_Type *base, uint16_t data) |
<> | 144:ef7eb2e8f9f7 | 616 | { |
<> | 144:ef7eb2e8f9f7 | 617 | #if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && (FSL_FEATURE_SPI_16BIT_TRANSFERS) |
<> | 144:ef7eb2e8f9f7 | 618 | base->DL = data & 0xFFU; |
<> | 144:ef7eb2e8f9f7 | 619 | base->DH = (data >> 8U) & 0xFFU; |
<> | 144:ef7eb2e8f9f7 | 620 | #else |
<> | 144:ef7eb2e8f9f7 | 621 | base->D = data & 0xFFU; |
<> | 144:ef7eb2e8f9f7 | 622 | #endif |
<> | 144:ef7eb2e8f9f7 | 623 | } |
<> | 144:ef7eb2e8f9f7 | 624 | |
<> | 144:ef7eb2e8f9f7 | 625 | uint16_t SPI_ReadData(SPI_Type *base) |
<> | 144:ef7eb2e8f9f7 | 626 | { |
<> | 144:ef7eb2e8f9f7 | 627 | uint16_t val = 0; |
<> | 144:ef7eb2e8f9f7 | 628 | #if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && (FSL_FEATURE_SPI_16BIT_TRANSFERS) |
<> | 144:ef7eb2e8f9f7 | 629 | val = base->DL; |
<> | 144:ef7eb2e8f9f7 | 630 | val |= (uint16_t)((uint16_t)(base->DH) << 8U); |
<> | 144:ef7eb2e8f9f7 | 631 | #else |
<> | 144:ef7eb2e8f9f7 | 632 | val = base->D; |
<> | 144:ef7eb2e8f9f7 | 633 | #endif |
<> | 144:ef7eb2e8f9f7 | 634 | return val; |
<> | 144:ef7eb2e8f9f7 | 635 | } |
<> | 144:ef7eb2e8f9f7 | 636 | |
<> | 144:ef7eb2e8f9f7 | 637 | status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer) |
<> | 144:ef7eb2e8f9f7 | 638 | { |
<> | 144:ef7eb2e8f9f7 | 639 | assert(xfer); |
<> | 144:ef7eb2e8f9f7 | 640 | |
<> | 144:ef7eb2e8f9f7 | 641 | uint8_t bytesPerFrame = 1U; |
<> | 144:ef7eb2e8f9f7 | 642 | |
<> | 144:ef7eb2e8f9f7 | 643 | /* Check if the argument is legal */ |
<> | 144:ef7eb2e8f9f7 | 644 | if ((xfer->txData == NULL) && (xfer->rxData == NULL)) |
<> | 144:ef7eb2e8f9f7 | 645 | { |
<> | 144:ef7eb2e8f9f7 | 646 | return kStatus_InvalidArgument; |
<> | 144:ef7eb2e8f9f7 | 647 | } |
<> | 144:ef7eb2e8f9f7 | 648 | |
<> | 144:ef7eb2e8f9f7 | 649 | #if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && FSL_FEATURE_SPI_16BIT_TRANSFERS |
<> | 144:ef7eb2e8f9f7 | 650 | /* Check if 16 bits or 8 bits */ |
<> | 144:ef7eb2e8f9f7 | 651 | bytesPerFrame = ((base->C2 & SPI_C2_SPIMODE_MASK) >> SPI_C2_SPIMODE_SHIFT) + 1U; |
<> | 144:ef7eb2e8f9f7 | 652 | #endif |
<> | 144:ef7eb2e8f9f7 | 653 | |
<> | 144:ef7eb2e8f9f7 | 654 | /* Disable SPI and then enable it, this is used to clear S register */ |
<> | 144:ef7eb2e8f9f7 | 655 | base->C1 &= ~SPI_C1_SPE_MASK; |
<> | 144:ef7eb2e8f9f7 | 656 | base->C1 |= SPI_C1_SPE_MASK; |
<> | 144:ef7eb2e8f9f7 | 657 | |
<> | 144:ef7eb2e8f9f7 | 658 | #if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO |
<> | 144:ef7eb2e8f9f7 | 659 | |
<> | 144:ef7eb2e8f9f7 | 660 | /* Disable FIFO, as the FIFO may cause data loss if the data size is not integer |
<> | 144:ef7eb2e8f9f7 | 661 | times of 2bytes. As SPI cannot set watermark to 0, only can set to 1/2 FIFO size or 3/4 FIFO |
<> | 144:ef7eb2e8f9f7 | 662 | size. */ |
<> | 144:ef7eb2e8f9f7 | 663 | if (FSL_FEATURE_SPI_FIFO_SIZEn(base) != 0) |
<> | 144:ef7eb2e8f9f7 | 664 | { |
<> | 144:ef7eb2e8f9f7 | 665 | base->C3 &= ~SPI_C3_FIFOMODE_MASK; |
<> | 144:ef7eb2e8f9f7 | 666 | } |
<> | 144:ef7eb2e8f9f7 | 667 | |
<> | 144:ef7eb2e8f9f7 | 668 | #endif /* FSL_FEATURE_SPI_HAS_FIFO */ |
<> | 144:ef7eb2e8f9f7 | 669 | |
<> | 144:ef7eb2e8f9f7 | 670 | /* Begin the polling transfer until all data sent */ |
<> | 144:ef7eb2e8f9f7 | 671 | while (xfer->dataSize > 0) |
<> | 144:ef7eb2e8f9f7 | 672 | { |
<> | 144:ef7eb2e8f9f7 | 673 | /* Data send */ |
<> | 144:ef7eb2e8f9f7 | 674 | while ((base->S & SPI_S_SPTEF_MASK) == 0U) |
<> | 144:ef7eb2e8f9f7 | 675 | { |
<> | 144:ef7eb2e8f9f7 | 676 | } |
<> | 144:ef7eb2e8f9f7 | 677 | SPI_WriteNonBlocking(base, xfer->txData, bytesPerFrame); |
<> | 144:ef7eb2e8f9f7 | 678 | if (xfer->txData) |
<> | 144:ef7eb2e8f9f7 | 679 | { |
<> | 144:ef7eb2e8f9f7 | 680 | xfer->txData += bytesPerFrame; |
<> | 144:ef7eb2e8f9f7 | 681 | } |
<> | 144:ef7eb2e8f9f7 | 682 | |
<> | 144:ef7eb2e8f9f7 | 683 | while ((base->S & SPI_S_SPRF_MASK) == 0U) |
<> | 144:ef7eb2e8f9f7 | 684 | { |
<> | 144:ef7eb2e8f9f7 | 685 | } |
<> | 144:ef7eb2e8f9f7 | 686 | SPI_ReadNonBlocking(base, xfer->rxData, bytesPerFrame); |
<> | 144:ef7eb2e8f9f7 | 687 | if (xfer->rxData) |
<> | 144:ef7eb2e8f9f7 | 688 | { |
<> | 144:ef7eb2e8f9f7 | 689 | xfer->rxData += bytesPerFrame; |
<> | 144:ef7eb2e8f9f7 | 690 | } |
<> | 144:ef7eb2e8f9f7 | 691 | |
<> | 144:ef7eb2e8f9f7 | 692 | /* Decrease the number */ |
<> | 144:ef7eb2e8f9f7 | 693 | xfer->dataSize -= bytesPerFrame; |
<> | 144:ef7eb2e8f9f7 | 694 | } |
<> | 144:ef7eb2e8f9f7 | 695 | |
<> | 144:ef7eb2e8f9f7 | 696 | return kStatus_Success; |
<> | 144:ef7eb2e8f9f7 | 697 | } |
<> | 144:ef7eb2e8f9f7 | 698 | |
<> | 144:ef7eb2e8f9f7 | 699 | void SPI_MasterTransferCreateHandle(SPI_Type *base, |
<> | 144:ef7eb2e8f9f7 | 700 | spi_master_handle_t *handle, |
<> | 144:ef7eb2e8f9f7 | 701 | spi_master_callback_t callback, |
<> | 144:ef7eb2e8f9f7 | 702 | void *userData) |
<> | 144:ef7eb2e8f9f7 | 703 | { |
<> | 144:ef7eb2e8f9f7 | 704 | assert(handle); |
<> | 144:ef7eb2e8f9f7 | 705 | |
<> | 144:ef7eb2e8f9f7 | 706 | uint8_t instance = SPI_GetInstance(base); |
<> | 144:ef7eb2e8f9f7 | 707 | |
<> | 144:ef7eb2e8f9f7 | 708 | /* Initialize the handle */ |
<> | 144:ef7eb2e8f9f7 | 709 | s_spiHandle[instance] = handle; |
<> | 144:ef7eb2e8f9f7 | 710 | handle->callback = callback; |
<> | 144:ef7eb2e8f9f7 | 711 | handle->userData = userData; |
<> | 144:ef7eb2e8f9f7 | 712 | s_spiIsr = SPI_MasterTransferHandleIRQ; |
<> | 144:ef7eb2e8f9f7 | 713 | |
<> | 144:ef7eb2e8f9f7 | 714 | #if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO |
<> | 144:ef7eb2e8f9f7 | 715 | uint8_t txSize = 0U; |
<> | 144:ef7eb2e8f9f7 | 716 | /* Get the number to be sent if there is FIFO */ |
<> | 144:ef7eb2e8f9f7 | 717 | if (FSL_FEATURE_SPI_FIFO_SIZEn(base) != 0) |
<> | 144:ef7eb2e8f9f7 | 718 | { |
<> | 144:ef7eb2e8f9f7 | 719 | txSize = (base->C3 & SPI_C3_TNEAREF_MARK_MASK) >> SPI_C3_TNEAREF_MARK_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 720 | if (txSize == 0U) |
<> | 144:ef7eb2e8f9f7 | 721 | { |
<> | 144:ef7eb2e8f9f7 | 722 | handle->watermark = FSL_FEATURE_SPI_FIFO_SIZEn(base) * 3U / 4U; |
<> | 144:ef7eb2e8f9f7 | 723 | } |
<> | 144:ef7eb2e8f9f7 | 724 | else |
<> | 144:ef7eb2e8f9f7 | 725 | { |
<> | 144:ef7eb2e8f9f7 | 726 | handle->watermark = FSL_FEATURE_SPI_FIFO_SIZEn(base) / 2U; |
<> | 144:ef7eb2e8f9f7 | 727 | } |
<> | 144:ef7eb2e8f9f7 | 728 | } |
<> | 144:ef7eb2e8f9f7 | 729 | /* If no FIFO, just set the watermark to 1 */ |
<> | 144:ef7eb2e8f9f7 | 730 | else |
<> | 144:ef7eb2e8f9f7 | 731 | { |
<> | 144:ef7eb2e8f9f7 | 732 | handle->watermark = 1U; |
<> | 144:ef7eb2e8f9f7 | 733 | } |
<> | 144:ef7eb2e8f9f7 | 734 | #else |
<> | 144:ef7eb2e8f9f7 | 735 | handle->watermark = 1U; |
<> | 144:ef7eb2e8f9f7 | 736 | #endif /* FSL_FEATURE_SPI_HAS_FIFO */ |
<> | 144:ef7eb2e8f9f7 | 737 | |
<> | 144:ef7eb2e8f9f7 | 738 | /* Get the bytes per frame */ |
<> | 144:ef7eb2e8f9f7 | 739 | #if defined(FSL_FEATURE_SPI_16BIT_TRANSFERS) && (FSL_FEATURE_SPI_16BIT_TRANSFERS) |
<> | 144:ef7eb2e8f9f7 | 740 | handle->bytePerFrame = ((base->C2 & SPI_C2_SPIMODE_MASK) >> SPI_C2_SPIMODE_SHIFT) + 1U; |
<> | 144:ef7eb2e8f9f7 | 741 | #else |
<> | 144:ef7eb2e8f9f7 | 742 | handle->bytePerFrame = 1U; |
<> | 144:ef7eb2e8f9f7 | 743 | #endif |
<> | 144:ef7eb2e8f9f7 | 744 | |
<> | 144:ef7eb2e8f9f7 | 745 | /* Enable SPI NVIC */ |
<> | 144:ef7eb2e8f9f7 | 746 | EnableIRQ(s_spiIRQ[instance]); |
<> | 144:ef7eb2e8f9f7 | 747 | } |
<> | 144:ef7eb2e8f9f7 | 748 | |
<> | 144:ef7eb2e8f9f7 | 749 | status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer) |
<> | 144:ef7eb2e8f9f7 | 750 | { |
<> | 144:ef7eb2e8f9f7 | 751 | assert(handle && xfer); |
<> | 144:ef7eb2e8f9f7 | 752 | |
<> | 144:ef7eb2e8f9f7 | 753 | /* Check if SPI is busy */ |
<> | 144:ef7eb2e8f9f7 | 754 | if (handle->state == kSPI_Busy) |
<> | 144:ef7eb2e8f9f7 | 755 | { |
<> | 144:ef7eb2e8f9f7 | 756 | return kStatus_SPI_Busy; |
<> | 144:ef7eb2e8f9f7 | 757 | } |
<> | 144:ef7eb2e8f9f7 | 758 | |
<> | 144:ef7eb2e8f9f7 | 759 | /* Check if the input arguments valid */ |
<> | 144:ef7eb2e8f9f7 | 760 | if (((xfer->txData == NULL) && (xfer->rxData == NULL)) || (xfer->dataSize == 0U)) |
<> | 144:ef7eb2e8f9f7 | 761 | { |
<> | 144:ef7eb2e8f9f7 | 762 | return kStatus_InvalidArgument; |
<> | 144:ef7eb2e8f9f7 | 763 | } |
<> | 144:ef7eb2e8f9f7 | 764 | |
<> | 144:ef7eb2e8f9f7 | 765 | /* Set the handle information */ |
<> | 144:ef7eb2e8f9f7 | 766 | handle->txData = xfer->txData; |
<> | 144:ef7eb2e8f9f7 | 767 | handle->rxData = xfer->rxData; |
<> | 144:ef7eb2e8f9f7 | 768 | handle->transferSize = xfer->dataSize; |
<> | 144:ef7eb2e8f9f7 | 769 | handle->txRemainingBytes = xfer->dataSize; |
<> | 144:ef7eb2e8f9f7 | 770 | handle->rxRemainingBytes = xfer->dataSize; |
<> | 144:ef7eb2e8f9f7 | 771 | |
<> | 144:ef7eb2e8f9f7 | 772 | /* Set the SPI state to busy */ |
<> | 144:ef7eb2e8f9f7 | 773 | handle->state = kSPI_Busy; |
<> | 144:ef7eb2e8f9f7 | 774 | |
<> | 144:ef7eb2e8f9f7 | 775 | /* Disable SPI and then enable it, this is used to clear S register*/ |
<> | 144:ef7eb2e8f9f7 | 776 | base->C1 &= ~SPI_C1_SPE_MASK; |
<> | 144:ef7eb2e8f9f7 | 777 | base->C1 |= SPI_C1_SPE_MASK; |
<> | 144:ef7eb2e8f9f7 | 778 | |
<> | 144:ef7eb2e8f9f7 | 779 | /* Enable Interrupt, only enable Rx interrupt, use rx interrupt to driver SPI transfer */ |
<> | 144:ef7eb2e8f9f7 | 780 | #if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO |
<> | 144:ef7eb2e8f9f7 | 781 | if (handle->watermark > 1U) |
<> | 144:ef7eb2e8f9f7 | 782 | { |
<> | 144:ef7eb2e8f9f7 | 783 | /* Enable Rx near full interrupt */ |
<> | 144:ef7eb2e8f9f7 | 784 | SPI_EnableInterrupts(base, kSPI_RxFifoNearFullInterruptEnable); |
<> | 144:ef7eb2e8f9f7 | 785 | } |
<> | 144:ef7eb2e8f9f7 | 786 | else |
<> | 144:ef7eb2e8f9f7 | 787 | { |
<> | 144:ef7eb2e8f9f7 | 788 | SPI_EnableInterrupts(base, kSPI_RxFullAndModfInterruptEnable); |
<> | 144:ef7eb2e8f9f7 | 789 | } |
<> | 144:ef7eb2e8f9f7 | 790 | #else |
<> | 144:ef7eb2e8f9f7 | 791 | SPI_EnableInterrupts(base, kSPI_RxFullAndModfInterruptEnable); |
<> | 144:ef7eb2e8f9f7 | 792 | #endif |
<> | 144:ef7eb2e8f9f7 | 793 | |
<> | 144:ef7eb2e8f9f7 | 794 | /* First send a piece of data to Tx Data or FIFO to start a SPI transfer */ |
<> | 144:ef7eb2e8f9f7 | 795 | SPI_SendTransfer(base, handle); |
<> | 144:ef7eb2e8f9f7 | 796 | |
<> | 144:ef7eb2e8f9f7 | 797 | return kStatus_Success; |
<> | 144:ef7eb2e8f9f7 | 798 | } |
<> | 144:ef7eb2e8f9f7 | 799 | |
<> | 144:ef7eb2e8f9f7 | 800 | status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count) |
<> | 144:ef7eb2e8f9f7 | 801 | { |
<> | 144:ef7eb2e8f9f7 | 802 | assert(handle); |
<> | 144:ef7eb2e8f9f7 | 803 | |
<> | 144:ef7eb2e8f9f7 | 804 | status_t status = kStatus_Success; |
<> | 144:ef7eb2e8f9f7 | 805 | |
<> | 144:ef7eb2e8f9f7 | 806 | if (handle->state != kStatus_SPI_Busy) |
<> | 144:ef7eb2e8f9f7 | 807 | { |
<> | 144:ef7eb2e8f9f7 | 808 | status = kStatus_NoTransferInProgress; |
<> | 144:ef7eb2e8f9f7 | 809 | } |
<> | 144:ef7eb2e8f9f7 | 810 | else |
<> | 144:ef7eb2e8f9f7 | 811 | { |
<> | 144:ef7eb2e8f9f7 | 812 | /* Return remaing bytes in different cases */ |
<> | 144:ef7eb2e8f9f7 | 813 | if (handle->rxData) |
<> | 144:ef7eb2e8f9f7 | 814 | { |
<> | 144:ef7eb2e8f9f7 | 815 | *count = handle->transferSize - handle->rxRemainingBytes; |
<> | 144:ef7eb2e8f9f7 | 816 | } |
<> | 144:ef7eb2e8f9f7 | 817 | else |
<> | 144:ef7eb2e8f9f7 | 818 | { |
<> | 144:ef7eb2e8f9f7 | 819 | *count = handle->transferSize - handle->txRemainingBytes; |
<> | 144:ef7eb2e8f9f7 | 820 | } |
<> | 144:ef7eb2e8f9f7 | 821 | } |
<> | 144:ef7eb2e8f9f7 | 822 | |
<> | 144:ef7eb2e8f9f7 | 823 | return status; |
<> | 144:ef7eb2e8f9f7 | 824 | } |
<> | 144:ef7eb2e8f9f7 | 825 | |
<> | 144:ef7eb2e8f9f7 | 826 | void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle) |
<> | 144:ef7eb2e8f9f7 | 827 | { |
<> | 144:ef7eb2e8f9f7 | 828 | assert(handle); |
<> | 144:ef7eb2e8f9f7 | 829 | |
<> | 144:ef7eb2e8f9f7 | 830 | /* Stop interrupts */ |
<> | 144:ef7eb2e8f9f7 | 831 | #if defined(FSL_FEATURE_SPI_HAS_FIFO) && FSL_FEATURE_SPI_HAS_FIFO |
<> | 144:ef7eb2e8f9f7 | 832 | if (handle->watermark > 1U) |
<> | 144:ef7eb2e8f9f7 | 833 | { |
<> | 144:ef7eb2e8f9f7 | 834 | SPI_DisableInterrupts(base, kSPI_RxFifoNearFullInterruptEnable | kSPI_RxFullAndModfInterruptEnable); |
<> | 144:ef7eb2e8f9f7 | 835 | } |
<> | 144:ef7eb2e8f9f7 | 836 | else |
<> | 144:ef7eb2e8f9f7 | 837 | { |
<> | 144:ef7eb2e8f9f7 | 838 | SPI_DisableInterrupts(base, kSPI_RxFullAndModfInterruptEnable); |
<> | 144:ef7eb2e8f9f7 | 839 | } |
<> | 144:ef7eb2e8f9f7 | 840 | #else |
<> | 144:ef7eb2e8f9f7 | 841 | SPI_DisableInterrupts(base, kSPI_RxFullAndModfInterruptEnable); |
<> | 144:ef7eb2e8f9f7 | 842 | #endif |
<> | 144:ef7eb2e8f9f7 | 843 | |
<> | 144:ef7eb2e8f9f7 | 844 | /* Transfer finished, set the state to Done*/ |
<> | 144:ef7eb2e8f9f7 | 845 | handle->state = kSPI_Idle; |
<> | 144:ef7eb2e8f9f7 | 846 | |
<> | 144:ef7eb2e8f9f7 | 847 | /* Clear the internal state */ |
<> | 144:ef7eb2e8f9f7 | 848 | handle->rxRemainingBytes = 0; |
<> | 144:ef7eb2e8f9f7 | 849 | handle->txRemainingBytes = 0; |
<> | 144:ef7eb2e8f9f7 | 850 | } |
<> | 144:ef7eb2e8f9f7 | 851 | |
<> | 144:ef7eb2e8f9f7 | 852 | void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle) |
<> | 144:ef7eb2e8f9f7 | 853 | { |
<> | 144:ef7eb2e8f9f7 | 854 | assert(handle); |
<> | 144:ef7eb2e8f9f7 | 855 | |
<> | 144:ef7eb2e8f9f7 | 856 | /* If needs to receive data, do a receive */ |
<> | 144:ef7eb2e8f9f7 | 857 | if (handle->rxRemainingBytes) |
<> | 144:ef7eb2e8f9f7 | 858 | { |
<> | 144:ef7eb2e8f9f7 | 859 | SPI_ReceiveTransfer(base, handle); |
<> | 144:ef7eb2e8f9f7 | 860 | } |
<> | 144:ef7eb2e8f9f7 | 861 | |
<> | 144:ef7eb2e8f9f7 | 862 | /* We always need to send a data to make the SPI run */ |
<> | 144:ef7eb2e8f9f7 | 863 | if (handle->txRemainingBytes) |
<> | 144:ef7eb2e8f9f7 | 864 | { |
<> | 144:ef7eb2e8f9f7 | 865 | SPI_SendTransfer(base, handle); |
<> | 144:ef7eb2e8f9f7 | 866 | } |
<> | 144:ef7eb2e8f9f7 | 867 | |
<> | 144:ef7eb2e8f9f7 | 868 | /* All the transfer finished */ |
<> | 144:ef7eb2e8f9f7 | 869 | if ((handle->txRemainingBytes == 0) && (handle->rxRemainingBytes == 0)) |
<> | 144:ef7eb2e8f9f7 | 870 | { |
<> | 144:ef7eb2e8f9f7 | 871 | /* Complete the transfer */ |
<> | 144:ef7eb2e8f9f7 | 872 | SPI_MasterTransferAbort(base, handle); |
<> | 144:ef7eb2e8f9f7 | 873 | |
<> | 144:ef7eb2e8f9f7 | 874 | if (handle->callback) |
<> | 144:ef7eb2e8f9f7 | 875 | { |
<> | 144:ef7eb2e8f9f7 | 876 | (handle->callback)(base, handle, kStatus_SPI_Idle, handle->userData); |
<> | 144:ef7eb2e8f9f7 | 877 | } |
<> | 144:ef7eb2e8f9f7 | 878 | } |
<> | 144:ef7eb2e8f9f7 | 879 | } |
<> | 144:ef7eb2e8f9f7 | 880 | |
<> | 144:ef7eb2e8f9f7 | 881 | void SPI_SlaveTransferCreateHandle(SPI_Type *base, |
<> | 144:ef7eb2e8f9f7 | 882 | spi_slave_handle_t *handle, |
<> | 144:ef7eb2e8f9f7 | 883 | spi_slave_callback_t callback, |
<> | 144:ef7eb2e8f9f7 | 884 | void *userData) |
<> | 144:ef7eb2e8f9f7 | 885 | { |
<> | 144:ef7eb2e8f9f7 | 886 | assert(handle); |
<> | 144:ef7eb2e8f9f7 | 887 | |
<> | 144:ef7eb2e8f9f7 | 888 | /* Slave create handle share same logic with master create handle, the only difference |
<> | 144:ef7eb2e8f9f7 | 889 | is the Isr pointer. */ |
<> | 144:ef7eb2e8f9f7 | 890 | SPI_MasterTransferCreateHandle(base, handle, callback, userData); |
<> | 144:ef7eb2e8f9f7 | 891 | s_spiIsr = SPI_SlaveTransferHandleIRQ; |
<> | 144:ef7eb2e8f9f7 | 892 | } |
<> | 144:ef7eb2e8f9f7 | 893 | |
<> | 144:ef7eb2e8f9f7 | 894 | void SPI_SlaveTransferHandleIRQ(SPI_Type *base, spi_slave_handle_t *handle) |
<> | 144:ef7eb2e8f9f7 | 895 | { |
<> | 144:ef7eb2e8f9f7 | 896 | assert(handle); |
<> | 144:ef7eb2e8f9f7 | 897 | |
<> | 144:ef7eb2e8f9f7 | 898 | /* Do data send first in case of data missing. */ |
<> | 144:ef7eb2e8f9f7 | 899 | if (handle->txRemainingBytes) |
<> | 144:ef7eb2e8f9f7 | 900 | { |
<> | 144:ef7eb2e8f9f7 | 901 | SPI_SendTransfer(base, handle); |
<> | 144:ef7eb2e8f9f7 | 902 | } |
<> | 144:ef7eb2e8f9f7 | 903 | |
<> | 144:ef7eb2e8f9f7 | 904 | /* If needs to receive data, do a receive */ |
<> | 144:ef7eb2e8f9f7 | 905 | if (handle->rxRemainingBytes) |
<> | 144:ef7eb2e8f9f7 | 906 | { |
<> | 144:ef7eb2e8f9f7 | 907 | SPI_ReceiveTransfer(base, handle); |
<> | 144:ef7eb2e8f9f7 | 908 | } |
<> | 144:ef7eb2e8f9f7 | 909 | |
<> | 144:ef7eb2e8f9f7 | 910 | /* All the transfer finished */ |
<> | 144:ef7eb2e8f9f7 | 911 | if ((handle->txRemainingBytes == 0) && (handle->rxRemainingBytes == 0)) |
<> | 144:ef7eb2e8f9f7 | 912 | { |
<> | 144:ef7eb2e8f9f7 | 913 | /* Complete the transfer */ |
<> | 144:ef7eb2e8f9f7 | 914 | SPI_SlaveTransferAbort(base, handle); |
<> | 144:ef7eb2e8f9f7 | 915 | |
<> | 144:ef7eb2e8f9f7 | 916 | if (handle->callback) |
<> | 144:ef7eb2e8f9f7 | 917 | { |
<> | 144:ef7eb2e8f9f7 | 918 | (handle->callback)(base, handle, kStatus_SPI_Idle, handle->userData); |
<> | 144:ef7eb2e8f9f7 | 919 | } |
<> | 144:ef7eb2e8f9f7 | 920 | } |
<> | 144:ef7eb2e8f9f7 | 921 | } |
<> | 144:ef7eb2e8f9f7 | 922 | |
<> | 144:ef7eb2e8f9f7 | 923 | #if defined(SPI0) |
<> | 144:ef7eb2e8f9f7 | 924 | void SPI0_DriverIRQHandler(void) |
<> | 144:ef7eb2e8f9f7 | 925 | { |
<> | 144:ef7eb2e8f9f7 | 926 | assert(s_spiHandle[0]); |
<> | 144:ef7eb2e8f9f7 | 927 | s_spiIsr(SPI0, s_spiHandle[0]); |
<> | 144:ef7eb2e8f9f7 | 928 | } |
<> | 144:ef7eb2e8f9f7 | 929 | #endif |
<> | 144:ef7eb2e8f9f7 | 930 | |
<> | 144:ef7eb2e8f9f7 | 931 | #if defined(SPI1) |
<> | 144:ef7eb2e8f9f7 | 932 | void SPI1_DriverIRQHandler(void) |
<> | 144:ef7eb2e8f9f7 | 933 | { |
<> | 144:ef7eb2e8f9f7 | 934 | assert(s_spiHandle[1]); |
<> | 144:ef7eb2e8f9f7 | 935 | s_spiIsr(SPI1, s_spiHandle[1]); |
<> | 144:ef7eb2e8f9f7 | 936 | } |
<> | 144:ef7eb2e8f9f7 | 937 | #endif |
<> | 144:ef7eb2e8f9f7 | 938 | |
<> | 144:ef7eb2e8f9f7 | 939 | #if defined(SPI2) |
<> | 144:ef7eb2e8f9f7 | 940 | void SPI2_DriverIRQHandler(void) |
<> | 144:ef7eb2e8f9f7 | 941 | { |
<> | 144:ef7eb2e8f9f7 | 942 | assert(s_spiHandle[2]); |
<> | 144:ef7eb2e8f9f7 | 943 | s_spiIsr(SPI0, s_spiHandle[2]); |
<> | 144:ef7eb2e8f9f7 | 944 | } |
<> | 144:ef7eb2e8f9f7 | 945 | #endif |