added prescaler for 16 bit pwm in LPC1347 target
Fork of mbed-dev by
targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/drivers/fsl_smc.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)
- Committer:
- <>
- Date:
- Fri Sep 02 15:07:44 2016 +0100
- Revision:
- 144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /* |
<> | 144:ef7eb2e8f9f7 | 2 | * Copyright (c) 2015, Freescale Semiconductor, Inc. |
<> | 144:ef7eb2e8f9f7 | 3 | * All rights reserved. |
<> | 144:ef7eb2e8f9f7 | 4 | * |
<> | 144:ef7eb2e8f9f7 | 5 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 144:ef7eb2e8f9f7 | 6 | * are permitted provided that the following conditions are met: |
<> | 144:ef7eb2e8f9f7 | 7 | * |
<> | 144:ef7eb2e8f9f7 | 8 | * o Redistributions of source code must retain the above copyright notice, this list |
<> | 144:ef7eb2e8f9f7 | 9 | * of conditions and the following disclaimer. |
<> | 144:ef7eb2e8f9f7 | 10 | * |
<> | 144:ef7eb2e8f9f7 | 11 | * o Redistributions in binary form must reproduce the above copyright notice, this |
<> | 144:ef7eb2e8f9f7 | 12 | * list of conditions and the following disclaimer in the documentation and/or |
<> | 144:ef7eb2e8f9f7 | 13 | * other materials provided with the distribution. |
<> | 144:ef7eb2e8f9f7 | 14 | * |
<> | 144:ef7eb2e8f9f7 | 15 | * o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
<> | 144:ef7eb2e8f9f7 | 16 | * contributors may be used to endorse or promote products derived from this |
<> | 144:ef7eb2e8f9f7 | 17 | * software without specific prior written permission. |
<> | 144:ef7eb2e8f9f7 | 18 | * |
<> | 144:ef7eb2e8f9f7 | 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
<> | 144:ef7eb2e8f9f7 | 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
<> | 144:ef7eb2e8f9f7 | 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 144:ef7eb2e8f9f7 | 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
<> | 144:ef7eb2e8f9f7 | 23 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
<> | 144:ef7eb2e8f9f7 | 24 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
<> | 144:ef7eb2e8f9f7 | 25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
<> | 144:ef7eb2e8f9f7 | 26 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
<> | 144:ef7eb2e8f9f7 | 27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
<> | 144:ef7eb2e8f9f7 | 28 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 144:ef7eb2e8f9f7 | 29 | */ |
<> | 144:ef7eb2e8f9f7 | 30 | |
<> | 144:ef7eb2e8f9f7 | 31 | #include "fsl_smc.h" |
<> | 144:ef7eb2e8f9f7 | 32 | |
<> | 144:ef7eb2e8f9f7 | 33 | #if (defined(FSL_FEATURE_SMC_HAS_PARAM) && FSL_FEATURE_SMC_HAS_PARAM) |
<> | 144:ef7eb2e8f9f7 | 34 | void SMC_GetParam(SMC_Type *base, smc_param_t *param) |
<> | 144:ef7eb2e8f9f7 | 35 | { |
<> | 144:ef7eb2e8f9f7 | 36 | uint32_t reg = base->PARAM; |
<> | 144:ef7eb2e8f9f7 | 37 | param->hsrunEnable = (bool)(reg & SMC_PARAM_EHSRUN_MASK); |
<> | 144:ef7eb2e8f9f7 | 38 | param->llsEnable = (bool)(reg & SMC_PARAM_ELLS_MASK); |
<> | 144:ef7eb2e8f9f7 | 39 | param->lls2Enable = (bool)(reg & SMC_PARAM_ELLS2_MASK); |
<> | 144:ef7eb2e8f9f7 | 40 | param->vlls0Enable = (bool)(reg & SMC_PARAM_EVLLS0_MASK); |
<> | 144:ef7eb2e8f9f7 | 41 | } |
<> | 144:ef7eb2e8f9f7 | 42 | #endif /* FSL_FEATURE_SMC_HAS_PARAM */ |
<> | 144:ef7eb2e8f9f7 | 43 | |
<> | 144:ef7eb2e8f9f7 | 44 | status_t SMC_SetPowerModeRun(SMC_Type *base) |
<> | 144:ef7eb2e8f9f7 | 45 | { |
<> | 144:ef7eb2e8f9f7 | 46 | uint8_t reg; |
<> | 144:ef7eb2e8f9f7 | 47 | |
<> | 144:ef7eb2e8f9f7 | 48 | reg = base->PMCTRL; |
<> | 144:ef7eb2e8f9f7 | 49 | /* configure Normal RUN mode */ |
<> | 144:ef7eb2e8f9f7 | 50 | reg &= ~SMC_PMCTRL_RUNM_MASK; |
<> | 144:ef7eb2e8f9f7 | 51 | reg |= (kSMC_RunNormal << SMC_PMCTRL_RUNM_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 52 | base->PMCTRL = reg; |
<> | 144:ef7eb2e8f9f7 | 53 | |
<> | 144:ef7eb2e8f9f7 | 54 | return kStatus_Success; |
<> | 144:ef7eb2e8f9f7 | 55 | } |
<> | 144:ef7eb2e8f9f7 | 56 | |
<> | 144:ef7eb2e8f9f7 | 57 | #if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) |
<> | 144:ef7eb2e8f9f7 | 58 | status_t SMC_SetPowerModeHsrun(SMC_Type *base) |
<> | 144:ef7eb2e8f9f7 | 59 | { |
<> | 144:ef7eb2e8f9f7 | 60 | uint8_t reg; |
<> | 144:ef7eb2e8f9f7 | 61 | |
<> | 144:ef7eb2e8f9f7 | 62 | reg = base->PMCTRL; |
<> | 144:ef7eb2e8f9f7 | 63 | /* configure High Speed RUN mode */ |
<> | 144:ef7eb2e8f9f7 | 64 | reg &= ~SMC_PMCTRL_RUNM_MASK; |
<> | 144:ef7eb2e8f9f7 | 65 | reg |= (kSMC_Hsrun << SMC_PMCTRL_RUNM_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 66 | base->PMCTRL = reg; |
<> | 144:ef7eb2e8f9f7 | 67 | |
<> | 144:ef7eb2e8f9f7 | 68 | return kStatus_Success; |
<> | 144:ef7eb2e8f9f7 | 69 | } |
<> | 144:ef7eb2e8f9f7 | 70 | #endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */ |
<> | 144:ef7eb2e8f9f7 | 71 | |
<> | 144:ef7eb2e8f9f7 | 72 | status_t SMC_SetPowerModeWait(SMC_Type *base) |
<> | 144:ef7eb2e8f9f7 | 73 | { |
<> | 144:ef7eb2e8f9f7 | 74 | /* configure Normal Wait mode */ |
<> | 144:ef7eb2e8f9f7 | 75 | SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; |
<> | 144:ef7eb2e8f9f7 | 76 | __WFI(); |
<> | 144:ef7eb2e8f9f7 | 77 | |
<> | 144:ef7eb2e8f9f7 | 78 | return kStatus_Success; |
<> | 144:ef7eb2e8f9f7 | 79 | } |
<> | 144:ef7eb2e8f9f7 | 80 | |
<> | 144:ef7eb2e8f9f7 | 81 | status_t SMC_SetPowerModeStop(SMC_Type *base, smc_partial_stop_option_t option) |
<> | 144:ef7eb2e8f9f7 | 82 | { |
<> | 144:ef7eb2e8f9f7 | 83 | uint8_t reg; |
<> | 144:ef7eb2e8f9f7 | 84 | |
<> | 144:ef7eb2e8f9f7 | 85 | #if (defined(FSL_FEATURE_SMC_HAS_PSTOPO) && FSL_FEATURE_SMC_HAS_PSTOPO) |
<> | 144:ef7eb2e8f9f7 | 86 | /* configure the Partial Stop mode in Noraml Stop mode */ |
<> | 144:ef7eb2e8f9f7 | 87 | reg = base->STOPCTRL; |
<> | 144:ef7eb2e8f9f7 | 88 | reg &= ~SMC_STOPCTRL_PSTOPO_MASK; |
<> | 144:ef7eb2e8f9f7 | 89 | reg |= ((uint32_t)option << SMC_STOPCTRL_PSTOPO_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 90 | base->STOPCTRL = reg; |
<> | 144:ef7eb2e8f9f7 | 91 | #endif |
<> | 144:ef7eb2e8f9f7 | 92 | |
<> | 144:ef7eb2e8f9f7 | 93 | /* configure Normal Stop mode */ |
<> | 144:ef7eb2e8f9f7 | 94 | reg = base->PMCTRL; |
<> | 144:ef7eb2e8f9f7 | 95 | reg &= ~SMC_PMCTRL_STOPM_MASK; |
<> | 144:ef7eb2e8f9f7 | 96 | reg |= (kSMC_StopNormal << SMC_PMCTRL_STOPM_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 97 | base->PMCTRL = reg; |
<> | 144:ef7eb2e8f9f7 | 98 | |
<> | 144:ef7eb2e8f9f7 | 99 | /* Set the SLEEPDEEP bit to enable deep sleep mode (stop mode) */ |
<> | 144:ef7eb2e8f9f7 | 100 | SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; |
<> | 144:ef7eb2e8f9f7 | 101 | |
<> | 144:ef7eb2e8f9f7 | 102 | /* read back to make sure the configuration valid before enter stop mode */ |
<> | 144:ef7eb2e8f9f7 | 103 | (void)base->PMCTRL; |
<> | 144:ef7eb2e8f9f7 | 104 | __WFI(); |
<> | 144:ef7eb2e8f9f7 | 105 | |
<> | 144:ef7eb2e8f9f7 | 106 | /* check whether the power mode enter Stop mode succeed */ |
<> | 144:ef7eb2e8f9f7 | 107 | if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK) |
<> | 144:ef7eb2e8f9f7 | 108 | { |
<> | 144:ef7eb2e8f9f7 | 109 | return kStatus_SMC_StopAbort; |
<> | 144:ef7eb2e8f9f7 | 110 | } |
<> | 144:ef7eb2e8f9f7 | 111 | else |
<> | 144:ef7eb2e8f9f7 | 112 | { |
<> | 144:ef7eb2e8f9f7 | 113 | return kStatus_Success; |
<> | 144:ef7eb2e8f9f7 | 114 | } |
<> | 144:ef7eb2e8f9f7 | 115 | } |
<> | 144:ef7eb2e8f9f7 | 116 | |
<> | 144:ef7eb2e8f9f7 | 117 | status_t SMC_SetPowerModeVlpr(SMC_Type *base |
<> | 144:ef7eb2e8f9f7 | 118 | #if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI) |
<> | 144:ef7eb2e8f9f7 | 119 | , |
<> | 144:ef7eb2e8f9f7 | 120 | bool wakeupMode |
<> | 144:ef7eb2e8f9f7 | 121 | #endif |
<> | 144:ef7eb2e8f9f7 | 122 | ) |
<> | 144:ef7eb2e8f9f7 | 123 | { |
<> | 144:ef7eb2e8f9f7 | 124 | uint8_t reg; |
<> | 144:ef7eb2e8f9f7 | 125 | |
<> | 144:ef7eb2e8f9f7 | 126 | reg = base->PMCTRL; |
<> | 144:ef7eb2e8f9f7 | 127 | #if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI) |
<> | 144:ef7eb2e8f9f7 | 128 | /* configure whether the system remains in VLP mode on an interrupt */ |
<> | 144:ef7eb2e8f9f7 | 129 | if (wakeupMode) |
<> | 144:ef7eb2e8f9f7 | 130 | { |
<> | 144:ef7eb2e8f9f7 | 131 | /* exits to RUN mode on an interrupt */ |
<> | 144:ef7eb2e8f9f7 | 132 | reg |= SMC_PMCTRL_LPWUI_MASK; |
<> | 144:ef7eb2e8f9f7 | 133 | } |
<> | 144:ef7eb2e8f9f7 | 134 | else |
<> | 144:ef7eb2e8f9f7 | 135 | { |
<> | 144:ef7eb2e8f9f7 | 136 | /* remains in VLP mode on an interrupt */ |
<> | 144:ef7eb2e8f9f7 | 137 | reg &= ~SMC_PMCTRL_LPWUI_MASK; |
<> | 144:ef7eb2e8f9f7 | 138 | } |
<> | 144:ef7eb2e8f9f7 | 139 | #endif /* FSL_FEATURE_SMC_HAS_LPWUI */ |
<> | 144:ef7eb2e8f9f7 | 140 | |
<> | 144:ef7eb2e8f9f7 | 141 | /* configure VLPR mode */ |
<> | 144:ef7eb2e8f9f7 | 142 | reg &= ~SMC_PMCTRL_RUNM_MASK; |
<> | 144:ef7eb2e8f9f7 | 143 | reg |= (kSMC_RunVlpr << SMC_PMCTRL_RUNM_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 144 | base->PMCTRL = reg; |
<> | 144:ef7eb2e8f9f7 | 145 | |
<> | 144:ef7eb2e8f9f7 | 146 | return kStatus_Success; |
<> | 144:ef7eb2e8f9f7 | 147 | } |
<> | 144:ef7eb2e8f9f7 | 148 | |
<> | 144:ef7eb2e8f9f7 | 149 | status_t SMC_SetPowerModeVlpw(SMC_Type *base) |
<> | 144:ef7eb2e8f9f7 | 150 | { |
<> | 144:ef7eb2e8f9f7 | 151 | /* Power mode transaction to VLPW can only happen in VLPR mode */ |
<> | 144:ef7eb2e8f9f7 | 152 | if (kSMC_PowerStateVlpr != SMC_GetPowerModeState(base)) |
<> | 144:ef7eb2e8f9f7 | 153 | { |
<> | 144:ef7eb2e8f9f7 | 154 | return kStatus_Fail; |
<> | 144:ef7eb2e8f9f7 | 155 | } |
<> | 144:ef7eb2e8f9f7 | 156 | |
<> | 144:ef7eb2e8f9f7 | 157 | /* configure VLPW mode */ |
<> | 144:ef7eb2e8f9f7 | 158 | /* Set the SLEEPDEEP bit to enable deep sleep mode */ |
<> | 144:ef7eb2e8f9f7 | 159 | SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; |
<> | 144:ef7eb2e8f9f7 | 160 | __WFI(); |
<> | 144:ef7eb2e8f9f7 | 161 | |
<> | 144:ef7eb2e8f9f7 | 162 | return kStatus_Success; |
<> | 144:ef7eb2e8f9f7 | 163 | } |
<> | 144:ef7eb2e8f9f7 | 164 | |
<> | 144:ef7eb2e8f9f7 | 165 | status_t SMC_SetPowerModeVlps(SMC_Type *base) |
<> | 144:ef7eb2e8f9f7 | 166 | { |
<> | 144:ef7eb2e8f9f7 | 167 | uint8_t reg; |
<> | 144:ef7eb2e8f9f7 | 168 | |
<> | 144:ef7eb2e8f9f7 | 169 | /* configure VLPS mode */ |
<> | 144:ef7eb2e8f9f7 | 170 | reg = base->PMCTRL; |
<> | 144:ef7eb2e8f9f7 | 171 | reg &= ~SMC_PMCTRL_STOPM_MASK; |
<> | 144:ef7eb2e8f9f7 | 172 | reg |= (kSMC_StopVlps << SMC_PMCTRL_STOPM_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 173 | base->PMCTRL = reg; |
<> | 144:ef7eb2e8f9f7 | 174 | |
<> | 144:ef7eb2e8f9f7 | 175 | /* Set the SLEEPDEEP bit to enable deep sleep mode */ |
<> | 144:ef7eb2e8f9f7 | 176 | SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; |
<> | 144:ef7eb2e8f9f7 | 177 | |
<> | 144:ef7eb2e8f9f7 | 178 | /* read back to make sure the configuration valid before enter stop mode */ |
<> | 144:ef7eb2e8f9f7 | 179 | (void)base->PMCTRL; |
<> | 144:ef7eb2e8f9f7 | 180 | __WFI(); |
<> | 144:ef7eb2e8f9f7 | 181 | |
<> | 144:ef7eb2e8f9f7 | 182 | /* check whether the power mode enter VLPS mode succeed */ |
<> | 144:ef7eb2e8f9f7 | 183 | if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK) |
<> | 144:ef7eb2e8f9f7 | 184 | { |
<> | 144:ef7eb2e8f9f7 | 185 | return kStatus_SMC_StopAbort; |
<> | 144:ef7eb2e8f9f7 | 186 | } |
<> | 144:ef7eb2e8f9f7 | 187 | else |
<> | 144:ef7eb2e8f9f7 | 188 | { |
<> | 144:ef7eb2e8f9f7 | 189 | return kStatus_Success; |
<> | 144:ef7eb2e8f9f7 | 190 | } |
<> | 144:ef7eb2e8f9f7 | 191 | } |
<> | 144:ef7eb2e8f9f7 | 192 | |
<> | 144:ef7eb2e8f9f7 | 193 | #if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) |
<> | 144:ef7eb2e8f9f7 | 194 | status_t SMC_SetPowerModeLls(SMC_Type *base |
<> | 144:ef7eb2e8f9f7 | 195 | #if ((defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) || \ |
<> | 144:ef7eb2e8f9f7 | 196 | (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO)) |
<> | 144:ef7eb2e8f9f7 | 197 | , |
<> | 144:ef7eb2e8f9f7 | 198 | const smc_power_mode_lls_config_t *config |
<> | 144:ef7eb2e8f9f7 | 199 | #endif |
<> | 144:ef7eb2e8f9f7 | 200 | ) |
<> | 144:ef7eb2e8f9f7 | 201 | { |
<> | 144:ef7eb2e8f9f7 | 202 | uint8_t reg; |
<> | 144:ef7eb2e8f9f7 | 203 | |
<> | 144:ef7eb2e8f9f7 | 204 | /* configure to LLS mode */ |
<> | 144:ef7eb2e8f9f7 | 205 | reg = base->PMCTRL; |
<> | 144:ef7eb2e8f9f7 | 206 | reg &= ~SMC_PMCTRL_STOPM_MASK; |
<> | 144:ef7eb2e8f9f7 | 207 | reg |= (kSMC_StopLls << SMC_PMCTRL_STOPM_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 208 | base->PMCTRL = reg; |
<> | 144:ef7eb2e8f9f7 | 209 | |
<> | 144:ef7eb2e8f9f7 | 210 | /* configure LLS sub-mode*/ |
<> | 144:ef7eb2e8f9f7 | 211 | #if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) |
<> | 144:ef7eb2e8f9f7 | 212 | reg = base->STOPCTRL; |
<> | 144:ef7eb2e8f9f7 | 213 | reg &= ~SMC_STOPCTRL_LLSM_MASK; |
<> | 144:ef7eb2e8f9f7 | 214 | reg |= ((uint32_t)config->subMode << SMC_STOPCTRL_LLSM_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 215 | base->STOPCTRL = reg; |
<> | 144:ef7eb2e8f9f7 | 216 | #endif /* FSL_FEATURE_SMC_HAS_LLS_SUBMODE */ |
<> | 144:ef7eb2e8f9f7 | 217 | |
<> | 144:ef7eb2e8f9f7 | 218 | #if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO) |
<> | 144:ef7eb2e8f9f7 | 219 | if (config->enableLpoClock) |
<> | 144:ef7eb2e8f9f7 | 220 | { |
<> | 144:ef7eb2e8f9f7 | 221 | base->STOPCTRL &= ~SMC_STOPCTRL_LPOPO_MASK; |
<> | 144:ef7eb2e8f9f7 | 222 | } |
<> | 144:ef7eb2e8f9f7 | 223 | else |
<> | 144:ef7eb2e8f9f7 | 224 | { |
<> | 144:ef7eb2e8f9f7 | 225 | base->STOPCTRL |= SMC_STOPCTRL_LPOPO_MASK; |
<> | 144:ef7eb2e8f9f7 | 226 | } |
<> | 144:ef7eb2e8f9f7 | 227 | #endif /* FSL_FEATURE_SMC_HAS_LPOPO */ |
<> | 144:ef7eb2e8f9f7 | 228 | |
<> | 144:ef7eb2e8f9f7 | 229 | /* Set the SLEEPDEEP bit to enable deep sleep mode */ |
<> | 144:ef7eb2e8f9f7 | 230 | SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; |
<> | 144:ef7eb2e8f9f7 | 231 | |
<> | 144:ef7eb2e8f9f7 | 232 | /* read back to make sure the configuration valid before enter stop mode */ |
<> | 144:ef7eb2e8f9f7 | 233 | (void)base->PMCTRL; |
<> | 144:ef7eb2e8f9f7 | 234 | __WFI(); |
<> | 144:ef7eb2e8f9f7 | 235 | |
<> | 144:ef7eb2e8f9f7 | 236 | /* check whether the power mode enter LLS mode succeed */ |
<> | 144:ef7eb2e8f9f7 | 237 | if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK) |
<> | 144:ef7eb2e8f9f7 | 238 | { |
<> | 144:ef7eb2e8f9f7 | 239 | return kStatus_SMC_StopAbort; |
<> | 144:ef7eb2e8f9f7 | 240 | } |
<> | 144:ef7eb2e8f9f7 | 241 | else |
<> | 144:ef7eb2e8f9f7 | 242 | { |
<> | 144:ef7eb2e8f9f7 | 243 | return kStatus_Success; |
<> | 144:ef7eb2e8f9f7 | 244 | } |
<> | 144:ef7eb2e8f9f7 | 245 | } |
<> | 144:ef7eb2e8f9f7 | 246 | #endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */ |
<> | 144:ef7eb2e8f9f7 | 247 | |
<> | 144:ef7eb2e8f9f7 | 248 | #if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) |
<> | 144:ef7eb2e8f9f7 | 249 | status_t SMC_SetPowerModeVlls(SMC_Type *base, const smc_power_mode_vlls_config_t *config) |
<> | 144:ef7eb2e8f9f7 | 250 | { |
<> | 144:ef7eb2e8f9f7 | 251 | uint8_t reg; |
<> | 144:ef7eb2e8f9f7 | 252 | |
<> | 144:ef7eb2e8f9f7 | 253 | #if (defined(FSL_FEATURE_SMC_HAS_PORPO) && FSL_FEATURE_SMC_HAS_PORPO) |
<> | 144:ef7eb2e8f9f7 | 254 | #if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) || \ |
<> | 144:ef7eb2e8f9f7 | 255 | (defined(FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) && FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) || \ |
<> | 144:ef7eb2e8f9f7 | 256 | (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) |
<> | 144:ef7eb2e8f9f7 | 257 | if (config->subMode == kSMC_StopSub0) |
<> | 144:ef7eb2e8f9f7 | 258 | #endif |
<> | 144:ef7eb2e8f9f7 | 259 | { |
<> | 144:ef7eb2e8f9f7 | 260 | /* configure whether the Por Detect work in Vlls0 mode */ |
<> | 144:ef7eb2e8f9f7 | 261 | if (config->enablePorDetectInVlls0) |
<> | 144:ef7eb2e8f9f7 | 262 | { |
<> | 144:ef7eb2e8f9f7 | 263 | #if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) |
<> | 144:ef7eb2e8f9f7 | 264 | base->VLLSCTRL &= ~SMC_VLLSCTRL_PORPO_MASK; |
<> | 144:ef7eb2e8f9f7 | 265 | #else |
<> | 144:ef7eb2e8f9f7 | 266 | base->STOPCTRL &= ~SMC_STOPCTRL_PORPO_MASK; |
<> | 144:ef7eb2e8f9f7 | 267 | #endif |
<> | 144:ef7eb2e8f9f7 | 268 | } |
<> | 144:ef7eb2e8f9f7 | 269 | else |
<> | 144:ef7eb2e8f9f7 | 270 | { |
<> | 144:ef7eb2e8f9f7 | 271 | #if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) |
<> | 144:ef7eb2e8f9f7 | 272 | base->VLLSCTRL |= SMC_VLLSCTRL_PORPO_MASK; |
<> | 144:ef7eb2e8f9f7 | 273 | #else |
<> | 144:ef7eb2e8f9f7 | 274 | base->STOPCTRL |= SMC_STOPCTRL_PORPO_MASK; |
<> | 144:ef7eb2e8f9f7 | 275 | #endif |
<> | 144:ef7eb2e8f9f7 | 276 | } |
<> | 144:ef7eb2e8f9f7 | 277 | } |
<> | 144:ef7eb2e8f9f7 | 278 | #endif /* FSL_FEATURE_SMC_HAS_PORPO */ |
<> | 144:ef7eb2e8f9f7 | 279 | |
<> | 144:ef7eb2e8f9f7 | 280 | #if (defined(FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION) && FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION) |
<> | 144:ef7eb2e8f9f7 | 281 | else if (config->subMode == kSMC_StopSub2) |
<> | 144:ef7eb2e8f9f7 | 282 | { |
<> | 144:ef7eb2e8f9f7 | 283 | /* configure whether the Por Detect work in Vlls0 mode */ |
<> | 144:ef7eb2e8f9f7 | 284 | if (config->enableRam2InVlls2) |
<> | 144:ef7eb2e8f9f7 | 285 | { |
<> | 144:ef7eb2e8f9f7 | 286 | #if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) |
<> | 144:ef7eb2e8f9f7 | 287 | base->VLLSCTRL |= SMC_VLLSCTRL_RAM2PO_MASK; |
<> | 144:ef7eb2e8f9f7 | 288 | #else |
<> | 144:ef7eb2e8f9f7 | 289 | base->STOPCTRL |= SMC_STOPCTRL_RAM2PO_MASK; |
<> | 144:ef7eb2e8f9f7 | 290 | #endif |
<> | 144:ef7eb2e8f9f7 | 291 | } |
<> | 144:ef7eb2e8f9f7 | 292 | else |
<> | 144:ef7eb2e8f9f7 | 293 | { |
<> | 144:ef7eb2e8f9f7 | 294 | #if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) |
<> | 144:ef7eb2e8f9f7 | 295 | base->VLLSCTRL &= ~SMC_VLLSCTRL_RAM2PO_MASK; |
<> | 144:ef7eb2e8f9f7 | 296 | #else |
<> | 144:ef7eb2e8f9f7 | 297 | base->STOPCTRL &= ~SMC_STOPCTRL_RAM2PO_MASK; |
<> | 144:ef7eb2e8f9f7 | 298 | #endif |
<> | 144:ef7eb2e8f9f7 | 299 | } |
<> | 144:ef7eb2e8f9f7 | 300 | } |
<> | 144:ef7eb2e8f9f7 | 301 | else |
<> | 144:ef7eb2e8f9f7 | 302 | { |
<> | 144:ef7eb2e8f9f7 | 303 | } |
<> | 144:ef7eb2e8f9f7 | 304 | #endif /* FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION */ |
<> | 144:ef7eb2e8f9f7 | 305 | |
<> | 144:ef7eb2e8f9f7 | 306 | /* configure to VLLS mode */ |
<> | 144:ef7eb2e8f9f7 | 307 | reg = base->PMCTRL; |
<> | 144:ef7eb2e8f9f7 | 308 | reg &= ~SMC_PMCTRL_STOPM_MASK; |
<> | 144:ef7eb2e8f9f7 | 309 | reg |= (kSMC_StopVlls << SMC_PMCTRL_STOPM_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 310 | base->PMCTRL = reg; |
<> | 144:ef7eb2e8f9f7 | 311 | |
<> | 144:ef7eb2e8f9f7 | 312 | /* configure the VLLS sub-mode */ |
<> | 144:ef7eb2e8f9f7 | 313 | #if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) |
<> | 144:ef7eb2e8f9f7 | 314 | reg = base->VLLSCTRL; |
<> | 144:ef7eb2e8f9f7 | 315 | reg &= ~SMC_VLLSCTRL_VLLSM_MASK; |
<> | 144:ef7eb2e8f9f7 | 316 | reg |= ((uint32_t)config->subMode << SMC_VLLSCTRL_VLLSM_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 317 | base->VLLSCTRL = reg; |
<> | 144:ef7eb2e8f9f7 | 318 | #else |
<> | 144:ef7eb2e8f9f7 | 319 | #if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) |
<> | 144:ef7eb2e8f9f7 | 320 | reg = base->STOPCTRL; |
<> | 144:ef7eb2e8f9f7 | 321 | reg &= ~SMC_STOPCTRL_LLSM_MASK; |
<> | 144:ef7eb2e8f9f7 | 322 | reg |= ((uint32_t)config->subMode << SMC_STOPCTRL_LLSM_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 323 | base->STOPCTRL = reg; |
<> | 144:ef7eb2e8f9f7 | 324 | #else |
<> | 144:ef7eb2e8f9f7 | 325 | reg = base->STOPCTRL; |
<> | 144:ef7eb2e8f9f7 | 326 | reg &= ~SMC_STOPCTRL_VLLSM_MASK; |
<> | 144:ef7eb2e8f9f7 | 327 | reg |= ((uint32_t)config->subMode << SMC_STOPCTRL_VLLSM_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 328 | base->STOPCTRL = reg; |
<> | 144:ef7eb2e8f9f7 | 329 | #endif /* FSL_FEATURE_SMC_HAS_LLS_SUBMODE */ |
<> | 144:ef7eb2e8f9f7 | 330 | #endif |
<> | 144:ef7eb2e8f9f7 | 331 | |
<> | 144:ef7eb2e8f9f7 | 332 | #if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO) |
<> | 144:ef7eb2e8f9f7 | 333 | if (config->enableLpoClock) |
<> | 144:ef7eb2e8f9f7 | 334 | { |
<> | 144:ef7eb2e8f9f7 | 335 | base->STOPCTRL &= ~SMC_STOPCTRL_LPOPO_MASK; |
<> | 144:ef7eb2e8f9f7 | 336 | } |
<> | 144:ef7eb2e8f9f7 | 337 | else |
<> | 144:ef7eb2e8f9f7 | 338 | { |
<> | 144:ef7eb2e8f9f7 | 339 | base->STOPCTRL |= SMC_STOPCTRL_LPOPO_MASK; |
<> | 144:ef7eb2e8f9f7 | 340 | } |
<> | 144:ef7eb2e8f9f7 | 341 | #endif /* FSL_FEATURE_SMC_HAS_LPOPO */ |
<> | 144:ef7eb2e8f9f7 | 342 | |
<> | 144:ef7eb2e8f9f7 | 343 | /* Set the SLEEPDEEP bit to enable deep sleep mode */ |
<> | 144:ef7eb2e8f9f7 | 344 | SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; |
<> | 144:ef7eb2e8f9f7 | 345 | |
<> | 144:ef7eb2e8f9f7 | 346 | /* read back to make sure the configuration valid before enter stop mode */ |
<> | 144:ef7eb2e8f9f7 | 347 | (void)base->PMCTRL; |
<> | 144:ef7eb2e8f9f7 | 348 | __WFI(); |
<> | 144:ef7eb2e8f9f7 | 349 | |
<> | 144:ef7eb2e8f9f7 | 350 | /* check whether the power mode enter LLS mode succeed */ |
<> | 144:ef7eb2e8f9f7 | 351 | if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK) |
<> | 144:ef7eb2e8f9f7 | 352 | { |
<> | 144:ef7eb2e8f9f7 | 353 | return kStatus_SMC_StopAbort; |
<> | 144:ef7eb2e8f9f7 | 354 | } |
<> | 144:ef7eb2e8f9f7 | 355 | else |
<> | 144:ef7eb2e8f9f7 | 356 | { |
<> | 144:ef7eb2e8f9f7 | 357 | return kStatus_Success; |
<> | 144:ef7eb2e8f9f7 | 358 | } |
<> | 144:ef7eb2e8f9f7 | 359 | } |
<> | 144:ef7eb2e8f9f7 | 360 | #endif /* FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE */ |