added prescaler for 16 bit pwm in LPC1347 target
Fork of mbed-dev by
targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/drivers/fsl_dma.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)
- Committer:
- <>
- Date:
- Fri Sep 02 15:07:44 2016 +0100
- Revision:
- 144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /* |
<> | 144:ef7eb2e8f9f7 | 2 | * Copyright (c) 2015, Freescale Semiconductor, Inc. |
<> | 144:ef7eb2e8f9f7 | 3 | * All rights reserved. |
<> | 144:ef7eb2e8f9f7 | 4 | * |
<> | 144:ef7eb2e8f9f7 | 5 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 144:ef7eb2e8f9f7 | 6 | * are permitted provided that the following conditions are met: |
<> | 144:ef7eb2e8f9f7 | 7 | * |
<> | 144:ef7eb2e8f9f7 | 8 | * o Redistributions of source code must retain the above copyright notice, this list |
<> | 144:ef7eb2e8f9f7 | 9 | * of conditions and the following disclaimer. |
<> | 144:ef7eb2e8f9f7 | 10 | * |
<> | 144:ef7eb2e8f9f7 | 11 | * o Redistributions in binary form must reproduce the above copyright notice, this |
<> | 144:ef7eb2e8f9f7 | 12 | * list of conditions and the following disclaimer in the documentation and/or |
<> | 144:ef7eb2e8f9f7 | 13 | * other materials provided with the distribution. |
<> | 144:ef7eb2e8f9f7 | 14 | * |
<> | 144:ef7eb2e8f9f7 | 15 | * o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
<> | 144:ef7eb2e8f9f7 | 16 | * contributors may be used to endorse or promote products derived from this |
<> | 144:ef7eb2e8f9f7 | 17 | * software without specific prior written permission. |
<> | 144:ef7eb2e8f9f7 | 18 | * |
<> | 144:ef7eb2e8f9f7 | 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
<> | 144:ef7eb2e8f9f7 | 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
<> | 144:ef7eb2e8f9f7 | 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 144:ef7eb2e8f9f7 | 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
<> | 144:ef7eb2e8f9f7 | 23 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
<> | 144:ef7eb2e8f9f7 | 24 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
<> | 144:ef7eb2e8f9f7 | 25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
<> | 144:ef7eb2e8f9f7 | 26 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
<> | 144:ef7eb2e8f9f7 | 27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
<> | 144:ef7eb2e8f9f7 | 28 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 144:ef7eb2e8f9f7 | 29 | */ |
<> | 144:ef7eb2e8f9f7 | 30 | |
<> | 144:ef7eb2e8f9f7 | 31 | #ifndef _FSL_DMA_H_ |
<> | 144:ef7eb2e8f9f7 | 32 | #define _FSL_DMA_H_ |
<> | 144:ef7eb2e8f9f7 | 33 | |
<> | 144:ef7eb2e8f9f7 | 34 | #include "fsl_common.h" |
<> | 144:ef7eb2e8f9f7 | 35 | |
<> | 144:ef7eb2e8f9f7 | 36 | /*! |
<> | 144:ef7eb2e8f9f7 | 37 | * @addtogroup dma_driver |
<> | 144:ef7eb2e8f9f7 | 38 | * @{ |
<> | 144:ef7eb2e8f9f7 | 39 | */ |
<> | 144:ef7eb2e8f9f7 | 40 | |
<> | 144:ef7eb2e8f9f7 | 41 | /*! @file */ |
<> | 144:ef7eb2e8f9f7 | 42 | |
<> | 144:ef7eb2e8f9f7 | 43 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 44 | * Definitions |
<> | 144:ef7eb2e8f9f7 | 45 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 46 | |
<> | 144:ef7eb2e8f9f7 | 47 | /*! @name Driver version */ |
<> | 144:ef7eb2e8f9f7 | 48 | /*@{*/ |
<> | 144:ef7eb2e8f9f7 | 49 | /*! @brief DMA driver version 2.0.0. */ |
<> | 144:ef7eb2e8f9f7 | 50 | #define FSL_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) |
<> | 144:ef7eb2e8f9f7 | 51 | /*@}*/ |
<> | 144:ef7eb2e8f9f7 | 52 | |
<> | 144:ef7eb2e8f9f7 | 53 | /*! @brief status flag for the DMA driver. */ |
<> | 144:ef7eb2e8f9f7 | 54 | enum _dma_channel_status_flags |
<> | 144:ef7eb2e8f9f7 | 55 | { |
<> | 144:ef7eb2e8f9f7 | 56 | kDMA_TransactionsBCRFlag = DMA_DSR_BCR_BCR_MASK, /*!< Contains the number of bytes yet to be |
<> | 144:ef7eb2e8f9f7 | 57 | transferred for a given block */ |
<> | 144:ef7eb2e8f9f7 | 58 | kDMA_TransactionsDoneFlag = DMA_DSR_BCR_DONE_MASK, /*!< Transactions Done */ |
<> | 144:ef7eb2e8f9f7 | 59 | kDMA_TransactionsBusyFlag = DMA_DSR_BCR_BSY_MASK, /*!< Transactions Busy */ |
<> | 144:ef7eb2e8f9f7 | 60 | kDMA_TransactionsRequestFlag = DMA_DSR_BCR_REQ_MASK, /*!< Transactions Request */ |
<> | 144:ef7eb2e8f9f7 | 61 | kDMA_BusErrorOnDestinationFlag = DMA_DSR_BCR_BED_MASK, /*!< Bus Error on Destination */ |
<> | 144:ef7eb2e8f9f7 | 62 | kDMA_BusErrorOnSourceFlag = DMA_DSR_BCR_BES_MASK, /*!< Bus Error on Source */ |
<> | 144:ef7eb2e8f9f7 | 63 | kDMA_ConfigurationErrorFlag = DMA_DSR_BCR_CE_MASK, /*!< Configuration Error */ |
<> | 144:ef7eb2e8f9f7 | 64 | }; |
<> | 144:ef7eb2e8f9f7 | 65 | |
<> | 144:ef7eb2e8f9f7 | 66 | /*! @brief DMA transfer size type*/ |
<> | 144:ef7eb2e8f9f7 | 67 | typedef enum _dma_transfer_size |
<> | 144:ef7eb2e8f9f7 | 68 | { |
<> | 144:ef7eb2e8f9f7 | 69 | kDMA_Transfersize32bits = 0x0U, /*!< 32 bits are transferred for every read/write */ |
<> | 144:ef7eb2e8f9f7 | 70 | kDMA_Transfersize8bits, /*!< 8 bits are transferred for every read/write */ |
<> | 144:ef7eb2e8f9f7 | 71 | kDMA_Transfersize16bits, /*!< 16b its are transferred for every read/write */ |
<> | 144:ef7eb2e8f9f7 | 72 | } dma_transfer_size_t; |
<> | 144:ef7eb2e8f9f7 | 73 | |
<> | 144:ef7eb2e8f9f7 | 74 | /*! @brief Configuration type for the DMA modulo */ |
<> | 144:ef7eb2e8f9f7 | 75 | typedef enum _dma_modulo |
<> | 144:ef7eb2e8f9f7 | 76 | { |
<> | 144:ef7eb2e8f9f7 | 77 | kDMA_ModuloDisable = 0x0U, /*!< Buffer disabled */ |
<> | 144:ef7eb2e8f9f7 | 78 | kDMA_Modulo16Bytes, /*!< Circular buffer size is 16 bytes. */ |
<> | 144:ef7eb2e8f9f7 | 79 | kDMA_Modulo32Bytes, /*!< Circular buffer size is 32 bytes. */ |
<> | 144:ef7eb2e8f9f7 | 80 | kDMA_Modulo64Bytes, /*!< Circular buffer size is 64 bytes. */ |
<> | 144:ef7eb2e8f9f7 | 81 | kDMA_Modulo128Bytes, /*!< Circular buffer size is 128 bytes. */ |
<> | 144:ef7eb2e8f9f7 | 82 | kDMA_Modulo256Bytes, /*!< Circular buffer size is 256 bytes. */ |
<> | 144:ef7eb2e8f9f7 | 83 | kDMA_Modulo512Bytes, /*!< Circular buffer size is 512 bytes. */ |
<> | 144:ef7eb2e8f9f7 | 84 | kDMA_Modulo1KBytes, /*!< Circular buffer size is 1 KB. */ |
<> | 144:ef7eb2e8f9f7 | 85 | kDMA_Modulo2KBytes, /*!< Circular buffer size is 2 KB. */ |
<> | 144:ef7eb2e8f9f7 | 86 | kDMA_Modulo4KBytes, /*!< Circular buffer size is 4 KB. */ |
<> | 144:ef7eb2e8f9f7 | 87 | kDMA_Modulo8KBytes, /*!< Circular buffer size is 8 KB. */ |
<> | 144:ef7eb2e8f9f7 | 88 | kDMA_Modulo16KBytes, /*!< Circular buffer size is 16 KB. */ |
<> | 144:ef7eb2e8f9f7 | 89 | kDMA_Modulo32KBytes, /*!< Circular buffer size is 32 KB. */ |
<> | 144:ef7eb2e8f9f7 | 90 | kDMA_Modulo64KBytes, /*!< Circular buffer size is 64 KB. */ |
<> | 144:ef7eb2e8f9f7 | 91 | kDMA_Modulo128KBytes, /*!< Circular buffer size is 128 KB. */ |
<> | 144:ef7eb2e8f9f7 | 92 | kDMA_Modulo256KBytes, /*!< Circular buffer size is 256 KB. */ |
<> | 144:ef7eb2e8f9f7 | 93 | } dma_modulo_t; |
<> | 144:ef7eb2e8f9f7 | 94 | |
<> | 144:ef7eb2e8f9f7 | 95 | /*! @brief DMA channel link type */ |
<> | 144:ef7eb2e8f9f7 | 96 | typedef enum _dma_channel_link_type |
<> | 144:ef7eb2e8f9f7 | 97 | { |
<> | 144:ef7eb2e8f9f7 | 98 | kDMA_ChannelLinkDisable = 0x0U, /*!< No channel link. */ |
<> | 144:ef7eb2e8f9f7 | 99 | kDMA_ChannelLinkChannel1AndChannel2, /*!< Perform a link to channel LCH1 after each cycle-steal transfer. |
<> | 144:ef7eb2e8f9f7 | 100 | followed by a link to LCH2 after the BCR decrements to 0. */ |
<> | 144:ef7eb2e8f9f7 | 101 | kDMA_ChannelLinkChannel1, /*!< Perform a link to LCH1 after each cycle-steal transfer. */ |
<> | 144:ef7eb2e8f9f7 | 102 | kDMA_ChannelLinkChannel1AfterBCR0, /*!< Perform a link to LCH1 after the BCR decrements. */ |
<> | 144:ef7eb2e8f9f7 | 103 | } dma_channel_link_type_t; |
<> | 144:ef7eb2e8f9f7 | 104 | |
<> | 144:ef7eb2e8f9f7 | 105 | /*! @brief DMA transfer type */ |
<> | 144:ef7eb2e8f9f7 | 106 | typedef enum _dma_transfer_type |
<> | 144:ef7eb2e8f9f7 | 107 | { |
<> | 144:ef7eb2e8f9f7 | 108 | kDMA_MemoryToMemory = 0x0U, /*!< Memory to Memory transfer. */ |
<> | 144:ef7eb2e8f9f7 | 109 | kDMA_PeripheralToMemory, /*!< Peripheral to Memory transfer. */ |
<> | 144:ef7eb2e8f9f7 | 110 | kDMA_MemoryToPeripheral, /*!< Memory to Peripheral transfer. */ |
<> | 144:ef7eb2e8f9f7 | 111 | } dma_transfer_type_t; |
<> | 144:ef7eb2e8f9f7 | 112 | |
<> | 144:ef7eb2e8f9f7 | 113 | /*! @brief DMA transfer options */ |
<> | 144:ef7eb2e8f9f7 | 114 | typedef enum _dma_transfer_options |
<> | 144:ef7eb2e8f9f7 | 115 | { |
<> | 144:ef7eb2e8f9f7 | 116 | kDMA_NoOptions = 0x0U, /*!< Transfer without options. */ |
<> | 144:ef7eb2e8f9f7 | 117 | kDMA_EnableInterrupt, /*!< Enable interrupt while transfer complete. */ |
<> | 144:ef7eb2e8f9f7 | 118 | } dma_transfer_options_t; |
<> | 144:ef7eb2e8f9f7 | 119 | |
<> | 144:ef7eb2e8f9f7 | 120 | /*! @brief DMA transfer status */ |
<> | 144:ef7eb2e8f9f7 | 121 | enum _dma_transfer_status |
<> | 144:ef7eb2e8f9f7 | 122 | { |
<> | 144:ef7eb2e8f9f7 | 123 | kStatus_DMA_Busy = MAKE_STATUS(kStatusGroup_DMA, 0), |
<> | 144:ef7eb2e8f9f7 | 124 | }; |
<> | 144:ef7eb2e8f9f7 | 125 | |
<> | 144:ef7eb2e8f9f7 | 126 | /*! @brief DMA transfer configuration structure */ |
<> | 144:ef7eb2e8f9f7 | 127 | typedef struct _dma_transfer_config |
<> | 144:ef7eb2e8f9f7 | 128 | { |
<> | 144:ef7eb2e8f9f7 | 129 | uint32_t srcAddr; /*!< DMA transfer source address. */ |
<> | 144:ef7eb2e8f9f7 | 130 | uint32_t destAddr; /*!< DMA destination address.*/ |
<> | 144:ef7eb2e8f9f7 | 131 | bool enableSrcIncrement; /*!< Source address increase after each transfer. */ |
<> | 144:ef7eb2e8f9f7 | 132 | dma_transfer_size_t srcSize; /*!< Source transfer size unit. */ |
<> | 144:ef7eb2e8f9f7 | 133 | bool enableDestIncrement; /*!< Destination address increase after each transfer. */ |
<> | 144:ef7eb2e8f9f7 | 134 | dma_transfer_size_t destSize; /*!< Destination transfer unit.*/ |
<> | 144:ef7eb2e8f9f7 | 135 | uint32_t transferSize; /*!< The number of bytes to be transferred. */ |
<> | 144:ef7eb2e8f9f7 | 136 | } dma_transfer_config_t; |
<> | 144:ef7eb2e8f9f7 | 137 | |
<> | 144:ef7eb2e8f9f7 | 138 | /*! @brief DMA transfer configuration structure */ |
<> | 144:ef7eb2e8f9f7 | 139 | typedef struct _dma_channel_link_config |
<> | 144:ef7eb2e8f9f7 | 140 | { |
<> | 144:ef7eb2e8f9f7 | 141 | dma_channel_link_type_t linkType; /*!< Channel link type. */ |
<> | 144:ef7eb2e8f9f7 | 142 | uint32_t channel1; /*!< The index of channel 1. */ |
<> | 144:ef7eb2e8f9f7 | 143 | uint32_t channel2; /*!< The index of channel 2. */ |
<> | 144:ef7eb2e8f9f7 | 144 | } dma_channel_link_config_t; |
<> | 144:ef7eb2e8f9f7 | 145 | |
<> | 144:ef7eb2e8f9f7 | 146 | struct _dma_handle; |
<> | 144:ef7eb2e8f9f7 | 147 | /*! @brief Callback function prototype for the DMA driver. */ |
<> | 144:ef7eb2e8f9f7 | 148 | typedef void (*dma_callback)(struct _dma_handle *handle, void *userData); |
<> | 144:ef7eb2e8f9f7 | 149 | |
<> | 144:ef7eb2e8f9f7 | 150 | /*! @brief DMA DMA handle structure */ |
<> | 144:ef7eb2e8f9f7 | 151 | typedef struct _dma_handle |
<> | 144:ef7eb2e8f9f7 | 152 | { |
<> | 144:ef7eb2e8f9f7 | 153 | DMA_Type *base; /*!< DMA peripheral address. */ |
<> | 144:ef7eb2e8f9f7 | 154 | uint8_t channel; /*!< DMA channel used. */ |
<> | 144:ef7eb2e8f9f7 | 155 | dma_callback callback; /*!< DMA callback function.*/ |
<> | 144:ef7eb2e8f9f7 | 156 | void *userData; /*!< Callback parameter. */ |
<> | 144:ef7eb2e8f9f7 | 157 | } dma_handle_t; |
<> | 144:ef7eb2e8f9f7 | 158 | |
<> | 144:ef7eb2e8f9f7 | 159 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 160 | * API |
<> | 144:ef7eb2e8f9f7 | 161 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 162 | #if defined(__cplusplus) |
<> | 144:ef7eb2e8f9f7 | 163 | extern "C" { |
<> | 144:ef7eb2e8f9f7 | 164 | #endif /* __cplusplus */ |
<> | 144:ef7eb2e8f9f7 | 165 | |
<> | 144:ef7eb2e8f9f7 | 166 | /*! |
<> | 144:ef7eb2e8f9f7 | 167 | * @name DMA Initialization and De-initialization |
<> | 144:ef7eb2e8f9f7 | 168 | * @{ |
<> | 144:ef7eb2e8f9f7 | 169 | */ |
<> | 144:ef7eb2e8f9f7 | 170 | |
<> | 144:ef7eb2e8f9f7 | 171 | /*! |
<> | 144:ef7eb2e8f9f7 | 172 | * @brief Initializes the DMA peripheral. |
<> | 144:ef7eb2e8f9f7 | 173 | * |
<> | 144:ef7eb2e8f9f7 | 174 | * This function ungates the DMA clock. |
<> | 144:ef7eb2e8f9f7 | 175 | * |
<> | 144:ef7eb2e8f9f7 | 176 | * @param base DMA peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 177 | */ |
<> | 144:ef7eb2e8f9f7 | 178 | void DMA_Init(DMA_Type *base); |
<> | 144:ef7eb2e8f9f7 | 179 | |
<> | 144:ef7eb2e8f9f7 | 180 | /*! |
<> | 144:ef7eb2e8f9f7 | 181 | * @brief Deinitializes the DMA peripheral. |
<> | 144:ef7eb2e8f9f7 | 182 | * |
<> | 144:ef7eb2e8f9f7 | 183 | * This function gates the DMA clock. |
<> | 144:ef7eb2e8f9f7 | 184 | * |
<> | 144:ef7eb2e8f9f7 | 185 | * @param base DMA peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 186 | */ |
<> | 144:ef7eb2e8f9f7 | 187 | void DMA_Deinit(DMA_Type *base); |
<> | 144:ef7eb2e8f9f7 | 188 | |
<> | 144:ef7eb2e8f9f7 | 189 | /* @} */ |
<> | 144:ef7eb2e8f9f7 | 190 | /*! |
<> | 144:ef7eb2e8f9f7 | 191 | * @name DMA Channel Operation |
<> | 144:ef7eb2e8f9f7 | 192 | * @{ |
<> | 144:ef7eb2e8f9f7 | 193 | */ |
<> | 144:ef7eb2e8f9f7 | 194 | |
<> | 144:ef7eb2e8f9f7 | 195 | /*! |
<> | 144:ef7eb2e8f9f7 | 196 | * @brief Resets the DMA channel. |
<> | 144:ef7eb2e8f9f7 | 197 | * |
<> | 144:ef7eb2e8f9f7 | 198 | * Sets all register values to reset values and enables |
<> | 144:ef7eb2e8f9f7 | 199 | * the cycle steal and auto stop channel request features. |
<> | 144:ef7eb2e8f9f7 | 200 | * |
<> | 144:ef7eb2e8f9f7 | 201 | * @param base DMA peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 202 | * @param channel DMA channel number. |
<> | 144:ef7eb2e8f9f7 | 203 | */ |
<> | 144:ef7eb2e8f9f7 | 204 | void DMA_ResetChannel(DMA_Type *base, uint32_t channel); |
<> | 144:ef7eb2e8f9f7 | 205 | |
<> | 144:ef7eb2e8f9f7 | 206 | /*! |
<> | 144:ef7eb2e8f9f7 | 207 | * @brief Configures the DMA transfer attribute. |
<> | 144:ef7eb2e8f9f7 | 208 | * |
<> | 144:ef7eb2e8f9f7 | 209 | * This function configures the transfer attribute including the source address, |
<> | 144:ef7eb2e8f9f7 | 210 | * destination address, transfer size, and so on. |
<> | 144:ef7eb2e8f9f7 | 211 | * This example shows how to set up the the dma_transfer_config_t |
<> | 144:ef7eb2e8f9f7 | 212 | * parameters and how to call the DMA_ConfigBasicTransfer function. |
<> | 144:ef7eb2e8f9f7 | 213 | * @code |
<> | 144:ef7eb2e8f9f7 | 214 | * dma_transfer_config_t transferConfig; |
<> | 144:ef7eb2e8f9f7 | 215 | * memset(&transferConfig, 0, sizeof(transferConfig)); |
<> | 144:ef7eb2e8f9f7 | 216 | * transferConfig.srcAddr = (uint32_t)srcAddr; |
<> | 144:ef7eb2e8f9f7 | 217 | * transferConfig.destAddr = (uint32_t)destAddr; |
<> | 144:ef7eb2e8f9f7 | 218 | * transferConfig.enbaleSrcIncrement = true; |
<> | 144:ef7eb2e8f9f7 | 219 | * transferConfig.enableDestIncrement = true; |
<> | 144:ef7eb2e8f9f7 | 220 | * transferConfig.srcSize = kDMA_Transfersize32bits; |
<> | 144:ef7eb2e8f9f7 | 221 | * transferConfig.destSize = kDMA_Transfersize32bits; |
<> | 144:ef7eb2e8f9f7 | 222 | * transferConfig.transferSize = sizeof(uint32_t) * BUFF_LENGTH; |
<> | 144:ef7eb2e8f9f7 | 223 | * DMA_SetTransferConfig(DMA0, 0, &transferConfig); |
<> | 144:ef7eb2e8f9f7 | 224 | * @endcode |
<> | 144:ef7eb2e8f9f7 | 225 | * |
<> | 144:ef7eb2e8f9f7 | 226 | * @param base DMA peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 227 | * @param channel DMA channel number. |
<> | 144:ef7eb2e8f9f7 | 228 | * @param config Pointer to the DMA transfer configuration structure. |
<> | 144:ef7eb2e8f9f7 | 229 | */ |
<> | 144:ef7eb2e8f9f7 | 230 | void DMA_SetTransferConfig(DMA_Type *base, uint32_t channel, const dma_transfer_config_t *config); |
<> | 144:ef7eb2e8f9f7 | 231 | |
<> | 144:ef7eb2e8f9f7 | 232 | /*! |
<> | 144:ef7eb2e8f9f7 | 233 | * @brief Configures the DMA channel link feature. |
<> | 144:ef7eb2e8f9f7 | 234 | * |
<> | 144:ef7eb2e8f9f7 | 235 | * This function allows DMA channels to have their transfers linked. The current DMA channel |
<> | 144:ef7eb2e8f9f7 | 236 | * triggers a DMA request to the linked channels (LCH1 or LCH2) depending on the channel link |
<> | 144:ef7eb2e8f9f7 | 237 | * type. |
<> | 144:ef7eb2e8f9f7 | 238 | * Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 |
<> | 144:ef7eb2e8f9f7 | 239 | * after the BCR decrements to 0 if the type is kDMA_ChannelLinkChannel1AndChannel2. |
<> | 144:ef7eb2e8f9f7 | 240 | * Perform a link to LCH1 after each cycle-steal transfer if the type is kDMA_ChannelLinkChannel1. |
<> | 144:ef7eb2e8f9f7 | 241 | * Perform a link to LCH1 after the BCR decrements to 0 if the type is kDMA_ChannelLinkChannel1AfterBCR0. |
<> | 144:ef7eb2e8f9f7 | 242 | * |
<> | 144:ef7eb2e8f9f7 | 243 | * @param base DMA peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 244 | * @param channel DMA channel number. |
<> | 144:ef7eb2e8f9f7 | 245 | * @param config Pointer to the channel link configuration structure. |
<> | 144:ef7eb2e8f9f7 | 246 | */ |
<> | 144:ef7eb2e8f9f7 | 247 | void DMA_SetChannelLinkConfig(DMA_Type *base, uint32_t channel, const dma_channel_link_config_t *config); |
<> | 144:ef7eb2e8f9f7 | 248 | |
<> | 144:ef7eb2e8f9f7 | 249 | /*! |
<> | 144:ef7eb2e8f9f7 | 250 | * @brief Sets the DMA source address for the DMA transfer. |
<> | 144:ef7eb2e8f9f7 | 251 | * |
<> | 144:ef7eb2e8f9f7 | 252 | * @param base DMA peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 253 | * @param channel DMA channel number. |
<> | 144:ef7eb2e8f9f7 | 254 | * @param srcAddr DMA source address. |
<> | 144:ef7eb2e8f9f7 | 255 | */ |
<> | 144:ef7eb2e8f9f7 | 256 | static inline void DMA_SetSourceAddress(DMA_Type *base, uint32_t channel, uint32_t srcAddr) |
<> | 144:ef7eb2e8f9f7 | 257 | { |
<> | 144:ef7eb2e8f9f7 | 258 | assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); |
<> | 144:ef7eb2e8f9f7 | 259 | |
<> | 144:ef7eb2e8f9f7 | 260 | base->DMA[channel].SAR = srcAddr; |
<> | 144:ef7eb2e8f9f7 | 261 | } |
<> | 144:ef7eb2e8f9f7 | 262 | |
<> | 144:ef7eb2e8f9f7 | 263 | /*! |
<> | 144:ef7eb2e8f9f7 | 264 | * @brief Sets the DMA destination address for the DMA transfer. |
<> | 144:ef7eb2e8f9f7 | 265 | * |
<> | 144:ef7eb2e8f9f7 | 266 | * @param base DMA peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 267 | * @param channel DMA channel number. |
<> | 144:ef7eb2e8f9f7 | 268 | * @param destAddr DMA destination address. |
<> | 144:ef7eb2e8f9f7 | 269 | */ |
<> | 144:ef7eb2e8f9f7 | 270 | static inline void DMA_SetDestinationAddress(DMA_Type *base, uint32_t channel, uint32_t destAddr) |
<> | 144:ef7eb2e8f9f7 | 271 | { |
<> | 144:ef7eb2e8f9f7 | 272 | assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); |
<> | 144:ef7eb2e8f9f7 | 273 | |
<> | 144:ef7eb2e8f9f7 | 274 | base->DMA[channel].DAR = destAddr; |
<> | 144:ef7eb2e8f9f7 | 275 | } |
<> | 144:ef7eb2e8f9f7 | 276 | |
<> | 144:ef7eb2e8f9f7 | 277 | /*! |
<> | 144:ef7eb2e8f9f7 | 278 | * @brief Sets the DMA transfer size for the DMA transfer. |
<> | 144:ef7eb2e8f9f7 | 279 | * |
<> | 144:ef7eb2e8f9f7 | 280 | * @param base DMA peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 281 | * @param channel DMA channel number. |
<> | 144:ef7eb2e8f9f7 | 282 | * @param size The number of bytes to be transferred. |
<> | 144:ef7eb2e8f9f7 | 283 | */ |
<> | 144:ef7eb2e8f9f7 | 284 | static inline void DMA_SetTransferSize(DMA_Type *base, uint32_t channel, uint32_t size) |
<> | 144:ef7eb2e8f9f7 | 285 | { |
<> | 144:ef7eb2e8f9f7 | 286 | assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); |
<> | 144:ef7eb2e8f9f7 | 287 | |
<> | 144:ef7eb2e8f9f7 | 288 | base->DMA[channel].DSR_BCR = DMA_DSR_BCR_BCR(size); |
<> | 144:ef7eb2e8f9f7 | 289 | } |
<> | 144:ef7eb2e8f9f7 | 290 | |
<> | 144:ef7eb2e8f9f7 | 291 | /*! |
<> | 144:ef7eb2e8f9f7 | 292 | * @brief Sets the DMA modulo for the DMA transfer. |
<> | 144:ef7eb2e8f9f7 | 293 | * |
<> | 144:ef7eb2e8f9f7 | 294 | * This function defines a specific address range specified to be the value after (SAR + SSIZE)/(DAR + DSIZE) |
<> | 144:ef7eb2e8f9f7 | 295 | * calculation is performed or the original register value. It provides the ability to implement a circular |
<> | 144:ef7eb2e8f9f7 | 296 | * data queue easily. |
<> | 144:ef7eb2e8f9f7 | 297 | * |
<> | 144:ef7eb2e8f9f7 | 298 | * @param base DMA peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 299 | * @param channel DMA channel number. |
<> | 144:ef7eb2e8f9f7 | 300 | * @param srcModulo source address modulo. |
<> | 144:ef7eb2e8f9f7 | 301 | * @param destModulo destination address modulo. |
<> | 144:ef7eb2e8f9f7 | 302 | */ |
<> | 144:ef7eb2e8f9f7 | 303 | void DMA_SetModulo(DMA_Type *base, uint32_t channel, dma_modulo_t srcModulo, dma_modulo_t destModulo); |
<> | 144:ef7eb2e8f9f7 | 304 | |
<> | 144:ef7eb2e8f9f7 | 305 | /*! |
<> | 144:ef7eb2e8f9f7 | 306 | * @brief Enables the DMA cycle steal for the DMA transfer. |
<> | 144:ef7eb2e8f9f7 | 307 | * |
<> | 144:ef7eb2e8f9f7 | 308 | * If the cycle steal feature is enabled (true), the DMA controller forces a single read/write transfer per request, |
<> | 144:ef7eb2e8f9f7 | 309 | * or it continuously makes read/write transfers until the BCR decrements to 0. |
<> | 144:ef7eb2e8f9f7 | 310 | * |
<> | 144:ef7eb2e8f9f7 | 311 | * @param base DMA peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 312 | * @param channel DMA channel number. |
<> | 144:ef7eb2e8f9f7 | 313 | * @param enable The command for enable (true) or disable (false). |
<> | 144:ef7eb2e8f9f7 | 314 | */ |
<> | 144:ef7eb2e8f9f7 | 315 | static inline void DMA_EnableCycleSteal(DMA_Type *base, uint32_t channel, bool enable) |
<> | 144:ef7eb2e8f9f7 | 316 | { |
<> | 144:ef7eb2e8f9f7 | 317 | assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); |
<> | 144:ef7eb2e8f9f7 | 318 | |
<> | 144:ef7eb2e8f9f7 | 319 | base->DMA[channel].DCR = (base->DMA[channel].DCR & (~DMA_DCR_CS_MASK)) | DMA_DCR_CS(enable); |
<> | 144:ef7eb2e8f9f7 | 320 | } |
<> | 144:ef7eb2e8f9f7 | 321 | |
<> | 144:ef7eb2e8f9f7 | 322 | /*! |
<> | 144:ef7eb2e8f9f7 | 323 | * @brief Enables the DMA auto align for the DMA transfer. |
<> | 144:ef7eb2e8f9f7 | 324 | * |
<> | 144:ef7eb2e8f9f7 | 325 | * If the auto align feature is enabled (true), the appropriate address register increments, |
<> | 144:ef7eb2e8f9f7 | 326 | * regardless of DINC or SINC. |
<> | 144:ef7eb2e8f9f7 | 327 | * |
<> | 144:ef7eb2e8f9f7 | 328 | * @param base DMA peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 329 | * @param channel DMA channel number. |
<> | 144:ef7eb2e8f9f7 | 330 | * @param enable The command for enable (true) or disable (false). |
<> | 144:ef7eb2e8f9f7 | 331 | */ |
<> | 144:ef7eb2e8f9f7 | 332 | static inline void DMA_EnableAutoAlign(DMA_Type *base, uint32_t channel, bool enable) |
<> | 144:ef7eb2e8f9f7 | 333 | { |
<> | 144:ef7eb2e8f9f7 | 334 | assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); |
<> | 144:ef7eb2e8f9f7 | 335 | |
<> | 144:ef7eb2e8f9f7 | 336 | base->DMA[channel].DCR = (base->DMA[channel].DCR & (~DMA_DCR_AA_MASK)) | DMA_DCR_AA(enable); |
<> | 144:ef7eb2e8f9f7 | 337 | } |
<> | 144:ef7eb2e8f9f7 | 338 | |
<> | 144:ef7eb2e8f9f7 | 339 | /*! |
<> | 144:ef7eb2e8f9f7 | 340 | * @brief Enables the DMA async request for the DMA transfer. |
<> | 144:ef7eb2e8f9f7 | 341 | * |
<> | 144:ef7eb2e8f9f7 | 342 | * If the async request feature is enabled (true), the DMA supports asynchronous DREQs |
<> | 144:ef7eb2e8f9f7 | 343 | * while the MCU is in stop mode. |
<> | 144:ef7eb2e8f9f7 | 344 | * |
<> | 144:ef7eb2e8f9f7 | 345 | * @param base DMA peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 346 | * @param channel DMA channel number. |
<> | 144:ef7eb2e8f9f7 | 347 | * @param enable The command for enable (true) or disable (false). |
<> | 144:ef7eb2e8f9f7 | 348 | */ |
<> | 144:ef7eb2e8f9f7 | 349 | static inline void DMA_EnableAsyncRequest(DMA_Type *base, uint32_t channel, bool enable) |
<> | 144:ef7eb2e8f9f7 | 350 | { |
<> | 144:ef7eb2e8f9f7 | 351 | assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); |
<> | 144:ef7eb2e8f9f7 | 352 | |
<> | 144:ef7eb2e8f9f7 | 353 | base->DMA[channel].DCR = (base->DMA[channel].DCR & (~DMA_DCR_EADREQ_MASK)) | DMA_DCR_EADREQ(enable); |
<> | 144:ef7eb2e8f9f7 | 354 | } |
<> | 144:ef7eb2e8f9f7 | 355 | |
<> | 144:ef7eb2e8f9f7 | 356 | /*! |
<> | 144:ef7eb2e8f9f7 | 357 | * @brief Enables an interrupt for the DMA transfer. |
<> | 144:ef7eb2e8f9f7 | 358 | * |
<> | 144:ef7eb2e8f9f7 | 359 | * @param base DMA peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 360 | * @param channel DMA channel number. |
<> | 144:ef7eb2e8f9f7 | 361 | */ |
<> | 144:ef7eb2e8f9f7 | 362 | static inline void DMA_EnableInterrupts(DMA_Type *base, uint32_t channel) |
<> | 144:ef7eb2e8f9f7 | 363 | { |
<> | 144:ef7eb2e8f9f7 | 364 | assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); |
<> | 144:ef7eb2e8f9f7 | 365 | |
<> | 144:ef7eb2e8f9f7 | 366 | base->DMA[channel].DCR |= DMA_DCR_EINT(true); |
<> | 144:ef7eb2e8f9f7 | 367 | } |
<> | 144:ef7eb2e8f9f7 | 368 | |
<> | 144:ef7eb2e8f9f7 | 369 | /*! |
<> | 144:ef7eb2e8f9f7 | 370 | * @brief Disables an interrupt for the DMA transfer. |
<> | 144:ef7eb2e8f9f7 | 371 | * |
<> | 144:ef7eb2e8f9f7 | 372 | * @param base DMA peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 373 | * @param channel DMA channel number. |
<> | 144:ef7eb2e8f9f7 | 374 | */ |
<> | 144:ef7eb2e8f9f7 | 375 | static inline void DMA_DisableInterrupts(DMA_Type *base, uint32_t channel) |
<> | 144:ef7eb2e8f9f7 | 376 | { |
<> | 144:ef7eb2e8f9f7 | 377 | assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); |
<> | 144:ef7eb2e8f9f7 | 378 | |
<> | 144:ef7eb2e8f9f7 | 379 | base->DMA[channel].DCR &= ~DMA_DCR_EINT_MASK; |
<> | 144:ef7eb2e8f9f7 | 380 | } |
<> | 144:ef7eb2e8f9f7 | 381 | |
<> | 144:ef7eb2e8f9f7 | 382 | /* @} */ |
<> | 144:ef7eb2e8f9f7 | 383 | /*! |
<> | 144:ef7eb2e8f9f7 | 384 | * @name DMA Channel Transfer Operation |
<> | 144:ef7eb2e8f9f7 | 385 | * @{ |
<> | 144:ef7eb2e8f9f7 | 386 | */ |
<> | 144:ef7eb2e8f9f7 | 387 | |
<> | 144:ef7eb2e8f9f7 | 388 | /*! |
<> | 144:ef7eb2e8f9f7 | 389 | * @brief Enables the DMA hardware channel request. |
<> | 144:ef7eb2e8f9f7 | 390 | * |
<> | 144:ef7eb2e8f9f7 | 391 | * @param base DMA peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 392 | * @param channel The DMA channel number. |
<> | 144:ef7eb2e8f9f7 | 393 | */ |
<> | 144:ef7eb2e8f9f7 | 394 | static inline void DMA_EnableChannelRequest(DMA_Type *base, uint32_t channel) |
<> | 144:ef7eb2e8f9f7 | 395 | { |
<> | 144:ef7eb2e8f9f7 | 396 | assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); |
<> | 144:ef7eb2e8f9f7 | 397 | |
<> | 144:ef7eb2e8f9f7 | 398 | base->DMA[channel].DCR |= DMA_DCR_ERQ_MASK; |
<> | 144:ef7eb2e8f9f7 | 399 | } |
<> | 144:ef7eb2e8f9f7 | 400 | |
<> | 144:ef7eb2e8f9f7 | 401 | /*! |
<> | 144:ef7eb2e8f9f7 | 402 | * @brief Disables the DMA hardware channel request. |
<> | 144:ef7eb2e8f9f7 | 403 | * |
<> | 144:ef7eb2e8f9f7 | 404 | * @param base DMA peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 405 | * @param channel DMA channel number. |
<> | 144:ef7eb2e8f9f7 | 406 | */ |
<> | 144:ef7eb2e8f9f7 | 407 | static inline void DMA_DisableChannelRequest(DMA_Type *base, uint32_t channel) |
<> | 144:ef7eb2e8f9f7 | 408 | { |
<> | 144:ef7eb2e8f9f7 | 409 | assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); |
<> | 144:ef7eb2e8f9f7 | 410 | |
<> | 144:ef7eb2e8f9f7 | 411 | base->DMA[channel].DCR &= ~DMA_DCR_ERQ_MASK; |
<> | 144:ef7eb2e8f9f7 | 412 | } |
<> | 144:ef7eb2e8f9f7 | 413 | |
<> | 144:ef7eb2e8f9f7 | 414 | /*! |
<> | 144:ef7eb2e8f9f7 | 415 | * @brief Starts the DMA transfer with a software trigger. |
<> | 144:ef7eb2e8f9f7 | 416 | * |
<> | 144:ef7eb2e8f9f7 | 417 | * This function starts only one read/write iteration. |
<> | 144:ef7eb2e8f9f7 | 418 | * |
<> | 144:ef7eb2e8f9f7 | 419 | * @param base DMA peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 420 | * @param channel The DMA channel number. |
<> | 144:ef7eb2e8f9f7 | 421 | */ |
<> | 144:ef7eb2e8f9f7 | 422 | static inline void DMA_TriggerChannelStart(DMA_Type *base, uint32_t channel) |
<> | 144:ef7eb2e8f9f7 | 423 | { |
<> | 144:ef7eb2e8f9f7 | 424 | assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); |
<> | 144:ef7eb2e8f9f7 | 425 | |
<> | 144:ef7eb2e8f9f7 | 426 | base->DMA[channel].DCR |= DMA_DCR_START_MASK; |
<> | 144:ef7eb2e8f9f7 | 427 | } |
<> | 144:ef7eb2e8f9f7 | 428 | |
<> | 144:ef7eb2e8f9f7 | 429 | /* @} */ |
<> | 144:ef7eb2e8f9f7 | 430 | /*! |
<> | 144:ef7eb2e8f9f7 | 431 | * @name DMA Channel Status Operation |
<> | 144:ef7eb2e8f9f7 | 432 | * @{ |
<> | 144:ef7eb2e8f9f7 | 433 | */ |
<> | 144:ef7eb2e8f9f7 | 434 | |
<> | 144:ef7eb2e8f9f7 | 435 | /*! |
<> | 144:ef7eb2e8f9f7 | 436 | * @brief Gets the remaining bytes of the current DMA transfer. |
<> | 144:ef7eb2e8f9f7 | 437 | * |
<> | 144:ef7eb2e8f9f7 | 438 | * @param base DMA peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 439 | * @param channel DMA channel number. |
<> | 144:ef7eb2e8f9f7 | 440 | * @return The number of bytes which have not been transferred yet. |
<> | 144:ef7eb2e8f9f7 | 441 | */ |
<> | 144:ef7eb2e8f9f7 | 442 | static inline uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel) |
<> | 144:ef7eb2e8f9f7 | 443 | { |
<> | 144:ef7eb2e8f9f7 | 444 | assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); |
<> | 144:ef7eb2e8f9f7 | 445 | |
<> | 144:ef7eb2e8f9f7 | 446 | return (base->DMA[channel].DSR_BCR & DMA_DSR_BCR_BCR_MASK) >> DMA_DSR_BCR_BCR_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 447 | } |
<> | 144:ef7eb2e8f9f7 | 448 | |
<> | 144:ef7eb2e8f9f7 | 449 | /*! |
<> | 144:ef7eb2e8f9f7 | 450 | * @brief Gets the DMA channel status flags. |
<> | 144:ef7eb2e8f9f7 | 451 | * |
<> | 144:ef7eb2e8f9f7 | 452 | * @param base DMA peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 453 | * @param channel DMA channel number. |
<> | 144:ef7eb2e8f9f7 | 454 | * @return The mask of the channel status. Use the _dma_channel_status_flags |
<> | 144:ef7eb2e8f9f7 | 455 | * type to decode the return 32 bit variables. |
<> | 144:ef7eb2e8f9f7 | 456 | */ |
<> | 144:ef7eb2e8f9f7 | 457 | static inline uint32_t DMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel) |
<> | 144:ef7eb2e8f9f7 | 458 | { |
<> | 144:ef7eb2e8f9f7 | 459 | assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); |
<> | 144:ef7eb2e8f9f7 | 460 | |
<> | 144:ef7eb2e8f9f7 | 461 | return base->DMA[channel].DSR_BCR; |
<> | 144:ef7eb2e8f9f7 | 462 | } |
<> | 144:ef7eb2e8f9f7 | 463 | |
<> | 144:ef7eb2e8f9f7 | 464 | /*! |
<> | 144:ef7eb2e8f9f7 | 465 | * @brief Clears the DMA channel status flags. |
<> | 144:ef7eb2e8f9f7 | 466 | * |
<> | 144:ef7eb2e8f9f7 | 467 | * @param base DMA peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 468 | * @param channel DMA channel number. |
<> | 144:ef7eb2e8f9f7 | 469 | * @param mask The mask of the channel status to be cleared. Use |
<> | 144:ef7eb2e8f9f7 | 470 | * the defined _dma_channel_status_flags type. |
<> | 144:ef7eb2e8f9f7 | 471 | */ |
<> | 144:ef7eb2e8f9f7 | 472 | static inline void DMA_ClearChannelStatusFlags(DMA_Type *base, uint32_t channel, uint32_t mask) |
<> | 144:ef7eb2e8f9f7 | 473 | { |
<> | 144:ef7eb2e8f9f7 | 474 | assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); |
<> | 144:ef7eb2e8f9f7 | 475 | |
<> | 144:ef7eb2e8f9f7 | 476 | if (mask != 0U) |
<> | 144:ef7eb2e8f9f7 | 477 | { |
<> | 144:ef7eb2e8f9f7 | 478 | base->DMA[channel].DSR_BCR |= DMA_DSR_BCR_DONE(true); |
<> | 144:ef7eb2e8f9f7 | 479 | } |
<> | 144:ef7eb2e8f9f7 | 480 | } |
<> | 144:ef7eb2e8f9f7 | 481 | |
<> | 144:ef7eb2e8f9f7 | 482 | /* @} */ |
<> | 144:ef7eb2e8f9f7 | 483 | /*! |
<> | 144:ef7eb2e8f9f7 | 484 | * @name DMA Channel Transactional Operation |
<> | 144:ef7eb2e8f9f7 | 485 | * @{ |
<> | 144:ef7eb2e8f9f7 | 486 | */ |
<> | 144:ef7eb2e8f9f7 | 487 | |
<> | 144:ef7eb2e8f9f7 | 488 | /*! |
<> | 144:ef7eb2e8f9f7 | 489 | * @brief Creates the DMA handle. |
<> | 144:ef7eb2e8f9f7 | 490 | * |
<> | 144:ef7eb2e8f9f7 | 491 | * This function is called first if using the transactional API for the DMA. This function |
<> | 144:ef7eb2e8f9f7 | 492 | * initializes the internal state of the DMA handle. |
<> | 144:ef7eb2e8f9f7 | 493 | * |
<> | 144:ef7eb2e8f9f7 | 494 | * @param handle DMA handle pointer. The DMA handle stores callback function and |
<> | 144:ef7eb2e8f9f7 | 495 | * parameters. |
<> | 144:ef7eb2e8f9f7 | 496 | * @param base DMA peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 497 | * @param channel DMA channel number. |
<> | 144:ef7eb2e8f9f7 | 498 | */ |
<> | 144:ef7eb2e8f9f7 | 499 | void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel); |
<> | 144:ef7eb2e8f9f7 | 500 | |
<> | 144:ef7eb2e8f9f7 | 501 | /*! |
<> | 144:ef7eb2e8f9f7 | 502 | * @brief Sets the DMA callback function. |
<> | 144:ef7eb2e8f9f7 | 503 | * |
<> | 144:ef7eb2e8f9f7 | 504 | * This callback is called in the DMA IRQ handler. Use the callback to do something |
<> | 144:ef7eb2e8f9f7 | 505 | * after the current transfer complete. |
<> | 144:ef7eb2e8f9f7 | 506 | * |
<> | 144:ef7eb2e8f9f7 | 507 | * @param handle DMA handle pointer. |
<> | 144:ef7eb2e8f9f7 | 508 | * @param callback DMA callback function pointer. |
<> | 144:ef7eb2e8f9f7 | 509 | * @param userData Parameter for callback function. If it is not needed, just set to NULL. |
<> | 144:ef7eb2e8f9f7 | 510 | */ |
<> | 144:ef7eb2e8f9f7 | 511 | void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData); |
<> | 144:ef7eb2e8f9f7 | 512 | |
<> | 144:ef7eb2e8f9f7 | 513 | /*! |
<> | 144:ef7eb2e8f9f7 | 514 | * @brief Prepares the DMA transfer configuration structure. |
<> | 144:ef7eb2e8f9f7 | 515 | * |
<> | 144:ef7eb2e8f9f7 | 516 | * This function prepares the transfer configuration structure according to the user input. |
<> | 144:ef7eb2e8f9f7 | 517 | * |
<> | 144:ef7eb2e8f9f7 | 518 | * @param config Pointer to the user configuration structure of type dma_transfer_config_t. |
<> | 144:ef7eb2e8f9f7 | 519 | * @param srcAddr DMA transfer source address. |
<> | 144:ef7eb2e8f9f7 | 520 | * @param srcWidth DMA transfer source address width (byte). |
<> | 144:ef7eb2e8f9f7 | 521 | * @param destAddr DMA transfer destination address. |
<> | 144:ef7eb2e8f9f7 | 522 | * @param destWidth DMA transfer destination address width (byte). |
<> | 144:ef7eb2e8f9f7 | 523 | * @param transferBytes DMA transfer bytes to be transferred. |
<> | 144:ef7eb2e8f9f7 | 524 | * @param type DMA transfer type. |
<> | 144:ef7eb2e8f9f7 | 525 | */ |
<> | 144:ef7eb2e8f9f7 | 526 | void DMA_PrepareTransfer(dma_transfer_config_t *config, |
<> | 144:ef7eb2e8f9f7 | 527 | void *srcAddr, |
<> | 144:ef7eb2e8f9f7 | 528 | uint32_t srcWidth, |
<> | 144:ef7eb2e8f9f7 | 529 | void *destAddr, |
<> | 144:ef7eb2e8f9f7 | 530 | uint32_t destWidth, |
<> | 144:ef7eb2e8f9f7 | 531 | uint32_t transferBytes, |
<> | 144:ef7eb2e8f9f7 | 532 | dma_transfer_type_t type); |
<> | 144:ef7eb2e8f9f7 | 533 | |
<> | 144:ef7eb2e8f9f7 | 534 | /*! |
<> | 144:ef7eb2e8f9f7 | 535 | * @brief Submits the DMA transfer request. |
<> | 144:ef7eb2e8f9f7 | 536 | * |
<> | 144:ef7eb2e8f9f7 | 537 | * This function submits the DMA transfer request according to the transfer configuration structure. |
<> | 144:ef7eb2e8f9f7 | 538 | * |
<> | 144:ef7eb2e8f9f7 | 539 | * @param handle DMA handle pointer. |
<> | 144:ef7eb2e8f9f7 | 540 | * @param config Pointer to DMA transfer configuration structure. |
<> | 144:ef7eb2e8f9f7 | 541 | * @param options Additional configurations for transfer. Use |
<> | 144:ef7eb2e8f9f7 | 542 | * the defined dma_transfer_options_t type. |
<> | 144:ef7eb2e8f9f7 | 543 | * @retval kStatus_DMA_Success It indicates that the DMA submit transfer request succeeded. |
<> | 144:ef7eb2e8f9f7 | 544 | * @retval kStatus_DMA_Busy It indicates that the DMA is busy. Submit transfer request is not allowed. |
<> | 144:ef7eb2e8f9f7 | 545 | * @note This function can't process multi transfer request. |
<> | 144:ef7eb2e8f9f7 | 546 | */ |
<> | 144:ef7eb2e8f9f7 | 547 | status_t DMA_SubmitTransfer(dma_handle_t *handle, const dma_transfer_config_t *config, uint32_t options); |
<> | 144:ef7eb2e8f9f7 | 548 | |
<> | 144:ef7eb2e8f9f7 | 549 | /*! |
<> | 144:ef7eb2e8f9f7 | 550 | * @brief DMA starts a transfer. |
<> | 144:ef7eb2e8f9f7 | 551 | * |
<> | 144:ef7eb2e8f9f7 | 552 | * This function enables the channel request. Call this function |
<> | 144:ef7eb2e8f9f7 | 553 | * after submitting a transfer request. |
<> | 144:ef7eb2e8f9f7 | 554 | * |
<> | 144:ef7eb2e8f9f7 | 555 | * @param handle DMA handle pointer. |
<> | 144:ef7eb2e8f9f7 | 556 | * @retval kStatus_DMA_Success It indicates that the DMA start transfer succeed. |
<> | 144:ef7eb2e8f9f7 | 557 | * @retval kStatus_DMA_Busy It indicates that the DMA has started a transfer. |
<> | 144:ef7eb2e8f9f7 | 558 | */ |
<> | 144:ef7eb2e8f9f7 | 559 | static inline void DMA_StartTransfer(dma_handle_t *handle) |
<> | 144:ef7eb2e8f9f7 | 560 | { |
<> | 144:ef7eb2e8f9f7 | 561 | assert(handle != NULL); |
<> | 144:ef7eb2e8f9f7 | 562 | |
<> | 144:ef7eb2e8f9f7 | 563 | handle->base->DMA[handle->channel].DCR |= DMA_DCR_ERQ_MASK; |
<> | 144:ef7eb2e8f9f7 | 564 | } |
<> | 144:ef7eb2e8f9f7 | 565 | |
<> | 144:ef7eb2e8f9f7 | 566 | /*! |
<> | 144:ef7eb2e8f9f7 | 567 | * @brief DMA stops a transfer. |
<> | 144:ef7eb2e8f9f7 | 568 | * |
<> | 144:ef7eb2e8f9f7 | 569 | * This function disables the channel request to stop a DMA transfer. |
<> | 144:ef7eb2e8f9f7 | 570 | * The transfer can be resumed by calling the DMA_StartTransfer. |
<> | 144:ef7eb2e8f9f7 | 571 | * |
<> | 144:ef7eb2e8f9f7 | 572 | * @param handle DMA handle pointer. |
<> | 144:ef7eb2e8f9f7 | 573 | */ |
<> | 144:ef7eb2e8f9f7 | 574 | static inline void DMA_StopTransfer(dma_handle_t *handle) |
<> | 144:ef7eb2e8f9f7 | 575 | { |
<> | 144:ef7eb2e8f9f7 | 576 | assert(handle != NULL); |
<> | 144:ef7eb2e8f9f7 | 577 | |
<> | 144:ef7eb2e8f9f7 | 578 | handle->base->DMA[handle->channel].DCR &= ~DMA_DCR_ERQ_MASK; |
<> | 144:ef7eb2e8f9f7 | 579 | } |
<> | 144:ef7eb2e8f9f7 | 580 | |
<> | 144:ef7eb2e8f9f7 | 581 | /*! |
<> | 144:ef7eb2e8f9f7 | 582 | * @brief DMA aborts a transfer. |
<> | 144:ef7eb2e8f9f7 | 583 | * |
<> | 144:ef7eb2e8f9f7 | 584 | * This function disables the channel request and clears all status bits. |
<> | 144:ef7eb2e8f9f7 | 585 | * Submit another transfer after calling this API. |
<> | 144:ef7eb2e8f9f7 | 586 | * |
<> | 144:ef7eb2e8f9f7 | 587 | * @param handle DMA handle pointer. |
<> | 144:ef7eb2e8f9f7 | 588 | */ |
<> | 144:ef7eb2e8f9f7 | 589 | void DMA_AbortTransfer(dma_handle_t *handle); |
<> | 144:ef7eb2e8f9f7 | 590 | |
<> | 144:ef7eb2e8f9f7 | 591 | /*! |
<> | 144:ef7eb2e8f9f7 | 592 | * @brief DMA IRQ handler for current transfer complete. |
<> | 144:ef7eb2e8f9f7 | 593 | * |
<> | 144:ef7eb2e8f9f7 | 594 | * This function clears the channel interrupt flag and calls |
<> | 144:ef7eb2e8f9f7 | 595 | * the callback function if it is not NULL. |
<> | 144:ef7eb2e8f9f7 | 596 | * |
<> | 144:ef7eb2e8f9f7 | 597 | * @param handle DMA handle pointer. |
<> | 144:ef7eb2e8f9f7 | 598 | */ |
<> | 144:ef7eb2e8f9f7 | 599 | void DMA_HandleIRQ(dma_handle_t *handle); |
<> | 144:ef7eb2e8f9f7 | 600 | |
<> | 144:ef7eb2e8f9f7 | 601 | /* @} */ |
<> | 144:ef7eb2e8f9f7 | 602 | |
<> | 144:ef7eb2e8f9f7 | 603 | #if defined(__cplusplus) |
<> | 144:ef7eb2e8f9f7 | 604 | } |
<> | 144:ef7eb2e8f9f7 | 605 | #endif /* __cplusplus */ |
<> | 144:ef7eb2e8f9f7 | 606 | |
<> | 144:ef7eb2e8f9f7 | 607 | /* @}*/ |
<> | 144:ef7eb2e8f9f7 | 608 | |
<> | 144:ef7eb2e8f9f7 | 609 | #endif /* _FSL_DMA_H_ */ |