added prescaler for 16 bit pwm in LPC1347 target
Fork of mbed-dev by
targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/drivers/fsl_dma.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)
- Committer:
- <>
- Date:
- Fri Sep 02 15:07:44 2016 +0100
- Revision:
- 144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /* |
<> | 144:ef7eb2e8f9f7 | 2 | * Copyright (c) 2015, Freescale Semiconductor, Inc. |
<> | 144:ef7eb2e8f9f7 | 3 | * All rights reserved. |
<> | 144:ef7eb2e8f9f7 | 4 | * |
<> | 144:ef7eb2e8f9f7 | 5 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 144:ef7eb2e8f9f7 | 6 | * are permitted provided that the following conditions are met: |
<> | 144:ef7eb2e8f9f7 | 7 | * |
<> | 144:ef7eb2e8f9f7 | 8 | * o Redistributions of source code must retain the above copyright notice, this list |
<> | 144:ef7eb2e8f9f7 | 9 | * of conditions and the following disclaimer. |
<> | 144:ef7eb2e8f9f7 | 10 | * |
<> | 144:ef7eb2e8f9f7 | 11 | * o Redistributions in binary form must reproduce the above copyright notice, this |
<> | 144:ef7eb2e8f9f7 | 12 | * list of conditions and the following disclaimer in the documentation and/or |
<> | 144:ef7eb2e8f9f7 | 13 | * other materials provided with the distribution. |
<> | 144:ef7eb2e8f9f7 | 14 | * |
<> | 144:ef7eb2e8f9f7 | 15 | * o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
<> | 144:ef7eb2e8f9f7 | 16 | * contributors may be used to endorse or promote products derived from this |
<> | 144:ef7eb2e8f9f7 | 17 | * software without specific prior written permission. |
<> | 144:ef7eb2e8f9f7 | 18 | * |
<> | 144:ef7eb2e8f9f7 | 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
<> | 144:ef7eb2e8f9f7 | 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
<> | 144:ef7eb2e8f9f7 | 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 144:ef7eb2e8f9f7 | 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
<> | 144:ef7eb2e8f9f7 | 23 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
<> | 144:ef7eb2e8f9f7 | 24 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
<> | 144:ef7eb2e8f9f7 | 25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
<> | 144:ef7eb2e8f9f7 | 26 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
<> | 144:ef7eb2e8f9f7 | 27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
<> | 144:ef7eb2e8f9f7 | 28 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 144:ef7eb2e8f9f7 | 29 | */ |
<> | 144:ef7eb2e8f9f7 | 30 | |
<> | 144:ef7eb2e8f9f7 | 31 | #include "fsl_dma.h" |
<> | 144:ef7eb2e8f9f7 | 32 | |
<> | 144:ef7eb2e8f9f7 | 33 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 34 | * Definitions |
<> | 144:ef7eb2e8f9f7 | 35 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 36 | |
<> | 144:ef7eb2e8f9f7 | 37 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 38 | * Prototypes |
<> | 144:ef7eb2e8f9f7 | 39 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 40 | |
<> | 144:ef7eb2e8f9f7 | 41 | /*! |
<> | 144:ef7eb2e8f9f7 | 42 | * @brief Get instance number for DMA. |
<> | 144:ef7eb2e8f9f7 | 43 | * |
<> | 144:ef7eb2e8f9f7 | 44 | * @param base DMA peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 45 | */ |
<> | 144:ef7eb2e8f9f7 | 46 | static uint32_t DMA_GetInstance(DMA_Type *base); |
<> | 144:ef7eb2e8f9f7 | 47 | |
<> | 144:ef7eb2e8f9f7 | 48 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 49 | * Variables |
<> | 144:ef7eb2e8f9f7 | 50 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 51 | |
<> | 144:ef7eb2e8f9f7 | 52 | /*! @brief Array to map DMA instance number to base pointer. */ |
<> | 144:ef7eb2e8f9f7 | 53 | static DMA_Type *const s_dmaBases[] = DMA_BASE_PTRS; |
<> | 144:ef7eb2e8f9f7 | 54 | |
<> | 144:ef7eb2e8f9f7 | 55 | /*! @brief Array to map DMA instance number to clock name. */ |
<> | 144:ef7eb2e8f9f7 | 56 | static const clock_ip_name_t s_dmaClockName[] = DMA_CLOCKS; |
<> | 144:ef7eb2e8f9f7 | 57 | |
<> | 144:ef7eb2e8f9f7 | 58 | /*! @brief Array to map DMA instance number to IRQ number. */ |
<> | 144:ef7eb2e8f9f7 | 59 | static const IRQn_Type s_dmaIRQNumber[] = DMA_CHN_IRQS; |
<> | 144:ef7eb2e8f9f7 | 60 | |
<> | 144:ef7eb2e8f9f7 | 61 | /*! @brief Pointers to transfer handle for each DMA channel. */ |
<> | 144:ef7eb2e8f9f7 | 62 | static dma_handle_t *s_DMAHandle[FSL_FEATURE_DMAMUX_MODULE_CHANNEL * FSL_FEATURE_SOC_DMA_COUNT]; |
<> | 144:ef7eb2e8f9f7 | 63 | |
<> | 144:ef7eb2e8f9f7 | 64 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 65 | * Code |
<> | 144:ef7eb2e8f9f7 | 66 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 67 | static uint32_t DMA_GetInstance(DMA_Type *base) |
<> | 144:ef7eb2e8f9f7 | 68 | { |
<> | 144:ef7eb2e8f9f7 | 69 | uint32_t instance; |
<> | 144:ef7eb2e8f9f7 | 70 | |
<> | 144:ef7eb2e8f9f7 | 71 | /* Find the instance index from base address mappings. */ |
<> | 144:ef7eb2e8f9f7 | 72 | for (instance = 0; instance < FSL_FEATURE_SOC_DMA_COUNT; instance++) |
<> | 144:ef7eb2e8f9f7 | 73 | { |
<> | 144:ef7eb2e8f9f7 | 74 | if (s_dmaBases[instance] == base) |
<> | 144:ef7eb2e8f9f7 | 75 | { |
<> | 144:ef7eb2e8f9f7 | 76 | break; |
<> | 144:ef7eb2e8f9f7 | 77 | } |
<> | 144:ef7eb2e8f9f7 | 78 | } |
<> | 144:ef7eb2e8f9f7 | 79 | |
<> | 144:ef7eb2e8f9f7 | 80 | assert(instance < FSL_FEATURE_SOC_DMA_COUNT); |
<> | 144:ef7eb2e8f9f7 | 81 | |
<> | 144:ef7eb2e8f9f7 | 82 | return instance; |
<> | 144:ef7eb2e8f9f7 | 83 | } |
<> | 144:ef7eb2e8f9f7 | 84 | |
<> | 144:ef7eb2e8f9f7 | 85 | void DMA_Init(DMA_Type *base) |
<> | 144:ef7eb2e8f9f7 | 86 | { |
<> | 144:ef7eb2e8f9f7 | 87 | CLOCK_EnableClock(s_dmaClockName[DMA_GetInstance(base)]); |
<> | 144:ef7eb2e8f9f7 | 88 | } |
<> | 144:ef7eb2e8f9f7 | 89 | |
<> | 144:ef7eb2e8f9f7 | 90 | void DMA_Deinit(DMA_Type *base) |
<> | 144:ef7eb2e8f9f7 | 91 | { |
<> | 144:ef7eb2e8f9f7 | 92 | CLOCK_DisableClock(s_dmaClockName[DMA_GetInstance(base)]); |
<> | 144:ef7eb2e8f9f7 | 93 | } |
<> | 144:ef7eb2e8f9f7 | 94 | |
<> | 144:ef7eb2e8f9f7 | 95 | void DMA_ResetChannel(DMA_Type *base, uint32_t channel) |
<> | 144:ef7eb2e8f9f7 | 96 | { |
<> | 144:ef7eb2e8f9f7 | 97 | assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); |
<> | 144:ef7eb2e8f9f7 | 98 | |
<> | 144:ef7eb2e8f9f7 | 99 | /* clear all status bit */ |
<> | 144:ef7eb2e8f9f7 | 100 | base->DMA[channel].DSR_BCR |= DMA_DSR_BCR_DONE(true); |
<> | 144:ef7eb2e8f9f7 | 101 | /* clear all registers */ |
<> | 144:ef7eb2e8f9f7 | 102 | base->DMA[channel].SAR = 0; |
<> | 144:ef7eb2e8f9f7 | 103 | base->DMA[channel].DAR = 0; |
<> | 144:ef7eb2e8f9f7 | 104 | base->DMA[channel].DSR_BCR = 0; |
<> | 144:ef7eb2e8f9f7 | 105 | /* enable cycle steal and enable auto disable channel request */ |
<> | 144:ef7eb2e8f9f7 | 106 | base->DMA[channel].DCR = DMA_DCR_D_REQ(true) | DMA_DCR_CS(true); |
<> | 144:ef7eb2e8f9f7 | 107 | } |
<> | 144:ef7eb2e8f9f7 | 108 | |
<> | 144:ef7eb2e8f9f7 | 109 | void DMA_SetTransferConfig(DMA_Type *base, uint32_t channel, const dma_transfer_config_t *config) |
<> | 144:ef7eb2e8f9f7 | 110 | { |
<> | 144:ef7eb2e8f9f7 | 111 | assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); |
<> | 144:ef7eb2e8f9f7 | 112 | assert(config != NULL); |
<> | 144:ef7eb2e8f9f7 | 113 | |
<> | 144:ef7eb2e8f9f7 | 114 | uint32_t tmpreg; |
<> | 144:ef7eb2e8f9f7 | 115 | |
<> | 144:ef7eb2e8f9f7 | 116 | /* Set source address */ |
<> | 144:ef7eb2e8f9f7 | 117 | base->DMA[channel].SAR = config->srcAddr; |
<> | 144:ef7eb2e8f9f7 | 118 | /* Set destination address */ |
<> | 144:ef7eb2e8f9f7 | 119 | base->DMA[channel].DAR = config->destAddr; |
<> | 144:ef7eb2e8f9f7 | 120 | /* Set transfer bytes */ |
<> | 144:ef7eb2e8f9f7 | 121 | base->DMA[channel].DSR_BCR = DMA_DSR_BCR_BCR(config->transferSize); |
<> | 144:ef7eb2e8f9f7 | 122 | /* Set DMA Control Register */ |
<> | 144:ef7eb2e8f9f7 | 123 | tmpreg = base->DMA[channel].DCR; |
<> | 144:ef7eb2e8f9f7 | 124 | tmpreg &= ~(DMA_DCR_DSIZE_MASK | DMA_DCR_DINC_MASK | DMA_DCR_SSIZE_MASK | DMA_DCR_SINC_MASK); |
<> | 144:ef7eb2e8f9f7 | 125 | tmpreg |= (DMA_DCR_DSIZE(config->destSize) | DMA_DCR_DINC(config->enableDestIncrement) | |
<> | 144:ef7eb2e8f9f7 | 126 | DMA_DCR_SSIZE(config->srcSize) | DMA_DCR_SINC(config->enableSrcIncrement)); |
<> | 144:ef7eb2e8f9f7 | 127 | base->DMA[channel].DCR = tmpreg; |
<> | 144:ef7eb2e8f9f7 | 128 | } |
<> | 144:ef7eb2e8f9f7 | 129 | |
<> | 144:ef7eb2e8f9f7 | 130 | void DMA_SetChannelLinkConfig(DMA_Type *base, uint32_t channel, const dma_channel_link_config_t *config) |
<> | 144:ef7eb2e8f9f7 | 131 | { |
<> | 144:ef7eb2e8f9f7 | 132 | assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); |
<> | 144:ef7eb2e8f9f7 | 133 | assert(config != NULL); |
<> | 144:ef7eb2e8f9f7 | 134 | |
<> | 144:ef7eb2e8f9f7 | 135 | uint32_t tmpreg; |
<> | 144:ef7eb2e8f9f7 | 136 | |
<> | 144:ef7eb2e8f9f7 | 137 | tmpreg = base->DMA[channel].DCR; |
<> | 144:ef7eb2e8f9f7 | 138 | tmpreg &= ~(DMA_DCR_LINKCC_MASK | DMA_DCR_LCH1_MASK | DMA_DCR_LCH2_MASK); |
<> | 144:ef7eb2e8f9f7 | 139 | tmpreg |= (DMA_DCR_LINKCC(config->linkType) | DMA_DCR_LCH1(config->channel1) | DMA_DCR_LCH2(config->channel2)); |
<> | 144:ef7eb2e8f9f7 | 140 | base->DMA[channel].DCR = tmpreg; |
<> | 144:ef7eb2e8f9f7 | 141 | } |
<> | 144:ef7eb2e8f9f7 | 142 | |
<> | 144:ef7eb2e8f9f7 | 143 | void DMA_SetModulo(DMA_Type *base, uint32_t channel, dma_modulo_t srcModulo, dma_modulo_t destModulo) |
<> | 144:ef7eb2e8f9f7 | 144 | { |
<> | 144:ef7eb2e8f9f7 | 145 | assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); |
<> | 144:ef7eb2e8f9f7 | 146 | |
<> | 144:ef7eb2e8f9f7 | 147 | uint32_t tmpreg; |
<> | 144:ef7eb2e8f9f7 | 148 | |
<> | 144:ef7eb2e8f9f7 | 149 | tmpreg = base->DMA[channel].DCR; |
<> | 144:ef7eb2e8f9f7 | 150 | tmpreg &= ~(DMA_DCR_SMOD_MASK | DMA_DCR_DMOD_MASK); |
<> | 144:ef7eb2e8f9f7 | 151 | tmpreg |= (DMA_DCR_SMOD(srcModulo) | DMA_DCR_DMOD(destModulo)); |
<> | 144:ef7eb2e8f9f7 | 152 | base->DMA[channel].DCR = tmpreg; |
<> | 144:ef7eb2e8f9f7 | 153 | } |
<> | 144:ef7eb2e8f9f7 | 154 | |
<> | 144:ef7eb2e8f9f7 | 155 | void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel) |
<> | 144:ef7eb2e8f9f7 | 156 | { |
<> | 144:ef7eb2e8f9f7 | 157 | assert(handle != NULL); |
<> | 144:ef7eb2e8f9f7 | 158 | assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); |
<> | 144:ef7eb2e8f9f7 | 159 | |
<> | 144:ef7eb2e8f9f7 | 160 | uint32_t dmaInstance; |
<> | 144:ef7eb2e8f9f7 | 161 | uint32_t channelIndex; |
<> | 144:ef7eb2e8f9f7 | 162 | |
<> | 144:ef7eb2e8f9f7 | 163 | handle->base = base; |
<> | 144:ef7eb2e8f9f7 | 164 | handle->channel = channel; |
<> | 144:ef7eb2e8f9f7 | 165 | /* Get the DMA instance number */ |
<> | 144:ef7eb2e8f9f7 | 166 | dmaInstance = DMA_GetInstance(base); |
<> | 144:ef7eb2e8f9f7 | 167 | channelIndex = (dmaInstance * FSL_FEATURE_DMAMUX_MODULE_CHANNEL) + channel; |
<> | 144:ef7eb2e8f9f7 | 168 | /* Store handle */ |
<> | 144:ef7eb2e8f9f7 | 169 | s_DMAHandle[channelIndex] = handle; |
<> | 144:ef7eb2e8f9f7 | 170 | /* Enable NVIC interrupt. */ |
<> | 144:ef7eb2e8f9f7 | 171 | EnableIRQ(s_dmaIRQNumber[channelIndex]); |
<> | 144:ef7eb2e8f9f7 | 172 | } |
<> | 144:ef7eb2e8f9f7 | 173 | |
<> | 144:ef7eb2e8f9f7 | 174 | void DMA_PrepareTransfer(dma_transfer_config_t *config, |
<> | 144:ef7eb2e8f9f7 | 175 | void *srcAddr, |
<> | 144:ef7eb2e8f9f7 | 176 | uint32_t srcWidth, |
<> | 144:ef7eb2e8f9f7 | 177 | void *destAddr, |
<> | 144:ef7eb2e8f9f7 | 178 | uint32_t destWidth, |
<> | 144:ef7eb2e8f9f7 | 179 | uint32_t transferBytes, |
<> | 144:ef7eb2e8f9f7 | 180 | dma_transfer_type_t type) |
<> | 144:ef7eb2e8f9f7 | 181 | { |
<> | 144:ef7eb2e8f9f7 | 182 | assert(config != NULL); |
<> | 144:ef7eb2e8f9f7 | 183 | assert(srcAddr != NULL); |
<> | 144:ef7eb2e8f9f7 | 184 | assert(destAddr != NULL); |
<> | 144:ef7eb2e8f9f7 | 185 | assert(srcWidth == 1U || srcWidth == 2U || srcWidth == 4U); |
<> | 144:ef7eb2e8f9f7 | 186 | assert(destWidth == 1U || destWidth == 2U || destWidth == 4U); |
<> | 144:ef7eb2e8f9f7 | 187 | |
<> | 144:ef7eb2e8f9f7 | 188 | config->srcAddr = (uint32_t)srcAddr; |
<> | 144:ef7eb2e8f9f7 | 189 | config->destAddr = (uint32_t)destAddr; |
<> | 144:ef7eb2e8f9f7 | 190 | config->transferSize = transferBytes; |
<> | 144:ef7eb2e8f9f7 | 191 | switch (srcWidth) |
<> | 144:ef7eb2e8f9f7 | 192 | { |
<> | 144:ef7eb2e8f9f7 | 193 | case 1U: |
<> | 144:ef7eb2e8f9f7 | 194 | config->srcSize = kDMA_Transfersize8bits; |
<> | 144:ef7eb2e8f9f7 | 195 | break; |
<> | 144:ef7eb2e8f9f7 | 196 | case 2U: |
<> | 144:ef7eb2e8f9f7 | 197 | config->srcSize = kDMA_Transfersize16bits; |
<> | 144:ef7eb2e8f9f7 | 198 | break; |
<> | 144:ef7eb2e8f9f7 | 199 | case 4U: |
<> | 144:ef7eb2e8f9f7 | 200 | config->srcSize = kDMA_Transfersize32bits; |
<> | 144:ef7eb2e8f9f7 | 201 | break; |
<> | 144:ef7eb2e8f9f7 | 202 | default: |
<> | 144:ef7eb2e8f9f7 | 203 | break; |
<> | 144:ef7eb2e8f9f7 | 204 | } |
<> | 144:ef7eb2e8f9f7 | 205 | switch (destWidth) |
<> | 144:ef7eb2e8f9f7 | 206 | { |
<> | 144:ef7eb2e8f9f7 | 207 | case 1U: |
<> | 144:ef7eb2e8f9f7 | 208 | config->destSize = kDMA_Transfersize8bits; |
<> | 144:ef7eb2e8f9f7 | 209 | break; |
<> | 144:ef7eb2e8f9f7 | 210 | case 2U: |
<> | 144:ef7eb2e8f9f7 | 211 | config->destSize = kDMA_Transfersize16bits; |
<> | 144:ef7eb2e8f9f7 | 212 | break; |
<> | 144:ef7eb2e8f9f7 | 213 | case 4U: |
<> | 144:ef7eb2e8f9f7 | 214 | config->destSize = kDMA_Transfersize32bits; |
<> | 144:ef7eb2e8f9f7 | 215 | break; |
<> | 144:ef7eb2e8f9f7 | 216 | default: |
<> | 144:ef7eb2e8f9f7 | 217 | break; |
<> | 144:ef7eb2e8f9f7 | 218 | } |
<> | 144:ef7eb2e8f9f7 | 219 | switch (type) |
<> | 144:ef7eb2e8f9f7 | 220 | { |
<> | 144:ef7eb2e8f9f7 | 221 | case kDMA_MemoryToMemory: |
<> | 144:ef7eb2e8f9f7 | 222 | config->enableSrcIncrement = true; |
<> | 144:ef7eb2e8f9f7 | 223 | config->enableDestIncrement = true; |
<> | 144:ef7eb2e8f9f7 | 224 | break; |
<> | 144:ef7eb2e8f9f7 | 225 | case kDMA_PeripheralToMemory: |
<> | 144:ef7eb2e8f9f7 | 226 | config->enableSrcIncrement = false; |
<> | 144:ef7eb2e8f9f7 | 227 | config->enableDestIncrement = true; |
<> | 144:ef7eb2e8f9f7 | 228 | break; |
<> | 144:ef7eb2e8f9f7 | 229 | case kDMA_MemoryToPeripheral: |
<> | 144:ef7eb2e8f9f7 | 230 | config->enableSrcIncrement = true; |
<> | 144:ef7eb2e8f9f7 | 231 | config->enableDestIncrement = false; |
<> | 144:ef7eb2e8f9f7 | 232 | break; |
<> | 144:ef7eb2e8f9f7 | 233 | default: |
<> | 144:ef7eb2e8f9f7 | 234 | break; |
<> | 144:ef7eb2e8f9f7 | 235 | } |
<> | 144:ef7eb2e8f9f7 | 236 | } |
<> | 144:ef7eb2e8f9f7 | 237 | |
<> | 144:ef7eb2e8f9f7 | 238 | void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData) |
<> | 144:ef7eb2e8f9f7 | 239 | { |
<> | 144:ef7eb2e8f9f7 | 240 | assert(handle != NULL); |
<> | 144:ef7eb2e8f9f7 | 241 | |
<> | 144:ef7eb2e8f9f7 | 242 | handle->callback = callback; |
<> | 144:ef7eb2e8f9f7 | 243 | handle->userData = userData; |
<> | 144:ef7eb2e8f9f7 | 244 | } |
<> | 144:ef7eb2e8f9f7 | 245 | |
<> | 144:ef7eb2e8f9f7 | 246 | status_t DMA_SubmitTransfer(dma_handle_t *handle, const dma_transfer_config_t *config, uint32_t options) |
<> | 144:ef7eb2e8f9f7 | 247 | { |
<> | 144:ef7eb2e8f9f7 | 248 | assert(handle != NULL); |
<> | 144:ef7eb2e8f9f7 | 249 | assert(config != NULL); |
<> | 144:ef7eb2e8f9f7 | 250 | |
<> | 144:ef7eb2e8f9f7 | 251 | /* Check if DMA is busy */ |
<> | 144:ef7eb2e8f9f7 | 252 | if (handle->base->DMA[handle->channel].DSR_BCR & DMA_DSR_BCR_BSY_MASK) |
<> | 144:ef7eb2e8f9f7 | 253 | { |
<> | 144:ef7eb2e8f9f7 | 254 | return kStatus_DMA_Busy; |
<> | 144:ef7eb2e8f9f7 | 255 | } |
<> | 144:ef7eb2e8f9f7 | 256 | DMA_ResetChannel(handle->base, handle->channel); |
<> | 144:ef7eb2e8f9f7 | 257 | DMA_SetTransferConfig(handle->base, handle->channel, config); |
<> | 144:ef7eb2e8f9f7 | 258 | if (options & kDMA_EnableInterrupt) |
<> | 144:ef7eb2e8f9f7 | 259 | { |
<> | 144:ef7eb2e8f9f7 | 260 | DMA_EnableInterrupts(handle->base, handle->channel); |
<> | 144:ef7eb2e8f9f7 | 261 | } |
<> | 144:ef7eb2e8f9f7 | 262 | return kStatus_Success; |
<> | 144:ef7eb2e8f9f7 | 263 | } |
<> | 144:ef7eb2e8f9f7 | 264 | |
<> | 144:ef7eb2e8f9f7 | 265 | void DMA_AbortTransfer(dma_handle_t *handle) |
<> | 144:ef7eb2e8f9f7 | 266 | { |
<> | 144:ef7eb2e8f9f7 | 267 | assert(handle != NULL); |
<> | 144:ef7eb2e8f9f7 | 268 | |
<> | 144:ef7eb2e8f9f7 | 269 | handle->base->DMA[handle->channel].DCR &= ~DMA_DCR_ERQ_MASK; |
<> | 144:ef7eb2e8f9f7 | 270 | /* clear all status bit */ |
<> | 144:ef7eb2e8f9f7 | 271 | handle->base->DMA[handle->channel].DSR_BCR |= DMA_DSR_BCR_DONE(true); |
<> | 144:ef7eb2e8f9f7 | 272 | } |
<> | 144:ef7eb2e8f9f7 | 273 | |
<> | 144:ef7eb2e8f9f7 | 274 | void DMA_HandleIRQ(dma_handle_t *handle) |
<> | 144:ef7eb2e8f9f7 | 275 | { |
<> | 144:ef7eb2e8f9f7 | 276 | assert(handle != NULL); |
<> | 144:ef7eb2e8f9f7 | 277 | |
<> | 144:ef7eb2e8f9f7 | 278 | /* Clear interrupt pending bit */ |
<> | 144:ef7eb2e8f9f7 | 279 | DMA_ClearChannelStatusFlags(handle->base, handle->channel, kDMA_TransactionsDoneFlag); |
<> | 144:ef7eb2e8f9f7 | 280 | if (handle->callback) |
<> | 144:ef7eb2e8f9f7 | 281 | { |
<> | 144:ef7eb2e8f9f7 | 282 | (handle->callback)(handle, handle->userData); |
<> | 144:ef7eb2e8f9f7 | 283 | } |
<> | 144:ef7eb2e8f9f7 | 284 | } |
<> | 144:ef7eb2e8f9f7 | 285 | |
<> | 144:ef7eb2e8f9f7 | 286 | #if defined(FSL_FEATURE_DMAMUX_MODULE_CHANNEL) && (FSL_FEATURE_DMAMUX_MODULE_CHANNEL == 4U) |
<> | 144:ef7eb2e8f9f7 | 287 | void DMA0_DriverIRQHandler(void) |
<> | 144:ef7eb2e8f9f7 | 288 | { |
<> | 144:ef7eb2e8f9f7 | 289 | DMA_HandleIRQ(s_DMAHandle[0]); |
<> | 144:ef7eb2e8f9f7 | 290 | } |
<> | 144:ef7eb2e8f9f7 | 291 | |
<> | 144:ef7eb2e8f9f7 | 292 | void DMA1_DriverIRQHandler(void) |
<> | 144:ef7eb2e8f9f7 | 293 | { |
<> | 144:ef7eb2e8f9f7 | 294 | DMA_HandleIRQ(s_DMAHandle[1]); |
<> | 144:ef7eb2e8f9f7 | 295 | } |
<> | 144:ef7eb2e8f9f7 | 296 | |
<> | 144:ef7eb2e8f9f7 | 297 | void DMA2_DriverIRQHandler(void) |
<> | 144:ef7eb2e8f9f7 | 298 | { |
<> | 144:ef7eb2e8f9f7 | 299 | DMA_HandleIRQ(s_DMAHandle[2]); |
<> | 144:ef7eb2e8f9f7 | 300 | } |
<> | 144:ef7eb2e8f9f7 | 301 | |
<> | 144:ef7eb2e8f9f7 | 302 | void DMA3_DriverIRQHandler(void) |
<> | 144:ef7eb2e8f9f7 | 303 | { |
<> | 144:ef7eb2e8f9f7 | 304 | DMA_HandleIRQ(s_DMAHandle[3]); |
<> | 144:ef7eb2e8f9f7 | 305 | } |
<> | 144:ef7eb2e8f9f7 | 306 | #endif /* FSL_FEATURE_DMAMUX_MODULE_CHANNEL */ |