Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_sdramc.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 144:ef7eb2e8f9f7 3 * All rights reserved.
<> 144:ef7eb2e8f9f7 4 *
<> 144:ef7eb2e8f9f7 5 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 6 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 144:ef7eb2e8f9f7 9 * of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 144:ef7eb2e8f9f7 12 * list of conditions and the following disclaimer in the documentation and/or
<> 144:ef7eb2e8f9f7 13 * other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 144:ef7eb2e8f9f7 16 * contributors may be used to endorse or promote products derived from this
<> 144:ef7eb2e8f9f7 17 * software without specific prior written permission.
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 29 */
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 #include "fsl_sdramc.h"
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 /*******************************************************************************
<> 144:ef7eb2e8f9f7 34 * Definitions
<> 144:ef7eb2e8f9f7 35 ******************************************************************************/
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 /*! @brief Define macros for SDRAM driver. */
<> 144:ef7eb2e8f9f7 38 #define SDRAMC_ONEMILLSEC_NANOSECONDS (1000000U)
<> 144:ef7eb2e8f9f7 39 #define SDRAMC_ONESECOND_MILLISECONDS (1000U)
<> 144:ef7eb2e8f9f7 40 #define SDRAMC_TIMEOUT_COUNT (0xFFFFU)
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 /*******************************************************************************
<> 144:ef7eb2e8f9f7 43 * Prototypes
<> 144:ef7eb2e8f9f7 44 ******************************************************************************/
<> 144:ef7eb2e8f9f7 45 /*!
<> 144:ef7eb2e8f9f7 46 * @brief Get instance number for SDRAMC module.
<> 144:ef7eb2e8f9f7 47 *
<> 144:ef7eb2e8f9f7 48 * @param base SDRAMC peripheral base address
<> 144:ef7eb2e8f9f7 49 */
<> 144:ef7eb2e8f9f7 50 static uint32_t SDRAMC_GetInstance(SDRAM_Type *base);
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 /*******************************************************************************
<> 144:ef7eb2e8f9f7 53 * Variables
<> 144:ef7eb2e8f9f7 54 ******************************************************************************/
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 /*! @brief Pointers to SDRAMC clocks for each instance. */
<> 144:ef7eb2e8f9f7 57 const clock_ip_name_t s_sdramClock[FSL_FEATURE_SOC_SDRAM_COUNT] = SDRAM_CLOCKS;
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /*! @brief Pointers to SDRAMC bases for each instance. */
<> 144:ef7eb2e8f9f7 60 static SDRAM_Type *const s_sdramcBases[] = SDRAM_BASE_PTRS;
<> 144:ef7eb2e8f9f7 61 /*******************************************************************************
<> 144:ef7eb2e8f9f7 62 * Code
<> 144:ef7eb2e8f9f7 63 ******************************************************************************/
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 static uint32_t SDRAMC_GetInstance(SDRAM_Type *base)
<> 144:ef7eb2e8f9f7 66 {
<> 144:ef7eb2e8f9f7 67 uint32_t instance;
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 /* Find the instance index from base address mappings. */
<> 144:ef7eb2e8f9f7 70 for (instance = 0; instance < FSL_FEATURE_SOC_SDRAM_COUNT; instance++)
<> 144:ef7eb2e8f9f7 71 {
<> 144:ef7eb2e8f9f7 72 if (s_sdramcBases[instance] == base)
<> 144:ef7eb2e8f9f7 73 {
<> 144:ef7eb2e8f9f7 74 break;
<> 144:ef7eb2e8f9f7 75 }
<> 144:ef7eb2e8f9f7 76 }
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 assert(instance < FSL_FEATURE_SOC_SDRAM_COUNT);
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 return instance;
<> 144:ef7eb2e8f9f7 81 }
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 void SDRAMC_Init(SDRAM_Type *base, sdramc_config_t *configure)
<> 144:ef7eb2e8f9f7 84 {
<> 144:ef7eb2e8f9f7 85 assert(configure);
<> 144:ef7eb2e8f9f7 86 assert(configure->refreshConfig);
<> 144:ef7eb2e8f9f7 87 assert(configure->blockConfig);
<> 144:ef7eb2e8f9f7 88 assert(configure->refreshConfig->busClock_Hz);
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 sdramc_blockctl_config_t *bctlConfig = configure->blockConfig;
<> 144:ef7eb2e8f9f7 91 sdramc_refresh_config_t *refreshConfig = configure->refreshConfig;
<> 144:ef7eb2e8f9f7 92 uint32_t count;
<> 144:ef7eb2e8f9f7 93 uint32_t index;
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 /* Un-gate sdram controller clock. */
<> 144:ef7eb2e8f9f7 96 CLOCK_EnableClock(s_sdramClock[SDRAMC_GetInstance(base)]);
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 /* Initialize sdram Auto refresh timing. */
<> 144:ef7eb2e8f9f7 99 count = refreshConfig->sdramRefreshRow * (refreshConfig->busClock_Hz / SDRAMC_ONESECOND_MILLISECONDS);
<> 144:ef7eb2e8f9f7 100 count = (count / SDRAMC_ONEMILLSEC_NANOSECONDS) / 16 - 1;
<> 144:ef7eb2e8f9f7 101 base->CTRL = SDRAM_CTRL_RC(count) | SDRAM_CTRL_RTIM(refreshConfig->refreshTime);
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 for (index = 0; index < configure->numBlockConfig; index++)
<> 144:ef7eb2e8f9f7 104 {
<> 144:ef7eb2e8f9f7 105 /* Set the sdram block control. */
<> 144:ef7eb2e8f9f7 106 base->BLOCK[index].AC = SDRAM_AC_PS(bctlConfig->portSize) | SDRAM_AC_CASL(bctlConfig->latency) |
<> 144:ef7eb2e8f9f7 107 SDRAM_AC_CBM(bctlConfig->location) | (bctlConfig->address & SDRAM_AC_BA_MASK);
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 base->BLOCK[index].CM = (bctlConfig->addressMask & SDRAM_CM_BAM_MASK) | SDRAM_CM_V_MASK;
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 /* Increases to the next sdram block. */
<> 144:ef7eb2e8f9f7 112 bctlConfig++;
<> 144:ef7eb2e8f9f7 113 }
<> 144:ef7eb2e8f9f7 114 }
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 void SDRAMC_Deinit(SDRAM_Type *base)
<> 144:ef7eb2e8f9f7 117 {
<> 144:ef7eb2e8f9f7 118 /* Set the SDRAMC invalid, do not decode DRAM accesses. */
<> 144:ef7eb2e8f9f7 119 SDRAMC_EnableOperateValid(base, kSDRAMC_Block0, false);
<> 144:ef7eb2e8f9f7 120 SDRAMC_EnableOperateValid(base, kSDRAMC_Block1, false);
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 /* Disable SDRAM clock. */
<> 144:ef7eb2e8f9f7 123 CLOCK_DisableClock(s_sdramClock[SDRAMC_GetInstance(base)]);
<> 144:ef7eb2e8f9f7 124 }
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 status_t SDRAMC_SendCommand(SDRAM_Type *base, sdramc_block_selection_t block, sdramc_command_t command)
<> 144:ef7eb2e8f9f7 127 {
<> 144:ef7eb2e8f9f7 128 status_t result = kStatus_Success;
<> 144:ef7eb2e8f9f7 129 uint32_t count = SDRAMC_TIMEOUT_COUNT;
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 switch (command)
<> 144:ef7eb2e8f9f7 132 {
<> 144:ef7eb2e8f9f7 133 /* Initiate mrs command. */
<> 144:ef7eb2e8f9f7 134 case kSDRAMC_ImrsCommand:
<> 144:ef7eb2e8f9f7 135 base->BLOCK[block].AC |= SDRAM_AC_IMRS_MASK;
<> 144:ef7eb2e8f9f7 136 while (count--)
<> 144:ef7eb2e8f9f7 137 {
<> 144:ef7eb2e8f9f7 138 if (!(base->BLOCK[block].AC & SDRAM_AC_IMRS_MASK))
<> 144:ef7eb2e8f9f7 139 {
<> 144:ef7eb2e8f9f7 140 break;
<> 144:ef7eb2e8f9f7 141 }
<> 144:ef7eb2e8f9f7 142 }
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 if (!count)
<> 144:ef7eb2e8f9f7 145 {
<> 144:ef7eb2e8f9f7 146 /* Timeout the mrs command is unfinished. */
<> 144:ef7eb2e8f9f7 147 result = kStatus_Fail;
<> 144:ef7eb2e8f9f7 148 }
<> 144:ef7eb2e8f9f7 149 break;
<> 144:ef7eb2e8f9f7 150 /* Initiate precharge command. */
<> 144:ef7eb2e8f9f7 151 case kSDRAMC_PrechargeCommand:
<> 144:ef7eb2e8f9f7 152 base->BLOCK[block].AC |= SDRAM_AC_IP_MASK;
<> 144:ef7eb2e8f9f7 153 while (count--)
<> 144:ef7eb2e8f9f7 154 {
<> 144:ef7eb2e8f9f7 155 if (!(base->BLOCK[block].AC & SDRAM_AC_IP_MASK))
<> 144:ef7eb2e8f9f7 156 {
<> 144:ef7eb2e8f9f7 157 break;
<> 144:ef7eb2e8f9f7 158 }
<> 144:ef7eb2e8f9f7 159 }
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 /* Timeout the precharge command is unfinished. */
<> 144:ef7eb2e8f9f7 162 if (!count)
<> 144:ef7eb2e8f9f7 163 {
<> 144:ef7eb2e8f9f7 164 result = kStatus_Fail;
<> 144:ef7eb2e8f9f7 165 }
<> 144:ef7eb2e8f9f7 166 break;
<> 144:ef7eb2e8f9f7 167 /* Enable Auto refresh command. */
<> 144:ef7eb2e8f9f7 168 case kSDRAMC_AutoRefreshEnableCommand:
<> 144:ef7eb2e8f9f7 169 base->BLOCK[block].AC |= SDRAM_AC_RE_MASK;
<> 144:ef7eb2e8f9f7 170 break;
<> 144:ef7eb2e8f9f7 171 /* Disable Auto refresh command. */
<> 144:ef7eb2e8f9f7 172 case kSDRAMC_AutoRefreshDisableCommand:
<> 144:ef7eb2e8f9f7 173 base->BLOCK[block].AC &= ~SDRAM_AC_RE_MASK;
<> 144:ef7eb2e8f9f7 174 break;
<> 144:ef7eb2e8f9f7 175 /* Enter self-refresh command. */
<> 144:ef7eb2e8f9f7 176 case kSDRAMC_SelfrefreshEnterCommand:
<> 144:ef7eb2e8f9f7 177 base->CTRL |= SDRAM_CTRL_IS_MASK;
<> 144:ef7eb2e8f9f7 178 break;
<> 144:ef7eb2e8f9f7 179 /* Exit self-refresh command. */
<> 144:ef7eb2e8f9f7 180 case kSDRAMC_SelfrefreshExitCommand:
<> 144:ef7eb2e8f9f7 181 base->CTRL &= ~SDRAM_CTRL_IS_MASK;
<> 144:ef7eb2e8f9f7 182 break;
<> 144:ef7eb2e8f9f7 183 default:
<> 144:ef7eb2e8f9f7 184 break;
<> 144:ef7eb2e8f9f7 185 }
<> 144:ef7eb2e8f9f7 186 return result;
<> 144:ef7eb2e8f9f7 187 }