added prescaler for 16 bit pwm in LPC1347 target
Fork of mbed-dev by
targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_lptmr.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)
- Committer:
- <>
- Date:
- Fri Sep 02 15:07:44 2016 +0100
- Revision:
- 144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /* |
<> | 144:ef7eb2e8f9f7 | 2 | * Copyright (c) 2015, Freescale Semiconductor, Inc. |
<> | 144:ef7eb2e8f9f7 | 3 | * All rights reserved. |
<> | 144:ef7eb2e8f9f7 | 4 | * |
<> | 144:ef7eb2e8f9f7 | 5 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 144:ef7eb2e8f9f7 | 6 | * are permitted provided that the following conditions are met: |
<> | 144:ef7eb2e8f9f7 | 7 | * |
<> | 144:ef7eb2e8f9f7 | 8 | * o Redistributions of source code must retain the above copyright notice, this list |
<> | 144:ef7eb2e8f9f7 | 9 | * of conditions and the following disclaimer. |
<> | 144:ef7eb2e8f9f7 | 10 | * |
<> | 144:ef7eb2e8f9f7 | 11 | * o Redistributions in binary form must reproduce the above copyright notice, this |
<> | 144:ef7eb2e8f9f7 | 12 | * list of conditions and the following disclaimer in the documentation and/or |
<> | 144:ef7eb2e8f9f7 | 13 | * other materials provided with the distribution. |
<> | 144:ef7eb2e8f9f7 | 14 | * |
<> | 144:ef7eb2e8f9f7 | 15 | * o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
<> | 144:ef7eb2e8f9f7 | 16 | * contributors may be used to endorse or promote products derived from this |
<> | 144:ef7eb2e8f9f7 | 17 | * software without specific prior written permission. |
<> | 144:ef7eb2e8f9f7 | 18 | * |
<> | 144:ef7eb2e8f9f7 | 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
<> | 144:ef7eb2e8f9f7 | 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
<> | 144:ef7eb2e8f9f7 | 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 144:ef7eb2e8f9f7 | 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
<> | 144:ef7eb2e8f9f7 | 23 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
<> | 144:ef7eb2e8f9f7 | 24 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
<> | 144:ef7eb2e8f9f7 | 25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
<> | 144:ef7eb2e8f9f7 | 26 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
<> | 144:ef7eb2e8f9f7 | 27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
<> | 144:ef7eb2e8f9f7 | 28 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 144:ef7eb2e8f9f7 | 29 | */ |
<> | 144:ef7eb2e8f9f7 | 30 | #ifndef _FSL_LPTMR_H_ |
<> | 144:ef7eb2e8f9f7 | 31 | #define _FSL_LPTMR_H_ |
<> | 144:ef7eb2e8f9f7 | 32 | |
<> | 144:ef7eb2e8f9f7 | 33 | #include "fsl_common.h" |
<> | 144:ef7eb2e8f9f7 | 34 | |
<> | 144:ef7eb2e8f9f7 | 35 | /*! |
<> | 144:ef7eb2e8f9f7 | 36 | * @addtogroup lptmr_driver |
<> | 144:ef7eb2e8f9f7 | 37 | * @{ |
<> | 144:ef7eb2e8f9f7 | 38 | */ |
<> | 144:ef7eb2e8f9f7 | 39 | |
<> | 144:ef7eb2e8f9f7 | 40 | /*! @file */ |
<> | 144:ef7eb2e8f9f7 | 41 | |
<> | 144:ef7eb2e8f9f7 | 42 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 43 | * Definitions |
<> | 144:ef7eb2e8f9f7 | 44 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 45 | |
<> | 144:ef7eb2e8f9f7 | 46 | /*! @name Driver version */ |
<> | 144:ef7eb2e8f9f7 | 47 | /*@{*/ |
<> | 144:ef7eb2e8f9f7 | 48 | #define FSL_LPTMR_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ |
<> | 144:ef7eb2e8f9f7 | 49 | /*@}*/ |
<> | 144:ef7eb2e8f9f7 | 50 | |
<> | 144:ef7eb2e8f9f7 | 51 | /*! @brief LPTMR pin selection, used in pulse counter mode.*/ |
<> | 144:ef7eb2e8f9f7 | 52 | typedef enum _lptmr_pin_select |
<> | 144:ef7eb2e8f9f7 | 53 | { |
<> | 144:ef7eb2e8f9f7 | 54 | kLPTMR_PinSelectInput_0 = 0x0U, /*!< Pulse counter input 0 is selected */ |
<> | 144:ef7eb2e8f9f7 | 55 | kLPTMR_PinSelectInput_1 = 0x1U, /*!< Pulse counter input 1 is selected */ |
<> | 144:ef7eb2e8f9f7 | 56 | kLPTMR_PinSelectInput_2 = 0x2U, /*!< Pulse counter input 2 is selected */ |
<> | 144:ef7eb2e8f9f7 | 57 | kLPTMR_PinSelectInput_3 = 0x3U /*!< Pulse counter input 3 is selected */ |
<> | 144:ef7eb2e8f9f7 | 58 | } lptmr_pin_select_t; |
<> | 144:ef7eb2e8f9f7 | 59 | |
<> | 144:ef7eb2e8f9f7 | 60 | /*! @brief LPTMR pin polarity, used in pulse counter mode.*/ |
<> | 144:ef7eb2e8f9f7 | 61 | typedef enum _lptmr_pin_polarity |
<> | 144:ef7eb2e8f9f7 | 62 | { |
<> | 144:ef7eb2e8f9f7 | 63 | kLPTMR_PinPolarityActiveHigh = 0x0U, /*!< Pulse Counter input source is active-high */ |
<> | 144:ef7eb2e8f9f7 | 64 | kLPTMR_PinPolarityActiveLow = 0x1U /*!< Pulse Counter input source is active-low */ |
<> | 144:ef7eb2e8f9f7 | 65 | } lptmr_pin_polarity_t; |
<> | 144:ef7eb2e8f9f7 | 66 | |
<> | 144:ef7eb2e8f9f7 | 67 | /*! @brief LPTMR timer mode selection.*/ |
<> | 144:ef7eb2e8f9f7 | 68 | typedef enum _lptmr_timer_mode |
<> | 144:ef7eb2e8f9f7 | 69 | { |
<> | 144:ef7eb2e8f9f7 | 70 | kLPTMR_TimerModeTimeCounter = 0x0U, /*!< Time Counter mode */ |
<> | 144:ef7eb2e8f9f7 | 71 | kLPTMR_TimerModePulseCounter = 0x1U /*!< Pulse Counter mode */ |
<> | 144:ef7eb2e8f9f7 | 72 | } lptmr_timer_mode_t; |
<> | 144:ef7eb2e8f9f7 | 73 | |
<> | 144:ef7eb2e8f9f7 | 74 | /*! @brief LPTMR prescaler/glitch filter values*/ |
<> | 144:ef7eb2e8f9f7 | 75 | typedef enum _lptmr_prescaler_glitch_value |
<> | 144:ef7eb2e8f9f7 | 76 | { |
<> | 144:ef7eb2e8f9f7 | 77 | kLPTMR_Prescale_Glitch_0 = 0x0U, /*!< Prescaler divide 2, glitch filter does not support this setting */ |
<> | 144:ef7eb2e8f9f7 | 78 | kLPTMR_Prescale_Glitch_1 = 0x1U, /*!< Prescaler divide 4, glitch filter 2 */ |
<> | 144:ef7eb2e8f9f7 | 79 | kLPTMR_Prescale_Glitch_2 = 0x2U, /*!< Prescaler divide 8, glitch filter 4 */ |
<> | 144:ef7eb2e8f9f7 | 80 | kLPTMR_Prescale_Glitch_3 = 0x3U, /*!< Prescaler divide 16, glitch filter 8 */ |
<> | 144:ef7eb2e8f9f7 | 81 | kLPTMR_Prescale_Glitch_4 = 0x4U, /*!< Prescaler divide 32, glitch filter 16 */ |
<> | 144:ef7eb2e8f9f7 | 82 | kLPTMR_Prescale_Glitch_5 = 0x5U, /*!< Prescaler divide 64, glitch filter 32 */ |
<> | 144:ef7eb2e8f9f7 | 83 | kLPTMR_Prescale_Glitch_6 = 0x6U, /*!< Prescaler divide 128, glitch filter 64 */ |
<> | 144:ef7eb2e8f9f7 | 84 | kLPTMR_Prescale_Glitch_7 = 0x7U, /*!< Prescaler divide 256, glitch filter 128 */ |
<> | 144:ef7eb2e8f9f7 | 85 | kLPTMR_Prescale_Glitch_8 = 0x8U, /*!< Prescaler divide 512, glitch filter 256 */ |
<> | 144:ef7eb2e8f9f7 | 86 | kLPTMR_Prescale_Glitch_9 = 0x9U, /*!< Prescaler divide 1024, glitch filter 512*/ |
<> | 144:ef7eb2e8f9f7 | 87 | kLPTMR_Prescale_Glitch_10 = 0xAU, /*!< Prescaler divide 2048 glitch filter 1024 */ |
<> | 144:ef7eb2e8f9f7 | 88 | kLPTMR_Prescale_Glitch_11 = 0xBU, /*!< Prescaler divide 4096, glitch filter 2048 */ |
<> | 144:ef7eb2e8f9f7 | 89 | kLPTMR_Prescale_Glitch_12 = 0xCU, /*!< Prescaler divide 8192, glitch filter 4096 */ |
<> | 144:ef7eb2e8f9f7 | 90 | kLPTMR_Prescale_Glitch_13 = 0xDU, /*!< Prescaler divide 16384, glitch filter 8192 */ |
<> | 144:ef7eb2e8f9f7 | 91 | kLPTMR_Prescale_Glitch_14 = 0xEU, /*!< Prescaler divide 32768, glitch filter 16384 */ |
<> | 144:ef7eb2e8f9f7 | 92 | kLPTMR_Prescale_Glitch_15 = 0xFU /*!< Prescaler divide 65536, glitch filter 32768 */ |
<> | 144:ef7eb2e8f9f7 | 93 | } lptmr_prescaler_glitch_value_t; |
<> | 144:ef7eb2e8f9f7 | 94 | |
<> | 144:ef7eb2e8f9f7 | 95 | /*! |
<> | 144:ef7eb2e8f9f7 | 96 | * @brief LPTMR prescaler/glitch filter clock select. |
<> | 144:ef7eb2e8f9f7 | 97 | * @note Clock connections are SoC-specific |
<> | 144:ef7eb2e8f9f7 | 98 | */ |
<> | 144:ef7eb2e8f9f7 | 99 | typedef enum _lptmr_prescaler_clock_select |
<> | 144:ef7eb2e8f9f7 | 100 | { |
<> | 144:ef7eb2e8f9f7 | 101 | kLPTMR_PrescalerClock_0 = 0x0U, /*!< Prescaler/glitch filter clock 0 selected. */ |
<> | 144:ef7eb2e8f9f7 | 102 | kLPTMR_PrescalerClock_1 = 0x1U, /*!< Prescaler/glitch filter clock 1 selected. */ |
<> | 144:ef7eb2e8f9f7 | 103 | kLPTMR_PrescalerClock_2 = 0x2U, /*!< Prescaler/glitch filter clock 2 selected. */ |
<> | 144:ef7eb2e8f9f7 | 104 | kLPTMR_PrescalerClock_3 = 0x3U, /*!< Prescaler/glitch filter clock 3 selected. */ |
<> | 144:ef7eb2e8f9f7 | 105 | } lptmr_prescaler_clock_select_t; |
<> | 144:ef7eb2e8f9f7 | 106 | |
<> | 144:ef7eb2e8f9f7 | 107 | /*! @brief List of LPTMR interrupts */ |
<> | 144:ef7eb2e8f9f7 | 108 | typedef enum _lptmr_interrupt_enable |
<> | 144:ef7eb2e8f9f7 | 109 | { |
<> | 144:ef7eb2e8f9f7 | 110 | kLPTMR_TimerInterruptEnable = LPTMR_CSR_TIE_MASK, /*!< Timer interrupt enable */ |
<> | 144:ef7eb2e8f9f7 | 111 | } lptmr_interrupt_enable_t; |
<> | 144:ef7eb2e8f9f7 | 112 | |
<> | 144:ef7eb2e8f9f7 | 113 | /*! @brief List of LPTMR status flags */ |
<> | 144:ef7eb2e8f9f7 | 114 | typedef enum _lptmr_status_flags |
<> | 144:ef7eb2e8f9f7 | 115 | { |
<> | 144:ef7eb2e8f9f7 | 116 | kLPTMR_TimerCompareFlag = LPTMR_CSR_TCF_MASK, /*!< Timer compare flag */ |
<> | 144:ef7eb2e8f9f7 | 117 | } lptmr_status_flags_t; |
<> | 144:ef7eb2e8f9f7 | 118 | |
<> | 144:ef7eb2e8f9f7 | 119 | /*! |
<> | 144:ef7eb2e8f9f7 | 120 | * @brief LPTMR config structure |
<> | 144:ef7eb2e8f9f7 | 121 | * |
<> | 144:ef7eb2e8f9f7 | 122 | * This structure holds the configuration settings for the LPTMR peripheral. To initialize this |
<> | 144:ef7eb2e8f9f7 | 123 | * structure to reasonable defaults, call the LPTMR_GetDefaultConfig() function and pass a |
<> | 144:ef7eb2e8f9f7 | 124 | * pointer to your config structure instance. |
<> | 144:ef7eb2e8f9f7 | 125 | * |
<> | 144:ef7eb2e8f9f7 | 126 | * The config struct can be made const so it resides in flash |
<> | 144:ef7eb2e8f9f7 | 127 | */ |
<> | 144:ef7eb2e8f9f7 | 128 | typedef struct _lptmr_config |
<> | 144:ef7eb2e8f9f7 | 129 | { |
<> | 144:ef7eb2e8f9f7 | 130 | lptmr_timer_mode_t timerMode; /*!< Time counter mode or pulse counter mode */ |
<> | 144:ef7eb2e8f9f7 | 131 | lptmr_pin_select_t pinSelect; /*!< LPTMR pulse input pin select; used only in pulse counter mode */ |
<> | 144:ef7eb2e8f9f7 | 132 | lptmr_pin_polarity_t pinPolarity; /*!< LPTMR pulse input pin polarity; used only in pulse counter mode */ |
<> | 144:ef7eb2e8f9f7 | 133 | bool enableFreeRunning; /*!< true: enable free running, counter is reset on overflow |
<> | 144:ef7eb2e8f9f7 | 134 | false: counter is reset when the compare flag is set */ |
<> | 144:ef7eb2e8f9f7 | 135 | bool bypassPrescaler; /*!< true: bypass prescaler; false: use clock from prescaler */ |
<> | 144:ef7eb2e8f9f7 | 136 | lptmr_prescaler_clock_select_t prescalerClockSource; /*!< LPTMR clock source */ |
<> | 144:ef7eb2e8f9f7 | 137 | lptmr_prescaler_glitch_value_t value; /*!< Prescaler or glitch filter value */ |
<> | 144:ef7eb2e8f9f7 | 138 | } lptmr_config_t; |
<> | 144:ef7eb2e8f9f7 | 139 | |
<> | 144:ef7eb2e8f9f7 | 140 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 141 | * API |
<> | 144:ef7eb2e8f9f7 | 142 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 143 | |
<> | 144:ef7eb2e8f9f7 | 144 | #if defined(__cplusplus) |
<> | 144:ef7eb2e8f9f7 | 145 | extern "C" { |
<> | 144:ef7eb2e8f9f7 | 146 | #endif |
<> | 144:ef7eb2e8f9f7 | 147 | |
<> | 144:ef7eb2e8f9f7 | 148 | /*! |
<> | 144:ef7eb2e8f9f7 | 149 | * @name Initialization and deinitialization |
<> | 144:ef7eb2e8f9f7 | 150 | * @{ |
<> | 144:ef7eb2e8f9f7 | 151 | */ |
<> | 144:ef7eb2e8f9f7 | 152 | |
<> | 144:ef7eb2e8f9f7 | 153 | /*! |
<> | 144:ef7eb2e8f9f7 | 154 | * @brief Ungate the LPTMR clock and configures the peripheral for basic operation. |
<> | 144:ef7eb2e8f9f7 | 155 | * |
<> | 144:ef7eb2e8f9f7 | 156 | * @note This API should be called at the beginning of the application using the LPTMR driver. |
<> | 144:ef7eb2e8f9f7 | 157 | * |
<> | 144:ef7eb2e8f9f7 | 158 | * @param base LPTMR peripheral base address |
<> | 144:ef7eb2e8f9f7 | 159 | * @param config Pointer to user's LPTMR config structure. |
<> | 144:ef7eb2e8f9f7 | 160 | */ |
<> | 144:ef7eb2e8f9f7 | 161 | void LPTMR_Init(LPTMR_Type *base, const lptmr_config_t *config); |
<> | 144:ef7eb2e8f9f7 | 162 | |
<> | 144:ef7eb2e8f9f7 | 163 | /*! |
<> | 144:ef7eb2e8f9f7 | 164 | * @brief Gate the LPTMR clock |
<> | 144:ef7eb2e8f9f7 | 165 | * |
<> | 144:ef7eb2e8f9f7 | 166 | * @param base LPTMR peripheral base address |
<> | 144:ef7eb2e8f9f7 | 167 | */ |
<> | 144:ef7eb2e8f9f7 | 168 | void LPTMR_Deinit(LPTMR_Type *base); |
<> | 144:ef7eb2e8f9f7 | 169 | |
<> | 144:ef7eb2e8f9f7 | 170 | /*! |
<> | 144:ef7eb2e8f9f7 | 171 | * @brief Fill in the LPTMR config struct with the default settings |
<> | 144:ef7eb2e8f9f7 | 172 | * |
<> | 144:ef7eb2e8f9f7 | 173 | * The default values are: |
<> | 144:ef7eb2e8f9f7 | 174 | * @code |
<> | 144:ef7eb2e8f9f7 | 175 | * config->timerMode = kLPTMR_TimerModeTimeCounter; |
<> | 144:ef7eb2e8f9f7 | 176 | * config->pinSelect = kLPTMR_PinSelectInput_0; |
<> | 144:ef7eb2e8f9f7 | 177 | * config->pinPolarity = kLPTMR_PinPolarityActiveHigh; |
<> | 144:ef7eb2e8f9f7 | 178 | * config->enableFreeRunning = false; |
<> | 144:ef7eb2e8f9f7 | 179 | * config->bypassPrescaler = true; |
<> | 144:ef7eb2e8f9f7 | 180 | * config->prescalerClockSource = kLPTMR_PrescalerClock_1; |
<> | 144:ef7eb2e8f9f7 | 181 | * config->value = kLPTMR_Prescale_Glitch_0; |
<> | 144:ef7eb2e8f9f7 | 182 | * @endcode |
<> | 144:ef7eb2e8f9f7 | 183 | * @param config Pointer to user's LPTMR config structure. |
<> | 144:ef7eb2e8f9f7 | 184 | */ |
<> | 144:ef7eb2e8f9f7 | 185 | void LPTMR_GetDefaultConfig(lptmr_config_t *config); |
<> | 144:ef7eb2e8f9f7 | 186 | |
<> | 144:ef7eb2e8f9f7 | 187 | /*! @}*/ |
<> | 144:ef7eb2e8f9f7 | 188 | |
<> | 144:ef7eb2e8f9f7 | 189 | /*! |
<> | 144:ef7eb2e8f9f7 | 190 | * @name Interrupt Interface |
<> | 144:ef7eb2e8f9f7 | 191 | * @{ |
<> | 144:ef7eb2e8f9f7 | 192 | */ |
<> | 144:ef7eb2e8f9f7 | 193 | |
<> | 144:ef7eb2e8f9f7 | 194 | /*! |
<> | 144:ef7eb2e8f9f7 | 195 | * @brief Enables the selected LPTMR interrupts. |
<> | 144:ef7eb2e8f9f7 | 196 | * |
<> | 144:ef7eb2e8f9f7 | 197 | * @param base LPTMR peripheral base address |
<> | 144:ef7eb2e8f9f7 | 198 | * @param mask The interrupts to enable. This is a logical OR of members of the |
<> | 144:ef7eb2e8f9f7 | 199 | * enumeration ::lptmr_interrupt_enable_t |
<> | 144:ef7eb2e8f9f7 | 200 | */ |
<> | 144:ef7eb2e8f9f7 | 201 | static inline void LPTMR_EnableInterrupts(LPTMR_Type *base, uint32_t mask) |
<> | 144:ef7eb2e8f9f7 | 202 | { |
<> | 144:ef7eb2e8f9f7 | 203 | base->CSR |= mask; |
<> | 144:ef7eb2e8f9f7 | 204 | } |
<> | 144:ef7eb2e8f9f7 | 205 | |
<> | 144:ef7eb2e8f9f7 | 206 | /*! |
<> | 144:ef7eb2e8f9f7 | 207 | * @brief Disables the selected LPTMR interrupts. |
<> | 144:ef7eb2e8f9f7 | 208 | * |
<> | 144:ef7eb2e8f9f7 | 209 | * @param base LPTMR peripheral base address |
<> | 144:ef7eb2e8f9f7 | 210 | * @param mask The interrupts to disable. This is a logical OR of members of the |
<> | 144:ef7eb2e8f9f7 | 211 | * enumeration ::lptmr_interrupt_enable_t |
<> | 144:ef7eb2e8f9f7 | 212 | */ |
<> | 144:ef7eb2e8f9f7 | 213 | static inline void LPTMR_DisableInterrupts(LPTMR_Type *base, uint32_t mask) |
<> | 144:ef7eb2e8f9f7 | 214 | { |
<> | 144:ef7eb2e8f9f7 | 215 | base->CSR &= ~mask; |
<> | 144:ef7eb2e8f9f7 | 216 | } |
<> | 144:ef7eb2e8f9f7 | 217 | |
<> | 144:ef7eb2e8f9f7 | 218 | /*! |
<> | 144:ef7eb2e8f9f7 | 219 | * @brief Gets the enabled LPTMR interrupts. |
<> | 144:ef7eb2e8f9f7 | 220 | * |
<> | 144:ef7eb2e8f9f7 | 221 | * @param base LPTMR peripheral base address |
<> | 144:ef7eb2e8f9f7 | 222 | * |
<> | 144:ef7eb2e8f9f7 | 223 | * @return The enabled interrupts. This is the logical OR of members of the |
<> | 144:ef7eb2e8f9f7 | 224 | * enumeration ::lptmr_interrupt_enable_t |
<> | 144:ef7eb2e8f9f7 | 225 | */ |
<> | 144:ef7eb2e8f9f7 | 226 | static inline uint32_t LPTMR_GetEnabledInterrupts(LPTMR_Type *base) |
<> | 144:ef7eb2e8f9f7 | 227 | { |
<> | 144:ef7eb2e8f9f7 | 228 | return (base->CSR & LPTMR_CSR_TIE_MASK); |
<> | 144:ef7eb2e8f9f7 | 229 | } |
<> | 144:ef7eb2e8f9f7 | 230 | |
<> | 144:ef7eb2e8f9f7 | 231 | /*! @}*/ |
<> | 144:ef7eb2e8f9f7 | 232 | |
<> | 144:ef7eb2e8f9f7 | 233 | /*! |
<> | 144:ef7eb2e8f9f7 | 234 | * @name Status Interface |
<> | 144:ef7eb2e8f9f7 | 235 | * @{ |
<> | 144:ef7eb2e8f9f7 | 236 | */ |
<> | 144:ef7eb2e8f9f7 | 237 | |
<> | 144:ef7eb2e8f9f7 | 238 | /*! |
<> | 144:ef7eb2e8f9f7 | 239 | * @brief Gets the LPTMR status flags |
<> | 144:ef7eb2e8f9f7 | 240 | * |
<> | 144:ef7eb2e8f9f7 | 241 | * @param base LPTMR peripheral base address |
<> | 144:ef7eb2e8f9f7 | 242 | * |
<> | 144:ef7eb2e8f9f7 | 243 | * @return The status flags. This is the logical OR of members of the |
<> | 144:ef7eb2e8f9f7 | 244 | * enumeration ::lptmr_status_flags_t |
<> | 144:ef7eb2e8f9f7 | 245 | */ |
<> | 144:ef7eb2e8f9f7 | 246 | static inline uint32_t LPTMR_GetStatusFlags(LPTMR_Type *base) |
<> | 144:ef7eb2e8f9f7 | 247 | { |
<> | 144:ef7eb2e8f9f7 | 248 | return (base->CSR & LPTMR_CSR_TCF_MASK); |
<> | 144:ef7eb2e8f9f7 | 249 | } |
<> | 144:ef7eb2e8f9f7 | 250 | |
<> | 144:ef7eb2e8f9f7 | 251 | /*! |
<> | 144:ef7eb2e8f9f7 | 252 | * @brief Clears the LPTMR status flags |
<> | 144:ef7eb2e8f9f7 | 253 | * |
<> | 144:ef7eb2e8f9f7 | 254 | * @param base LPTMR peripheral base address |
<> | 144:ef7eb2e8f9f7 | 255 | * @param mask The status flags to clear. This is a logical OR of members of the |
<> | 144:ef7eb2e8f9f7 | 256 | * enumeration ::lptmr_status_flags_t |
<> | 144:ef7eb2e8f9f7 | 257 | */ |
<> | 144:ef7eb2e8f9f7 | 258 | static inline void LPTMR_ClearStatusFlags(LPTMR_Type *base, uint32_t mask) |
<> | 144:ef7eb2e8f9f7 | 259 | { |
<> | 144:ef7eb2e8f9f7 | 260 | base->CSR |= mask; |
<> | 144:ef7eb2e8f9f7 | 261 | } |
<> | 144:ef7eb2e8f9f7 | 262 | |
<> | 144:ef7eb2e8f9f7 | 263 | /*! @}*/ |
<> | 144:ef7eb2e8f9f7 | 264 | |
<> | 144:ef7eb2e8f9f7 | 265 | /*! |
<> | 144:ef7eb2e8f9f7 | 266 | * @name Read and Write the timer period |
<> | 144:ef7eb2e8f9f7 | 267 | * @{ |
<> | 144:ef7eb2e8f9f7 | 268 | */ |
<> | 144:ef7eb2e8f9f7 | 269 | |
<> | 144:ef7eb2e8f9f7 | 270 | /*! |
<> | 144:ef7eb2e8f9f7 | 271 | * @brief Sets the timer period in units of count. |
<> | 144:ef7eb2e8f9f7 | 272 | * |
<> | 144:ef7eb2e8f9f7 | 273 | * Timers counts from 0 till it equals the count value set here. The count value is written to |
<> | 144:ef7eb2e8f9f7 | 274 | * the CMR register. |
<> | 144:ef7eb2e8f9f7 | 275 | * |
<> | 144:ef7eb2e8f9f7 | 276 | * @note |
<> | 144:ef7eb2e8f9f7 | 277 | * 1. The TCF flag is set with the CNR equals the count provided here and then increments. |
<> | 144:ef7eb2e8f9f7 | 278 | * 2. User can call the utility macros provided in fsl_common.h to convert to ticks |
<> | 144:ef7eb2e8f9f7 | 279 | * |
<> | 144:ef7eb2e8f9f7 | 280 | * @param base LPTMR peripheral base address |
<> | 144:ef7eb2e8f9f7 | 281 | * @param ticks Timer period in units of ticks |
<> | 144:ef7eb2e8f9f7 | 282 | */ |
<> | 144:ef7eb2e8f9f7 | 283 | static inline void LPTMR_SetTimerPeriod(LPTMR_Type *base, uint16_t ticks) |
<> | 144:ef7eb2e8f9f7 | 284 | { |
<> | 144:ef7eb2e8f9f7 | 285 | base->CMR = ticks; |
<> | 144:ef7eb2e8f9f7 | 286 | } |
<> | 144:ef7eb2e8f9f7 | 287 | |
<> | 144:ef7eb2e8f9f7 | 288 | /*! |
<> | 144:ef7eb2e8f9f7 | 289 | * @brief Reads the current timer counting value. |
<> | 144:ef7eb2e8f9f7 | 290 | * |
<> | 144:ef7eb2e8f9f7 | 291 | * This function returns the real-time timer counting value, in a range from 0 to a |
<> | 144:ef7eb2e8f9f7 | 292 | * timer period. |
<> | 144:ef7eb2e8f9f7 | 293 | * |
<> | 144:ef7eb2e8f9f7 | 294 | * @note User can call the utility macros provided in fsl_common.h to convert ticks to usec or msec |
<> | 144:ef7eb2e8f9f7 | 295 | * |
<> | 144:ef7eb2e8f9f7 | 296 | * @param base LPTMR peripheral base address |
<> | 144:ef7eb2e8f9f7 | 297 | * |
<> | 144:ef7eb2e8f9f7 | 298 | * @return Current counter value in ticks |
<> | 144:ef7eb2e8f9f7 | 299 | */ |
<> | 144:ef7eb2e8f9f7 | 300 | static inline uint16_t LPTMR_GetCurrentTimerCount(LPTMR_Type *base) |
<> | 144:ef7eb2e8f9f7 | 301 | { |
<> | 144:ef7eb2e8f9f7 | 302 | /* Must first write any value to the CNR. This will synchronize and register the current value |
<> | 144:ef7eb2e8f9f7 | 303 | * of the CNR into a temporary register which can then be read |
<> | 144:ef7eb2e8f9f7 | 304 | */ |
<> | 144:ef7eb2e8f9f7 | 305 | base->CNR = 0U; |
<> | 144:ef7eb2e8f9f7 | 306 | return (uint16_t)base->CNR; |
<> | 144:ef7eb2e8f9f7 | 307 | } |
<> | 144:ef7eb2e8f9f7 | 308 | |
<> | 144:ef7eb2e8f9f7 | 309 | /*! @}*/ |
<> | 144:ef7eb2e8f9f7 | 310 | |
<> | 144:ef7eb2e8f9f7 | 311 | /*! |
<> | 144:ef7eb2e8f9f7 | 312 | * @name Timer Start and Stop |
<> | 144:ef7eb2e8f9f7 | 313 | * @{ |
<> | 144:ef7eb2e8f9f7 | 314 | */ |
<> | 144:ef7eb2e8f9f7 | 315 | |
<> | 144:ef7eb2e8f9f7 | 316 | /*! |
<> | 144:ef7eb2e8f9f7 | 317 | * @brief Starts the timer counting. |
<> | 144:ef7eb2e8f9f7 | 318 | * |
<> | 144:ef7eb2e8f9f7 | 319 | * After calling this function, the timer counts up to the CMR register value. |
<> | 144:ef7eb2e8f9f7 | 320 | * Each time the timer reaches CMR value and then increments, it generates a |
<> | 144:ef7eb2e8f9f7 | 321 | * trigger pulse and sets the timeout interrupt flag. An interrupt will also be |
<> | 144:ef7eb2e8f9f7 | 322 | * triggered if the timer interrupt is enabled. |
<> | 144:ef7eb2e8f9f7 | 323 | * |
<> | 144:ef7eb2e8f9f7 | 324 | * @param base LPTMR peripheral base address |
<> | 144:ef7eb2e8f9f7 | 325 | */ |
<> | 144:ef7eb2e8f9f7 | 326 | static inline void LPTMR_StartTimer(LPTMR_Type *base) |
<> | 144:ef7eb2e8f9f7 | 327 | { |
<> | 144:ef7eb2e8f9f7 | 328 | base->CSR |= LPTMR_CSR_TEN_MASK; |
<> | 144:ef7eb2e8f9f7 | 329 | } |
<> | 144:ef7eb2e8f9f7 | 330 | |
<> | 144:ef7eb2e8f9f7 | 331 | /*! |
<> | 144:ef7eb2e8f9f7 | 332 | * @brief Stops the timer counting. |
<> | 144:ef7eb2e8f9f7 | 333 | * |
<> | 144:ef7eb2e8f9f7 | 334 | * This function stops the timer counting and resets the timer's counter register |
<> | 144:ef7eb2e8f9f7 | 335 | * |
<> | 144:ef7eb2e8f9f7 | 336 | * @param base LPTMR peripheral base address |
<> | 144:ef7eb2e8f9f7 | 337 | */ |
<> | 144:ef7eb2e8f9f7 | 338 | static inline void LPTMR_StopTimer(LPTMR_Type *base) |
<> | 144:ef7eb2e8f9f7 | 339 | { |
<> | 144:ef7eb2e8f9f7 | 340 | base->CSR &= ~LPTMR_CSR_TEN_MASK; |
<> | 144:ef7eb2e8f9f7 | 341 | } |
<> | 144:ef7eb2e8f9f7 | 342 | |
<> | 144:ef7eb2e8f9f7 | 343 | /*! @}*/ |
<> | 144:ef7eb2e8f9f7 | 344 | |
<> | 144:ef7eb2e8f9f7 | 345 | #if defined(__cplusplus) |
<> | 144:ef7eb2e8f9f7 | 346 | } |
<> | 144:ef7eb2e8f9f7 | 347 | #endif |
<> | 144:ef7eb2e8f9f7 | 348 | |
<> | 144:ef7eb2e8f9f7 | 349 | /*! @}*/ |
<> | 144:ef7eb2e8f9f7 | 350 | |
<> | 144:ef7eb2e8f9f7 | 351 | #endif /* _FSL_LPTMR_H_ */ |