Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_cmt.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 144:ef7eb2e8f9f7 3 * All rights reserved.
<> 144:ef7eb2e8f9f7 4 *
<> 144:ef7eb2e8f9f7 5 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 6 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 144:ef7eb2e8f9f7 9 * of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 144:ef7eb2e8f9f7 12 * list of conditions and the following disclaimer in the documentation and/or
<> 144:ef7eb2e8f9f7 13 * other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 144:ef7eb2e8f9f7 16 * contributors may be used to endorse or promote products derived from this
<> 144:ef7eb2e8f9f7 17 * software without specific prior written permission.
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 29 */
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 #include "fsl_cmt.h"
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 /*******************************************************************************
<> 144:ef7eb2e8f9f7 34 * Definitions
<> 144:ef7eb2e8f9f7 35 ******************************************************************************/
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 /* The standard intermediate frequency (IF). */
<> 144:ef7eb2e8f9f7 38 #define CMT_INTERMEDIATEFREQUENCY_8MHZ (8000000U)
<> 144:ef7eb2e8f9f7 39 /* CMT data modulate mask. */
<> 144:ef7eb2e8f9f7 40 #define CMT_MODULATE_COUNT_WIDTH (8U)
<> 144:ef7eb2e8f9f7 41 /* CMT diver 1. */
<> 144:ef7eb2e8f9f7 42 #define CMT_CMTDIV_ONE (1)
<> 144:ef7eb2e8f9f7 43 /* CMT diver 2. */
<> 144:ef7eb2e8f9f7 44 #define CMT_CMTDIV_TWO (2)
<> 144:ef7eb2e8f9f7 45 /* CMT diver 4. */
<> 144:ef7eb2e8f9f7 46 #define CMT_CMTDIV_FOUR (4)
<> 144:ef7eb2e8f9f7 47 /* CMT diver 8. */
<> 144:ef7eb2e8f9f7 48 #define CMT_CMTDIV_EIGHT (8)
<> 144:ef7eb2e8f9f7 49 /* CMT mode bit mask. */
<> 144:ef7eb2e8f9f7 50 #define CMT_MODE_BIT_MASK (CMT_MSC_MCGEN_MASK | CMT_MSC_FSK_MASK | CMT_MSC_BASE_MASK)
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 /*******************************************************************************
<> 144:ef7eb2e8f9f7 53 * Prototypes
<> 144:ef7eb2e8f9f7 54 ******************************************************************************/
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 /*!
<> 144:ef7eb2e8f9f7 57 * @brief Get instance number for CMT module.
<> 144:ef7eb2e8f9f7 58 *
<> 144:ef7eb2e8f9f7 59 * @param base CMT peripheral base address.
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61 static uint32_t CMT_GetInstance(CMT_Type *base);
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /*******************************************************************************
<> 144:ef7eb2e8f9f7 64 * Variables
<> 144:ef7eb2e8f9f7 65 ******************************************************************************/
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 /*! @brief Pointers to cmt clocks for each instance. */
<> 144:ef7eb2e8f9f7 68 const clock_ip_name_t s_cmtClock[FSL_FEATURE_SOC_CMT_COUNT] = CMT_CLOCKS;
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 /*! @brief Pointers to cmt bases for each instance. */
<> 144:ef7eb2e8f9f7 71 static CMT_Type *const s_cmtBases[] = CMT_BASE_PTRS;
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 /*! @brief Pointers to cmt IRQ number for each instance. */
<> 144:ef7eb2e8f9f7 74 const IRQn_Type s_cmtIrqs[] = CMT_IRQS;
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 /*******************************************************************************
<> 144:ef7eb2e8f9f7 77 * Codes
<> 144:ef7eb2e8f9f7 78 ******************************************************************************/
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 static uint32_t CMT_GetInstance(CMT_Type *base)
<> 144:ef7eb2e8f9f7 81 {
<> 144:ef7eb2e8f9f7 82 uint32_t instance;
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 /* Find the instance index from base address mappings. */
<> 144:ef7eb2e8f9f7 85 for (instance = 0; instance < FSL_FEATURE_SOC_CMT_COUNT; instance++)
<> 144:ef7eb2e8f9f7 86 {
<> 144:ef7eb2e8f9f7 87 if (s_cmtBases[instance] == base)
<> 144:ef7eb2e8f9f7 88 {
<> 144:ef7eb2e8f9f7 89 break;
<> 144:ef7eb2e8f9f7 90 }
<> 144:ef7eb2e8f9f7 91 }
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 assert(instance < FSL_FEATURE_SOC_CMT_COUNT);
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 return instance;
<> 144:ef7eb2e8f9f7 96 }
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 void CMT_GetDefaultConfig(cmt_config_t *config)
<> 144:ef7eb2e8f9f7 99 {
<> 144:ef7eb2e8f9f7 100 assert(config);
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 /* Default infrared output is enabled and set with high active, the divider is set to 1. */
<> 144:ef7eb2e8f9f7 103 config->isInterruptEnabled = false;
<> 144:ef7eb2e8f9f7 104 config->isIroEnabled = true;
<> 144:ef7eb2e8f9f7 105 config->iroPolarity = kCMT_IROActiveHigh;
<> 144:ef7eb2e8f9f7 106 config->divider = kCMT_SecondClkDiv1;
<> 144:ef7eb2e8f9f7 107 }
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 void CMT_Init(CMT_Type *base, const cmt_config_t *config, uint32_t busClock_Hz)
<> 144:ef7eb2e8f9f7 110 {
<> 144:ef7eb2e8f9f7 111 assert(config);
<> 144:ef7eb2e8f9f7 112 assert(busClock_Hz >= CMT_INTERMEDIATEFREQUENCY_8MHZ);
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 uint8_t divider;
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 /* Ungate clock. */
<> 144:ef7eb2e8f9f7 117 CLOCK_EnableClock(s_cmtClock[CMT_GetInstance(base)]);
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 /* Sets clock divider. The divider set in pps should be set
<> 144:ef7eb2e8f9f7 120 to make sycClock_Hz/divder = 8MHz */
<> 144:ef7eb2e8f9f7 121 base->PPS = CMT_PPS_PPSDIV(busClock_Hz / CMT_INTERMEDIATEFREQUENCY_8MHZ - 1);
<> 144:ef7eb2e8f9f7 122 divider = base->MSC;
<> 144:ef7eb2e8f9f7 123 divider &= ~CMT_MSC_CMTDIV_MASK;
<> 144:ef7eb2e8f9f7 124 divider |= CMT_MSC_CMTDIV(config->divider);
<> 144:ef7eb2e8f9f7 125 base->MSC = divider;
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 /* Set the IRO signal. */
<> 144:ef7eb2e8f9f7 128 base->OC = CMT_OC_CMTPOL(config->iroPolarity) | CMT_OC_IROPEN(config->isIroEnabled);
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 /* Set interrupt. */
<> 144:ef7eb2e8f9f7 131 if (config->isInterruptEnabled)
<> 144:ef7eb2e8f9f7 132 {
<> 144:ef7eb2e8f9f7 133 CMT_EnableInterrupts(base, kCMT_EndOfCycleInterruptEnable);
<> 144:ef7eb2e8f9f7 134 EnableIRQ(s_cmtIrqs[CMT_GetInstance(base)]);
<> 144:ef7eb2e8f9f7 135 }
<> 144:ef7eb2e8f9f7 136 }
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 void CMT_Deinit(CMT_Type *base)
<> 144:ef7eb2e8f9f7 139 {
<> 144:ef7eb2e8f9f7 140 /*Disable the CMT modulator. */
<> 144:ef7eb2e8f9f7 141 base->MSC = 0;
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 /* Disable the interrupt. */
<> 144:ef7eb2e8f9f7 144 CMT_DisableInterrupts(base, kCMT_EndOfCycleInterruptEnable);
<> 144:ef7eb2e8f9f7 145 DisableIRQ(s_cmtIrqs[CMT_GetInstance(base)]);
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 /* Gate the clock. */
<> 144:ef7eb2e8f9f7 148 CLOCK_DisableClock(s_cmtClock[CMT_GetInstance(base)]);
<> 144:ef7eb2e8f9f7 149 }
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 void CMT_SetMode(CMT_Type *base, cmt_mode_t mode, cmt_modulate_config_t *modulateConfig)
<> 144:ef7eb2e8f9f7 152 {
<> 144:ef7eb2e8f9f7 153 uint8_t mscReg;
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 /* Set the mode. */
<> 144:ef7eb2e8f9f7 156 if (mode != kCMT_DirectIROCtl)
<> 144:ef7eb2e8f9f7 157 {
<> 144:ef7eb2e8f9f7 158 assert(modulateConfig);
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 /* Set carrier generator. */
<> 144:ef7eb2e8f9f7 161 CMT_SetCarrirGenerateCountOne(base, modulateConfig->highCount1, modulateConfig->lowCount1);
<> 144:ef7eb2e8f9f7 162 if (mode == kCMT_FSKMode)
<> 144:ef7eb2e8f9f7 163 {
<> 144:ef7eb2e8f9f7 164 CMT_SetCarrirGenerateCountTwo(base, modulateConfig->highCount2, modulateConfig->lowCount2);
<> 144:ef7eb2e8f9f7 165 }
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 /* Set carrier modulator. */
<> 144:ef7eb2e8f9f7 168 CMT_SetModulateMarkSpace(base, modulateConfig->markCount, modulateConfig->spaceCount);
<> 144:ef7eb2e8f9f7 169 }
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 /* Set the CMT mode. */
<> 144:ef7eb2e8f9f7 172 mscReg = base->MSC;
<> 144:ef7eb2e8f9f7 173 mscReg &= ~CMT_MODE_BIT_MASK;
<> 144:ef7eb2e8f9f7 174 mscReg |= mode;
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 base->MSC = mscReg;
<> 144:ef7eb2e8f9f7 177 }
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 cmt_mode_t CMT_GetMode(CMT_Type *base)
<> 144:ef7eb2e8f9f7 180 {
<> 144:ef7eb2e8f9f7 181 uint8_t mode = base->MSC;
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 if (!(mode & CMT_MSC_MCGEN_MASK))
<> 144:ef7eb2e8f9f7 184 { /* Carrier modulator disabled and the IRO signal is in direct software control. */
<> 144:ef7eb2e8f9f7 185 return kCMT_DirectIROCtl;
<> 144:ef7eb2e8f9f7 186 }
<> 144:ef7eb2e8f9f7 187 else
<> 144:ef7eb2e8f9f7 188 {
<> 144:ef7eb2e8f9f7 189 /* Carrier modulator is enabled. */
<> 144:ef7eb2e8f9f7 190 if (mode & CMT_MSC_BASE_MASK)
<> 144:ef7eb2e8f9f7 191 {
<> 144:ef7eb2e8f9f7 192 /* Base band mode. */
<> 144:ef7eb2e8f9f7 193 return kCMT_BasebandMode;
<> 144:ef7eb2e8f9f7 194 }
<> 144:ef7eb2e8f9f7 195 else if (mode & CMT_MSC_FSK_MASK)
<> 144:ef7eb2e8f9f7 196 {
<> 144:ef7eb2e8f9f7 197 /* FSK mode. */
<> 144:ef7eb2e8f9f7 198 return kCMT_FSKMode;
<> 144:ef7eb2e8f9f7 199 }
<> 144:ef7eb2e8f9f7 200 else
<> 144:ef7eb2e8f9f7 201 {
<> 144:ef7eb2e8f9f7 202 /* Time mode. */
<> 144:ef7eb2e8f9f7 203 return kCMT_TimeMode;
<> 144:ef7eb2e8f9f7 204 }
<> 144:ef7eb2e8f9f7 205 }
<> 144:ef7eb2e8f9f7 206 }
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 uint32_t CMT_GetCMTFrequency(CMT_Type *base, uint32_t busClock_Hz)
<> 144:ef7eb2e8f9f7 209 {
<> 144:ef7eb2e8f9f7 210 uint32_t frequency;
<> 144:ef7eb2e8f9f7 211 uint32_t divider;
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 /* Get intermediate frequency. */
<> 144:ef7eb2e8f9f7 214 frequency = busClock_Hz / ((base->PPS & CMT_PPS_PPSDIV_MASK) + 1);
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 /* Get the second divider. */
<> 144:ef7eb2e8f9f7 217 divider = ((base->MSC & CMT_MSC_CMTDIV_MASK) >> CMT_MSC_CMTDIV_SHIFT);
<> 144:ef7eb2e8f9f7 218 /* Get CMT frequency. */
<> 144:ef7eb2e8f9f7 219 switch ((cmt_second_clkdiv_t)divider)
<> 144:ef7eb2e8f9f7 220 {
<> 144:ef7eb2e8f9f7 221 case kCMT_SecondClkDiv1:
<> 144:ef7eb2e8f9f7 222 frequency = frequency / CMT_CMTDIV_ONE;
<> 144:ef7eb2e8f9f7 223 break;
<> 144:ef7eb2e8f9f7 224 case kCMT_SecondClkDiv2:
<> 144:ef7eb2e8f9f7 225 frequency = frequency / CMT_CMTDIV_TWO;
<> 144:ef7eb2e8f9f7 226 break;
<> 144:ef7eb2e8f9f7 227 case kCMT_SecondClkDiv4:
<> 144:ef7eb2e8f9f7 228 frequency = frequency / CMT_CMTDIV_FOUR;
<> 144:ef7eb2e8f9f7 229 break;
<> 144:ef7eb2e8f9f7 230 case kCMT_SecondClkDiv8:
<> 144:ef7eb2e8f9f7 231 frequency = frequency / CMT_CMTDIV_EIGHT;
<> 144:ef7eb2e8f9f7 232 break;
<> 144:ef7eb2e8f9f7 233 default:
<> 144:ef7eb2e8f9f7 234 frequency = frequency / CMT_CMTDIV_ONE;
<> 144:ef7eb2e8f9f7 235 break;
<> 144:ef7eb2e8f9f7 236 }
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 return frequency;
<> 144:ef7eb2e8f9f7 239 }
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 void CMT_SetModulateMarkSpace(CMT_Type *base, uint32_t markCount, uint32_t spaceCount)
<> 144:ef7eb2e8f9f7 242 {
<> 144:ef7eb2e8f9f7 243 /* Set modulate mark. */
<> 144:ef7eb2e8f9f7 244 base->CMD1 = (markCount >> CMT_MODULATE_COUNT_WIDTH) & CMT_CMD1_MB_MASK;
<> 144:ef7eb2e8f9f7 245 base->CMD2 = (markCount & CMT_CMD2_MB_MASK);
<> 144:ef7eb2e8f9f7 246 /* Set modulate space. */
<> 144:ef7eb2e8f9f7 247 base->CMD3 = (spaceCount >> CMT_MODULATE_COUNT_WIDTH) & CMT_CMD3_SB_MASK;
<> 144:ef7eb2e8f9f7 248 base->CMD4 = spaceCount & CMT_CMD4_SB_MASK;
<> 144:ef7eb2e8f9f7 249 }
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 void CMT_SetIroState(CMT_Type *base, cmt_infrared_output_state_t state)
<> 144:ef7eb2e8f9f7 252 {
<> 144:ef7eb2e8f9f7 253 uint8_t ocReg = base->OC;
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 ocReg &= ~CMT_OC_IROL_MASK;
<> 144:ef7eb2e8f9f7 256 ocReg |= CMT_OC_IROL(state);
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 /* Set the infrared output signal control. */
<> 144:ef7eb2e8f9f7 259 base->OC = ocReg;
<> 144:ef7eb2e8f9f7 260 }