added prescaler for 16 bit pwm in LPC1347 target
Fork of mbed-dev by
targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/gpio_irq_api.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)
- Committer:
- <>
- Date:
- Fri Sep 02 15:07:44 2016 +0100
- Revision:
- 144:ef7eb2e8f9f7
- Parent:
- 0:9b334a45a8ff
This updates the lib to the mbed lib v125
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /* mbed Microcontroller Library |
<> | 144:ef7eb2e8f9f7 | 2 | * Copyright (c) 2006-2013 ARM Limited |
<> | 144:ef7eb2e8f9f7 | 3 | * |
<> | 144:ef7eb2e8f9f7 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
<> | 144:ef7eb2e8f9f7 | 5 | * you may not use this file except in compliance with the License. |
<> | 144:ef7eb2e8f9f7 | 6 | * You may obtain a copy of the License at |
<> | 144:ef7eb2e8f9f7 | 7 | * |
<> | 144:ef7eb2e8f9f7 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
<> | 144:ef7eb2e8f9f7 | 9 | * |
<> | 144:ef7eb2e8f9f7 | 10 | * Unless required by applicable law or agreed to in writing, software |
<> | 144:ef7eb2e8f9f7 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
<> | 144:ef7eb2e8f9f7 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
<> | 144:ef7eb2e8f9f7 | 13 | * See the License for the specific language governing permissions and |
<> | 144:ef7eb2e8f9f7 | 14 | * limitations under the License. |
<> | 144:ef7eb2e8f9f7 | 15 | */ |
<> | 144:ef7eb2e8f9f7 | 16 | #include <stddef.h> |
<> | 144:ef7eb2e8f9f7 | 17 | #include "cmsis.h" |
<> | 144:ef7eb2e8f9f7 | 18 | |
<> | 144:ef7eb2e8f9f7 | 19 | #include "gpio_irq_api.h" |
<> | 144:ef7eb2e8f9f7 | 20 | #include "gpio_api.h" |
<> | 144:ef7eb2e8f9f7 | 21 | #include "mbed_error.h" |
<> | 144:ef7eb2e8f9f7 | 22 | |
<> | 144:ef7eb2e8f9f7 | 23 | #define CHANNEL_NUM 96 |
<> | 144:ef7eb2e8f9f7 | 24 | |
<> | 144:ef7eb2e8f9f7 | 25 | static uint32_t channel_ids[CHANNEL_NUM] = {0}; |
<> | 144:ef7eb2e8f9f7 | 26 | static gpio_irq_handler irq_handler; |
<> | 144:ef7eb2e8f9f7 | 27 | |
<> | 144:ef7eb2e8f9f7 | 28 | #define IRQ_DISABLED (0) |
<> | 144:ef7eb2e8f9f7 | 29 | #define IRQ_RAISING_EDGE PORT_PCR_IRQC(9) |
<> | 144:ef7eb2e8f9f7 | 30 | #define IRQ_FALLING_EDGE PORT_PCR_IRQC(10) |
<> | 144:ef7eb2e8f9f7 | 31 | #define IRQ_EITHER_EDGE PORT_PCR_IRQC(11) |
<> | 144:ef7eb2e8f9f7 | 32 | |
<> | 144:ef7eb2e8f9f7 | 33 | const uint32_t search_bits[] = {0x0000FFFF, 0x000000FF, 0x0000000F, 0x00000003, 0x00000001}; |
<> | 144:ef7eb2e8f9f7 | 34 | |
<> | 144:ef7eb2e8f9f7 | 35 | static void handle_interrupt_in(PORT_Type *port, int ch_base) { |
<> | 144:ef7eb2e8f9f7 | 36 | uint32_t isfr; |
<> | 144:ef7eb2e8f9f7 | 37 | uint8_t location; |
<> | 144:ef7eb2e8f9f7 | 38 | |
<> | 144:ef7eb2e8f9f7 | 39 | while((isfr = port->ISFR) != 0) { |
<> | 144:ef7eb2e8f9f7 | 40 | location = 0; |
<> | 144:ef7eb2e8f9f7 | 41 | for (int i = 0; i < 5; i++) { |
<> | 144:ef7eb2e8f9f7 | 42 | if (!(isfr & (search_bits[i] << location))) |
<> | 144:ef7eb2e8f9f7 | 43 | location += 1 << (4 - i); |
<> | 144:ef7eb2e8f9f7 | 44 | } |
<> | 144:ef7eb2e8f9f7 | 45 | |
<> | 144:ef7eb2e8f9f7 | 46 | uint32_t id = channel_ids[ch_base + location]; |
<> | 144:ef7eb2e8f9f7 | 47 | if (id == 0) { |
<> | 144:ef7eb2e8f9f7 | 48 | continue; |
<> | 144:ef7eb2e8f9f7 | 49 | } |
<> | 144:ef7eb2e8f9f7 | 50 | |
<> | 144:ef7eb2e8f9f7 | 51 | FGPIO_Type *gpio; |
<> | 144:ef7eb2e8f9f7 | 52 | gpio_irq_event event = IRQ_NONE; |
<> | 144:ef7eb2e8f9f7 | 53 | switch (port->PCR[location] & PORT_PCR_IRQC_MASK) { |
<> | 144:ef7eb2e8f9f7 | 54 | case IRQ_RAISING_EDGE: |
<> | 144:ef7eb2e8f9f7 | 55 | event = IRQ_RISE; |
<> | 144:ef7eb2e8f9f7 | 56 | break; |
<> | 144:ef7eb2e8f9f7 | 57 | |
<> | 144:ef7eb2e8f9f7 | 58 | case IRQ_FALLING_EDGE: |
<> | 144:ef7eb2e8f9f7 | 59 | event = IRQ_FALL; |
<> | 144:ef7eb2e8f9f7 | 60 | break; |
<> | 144:ef7eb2e8f9f7 | 61 | |
<> | 144:ef7eb2e8f9f7 | 62 | case IRQ_EITHER_EDGE: |
<> | 144:ef7eb2e8f9f7 | 63 | if (port == PORTA) { |
<> | 144:ef7eb2e8f9f7 | 64 | gpio = FPTA; |
<> | 144:ef7eb2e8f9f7 | 65 | } else if (port == PORTC) { |
<> | 144:ef7eb2e8f9f7 | 66 | gpio = FPTC; |
<> | 144:ef7eb2e8f9f7 | 67 | } else { |
<> | 144:ef7eb2e8f9f7 | 68 | gpio = FPTD; |
<> | 144:ef7eb2e8f9f7 | 69 | } |
<> | 144:ef7eb2e8f9f7 | 70 | event = (gpio->PDIR & (1<<location)) ? (IRQ_RISE) : (IRQ_FALL); |
<> | 144:ef7eb2e8f9f7 | 71 | break; |
<> | 144:ef7eb2e8f9f7 | 72 | } |
<> | 144:ef7eb2e8f9f7 | 73 | if (event != IRQ_NONE) { |
<> | 144:ef7eb2e8f9f7 | 74 | irq_handler(id, event); |
<> | 144:ef7eb2e8f9f7 | 75 | } |
<> | 144:ef7eb2e8f9f7 | 76 | port->ISFR = 1 << location; |
<> | 144:ef7eb2e8f9f7 | 77 | } |
<> | 144:ef7eb2e8f9f7 | 78 | } |
<> | 144:ef7eb2e8f9f7 | 79 | |
<> | 144:ef7eb2e8f9f7 | 80 | void gpio_irqA(void) { |
<> | 144:ef7eb2e8f9f7 | 81 | handle_interrupt_in(PORTA, 0); |
<> | 144:ef7eb2e8f9f7 | 82 | } |
<> | 144:ef7eb2e8f9f7 | 83 | |
<> | 144:ef7eb2e8f9f7 | 84 | /* PORTC and PORTD share same vector */ |
<> | 144:ef7eb2e8f9f7 | 85 | void gpio_irqCD(void) { |
<> | 144:ef7eb2e8f9f7 | 86 | if ((SIM->SCGC5 & SIM_SCGC5_PORTC_MASK) && (PORTC->ISFR)) { |
<> | 144:ef7eb2e8f9f7 | 87 | handle_interrupt_in(PORTC, 32); |
<> | 144:ef7eb2e8f9f7 | 88 | } else if ((SIM->SCGC5 & SIM_SCGC5_PORTD_MASK) && (PORTD->ISFR)) { |
<> | 144:ef7eb2e8f9f7 | 89 | handle_interrupt_in(PORTD, 64); |
<> | 144:ef7eb2e8f9f7 | 90 | } |
<> | 144:ef7eb2e8f9f7 | 91 | } |
<> | 144:ef7eb2e8f9f7 | 92 | |
<> | 144:ef7eb2e8f9f7 | 93 | int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) { |
<> | 144:ef7eb2e8f9f7 | 94 | if (pin == NC) |
<> | 144:ef7eb2e8f9f7 | 95 | return -1; |
<> | 144:ef7eb2e8f9f7 | 96 | |
<> | 144:ef7eb2e8f9f7 | 97 | irq_handler = handler; |
<> | 144:ef7eb2e8f9f7 | 98 | |
<> | 144:ef7eb2e8f9f7 | 99 | obj->port = pin >> PORT_SHIFT; |
<> | 144:ef7eb2e8f9f7 | 100 | obj->pin = (pin & 0x7F) >> 2; |
<> | 144:ef7eb2e8f9f7 | 101 | |
<> | 144:ef7eb2e8f9f7 | 102 | uint32_t ch_base, vector; |
<> | 144:ef7eb2e8f9f7 | 103 | IRQn_Type irq_n; |
<> | 144:ef7eb2e8f9f7 | 104 | switch (obj->port) { |
<> | 144:ef7eb2e8f9f7 | 105 | case PortA: |
<> | 144:ef7eb2e8f9f7 | 106 | ch_base = 0; irq_n = PORTA_IRQn; vector = (uint32_t)gpio_irqA; |
<> | 144:ef7eb2e8f9f7 | 107 | break; |
<> | 144:ef7eb2e8f9f7 | 108 | |
<> | 144:ef7eb2e8f9f7 | 109 | case PortC: |
<> | 144:ef7eb2e8f9f7 | 110 | ch_base = 32; irq_n = PORTC_PORTD_IRQn; vector = (uint32_t)gpio_irqCD; |
<> | 144:ef7eb2e8f9f7 | 111 | break; |
<> | 144:ef7eb2e8f9f7 | 112 | |
<> | 144:ef7eb2e8f9f7 | 113 | case PortD: |
<> | 144:ef7eb2e8f9f7 | 114 | ch_base = 64; irq_n = PORTC_PORTD_IRQn; vector = (uint32_t)gpio_irqCD; |
<> | 144:ef7eb2e8f9f7 | 115 | break; |
<> | 144:ef7eb2e8f9f7 | 116 | |
<> | 144:ef7eb2e8f9f7 | 117 | default: |
<> | 144:ef7eb2e8f9f7 | 118 | error("gpio_irq only supported on port A,C and D"); |
<> | 144:ef7eb2e8f9f7 | 119 | break; |
<> | 144:ef7eb2e8f9f7 | 120 | } |
<> | 144:ef7eb2e8f9f7 | 121 | NVIC_SetVector(irq_n, vector); |
<> | 144:ef7eb2e8f9f7 | 122 | NVIC_EnableIRQ(irq_n); |
<> | 144:ef7eb2e8f9f7 | 123 | |
<> | 144:ef7eb2e8f9f7 | 124 | obj->ch = ch_base + obj->pin; |
<> | 144:ef7eb2e8f9f7 | 125 | channel_ids[obj->ch] = id; |
<> | 144:ef7eb2e8f9f7 | 126 | |
<> | 144:ef7eb2e8f9f7 | 127 | return 0; |
<> | 144:ef7eb2e8f9f7 | 128 | } |
<> | 144:ef7eb2e8f9f7 | 129 | |
<> | 144:ef7eb2e8f9f7 | 130 | void gpio_irq_free(gpio_irq_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 131 | channel_ids[obj->ch] = 0; |
<> | 144:ef7eb2e8f9f7 | 132 | } |
<> | 144:ef7eb2e8f9f7 | 133 | |
<> | 144:ef7eb2e8f9f7 | 134 | void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) { |
<> | 144:ef7eb2e8f9f7 | 135 | PORT_Type *port = (PORT_Type *)(PORTA_BASE + 0x1000 * obj->port); |
<> | 144:ef7eb2e8f9f7 | 136 | |
<> | 144:ef7eb2e8f9f7 | 137 | uint32_t irq_settings = IRQ_DISABLED; |
<> | 144:ef7eb2e8f9f7 | 138 | |
<> | 144:ef7eb2e8f9f7 | 139 | switch (port->PCR[obj->pin] & PORT_PCR_IRQC_MASK) { |
<> | 144:ef7eb2e8f9f7 | 140 | case IRQ_DISABLED: |
<> | 144:ef7eb2e8f9f7 | 141 | if (enable) { |
<> | 144:ef7eb2e8f9f7 | 142 | irq_settings = (event == IRQ_RISE) ? (IRQ_RAISING_EDGE) : (IRQ_FALLING_EDGE); |
<> | 144:ef7eb2e8f9f7 | 143 | } |
<> | 144:ef7eb2e8f9f7 | 144 | break; |
<> | 144:ef7eb2e8f9f7 | 145 | |
<> | 144:ef7eb2e8f9f7 | 146 | case IRQ_RAISING_EDGE: |
<> | 144:ef7eb2e8f9f7 | 147 | if (enable) { |
<> | 144:ef7eb2e8f9f7 | 148 | irq_settings = (event == IRQ_RISE) ? (IRQ_RAISING_EDGE) : (IRQ_EITHER_EDGE); |
<> | 144:ef7eb2e8f9f7 | 149 | } else { |
<> | 144:ef7eb2e8f9f7 | 150 | if (event == IRQ_FALL) |
<> | 144:ef7eb2e8f9f7 | 151 | irq_settings = IRQ_RAISING_EDGE; |
<> | 144:ef7eb2e8f9f7 | 152 | } |
<> | 144:ef7eb2e8f9f7 | 153 | break; |
<> | 144:ef7eb2e8f9f7 | 154 | |
<> | 144:ef7eb2e8f9f7 | 155 | case IRQ_FALLING_EDGE: |
<> | 144:ef7eb2e8f9f7 | 156 | if (enable) { |
<> | 144:ef7eb2e8f9f7 | 157 | irq_settings = (event == IRQ_FALL) ? (IRQ_FALLING_EDGE) : (IRQ_EITHER_EDGE); |
<> | 144:ef7eb2e8f9f7 | 158 | } else { |
<> | 144:ef7eb2e8f9f7 | 159 | if (event == IRQ_RISE) |
<> | 144:ef7eb2e8f9f7 | 160 | irq_settings = IRQ_FALLING_EDGE; |
<> | 144:ef7eb2e8f9f7 | 161 | } |
<> | 144:ef7eb2e8f9f7 | 162 | break; |
<> | 144:ef7eb2e8f9f7 | 163 | |
<> | 144:ef7eb2e8f9f7 | 164 | case IRQ_EITHER_EDGE: |
<> | 144:ef7eb2e8f9f7 | 165 | if (enable) { |
<> | 144:ef7eb2e8f9f7 | 166 | irq_settings = IRQ_EITHER_EDGE; |
<> | 144:ef7eb2e8f9f7 | 167 | } else { |
<> | 144:ef7eb2e8f9f7 | 168 | irq_settings = (event == IRQ_RISE) ? (IRQ_FALLING_EDGE) : (IRQ_RAISING_EDGE); |
<> | 144:ef7eb2e8f9f7 | 169 | } |
<> | 144:ef7eb2e8f9f7 | 170 | break; |
<> | 144:ef7eb2e8f9f7 | 171 | } |
<> | 144:ef7eb2e8f9f7 | 172 | |
<> | 144:ef7eb2e8f9f7 | 173 | // Interrupt configuration and clear interrupt |
<> | 144:ef7eb2e8f9f7 | 174 | port->PCR[obj->pin] = (port->PCR[obj->pin] & ~PORT_PCR_IRQC_MASK) | irq_settings | PORT_PCR_ISF_MASK; |
<> | 144:ef7eb2e8f9f7 | 175 | } |
<> | 144:ef7eb2e8f9f7 | 176 | |
<> | 144:ef7eb2e8f9f7 | 177 | void gpio_irq_enable(gpio_irq_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 178 | if (obj->port == PortA) { |
<> | 144:ef7eb2e8f9f7 | 179 | NVIC_EnableIRQ(PORTA_IRQn); |
<> | 144:ef7eb2e8f9f7 | 180 | } else { |
<> | 144:ef7eb2e8f9f7 | 181 | NVIC_EnableIRQ(PORTC_PORTD_IRQn); |
<> | 144:ef7eb2e8f9f7 | 182 | } |
<> | 144:ef7eb2e8f9f7 | 183 | } |
<> | 144:ef7eb2e8f9f7 | 184 | |
<> | 144:ef7eb2e8f9f7 | 185 | void gpio_irq_disable(gpio_irq_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 186 | if (obj->port == PortA) { |
<> | 144:ef7eb2e8f9f7 | 187 | NVIC_DisableIRQ(PORTA_IRQn); |
<> | 144:ef7eb2e8f9f7 | 188 | } else { |
<> | 144:ef7eb2e8f9f7 | 189 | NVIC_DisableIRQ(PORTC_PORTD_IRQn); |
<> | 144:ef7eb2e8f9f7 | 190 | } |
<> | 144:ef7eb2e8f9f7 | 191 | } |