Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_NXP/TARGET_LPC408X/system_LPC407x_8x_177x_8x.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
0:9b334a45a8ff 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**********************************************************************
<> 144:ef7eb2e8f9f7 2 * $Id$ system_LPC407x_8x_177x_8x.c 2012-01-16
<> 144:ef7eb2e8f9f7 3 *//**
<> 144:ef7eb2e8f9f7 4 * @file system_LPC407x_8x_177x_8x.c
<> 144:ef7eb2e8f9f7 5 * @brief CMSIS Cortex-M3, M4 Device Peripheral Access Layer Source File
<> 144:ef7eb2e8f9f7 6 * for the NXP LPC407x_8x_177x_8x Device Series
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * ARM Limited (ARM) is supplying this software for use with
<> 144:ef7eb2e8f9f7 9 * Cortex-M processor based microcontrollers. This file can be
<> 144:ef7eb2e8f9f7 10 * freely distributed within development tools that are supporting
<> 144:ef7eb2e8f9f7 11 * such ARM based processors.
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * @version 1.2
<> 144:ef7eb2e8f9f7 14 * @date 20. June. 2012
<> 144:ef7eb2e8f9f7 15 * @author NXP MCU SW Application Team
<> 144:ef7eb2e8f9f7 16 *
<> 144:ef7eb2e8f9f7 17 * Copyright(C) 2012, NXP Semiconductor
<> 144:ef7eb2e8f9f7 18 * All rights reserved.
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 ***********************************************************************
<> 144:ef7eb2e8f9f7 21 * Software that is described herein is for illustrative purposes only
<> 144:ef7eb2e8f9f7 22 * which provides customers with programming information regarding the
<> 144:ef7eb2e8f9f7 23 * products. This software is supplied "AS IS" without any warranties.
<> 144:ef7eb2e8f9f7 24 * NXP Semiconductors assumes no responsibility or liability for the
<> 144:ef7eb2e8f9f7 25 * use of the software, conveys no license or title under any patent,
<> 144:ef7eb2e8f9f7 26 * copyright, or mask work right to the product. NXP Semiconductors
<> 144:ef7eb2e8f9f7 27 * reserves the right to make changes in the software without
<> 144:ef7eb2e8f9f7 28 * notification. NXP Semiconductors also make no representation or
<> 144:ef7eb2e8f9f7 29 * warranty that such application will be suitable for the specified
<> 144:ef7eb2e8f9f7 30 * use without further testing or modification.
<> 144:ef7eb2e8f9f7 31 **********************************************************************/
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 #include <stdint.h>
<> 144:ef7eb2e8f9f7 34 #include "LPC407x_8x_177x_8x.h"
<> 144:ef7eb2e8f9f7 35 #include "system_LPC407x_8x_177x_8x.h"
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 #define __CLK_DIV(x,y) (((y) == 0) ? 0: (x)/(y))
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 /*
<> 144:ef7eb2e8f9f7 40 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
<> 144:ef7eb2e8f9f7 41 */
<> 144:ef7eb2e8f9f7 42 /*--------------------- Clock Configuration ----------------------------------
<> 144:ef7eb2e8f9f7 43 //
<> 144:ef7eb2e8f9f7 44 // <e> Clock Configuration
<> 144:ef7eb2e8f9f7 45 // <h> System Controls and Status Register (SCS - address 0x400F C1A0)
<> 144:ef7eb2e8f9f7 46 // <o1.0> EMC Shift Control Bit
<> 144:ef7eb2e8f9f7 47 // <i> Controls how addresses are output on the EMC address pins for static memories
<> 144:ef7eb2e8f9f7 48 // <0=> Static CS addresses match bus width; AD[1] = 0 for 32 bit, AD[0] = 0 for 16+32 bit (Bit 0 is 0)
<> 144:ef7eb2e8f9f7 49 // <1=> Static CS addresses start at LSB 0 regardless of memory width (Bit 0 is 1)
<> 144:ef7eb2e8f9f7 50 //
<> 144:ef7eb2e8f9f7 51 // <o1.1> EMC Reset Disable Bit
<> 144:ef7eb2e8f9f7 52 // <i> If 0 (zero), all registers and functions of the EMC are initialized upon any reset condition
<> 144:ef7eb2e8f9f7 53 // <i> If 1, EMC is still retained its state through a warm reset
<> 144:ef7eb2e8f9f7 54 // <0=> Both EMC resets are asserted when any type of chip reset event occurs (Bit 1 is 0)
<> 144:ef7eb2e8f9f7 55 // <1=> Portions of EMC will only be reset by POR or BOR event (Bit 1 is 1)
<> 144:ef7eb2e8f9f7 56 //
<> 144:ef7eb2e8f9f7 57 // <o1.2> EMC Burst Control
<> 144:ef7eb2e8f9f7 58 // <i> Set to 1 to prevent multiple sequential accesses to memory via EMC static memory chip selects
<> 144:ef7eb2e8f9f7 59 // <0=> Burst enabled (Bit 2 is 0)
<> 144:ef7eb2e8f9f7 60 // <1=> Bust disbled (Bit 2 is 1)
<> 144:ef7eb2e8f9f7 61 //
<> 144:ef7eb2e8f9f7 62 // <o1.3> MCIPWR Active Level
<> 144:ef7eb2e8f9f7 63 // <i> Selects the active level for the SD card interface signal SD_PWR
<> 144:ef7eb2e8f9f7 64 // <0=> SD_PWR is active low (inverted output of the SD Card interface block) (Bit 3 is 0)
<> 144:ef7eb2e8f9f7 65 // <1=> SD_PWR is active high (follows the output of the SD Card interface block) (Bit 3 is 1)
<> 144:ef7eb2e8f9f7 66 //
<> 144:ef7eb2e8f9f7 67 // <o1.4> Main Oscillator Range Select
<> 144:ef7eb2e8f9f7 68 // <0=> In Range 1 MHz to 20 MHz (Bit 4 is 0)
<> 144:ef7eb2e8f9f7 69 // <1=> In Range 15 MHz to 25 MHz (Bit 4 is 1)
<> 144:ef7eb2e8f9f7 70 //
<> 144:ef7eb2e8f9f7 71 // <o1.5> Main Oscillator enable
<> 144:ef7eb2e8f9f7 72 // <i> 0 (zero) means disabled, 1 means enable
<> 144:ef7eb2e8f9f7 73 //
<> 144:ef7eb2e8f9f7 74 // <o1.6> Main Oscillator status (Read-Only)
<> 144:ef7eb2e8f9f7 75 // </h>
<> 144:ef7eb2e8f9f7 76 //
<> 144:ef7eb2e8f9f7 77 // <h> Clock Source Select Register (CLKSRCSEL - address 0x400F C10C)
<> 144:ef7eb2e8f9f7 78 // <o2.0> CLKSRC: Select the clock source for sysclk to PLL0 clock
<> 144:ef7eb2e8f9f7 79 // <0=> Internal RC oscillator (Bit 0 is 0)
<> 144:ef7eb2e8f9f7 80 // <1=> Main oscillator (Bit 0 is 1)
<> 144:ef7eb2e8f9f7 81 // </h>
<> 144:ef7eb2e8f9f7 82 //
<> 144:ef7eb2e8f9f7 83 // <e3>PLL0 Configuration (Main PLL PLL0CFG - address 0x400F C084)
<> 144:ef7eb2e8f9f7 84 // <i> F_in is in the range of 1 MHz to 25 MHz
<> 144:ef7eb2e8f9f7 85 // <i> F_cco = (F_in * M * 2 * P) is in range of 156 MHz to 320 MHz
<> 144:ef7eb2e8f9f7 86 // <i> PLL out clock = (F_cco / (2 * P)) is in rane of 9.75 MHz to 160 MHz
<> 144:ef7eb2e8f9f7 87 //
<> 144:ef7eb2e8f9f7 88 // <o4.0..4> MSEL: PLL Multiplier Value
<> 144:ef7eb2e8f9f7 89 // <i> M Value
<> 144:ef7eb2e8f9f7 90 // <1-32><#-1>
<> 144:ef7eb2e8f9f7 91 //
<> 144:ef7eb2e8f9f7 92 // <o4.5..6> PSEL: PLL Divider Value
<> 144:ef7eb2e8f9f7 93 // <i> P Value
<> 144:ef7eb2e8f9f7 94 // <0=> 1
<> 144:ef7eb2e8f9f7 95 // <1=> 2
<> 144:ef7eb2e8f9f7 96 // <2=> 4
<> 144:ef7eb2e8f9f7 97 // <3=> 8
<> 144:ef7eb2e8f9f7 98 // </e>
<> 144:ef7eb2e8f9f7 99 //
<> 144:ef7eb2e8f9f7 100 // <e5>PLL1 Configuration (Alt PLL PLL1CFG - address 0x400F C0A4)
<> 144:ef7eb2e8f9f7 101 // <i> F_in is in the range of 1 MHz to 25 MHz
<> 144:ef7eb2e8f9f7 102 // <i> F_cco = (F_in * M * 2 * P) is in range of 156 MHz to 320 MHz
<> 144:ef7eb2e8f9f7 103 // <i> PLL out clock = (F_cco / (2 * P)) is in rane of 9.75 MHz to 160 MHz
<> 144:ef7eb2e8f9f7 104 //
<> 144:ef7eb2e8f9f7 105 // <o6.0..4> MSEL: PLL Multiplier Value
<> 144:ef7eb2e8f9f7 106 // <i> M Value
<> 144:ef7eb2e8f9f7 107 // <1-32><#-1>
<> 144:ef7eb2e8f9f7 108 //
<> 144:ef7eb2e8f9f7 109 // <o6.5..6> PSEL: PLL Divider Value
<> 144:ef7eb2e8f9f7 110 // <i> P Value
<> 144:ef7eb2e8f9f7 111 // <0=> 1
<> 144:ef7eb2e8f9f7 112 // <1=> 2
<> 144:ef7eb2e8f9f7 113 // <2=> 4
<> 144:ef7eb2e8f9f7 114 // <3=> 8
<> 144:ef7eb2e8f9f7 115 // </e>
<> 144:ef7eb2e8f9f7 116 //
<> 144:ef7eb2e8f9f7 117 // <h> CPU Clock Selection Register (CCLKSEL - address 0x400F C104)
<> 144:ef7eb2e8f9f7 118 // <o7.0..4> CCLKDIV: Select the value for divider of CPU clock (CCLK)
<> 144:ef7eb2e8f9f7 119 // <i> 0: The divider is turned off. No clock will be provided to the CPU
<> 144:ef7eb2e8f9f7 120 // <i> n: The input clock is divided by n to produce the CPU clock
<> 144:ef7eb2e8f9f7 121 // <0-31>
<> 144:ef7eb2e8f9f7 122 //
<> 144:ef7eb2e8f9f7 123 // <o7.8> CCLKSEL: Select the input to the divider of CPU clock
<> 144:ef7eb2e8f9f7 124 // <0=> sysclk clock is used
<> 144:ef7eb2e8f9f7 125 // <1=> Main PLL0 clock is used
<> 144:ef7eb2e8f9f7 126 // </h>
<> 144:ef7eb2e8f9f7 127 //
<> 144:ef7eb2e8f9f7 128 // <h> USB Clock Selection Register (USBCLKSEL - 0x400F C108)
<> 144:ef7eb2e8f9f7 129 // <o8.0..4> USBDIV: USB clock (source PLL0) divider selection
<> 144:ef7eb2e8f9f7 130 // <0=> Divider is off and no clock provides to USB subsystem
<> 144:ef7eb2e8f9f7 131 // <4=> Divider value is 4 (The source clock is divided by 4)
<> 144:ef7eb2e8f9f7 132 // <6=> Divider value is 6 (The source clock is divided by 6)
<> 144:ef7eb2e8f9f7 133 //
<> 144:ef7eb2e8f9f7 134 // <o8.8..9> USBSEL: Select the source for USB clock divider
<> 144:ef7eb2e8f9f7 135 // <i> When CPU clock is selected, the USB can be accessed
<> 144:ef7eb2e8f9f7 136 // <i> by software but cannot perform USB functions
<> 144:ef7eb2e8f9f7 137 // <0=> sysclk clock (the clock input to PLL0)
<> 144:ef7eb2e8f9f7 138 // <1=> The clock output from PLL0
<> 144:ef7eb2e8f9f7 139 // <2=> The clock output from PLL1
<> 144:ef7eb2e8f9f7 140 // </h>
<> 144:ef7eb2e8f9f7 141 //
<> 144:ef7eb2e8f9f7 142 // <h> EMC Clock Selection Register (EMCCLKSEL - address 0x400F C100)
<> 144:ef7eb2e8f9f7 143 // <o9.0> EMCDIV: Set the divider for EMC clock
<> 144:ef7eb2e8f9f7 144 // <0=> Divider value is 1
<> 144:ef7eb2e8f9f7 145 // <1=> Divider value is 2 (EMC clock is equal a half of input clock)
<> 144:ef7eb2e8f9f7 146 // </h>
<> 144:ef7eb2e8f9f7 147 //
<> 144:ef7eb2e8f9f7 148 // <h> Peripheral Clock Selection Register (PCLKSEL - address 0x400F C1A8)
<> 144:ef7eb2e8f9f7 149 // <o10.0..4> PCLKDIV: APB Peripheral clock divider
<> 144:ef7eb2e8f9f7 150 // <i> 0: The divider is turned off. No clock will be provided to APB peripherals
<> 144:ef7eb2e8f9f7 151 // <i> n: The input clock is divided by n to produce the APB peripheral clock
<> 144:ef7eb2e8f9f7 152 // <0-31>
<> 144:ef7eb2e8f9f7 153 // </h>
<> 144:ef7eb2e8f9f7 154 //
<> 144:ef7eb2e8f9f7 155 // <h> SPIFI Clock Selection Register (SPIFICLKSEL - address 0x400F C1B4)
<> 144:ef7eb2e8f9f7 156 // <o11.0..4> SPIFIDIV: Set the divider for SPIFI clock
<> 144:ef7eb2e8f9f7 157 // <i> 0: The divider is turned off. No clock will be provided to the SPIFI
<> 144:ef7eb2e8f9f7 158 // <i> n: The input clock is divided by n to produce the SPIFI clock
<> 144:ef7eb2e8f9f7 159 // <0-31>
<> 144:ef7eb2e8f9f7 160 //
<> 144:ef7eb2e8f9f7 161 // <o11.8..9> SPIFISEL: Select the input clock for SPIFI clock divider
<> 144:ef7eb2e8f9f7 162 // <0=> sysclk clock (the clock input to PLL0)
<> 144:ef7eb2e8f9f7 163 // <1=> The clock output from PLL0
<> 144:ef7eb2e8f9f7 164 // <2=> The clock output from PLL1
<> 144:ef7eb2e8f9f7 165 // </h>
<> 144:ef7eb2e8f9f7 166 //
<> 144:ef7eb2e8f9f7 167 // <h> Power Control for Peripherals Register (PCONP - address 0x400F C1C8)
<> 144:ef7eb2e8f9f7 168 // <o12.0> PCLCD: LCD controller power/clock enable (bit 0)
<> 144:ef7eb2e8f9f7 169 // <o12.1> PCTIM0: Timer/Counter 0 power/clock enable (bit 1)
<> 144:ef7eb2e8f9f7 170 // <o12.2> PCTIM1: Timer/Counter 1 power/clock enable (bit 2)
<> 144:ef7eb2e8f9f7 171 // <o12.3> PCUART0: UART 0 power/clock enable (bit 3)
<> 144:ef7eb2e8f9f7 172 // <o12.4> PCUART1: UART 1 power/clock enable (bit 4)
<> 144:ef7eb2e8f9f7 173 // <o12.5> PCPWM0: PWM0 power/clock enable (bit 5)
<> 144:ef7eb2e8f9f7 174 // <o12.6> PCPWM1: PWM1 power/clock enable (bit 6)
<> 144:ef7eb2e8f9f7 175 // <o12.7> PCI2C0: I2C 0 interface power/clock enable (bit 7)
<> 144:ef7eb2e8f9f7 176 // <o12.8> PCUART4: UART 4 power/clock enable (bit 8)
<> 144:ef7eb2e8f9f7 177 // <o12.9> PCRTC: RTC and Event Recorder power/clock enable (bit 9)
<> 144:ef7eb2e8f9f7 178 // <o12.10> PCSSP1: SSP 1 interface power/clock enable (bit 10)
<> 144:ef7eb2e8f9f7 179 // <o12.11> PCEMC: External Memory Controller power/clock enable (bit 11)
<> 144:ef7eb2e8f9f7 180 // <o12.12> PCADC: A/D converter power/clock enable (bit 12)
<> 144:ef7eb2e8f9f7 181 // <o12.13> PCCAN1: CAN controller 1 power/clock enable (bit 13)
<> 144:ef7eb2e8f9f7 182 // <o12.14> PCCAN2: CAN controller 2 power/clock enable (bit 14)
<> 144:ef7eb2e8f9f7 183 // <o12.15> PCGPIO: IOCON, GPIO, and GPIO interrupts power/clock enable (bit 15)
<> 144:ef7eb2e8f9f7 184 // <o12.17> PCMCPWM: Motor Control PWM power/clock enable (bit 17)
<> 144:ef7eb2e8f9f7 185 // <o12.18> PCQEI: Quadrature encoder interface power/clock enable (bit 18)
<> 144:ef7eb2e8f9f7 186 // <o12.19> PCI2C1: I2C 1 interface power/clock enable (bit 19)
<> 144:ef7eb2e8f9f7 187 // <o12.20> PCSSP2: SSP 2 interface power/clock enable (bit 20)
<> 144:ef7eb2e8f9f7 188 // <o12.21> PCSSP0: SSP 0 interface power/clock enable (bit 21)
<> 144:ef7eb2e8f9f7 189 // <o12.22> PCTIM2: Timer 2 power/clock enable (bit 22)
<> 144:ef7eb2e8f9f7 190 // <o12.23> PCTIM3: Timer 3 power/clock enable (bit 23)
<> 144:ef7eb2e8f9f7 191 // <o12.24> PCUART2: UART 2 power/clock enable (bit 24)
<> 144:ef7eb2e8f9f7 192 // <o12.25> PCUART3: UART 3 power/clock enable (bit 25)
<> 144:ef7eb2e8f9f7 193 // <o12.26> PCI2C2: I2C 2 interface power/clock enable (bit 26)
<> 144:ef7eb2e8f9f7 194 // <o12.27> PCI2S: I2S interface power/clock enable (bit 27)
<> 144:ef7eb2e8f9f7 195 // <o12.28> PCSDC: SD Card interface power/clock enable (bit 28)
<> 144:ef7eb2e8f9f7 196 // <o12.29> PCGPDMA: GPDMA function power/clock enable (bit 29)
<> 144:ef7eb2e8f9f7 197 // <o12.30> PCENET: Ethernet block power/clock enable (bit 30)
<> 144:ef7eb2e8f9f7 198 // <o12.31> PCUSB: USB interface power/clock enable (bit 31)
<> 144:ef7eb2e8f9f7 199 // </h>
<> 144:ef7eb2e8f9f7 200 //
<> 144:ef7eb2e8f9f7 201 // <h> Clock Output Configuration Register (CLKOUTCFG)
<> 144:ef7eb2e8f9f7 202 // <o13.0..3> CLKOUTSEL: Clock Source for CLKOUT Selection
<> 144:ef7eb2e8f9f7 203 // <0=> CPU clock
<> 144:ef7eb2e8f9f7 204 // <1=> Main Oscillator
<> 144:ef7eb2e8f9f7 205 // <2=> Internal RC Oscillator
<> 144:ef7eb2e8f9f7 206 // <3=> USB clock
<> 144:ef7eb2e8f9f7 207 // <4=> RTC Oscillator
<> 144:ef7eb2e8f9f7 208 // <5=> unused
<> 144:ef7eb2e8f9f7 209 // <6=> Watchdog Oscillator
<> 144:ef7eb2e8f9f7 210 //
<> 144:ef7eb2e8f9f7 211 // <o13.4..7> CLKOUTDIV: Output Clock Divider
<> 144:ef7eb2e8f9f7 212 // <1-16><#-1>
<> 144:ef7eb2e8f9f7 213 //
<> 144:ef7eb2e8f9f7 214 // <o13.8> CLKOUT_EN: CLKOUT enable
<> 144:ef7eb2e8f9f7 215 // </h>
<> 144:ef7eb2e8f9f7 216 //
<> 144:ef7eb2e8f9f7 217 // </e>
<> 144:ef7eb2e8f9f7 218 */
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 #define CLOCK_SETUP 1
<> 144:ef7eb2e8f9f7 221 #define SCS_Val 0x00000020
<> 144:ef7eb2e8f9f7 222 #define CLKSRCSEL_Val 0x00000001
<> 144:ef7eb2e8f9f7 223 #define PLL0_SETUP 1
<> 144:ef7eb2e8f9f7 224 #define PLL0CFG_Val 0x00000009
<> 144:ef7eb2e8f9f7 225 #define PLL1_SETUP 1
<> 144:ef7eb2e8f9f7 226 #define PLL1CFG_Val 0x00000023
<> 144:ef7eb2e8f9f7 227 #define CCLKSEL_Val 0x00000101
<> 144:ef7eb2e8f9f7 228 #define USBCLKSEL_Val 0x00000201
<> 144:ef7eb2e8f9f7 229 #define EMCCLKSEL_Val 0x00000001
<> 144:ef7eb2e8f9f7 230 #define PCLKSEL_Val 0x00000002
<> 144:ef7eb2e8f9f7 231 #define SPIFICLKSEL_Val 0x00000002
<> 144:ef7eb2e8f9f7 232 #define PCONP_Val 0x042887DE
<> 144:ef7eb2e8f9f7 233 #define CLKOUTCFG_Val 0x00000100
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 #ifdef CORE_M4
<> 144:ef7eb2e8f9f7 236 #define LPC_CPACR 0xE000ED88
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 #define SCB_MVFR0 0xE000EF40
<> 144:ef7eb2e8f9f7 239 #define SCB_MVFR0_RESET 0x10110021
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 #define SCB_MVFR1 0xE000EF44
<> 144:ef7eb2e8f9f7 242 #define SCB_MVFR1_RESET 0x11000011
<> 144:ef7eb2e8f9f7 243 #endif
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 /*--------------------- Flash Accelerator Configuration ----------------------
<> 144:ef7eb2e8f9f7 247 //
<> 144:ef7eb2e8f9f7 248 // <e> Flash Accelerator Configuration register (FLASHCFG - address 0x400F C000)
<> 144:ef7eb2e8f9f7 249 // <o1.12..15> FLASHTIM: Flash Access Time
<> 144:ef7eb2e8f9f7 250 // <0=> 1 CPU clock (for CPU clock up to 20 MHz)
<> 144:ef7eb2e8f9f7 251 // <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
<> 144:ef7eb2e8f9f7 252 // <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
<> 144:ef7eb2e8f9f7 253 // <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
<> 144:ef7eb2e8f9f7 254 // <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
<> 144:ef7eb2e8f9f7 255 // <5=> 6 CPU clocks (for any CPU clock)
<> 144:ef7eb2e8f9f7 256 // </e>
<> 144:ef7eb2e8f9f7 257 */
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 #define FLASH_SETUP 1
<> 144:ef7eb2e8f9f7 260 #define FLASHCFG_Val 0x00005000
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 /*----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 263 Check the register settings
<> 144:ef7eb2e8f9f7 264 *----------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 265 #define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
<> 144:ef7eb2e8f9f7 266 #define CHECK_RSVD(val, mask) (val & mask)
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 /* Clock Configuration -------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 269 #if (CHECK_RSVD((SCS_Val), ~0x0000003F))
<> 144:ef7eb2e8f9f7 270 #error "SCS: Invalid values of reserved bits!"
<> 144:ef7eb2e8f9f7 271 #endif
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 #if (CHECK_RANGE((CLKSRCSEL_Val), 0, 1))
<> 144:ef7eb2e8f9f7 274 #error "CLKSRCSEL: Value out of range!"
<> 144:ef7eb2e8f9f7 275 #endif
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 #if (CHECK_RSVD((PLL0CFG_Val), ~0x0000007F))
<> 144:ef7eb2e8f9f7 278 #error "PLL0CFG: Invalid values of reserved bits!"
<> 144:ef7eb2e8f9f7 279 #endif
<> 144:ef7eb2e8f9f7 280
<> 144:ef7eb2e8f9f7 281 #if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F))
<> 144:ef7eb2e8f9f7 282 #error "PLL1CFG: Invalid values of reserved bits!"
<> 144:ef7eb2e8f9f7 283 #endif
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 #if (CHECK_RSVD((CCLKSEL_Val), ~0x0000011F))
<> 144:ef7eb2e8f9f7 286 #error "CCLKSEL: Invalid values of reserved bits!"
<> 144:ef7eb2e8f9f7 287 #endif
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 #if (CHECK_RSVD((USBCLKSEL_Val), ~0x0000031F))
<> 144:ef7eb2e8f9f7 290 #error "USBCLKSEL: Invalid values of reserved bits!"
<> 144:ef7eb2e8f9f7 291 #endif
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 #if (CHECK_RSVD((EMCCLKSEL_Val), ~0x00000001))
<> 144:ef7eb2e8f9f7 294 #error "EMCCLKSEL: Invalid values of reserved bits!"
<> 144:ef7eb2e8f9f7 295 #endif
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 #if (CHECK_RSVD((PCLKSEL_Val), ~0x0000001F))
<> 144:ef7eb2e8f9f7 298 #error "PCLKSEL: Invalid values of reserved bits!"
<> 144:ef7eb2e8f9f7 299 #endif
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 #if (CHECK_RSVD((PCONP_Val), ~0xFFFEFFFF))
<> 144:ef7eb2e8f9f7 302 #error "PCONP: Invalid values of reserved bits!"
<> 144:ef7eb2e8f9f7 303 #endif
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 #if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
<> 144:ef7eb2e8f9f7 306 #error "CLKOUTCFG: Invalid values of reserved bits!"
<> 144:ef7eb2e8f9f7 307 #endif
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 /* Flash Accelerator Configuration -------------------------------------------*/
<> 144:ef7eb2e8f9f7 310 #if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F000))
<> 144:ef7eb2e8f9f7 311 #warning "FLASHCFG: Invalid values of reserved bits!"
<> 144:ef7eb2e8f9f7 312 #endif
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314
<> 144:ef7eb2e8f9f7 315 /*----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 316 DEFINES
<> 144:ef7eb2e8f9f7 317 *----------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 318 /* pll_out_clk = F_cco / (2 � P)
<> 144:ef7eb2e8f9f7 319 F_cco = pll_in_clk � M � 2 � P */
<> 144:ef7eb2e8f9f7 320 #define __M ((PLL0CFG_Val & 0x1F) + 1)
<> 144:ef7eb2e8f9f7 321 #define __PLL0_CLK(__F_IN) (__F_IN * __M)
<> 144:ef7eb2e8f9f7 322 #define __CCLK_DIV (CCLKSEL_Val & 0x1F)
<> 144:ef7eb2e8f9f7 323 #define __PCLK_DIV (PCLKSEL_Val & 0x1F)
<> 144:ef7eb2e8f9f7 324 #define __ECLK_DIV ((EMCCLKSEL_Val & 0x01) + 1)
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 /* Determine core clock frequency according to settings */
<> 144:ef7eb2e8f9f7 327 #if (CLOCK_SETUP) /* Clock Setup */
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 #if ((CLKSRCSEL_Val & 0x01) == 1) && ((SCS_Val & 0x20)== 0)
<> 144:ef7eb2e8f9f7 330 #error "Main Oscillator is selected as clock source but is not enabled!"
<> 144:ef7eb2e8f9f7 331 #endif
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 #if ((CCLKSEL_Val & 0x100) == 0x100) && (PLL0_SETUP == 0)
<> 144:ef7eb2e8f9f7 334 #error "Main PLL is selected as clock source but is not enabled!"
<> 144:ef7eb2e8f9f7 335 #endif
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 #if ((CCLKSEL_Val & 0x100) == 0) /* cclk = sysclk */
<> 144:ef7eb2e8f9f7 338 #if ((CLKSRCSEL_Val & 0x01) == 0) /* sysclk = irc_clk */
<> 144:ef7eb2e8f9f7 339 #define __CORE_CLK (IRC_OSC / __CCLK_DIV)
<> 144:ef7eb2e8f9f7 340 #define __PER_CLK (IRC_OSC/ __PCLK_DIV)
<> 144:ef7eb2e8f9f7 341 #define __EMC_CLK (__CORE_CLK/ __ECLK_DIV)
<> 144:ef7eb2e8f9f7 342 #else /* sysclk = osc_clk */
<> 144:ef7eb2e8f9f7 343 #define __CORE_CLK (OSC_CLK / __CCLK_DIV)
<> 144:ef7eb2e8f9f7 344 #define __PER_CLK (OSC_CLK/ __PCLK_DIV)
<> 144:ef7eb2e8f9f7 345 #define __EMC_CLK (__CORE_CLK/ __ECLK_DIV)
<> 144:ef7eb2e8f9f7 346 #endif
<> 144:ef7eb2e8f9f7 347 #else /* cclk = pll_clk */
<> 144:ef7eb2e8f9f7 348 #if ((CLKSRCSEL_Val & 0x01) == 0) /* sysclk = irc_clk */
<> 144:ef7eb2e8f9f7 349 #define __CORE_CLK (__PLL0_CLK(IRC_OSC) / __CCLK_DIV)
<> 144:ef7eb2e8f9f7 350 #define __PER_CLK (__PLL0_CLK(IRC_OSC) / __PCLK_DIV)
<> 144:ef7eb2e8f9f7 351 #define __EMC_CLK (__CORE_CLK / __ECLK_DIV)
<> 144:ef7eb2e8f9f7 352 #else /* sysclk = osc_clk */
<> 144:ef7eb2e8f9f7 353 #define __CORE_CLK (__PLL0_CLK(OSC_CLK) / __CCLK_DIV)
<> 144:ef7eb2e8f9f7 354 #define __PER_CLK (__PLL0_CLK(OSC_CLK) / __PCLK_DIV)
<> 144:ef7eb2e8f9f7 355 #define __EMC_CLK (__CORE_CLK / __ECLK_DIV)
<> 144:ef7eb2e8f9f7 356 #endif
<> 144:ef7eb2e8f9f7 357 #endif
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 #else
<> 144:ef7eb2e8f9f7 360 #define __CORE_CLK (IRC_OSC)
<> 144:ef7eb2e8f9f7 361 #define __PER_CLK (IRC_OSC)
<> 144:ef7eb2e8f9f7 362 #define __EMC_CLK (__CORE_CLK)
<> 144:ef7eb2e8f9f7 363 #endif
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 /*----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 366 Clock Variable definitions
<> 144:ef7eb2e8f9f7 367 *----------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 368 uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
<> 144:ef7eb2e8f9f7 369 uint32_t PeripheralClock = __PER_CLK; /*!< Peripheral Clock Frequency (Pclk) */
<> 144:ef7eb2e8f9f7 370 uint32_t EMCClock = __EMC_CLK; /*!< EMC Clock Frequency */
<> 144:ef7eb2e8f9f7 371 uint32_t USBClock = (48000000UL); /*!< USB Clock Frequency - this value will
<> 144:ef7eb2e8f9f7 372 be updated after call SystemCoreClockUpdate, should be 48MHz*/
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 /*----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 376 Clock functions
<> 144:ef7eb2e8f9f7 377 *----------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 378 void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
<> 144:ef7eb2e8f9f7 379 {
<> 144:ef7eb2e8f9f7 380 /* Determine clock frequency according to clock register values */
<> 144:ef7eb2e8f9f7 381 if ((LPC_SC->CCLKSEL &0x100) == 0) { /* cclk = sysclk */
<> 144:ef7eb2e8f9f7 382 if ((LPC_SC->CLKSRCSEL & 0x01) == 0) { /* sysclk = irc_clk */
<> 144:ef7eb2e8f9f7 383 SystemCoreClock = __CLK_DIV(IRC_OSC , (LPC_SC->CCLKSEL & 0x1F));
<> 144:ef7eb2e8f9f7 384 PeripheralClock = __CLK_DIV(IRC_OSC , (LPC_SC->PCLKSEL & 0x1F));
<> 144:ef7eb2e8f9f7 385 EMCClock = (SystemCoreClock / ((LPC_SC->EMCCLKSEL & 0x01)+1));
<> 144:ef7eb2e8f9f7 386 }
<> 144:ef7eb2e8f9f7 387 else { /* sysclk = osc_clk */
<> 144:ef7eb2e8f9f7 388 if ((LPC_SC->SCS & 0x40) == 0) {
<> 144:ef7eb2e8f9f7 389 SystemCoreClock = 0; /* this should never happen! */
<> 144:ef7eb2e8f9f7 390 PeripheralClock = 0;
<> 144:ef7eb2e8f9f7 391 EMCClock = 0;
<> 144:ef7eb2e8f9f7 392 }
<> 144:ef7eb2e8f9f7 393 else {
<> 144:ef7eb2e8f9f7 394 SystemCoreClock = __CLK_DIV(OSC_CLK , (LPC_SC->CCLKSEL & 0x1F));
<> 144:ef7eb2e8f9f7 395 PeripheralClock = __CLK_DIV(OSC_CLK , (LPC_SC->PCLKSEL & 0x1F));
<> 144:ef7eb2e8f9f7 396 EMCClock = (SystemCoreClock / ((LPC_SC->EMCCLKSEL & 0x01)+1));
<> 144:ef7eb2e8f9f7 397 }
<> 144:ef7eb2e8f9f7 398 }
<> 144:ef7eb2e8f9f7 399 }
<> 144:ef7eb2e8f9f7 400 else { /* cclk = pll_clk */
<> 144:ef7eb2e8f9f7 401 if ((LPC_SC->PLL0STAT & 0x100) == 0) { /* PLL0 not enabled */
<> 144:ef7eb2e8f9f7 402 SystemCoreClock = 0; /* this should never happen! */
<> 144:ef7eb2e8f9f7 403 PeripheralClock = 0;
<> 144:ef7eb2e8f9f7 404 EMCClock = 0;
<> 144:ef7eb2e8f9f7 405 }
<> 144:ef7eb2e8f9f7 406 else {
<> 144:ef7eb2e8f9f7 407 if ((LPC_SC->CLKSRCSEL & 0x01) == 0) { /* sysclk = irc_clk */
<> 144:ef7eb2e8f9f7 408 uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1);
<> 144:ef7eb2e8f9f7 409 uint8_t cpu_div = (LPC_SC->CCLKSEL & 0x1F);
<> 144:ef7eb2e8f9f7 410 uint8_t per_div = (LPC_SC->PCLKSEL & 0x1F);
<> 144:ef7eb2e8f9f7 411 uint8_t emc_div = (LPC_SC->EMCCLKSEL & 0x01)+1;
<> 144:ef7eb2e8f9f7 412 SystemCoreClock = __CLK_DIV(IRC_OSC * mul , cpu_div);
<> 144:ef7eb2e8f9f7 413 PeripheralClock = __CLK_DIV(IRC_OSC * mul , per_div);
<> 144:ef7eb2e8f9f7 414 EMCClock = SystemCoreClock / emc_div;
<> 144:ef7eb2e8f9f7 415 }
<> 144:ef7eb2e8f9f7 416 else { /* sysclk = osc_clk */
<> 144:ef7eb2e8f9f7 417 if ((LPC_SC->SCS & 0x40) == 0) {
<> 144:ef7eb2e8f9f7 418 SystemCoreClock = 0; /* this should never happen! */
<> 144:ef7eb2e8f9f7 419 PeripheralClock = 0;
<> 144:ef7eb2e8f9f7 420 EMCClock = 0;
<> 144:ef7eb2e8f9f7 421 }
<> 144:ef7eb2e8f9f7 422 else {
<> 144:ef7eb2e8f9f7 423 uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1);
<> 144:ef7eb2e8f9f7 424 uint8_t cpu_div = (LPC_SC->CCLKSEL & 0x1F);
<> 144:ef7eb2e8f9f7 425 uint8_t per_div = (LPC_SC->PCLKSEL & 0x1F);
<> 144:ef7eb2e8f9f7 426 uint8_t emc_div = (LPC_SC->EMCCLKSEL & 0x01)+1;
<> 144:ef7eb2e8f9f7 427 SystemCoreClock = __CLK_DIV(OSC_CLK * mul , cpu_div);
<> 144:ef7eb2e8f9f7 428 PeripheralClock = __CLK_DIV(OSC_CLK * mul , per_div);
<> 144:ef7eb2e8f9f7 429 EMCClock = SystemCoreClock / emc_div;
<> 144:ef7eb2e8f9f7 430 }
<> 144:ef7eb2e8f9f7 431 }
<> 144:ef7eb2e8f9f7 432 }
<> 144:ef7eb2e8f9f7 433 }
<> 144:ef7eb2e8f9f7 434 /* ---update USBClock------------------*/
<> 144:ef7eb2e8f9f7 435 if(LPC_SC->USBCLKSEL & (0x01<<8))//Use PLL0 as the input to the USB clock divider
<> 144:ef7eb2e8f9f7 436 {
<> 144:ef7eb2e8f9f7 437 switch (LPC_SC->USBCLKSEL & 0x1F)
<> 144:ef7eb2e8f9f7 438 {
<> 144:ef7eb2e8f9f7 439 case 0:
<> 144:ef7eb2e8f9f7 440 USBClock = 0; //no clock will be provided to the USB subsystem
<> 144:ef7eb2e8f9f7 441 break;
<> 144:ef7eb2e8f9f7 442 case 4:
<> 144:ef7eb2e8f9f7 443 case 6:
<> 144:ef7eb2e8f9f7 444 {
<> 144:ef7eb2e8f9f7 445 uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1);
<> 144:ef7eb2e8f9f7 446 uint8_t usb_div = (LPC_SC->USBCLKSEL & 0x1F);
<> 144:ef7eb2e8f9f7 447 if(LPC_SC->CLKSRCSEL & 0x01) //pll_clk_in = main_osc
<> 144:ef7eb2e8f9f7 448 USBClock = OSC_CLK * mul / usb_div;
<> 144:ef7eb2e8f9f7 449 else //pll_clk_in = irc_clk
<> 144:ef7eb2e8f9f7 450 USBClock = IRC_OSC * mul / usb_div;
<> 144:ef7eb2e8f9f7 451 }
<> 144:ef7eb2e8f9f7 452 break;
<> 144:ef7eb2e8f9f7 453 default:
<> 144:ef7eb2e8f9f7 454 USBClock = 0; /* this should never happen! */
<> 144:ef7eb2e8f9f7 455 }
<> 144:ef7eb2e8f9f7 456 }
<> 144:ef7eb2e8f9f7 457 else if(LPC_SC->USBCLKSEL & (0x02<<8))//usb_input_clk = alt_pll (pll1)
<> 144:ef7eb2e8f9f7 458 {
<> 144:ef7eb2e8f9f7 459 if(LPC_SC->CLKSRCSEL & 0x01) //pll1_clk_in = main_osc
<> 144:ef7eb2e8f9f7 460 USBClock = (OSC_CLK * ((LPC_SC->PLL1STAT & 0x1F) + 1));
<> 144:ef7eb2e8f9f7 461 else //pll1_clk_in = irc_clk
<> 144:ef7eb2e8f9f7 462 USBClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1));
<> 144:ef7eb2e8f9f7 463 }
<> 144:ef7eb2e8f9f7 464 else
<> 144:ef7eb2e8f9f7 465 USBClock = 0; /* this should never happen! */
<> 144:ef7eb2e8f9f7 466 }
<> 144:ef7eb2e8f9f7 467
<> 144:ef7eb2e8f9f7 468 /* Determine clock frequency according to clock register values */
<> 144:ef7eb2e8f9f7 469
<> 144:ef7eb2e8f9f7 470 #ifdef CORE_M4
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 void fpu_init(void)
<> 144:ef7eb2e8f9f7 473 {
<> 144:ef7eb2e8f9f7 474 // from arm trm manual:
<> 144:ef7eb2e8f9f7 475 // ; CPACR is located at address 0xE000ED88
<> 144:ef7eb2e8f9f7 476 // LDR.W R0, =0xE000ED88
<> 144:ef7eb2e8f9f7 477 // ; Read CPACR
<> 144:ef7eb2e8f9f7 478 // LDR R1, [R0]
<> 144:ef7eb2e8f9f7 479 // ; Set bits 20-23 to enable CP10 and CP11 coprocessors
<> 144:ef7eb2e8f9f7 480 // ORR R1, R1, #(0xF << 20)
<> 144:ef7eb2e8f9f7 481 // ; Write back the modified value to the CPACR
<> 144:ef7eb2e8f9f7 482 // STR R1, [R0]
<> 144:ef7eb2e8f9f7 483
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485 volatile uint32_t* regCpacr = (uint32_t*) LPC_CPACR;
<> 144:ef7eb2e8f9f7 486 volatile uint32_t* regMvfr0 = (uint32_t*) SCB_MVFR0;
<> 144:ef7eb2e8f9f7 487 volatile uint32_t* regMvfr1 = (uint32_t*) SCB_MVFR1;
<> 144:ef7eb2e8f9f7 488 volatile uint32_t Cpacr;
<> 144:ef7eb2e8f9f7 489 volatile uint32_t Mvfr0;
<> 144:ef7eb2e8f9f7 490 volatile uint32_t Mvfr1;
<> 144:ef7eb2e8f9f7 491 char vfpPresent = 0;
<> 144:ef7eb2e8f9f7 492
<> 144:ef7eb2e8f9f7 493 Mvfr0 = *regMvfr0;
<> 144:ef7eb2e8f9f7 494 Mvfr1 = *regMvfr1;
<> 144:ef7eb2e8f9f7 495
<> 144:ef7eb2e8f9f7 496 vfpPresent = ((SCB_MVFR0_RESET == Mvfr0) && (SCB_MVFR1_RESET == Mvfr1));
<> 144:ef7eb2e8f9f7 497
<> 144:ef7eb2e8f9f7 498 if(vfpPresent)
<> 144:ef7eb2e8f9f7 499 {
<> 144:ef7eb2e8f9f7 500 Cpacr = *regCpacr;
<> 144:ef7eb2e8f9f7 501 Cpacr |= (0xF << 20);
<> 144:ef7eb2e8f9f7 502 *regCpacr = Cpacr; // enable CP10 and CP11 for full access
<> 144:ef7eb2e8f9f7 503 }
<> 144:ef7eb2e8f9f7 504
<> 144:ef7eb2e8f9f7 505 }
<> 144:ef7eb2e8f9f7 506 #endif
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 /**
<> 144:ef7eb2e8f9f7 509 * Initialize the system
<> 144:ef7eb2e8f9f7 510 *
<> 144:ef7eb2e8f9f7 511 * @param none
<> 144:ef7eb2e8f9f7 512 * @return none
<> 144:ef7eb2e8f9f7 513 *
<> 144:ef7eb2e8f9f7 514 * @brief Setup the microcontroller system.
<> 144:ef7eb2e8f9f7 515 * Initialize the System.
<> 144:ef7eb2e8f9f7 516 */
<> 144:ef7eb2e8f9f7 517 void SystemInit (void)
<> 144:ef7eb2e8f9f7 518 {
<> 144:ef7eb2e8f9f7 519 #ifndef __CODE_RED
<> 144:ef7eb2e8f9f7 520 #ifdef CORE_M4
<> 144:ef7eb2e8f9f7 521 fpu_init();
<> 144:ef7eb2e8f9f7 522 #endif
<> 144:ef7eb2e8f9f7 523 #endif
<> 144:ef7eb2e8f9f7 524
<> 144:ef7eb2e8f9f7 525 #if (CLOCK_SETUP) /* Clock Setup */
<> 144:ef7eb2e8f9f7 526 LPC_SC->SCS = SCS_Val;
<> 144:ef7eb2e8f9f7 527 if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */
<> 144:ef7eb2e8f9f7 528 while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */
<> 144:ef7eb2e8f9f7 529 }
<> 144:ef7eb2e8f9f7 530
<> 144:ef7eb2e8f9f7 531 LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for sysclk/PLL0*/
<> 144:ef7eb2e8f9f7 532
<> 144:ef7eb2e8f9f7 533 #if (PLL0_SETUP)
<> 144:ef7eb2e8f9f7 534 LPC_SC->PLL0CFG = PLL0CFG_Val;
<> 144:ef7eb2e8f9f7 535 LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */
<> 144:ef7eb2e8f9f7 536 LPC_SC->PLL0FEED = 0xAA;
<> 144:ef7eb2e8f9f7 537 LPC_SC->PLL0FEED = 0x55;
<> 144:ef7eb2e8f9f7 538 while (!(LPC_SC->PLL0STAT & (1<<10)));/* Wait for PLOCK0 */
<> 144:ef7eb2e8f9f7 539 #endif
<> 144:ef7eb2e8f9f7 540
<> 144:ef7eb2e8f9f7 541 #if (PLL1_SETUP)
<> 144:ef7eb2e8f9f7 542 LPC_SC->PLL1CFG = PLL1CFG_Val;
<> 144:ef7eb2e8f9f7 543 LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */
<> 144:ef7eb2e8f9f7 544 LPC_SC->PLL1FEED = 0xAA;
<> 144:ef7eb2e8f9f7 545 LPC_SC->PLL1FEED = 0x55;
<> 144:ef7eb2e8f9f7 546 while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */
<> 144:ef7eb2e8f9f7 547 #endif
<> 144:ef7eb2e8f9f7 548
<> 144:ef7eb2e8f9f7 549 LPC_SC->CCLKSEL = CCLKSEL_Val; /* Setup Clock Divider */
<> 144:ef7eb2e8f9f7 550 LPC_SC->USBCLKSEL = USBCLKSEL_Val; /* Setup USB Clock Divider */
<> 144:ef7eb2e8f9f7 551 LPC_SC->EMCCLKSEL = EMCCLKSEL_Val; /* EMC Clock Selection */
<> 144:ef7eb2e8f9f7 552 LPC_SC->SPIFICLKSEL = SPIFICLKSEL_Val; /* SPIFI Clock Selection */
<> 144:ef7eb2e8f9f7 553 LPC_SC->PCLKSEL = PCLKSEL_Val; /* Peripheral Clock Selection */
<> 144:ef7eb2e8f9f7 554 LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
<> 144:ef7eb2e8f9f7 555 LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */
<> 144:ef7eb2e8f9f7 556 #endif
<> 144:ef7eb2e8f9f7 557
<> 144:ef7eb2e8f9f7 558 LPC_SC->PBOOST |= 0x03; /* Power Boost control */
<> 144:ef7eb2e8f9f7 559
<> 144:ef7eb2e8f9f7 560 #if (FLASH_SETUP == 1) /* Flash Accelerator Setup */
<> 144:ef7eb2e8f9f7 561 LPC_SC->FLASHCFG = FLASHCFG_Val|0x03A;
<> 144:ef7eb2e8f9f7 562 #endif
<> 144:ef7eb2e8f9f7 563 #ifndef __CODE_RED
<> 144:ef7eb2e8f9f7 564 #ifdef __RAM_MODE__
<> 144:ef7eb2e8f9f7 565 SCB->VTOR = 0x10000000 & 0x3FFFFF80;
<> 144:ef7eb2e8f9f7 566 #else
<> 144:ef7eb2e8f9f7 567 SCB->VTOR = 0x00000000 & 0x3FFFFF80;
<> 144:ef7eb2e8f9f7 568 #endif
<> 144:ef7eb2e8f9f7 569 #endif
<> 144:ef7eb2e8f9f7 570
<> 144:ef7eb2e8f9f7 571 /* Must set ROM_LAT bit in the Matrix Arbitration Register otherwise SPIFI
<> 144:ef7eb2e8f9f7 572 * initialization will cause debugging to HardFault */
<> 144:ef7eb2e8f9f7 573 LPC_SC->MATRIXARB |= (1<<16);
<> 144:ef7eb2e8f9f7 574
<> 144:ef7eb2e8f9f7 575 /* Reset LCD Controller to prevent strange behavior when doing a partial
<> 144:ef7eb2e8f9f7 576 * reset (happens when debugging).
<> 144:ef7eb2e8f9f7 577 */
<> 144:ef7eb2e8f9f7 578 LPC_SC->RSTCON0 = 1;
<> 144:ef7eb2e8f9f7 579
<> 144:ef7eb2e8f9f7 580 SystemCoreClockUpdate();
<> 144:ef7eb2e8f9f7 581 }