Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_IAR/startup_MKL46Z4.S@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
0:9b334a45a8ff 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**************************************************
<> 144:ef7eb2e8f9f7 2 *
<> 144:ef7eb2e8f9f7 3 * Copyright 2010 IAR Systems. All rights reserved.
<> 144:ef7eb2e8f9f7 4 *
<> 144:ef7eb2e8f9f7 5 * $Revision: 16 $
<> 144:ef7eb2e8f9f7 6 *
<> 144:ef7eb2e8f9f7 7 **************************************************/
<> 144:ef7eb2e8f9f7 8
<> 144:ef7eb2e8f9f7 9 ;
<> 144:ef7eb2e8f9f7 10 ; The modules in this file are included in the libraries, and may be replaced
<> 144:ef7eb2e8f9f7 11 ; by any user-defined modules that define the PUBLIC symbol _program_start or
<> 144:ef7eb2e8f9f7 12 ; a user defined start symbol.
<> 144:ef7eb2e8f9f7 13 ; To override the cstartup defined in the library, simply add your modified
<> 144:ef7eb2e8f9f7 14 ; version to the workbench project.
<> 144:ef7eb2e8f9f7 15 ;
<> 144:ef7eb2e8f9f7 16 ; The vector table is normally located at address 0.
<> 144:ef7eb2e8f9f7 17 ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
<> 144:ef7eb2e8f9f7 18 ; The name "__vector_table" has special meaning for C-SPY:
<> 144:ef7eb2e8f9f7 19 ; it is where the SP start value is found, and the NVIC vector
<> 144:ef7eb2e8f9f7 20 ; table register (VTOR) is initialized to this address if != 0.
<> 144:ef7eb2e8f9f7 21 ;
<> 144:ef7eb2e8f9f7 22 ; Cortex-M version
<> 144:ef7eb2e8f9f7 23 ;
<> 144:ef7eb2e8f9f7 24
<> 144:ef7eb2e8f9f7 25 MODULE ?cstartup
<> 144:ef7eb2e8f9f7 26
<> 144:ef7eb2e8f9f7 27 ;; Forward declaration of sections.
<> 144:ef7eb2e8f9f7 28 SECTION CSTACK:DATA:NOROOT(3)
<> 144:ef7eb2e8f9f7 29
<> 144:ef7eb2e8f9f7 30 SECTION .intvec:CODE:ROOT(2)
<> 144:ef7eb2e8f9f7 31
<> 144:ef7eb2e8f9f7 32 EXTERN __iar_program_start
<> 144:ef7eb2e8f9f7 33 EXTERN SystemInit
<> 144:ef7eb2e8f9f7 34 PUBLIC __vector_table
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 DATA
<> 144:ef7eb2e8f9f7 37 __vector_table
<> 144:ef7eb2e8f9f7 38 DCD sfe(CSTACK) ; Top of Stack
<> 144:ef7eb2e8f9f7 39 DCD Reset_Handler ; Reset Handler
<> 144:ef7eb2e8f9f7 40 DCD NMI_Handler ; NMI Handler
<> 144:ef7eb2e8f9f7 41 DCD HardFault_Handler ; Hard Fault Handler
<> 144:ef7eb2e8f9f7 42 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 43 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 44 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 45 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 46 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 47 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 48 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 49 DCD SVC_Handler ; SVCall Handler
<> 144:ef7eb2e8f9f7 50 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 51 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 52 DCD PendSV_Handler ; PendSV Handler
<> 144:ef7eb2e8f9f7 53 DCD SysTick_Handler ; SysTick Handler
<> 144:ef7eb2e8f9f7 54 ; External Interrupts
<> 144:ef7eb2e8f9f7 55 DCD DMA0_IRQHandler ; DMA channel 0 transfer complete/error interrupt
<> 144:ef7eb2e8f9f7 56 DCD DMA1_IRQHandler ; DMA channel 1 transfer complete/error interrupt
<> 144:ef7eb2e8f9f7 57 DCD DMA2_IRQHandler ; DMA channel 2 transfer complete/error interrupt
<> 144:ef7eb2e8f9f7 58 DCD DMA3_IRQHandler ; DMA channel 3 transfer complete/error interrupt
<> 144:ef7eb2e8f9f7 59 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 60 DCD FTFA_IRQHandler ; FTFA command complete/read collision interrupt
<> 144:ef7eb2e8f9f7 61 DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
<> 144:ef7eb2e8f9f7 62 DCD LLW_IRQHandler ; Low Leakage Wakeup
<> 144:ef7eb2e8f9f7 63 DCD I2C0_IRQHandler ; I2C0 interrupt
<> 144:ef7eb2e8f9f7 64 DCD I2C1_IRQHandler ; I2C0 interrupt 25
<> 144:ef7eb2e8f9f7 65 DCD SPI0_IRQHandler ; SPI0 interrupt
<> 144:ef7eb2e8f9f7 66 DCD SPI1_IRQHandler ; SPI1 interrupt
<> 144:ef7eb2e8f9f7 67 DCD UART0_IRQHandler ; UART0 status/error interrupt
<> 144:ef7eb2e8f9f7 68 DCD UART1_IRQHandler ; UART1 status/error interrupt
<> 144:ef7eb2e8f9f7 69 DCD UART2_IRQHandler ; UART2 status/error interrupt
<> 144:ef7eb2e8f9f7 70 DCD ADC0_IRQHandler ; ADC0 interrupt
<> 144:ef7eb2e8f9f7 71 DCD CMP0_IRQHandler ; CMP0 interrupt
<> 144:ef7eb2e8f9f7 72 DCD TPM0_IRQHandler ; TPM0 fault, overflow and channels interrupt
<> 144:ef7eb2e8f9f7 73 DCD TPM1_IRQHandler ; TPM1 fault, overflow and channels interrupt
<> 144:ef7eb2e8f9f7 74 DCD TPM2_IRQHandler ; TPM2 fault, overflow and channels interrupt
<> 144:ef7eb2e8f9f7 75 DCD RTC_IRQHandler ; RTC interrupt
<> 144:ef7eb2e8f9f7 76 DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
<> 144:ef7eb2e8f9f7 77 DCD PIT_IRQHandler ; PIT timer interrupt
<> 144:ef7eb2e8f9f7 78 DCD I2S0_IRQHandler ; I2S0 transmit interrupt
<> 144:ef7eb2e8f9f7 79 DCD USB0_IRQHandler ; USB0 interrupt
<> 144:ef7eb2e8f9f7 80 DCD DAC0_IRQHandler ; DAC0 interrupt
<> 144:ef7eb2e8f9f7 81 DCD TSI0_IRQHandler ; TSI0 interrupt
<> 144:ef7eb2e8f9f7 82 DCD MCG_IRQHandler ; MCG interrupt
<> 144:ef7eb2e8f9f7 83 DCD LPTimer_IRQHandler ; LPTimer interrupt
<> 144:ef7eb2e8f9f7 84 DCD LCD_IRQHandler ; Segment LCD Interrupt
<> 144:ef7eb2e8f9f7 85 DCD PORTA_IRQHandler ; Port A interrupt
<> 144:ef7eb2e8f9f7 86 DCD PORTD_IRQHandler ; Port D interrupt
<> 144:ef7eb2e8f9f7 87 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
<> 144:ef7eb2e8f9f7 88 ;;Flash Configuration
<> 144:ef7eb2e8f9f7 89 ;;16-byte flash configuration field that stores default protection settings (loaded on reset)
<> 144:ef7eb2e8f9f7 90 ;;and security information that allows the MCU to restrict acces to the FTFL module.
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 BackDoorK0 EQU 0xFF
<> 144:ef7eb2e8f9f7 93 BackDoorK1 EQU 0xFF
<> 144:ef7eb2e8f9f7 94 BackDoorK2 EQU 0xFF
<> 144:ef7eb2e8f9f7 95 BackDoorK3 EQU 0xFF
<> 144:ef7eb2e8f9f7 96 BackDoorK4 EQU 0xFF
<> 144:ef7eb2e8f9f7 97 BackDoorK5 EQU 0xFF
<> 144:ef7eb2e8f9f7 98 BackDoorK6 EQU 0xFF
<> 144:ef7eb2e8f9f7 99 BackDoorK7 EQU 0xFF
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 nFPROT0 EQU 0x00
<> 144:ef7eb2e8f9f7 102 FPROT0 EQU nFPROT0^0xFF
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 nFPROT1 EQU 0x00
<> 144:ef7eb2e8f9f7 105 FPROT1 EQU nFPROT1^0xFF
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 nFPROT2 EQU 0x00
<> 144:ef7eb2e8f9f7 108 FPROT2 EQU nFPROT2^0xFF
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 nFPROT3 EQU 0x00
<> 144:ef7eb2e8f9f7 111 FPROT3 EQU nFPROT3^0xFF
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 FOPT EQU 0xFF
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 FSEC EQU 0xFE
<> 144:ef7eb2e8f9f7 116 SECTION FlashConfig:CONST:REORDER:ROOT(2)
<> 144:ef7eb2e8f9f7 117 Config:
<> 144:ef7eb2e8f9f7 118 DATA
<> 144:ef7eb2e8f9f7 119 DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
<> 144:ef7eb2e8f9f7 120 DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
<> 144:ef7eb2e8f9f7 121 DCB FPROT0, FPROT1, FPROT2, FPROT3
<> 144:ef7eb2e8f9f7 122 DCB FSEC, FOPT, 0xFF, 0xFF
<> 144:ef7eb2e8f9f7 123 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
<> 144:ef7eb2e8f9f7 124 ;;
<> 144:ef7eb2e8f9f7 125 ;; Default interrupt handlers.
<> 144:ef7eb2e8f9f7 126 ;;
<> 144:ef7eb2e8f9f7 127 THUMB
<> 144:ef7eb2e8f9f7 128 PUBWEAK Reset_Handler
<> 144:ef7eb2e8f9f7 129 SECTION .text:CODE:NOROOT:REORDER(2)
<> 144:ef7eb2e8f9f7 130 Reset_Handler
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 LDR R0, =SystemInit
<> 144:ef7eb2e8f9f7 133 BLX R0
<> 144:ef7eb2e8f9f7 134 LDR R0, =__iar_program_start
<> 144:ef7eb2e8f9f7 135 BX R0
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 PUBWEAK NMI_Handler
<> 144:ef7eb2e8f9f7 138 PUBWEAK HardFault_Handler
<> 144:ef7eb2e8f9f7 139 PUBWEAK SVC_Handler
<> 144:ef7eb2e8f9f7 140 PUBWEAK PendSV_Handler
<> 144:ef7eb2e8f9f7 141 PUBWEAK SysTick_Handler
<> 144:ef7eb2e8f9f7 142 PUBWEAK DMA0_IRQHandler
<> 144:ef7eb2e8f9f7 143 PUBWEAK DMA1_IRQHandler
<> 144:ef7eb2e8f9f7 144 PUBWEAK DMA2_IRQHandler
<> 144:ef7eb2e8f9f7 145 PUBWEAK DMA3_IRQHandler
<> 144:ef7eb2e8f9f7 146 PUBWEAK Reserved20_IRQHandler
<> 144:ef7eb2e8f9f7 147 PUBWEAK FTFA_IRQHandler
<> 144:ef7eb2e8f9f7 148 PUBWEAK LVD_LVW_IRQHandler
<> 144:ef7eb2e8f9f7 149 PUBWEAK LLW_IRQHandler
<> 144:ef7eb2e8f9f7 150 PUBWEAK I2C0_IRQHandler
<> 144:ef7eb2e8f9f7 151 PUBWEAK I2C1_IRQHandler
<> 144:ef7eb2e8f9f7 152 PUBWEAK SPI0_IRQHandler
<> 144:ef7eb2e8f9f7 153 PUBWEAK SPI1_IRQHandler
<> 144:ef7eb2e8f9f7 154 PUBWEAK UART0_IRQHandler
<> 144:ef7eb2e8f9f7 155 PUBWEAK UART1_IRQHandler
<> 144:ef7eb2e8f9f7 156 PUBWEAK UART2_IRQHandler
<> 144:ef7eb2e8f9f7 157 PUBWEAK ADC0_IRQHandler
<> 144:ef7eb2e8f9f7 158 PUBWEAK CMP0_IRQHandler
<> 144:ef7eb2e8f9f7 159 PUBWEAK TPM0_IRQHandler
<> 144:ef7eb2e8f9f7 160 PUBWEAK TPM1_IRQHandler
<> 144:ef7eb2e8f9f7 161 PUBWEAK TPM2_IRQHandler
<> 144:ef7eb2e8f9f7 162 PUBWEAK RTC_IRQHandler
<> 144:ef7eb2e8f9f7 163 PUBWEAK RTC_Seconds_IRQHandler
<> 144:ef7eb2e8f9f7 164 PUBWEAK PIT_IRQHandler
<> 144:ef7eb2e8f9f7 165 PUBWEAK I2S0_IRQHandler
<> 144:ef7eb2e8f9f7 166 PUBWEAK USB0_IRQHandler
<> 144:ef7eb2e8f9f7 167 PUBWEAK DAC0_IRQHandler
<> 144:ef7eb2e8f9f7 168 PUBWEAK TSI0_IRQHandler
<> 144:ef7eb2e8f9f7 169 PUBWEAK MCG_IRQHandler
<> 144:ef7eb2e8f9f7 170 PUBWEAK LPTimer_IRQHandler
<> 144:ef7eb2e8f9f7 171 PUBWEAK LCD_IRQHandler
<> 144:ef7eb2e8f9f7 172 PUBWEAK PORTA_IRQHandler
<> 144:ef7eb2e8f9f7 173 PUBWEAK PORTD_IRQHandler
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 SECTION .text:CODE:REORDER:NOROOT(1)
<> 144:ef7eb2e8f9f7 176 THUMB
<> 144:ef7eb2e8f9f7 177 NMI_Handler
<> 144:ef7eb2e8f9f7 178 HardFault_Handler
<> 144:ef7eb2e8f9f7 179 SVC_Handler
<> 144:ef7eb2e8f9f7 180 PendSV_Handler
<> 144:ef7eb2e8f9f7 181 SysTick_Handler
<> 144:ef7eb2e8f9f7 182 DMA0_IRQHandler
<> 144:ef7eb2e8f9f7 183 DMA1_IRQHandler
<> 144:ef7eb2e8f9f7 184 DMA2_IRQHandler
<> 144:ef7eb2e8f9f7 185 DMA3_IRQHandler
<> 144:ef7eb2e8f9f7 186 Reserved20_IRQHandler
<> 144:ef7eb2e8f9f7 187 FTFA_IRQHandler
<> 144:ef7eb2e8f9f7 188 LVD_LVW_IRQHandler
<> 144:ef7eb2e8f9f7 189 LLW_IRQHandler
<> 144:ef7eb2e8f9f7 190 I2C0_IRQHandler
<> 144:ef7eb2e8f9f7 191 I2C1_IRQHandler
<> 144:ef7eb2e8f9f7 192 SPI0_IRQHandler
<> 144:ef7eb2e8f9f7 193 SPI1_IRQHandler
<> 144:ef7eb2e8f9f7 194 UART0_IRQHandler
<> 144:ef7eb2e8f9f7 195 UART1_IRQHandler
<> 144:ef7eb2e8f9f7 196 UART2_IRQHandler
<> 144:ef7eb2e8f9f7 197 ADC0_IRQHandler
<> 144:ef7eb2e8f9f7 198 CMP0_IRQHandler
<> 144:ef7eb2e8f9f7 199 TPM0_IRQHandler
<> 144:ef7eb2e8f9f7 200 TPM1_IRQHandler
<> 144:ef7eb2e8f9f7 201 TPM2_IRQHandler
<> 144:ef7eb2e8f9f7 202 RTC_IRQHandler
<> 144:ef7eb2e8f9f7 203 RTC_Seconds_IRQHandler
<> 144:ef7eb2e8f9f7 204 PIT_IRQHandler
<> 144:ef7eb2e8f9f7 205 I2S0_IRQHandler
<> 144:ef7eb2e8f9f7 206 USB0_IRQHandler
<> 144:ef7eb2e8f9f7 207 DAC0_IRQHandler
<> 144:ef7eb2e8f9f7 208 TSI0_IRQHandler
<> 144:ef7eb2e8f9f7 209 MCG_IRQHandler
<> 144:ef7eb2e8f9f7 210 LPTimer_IRQHandler
<> 144:ef7eb2e8f9f7 211 LCD_IRQHandler
<> 144:ef7eb2e8f9f7 212 PORTA_IRQHandler
<> 144:ef7eb2e8f9f7 213 PORTD_IRQHandler
<> 144:ef7eb2e8f9f7 214 Default_Handler
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 B Default_Handler
<> 144:ef7eb2e8f9f7 217 END