Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/fcache_api.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16
<> 144:ef7eb2e8f9f7 17 #include "fcache_api.h"
<> 144:ef7eb2e8f9f7 18
<> 144:ef7eb2e8f9f7 19 static unsigned int enabled;
<> 144:ef7eb2e8f9f7 20 static unsigned int fcache_mode;
<> 144:ef7eb2e8f9f7 21 /* Functions */
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 /*
<> 144:ef7eb2e8f9f7 24 * FCache_DriverInitialize: flash cache driver initialize funtion
<> 144:ef7eb2e8f9f7 25 */
<> 144:ef7eb2e8f9f7 26 void FCache_DriverInitialize()
<> 144:ef7eb2e8f9f7 27 {
<> 144:ef7eb2e8f9f7 28 unsigned int irqstat;
<> 144:ef7eb2e8f9f7 29
<> 144:ef7eb2e8f9f7 30 /* Clear interrupt status register */
<> 144:ef7eb2e8f9f7 31 irqstat = FCache_Readl(SYS_FCACHE_IRQSTAT) & (FCACHE_POW_ERR | FCACHE_MAN_INV_ERR);
<> 144:ef7eb2e8f9f7 32 FCache_Writel(SYS_FCACHE_IRQSTAT, irqstat);
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 /* Cache Disabled: Set enabled to 0 */
<> 144:ef7eb2e8f9f7 35 enabled = 0;
<> 144:ef7eb2e8f9f7 36 }
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /*
<> 144:ef7eb2e8f9f7 39 * FCache_Enable: Enables the flash cache mode
<> 144:ef7eb2e8f9f7 40 * mode: supported modes:
<> 144:ef7eb2e8f9f7 41 * 0 - auto-power auto-invalidate
<> 144:ef7eb2e8f9f7 42 * 1 - manual-power, manual-invalidate
<> 144:ef7eb2e8f9f7 43 */
<> 144:ef7eb2e8f9f7 44 void FCache_Enable(int mode)
<> 144:ef7eb2e8f9f7 45 {
<> 144:ef7eb2e8f9f7 46 /* Save Enable Mode */
<> 144:ef7eb2e8f9f7 47 fcache_mode = mode;
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /* Enable the FCache */
<> 144:ef7eb2e8f9f7 50 switch (fcache_mode) {
<> 144:ef7eb2e8f9f7 51 case 0:
<> 144:ef7eb2e8f9f7 52 /* Statistic counters enabled, Cache enable,
<> 144:ef7eb2e8f9f7 53 * auto-inval, auto-power control
<> 144:ef7eb2e8f9f7 54 */
<> 144:ef7eb2e8f9f7 55 FCache_Writel(SYS_FCACHE_CCR, (FCACHE_EN | FCACHE_STATISTIC_EN));
<> 144:ef7eb2e8f9f7 56 /* Wait until the cache is enabled */
<> 144:ef7eb2e8f9f7 57 while ((FCache_Readl(SYS_FCACHE_SR) & FCACHE_CS) != FCACHE_CS_ENABLED);
<> 144:ef7eb2e8f9f7 58 /* Cache Enabled: Set enabled to 1 */
<> 144:ef7eb2e8f9f7 59 enabled = 1;
<> 144:ef7eb2e8f9f7 60 break;
<> 144:ef7eb2e8f9f7 61 case 1:
<> 144:ef7eb2e8f9f7 62 /*
<> 144:ef7eb2e8f9f7 63 * Statistic counters enabled, Cache disabled,
<> 144:ef7eb2e8f9f7 64 * Manual power request (Setting: Power CTRL:
<> 144:ef7eb2e8f9f7 65 * Manual, Invalidate: Manual)
<> 144:ef7eb2e8f9f7 66 */
<> 144:ef7eb2e8f9f7 67 FCache_Writel(SYS_FCACHE_CCR, (FCACHE_POW_REQ
<> 144:ef7eb2e8f9f7 68 | FCACHE_SET_MAN_POW
<> 144:ef7eb2e8f9f7 69 | FCACHE_SET_MAN_INV
<> 144:ef7eb2e8f9f7 70 | FCACHE_STATISTIC_EN));
<> 144:ef7eb2e8f9f7 71 /* Wait until the cache rams are powered */
<> 144:ef7eb2e8f9f7 72 while ((FCache_Readl(SYS_FCACHE_SR) & FCACHE_POW_STAT) != FCACHE_POW_STAT);
<> 144:ef7eb2e8f9f7 73 /* Statistic counters enabled, Cache enabled
<> 144:ef7eb2e8f9f7 74 * Manual invalidate request (Setting: Power CTRL:
<> 144:ef7eb2e8f9f7 75 * Manual, Invalidate: Manual)
<> 144:ef7eb2e8f9f7 76 */
<> 144:ef7eb2e8f9f7 77 FCache_Writel(SYS_FCACHE_CCR, (FCACHE_INV_REQ
<> 144:ef7eb2e8f9f7 78 | FCACHE_POW_REQ
<> 144:ef7eb2e8f9f7 79 | FCACHE_SET_MAN_POW
<> 144:ef7eb2e8f9f7 80 | FCACHE_SET_MAN_INV
<> 144:ef7eb2e8f9f7 81 | FCACHE_STATISTIC_EN));
<> 144:ef7eb2e8f9f7 82 /* Wait until the cache is invalidated */
<> 144:ef7eb2e8f9f7 83 while ((FCache_Readl(SYS_FCACHE_SR) & FCACHE_INV_STAT) == FCACHE_INV_STAT);
<> 144:ef7eb2e8f9f7 84 /* Statistic counters enabled, Cache enable,
<> 144:ef7eb2e8f9f7 85 * manual-inval, manual-power control
<> 144:ef7eb2e8f9f7 86 */
<> 144:ef7eb2e8f9f7 87 FCache_Writel(SYS_FCACHE_CCR, (FCACHE_EN
<> 144:ef7eb2e8f9f7 88 | FCACHE_POW_REQ
<> 144:ef7eb2e8f9f7 89 | FCACHE_SET_MAN_POW
<> 144:ef7eb2e8f9f7 90 | FCACHE_SET_MAN_INV
<> 144:ef7eb2e8f9f7 91 | FCACHE_STATISTIC_EN));
<> 144:ef7eb2e8f9f7 92 /* Wait until the cache is enabled */
<> 144:ef7eb2e8f9f7 93 while ((FCache_Readl(SYS_FCACHE_SR) & FCACHE_CS) != FCACHE_CS_ENABLED);
<> 144:ef7eb2e8f9f7 94 /* Cache Enabled: Set enabled to 1 */
<> 144:ef7eb2e8f9f7 95 enabled = 1;
<> 144:ef7eb2e8f9f7 96 break;
<> 144:ef7eb2e8f9f7 97 default:
<> 144:ef7eb2e8f9f7 98 break;
<> 144:ef7eb2e8f9f7 99 }
<> 144:ef7eb2e8f9f7 100 }
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 /*
<> 144:ef7eb2e8f9f7 103 * FCache_Disable: Disables the flash cache mode previously enabled
<> 144:ef7eb2e8f9f7 104 */
<> 144:ef7eb2e8f9f7 105 void FCache_Disable()
<> 144:ef7eb2e8f9f7 106 {
<> 144:ef7eb2e8f9f7 107 /* Disable the FCache */
<> 144:ef7eb2e8f9f7 108 switch (fcache_mode) {
<> 144:ef7eb2e8f9f7 109 case 0:
<> 144:ef7eb2e8f9f7 110 /* Statistic counters enabled, Cache disable,
<> 144:ef7eb2e8f9f7 111 * auto-inval, auto-power control
<> 144:ef7eb2e8f9f7 112 */
<> 144:ef7eb2e8f9f7 113 FCache_Writel(SYS_FCACHE_CCR, FCACHE_STATISTIC_EN);
<> 144:ef7eb2e8f9f7 114 /* Wait until the cache is disabled */
<> 144:ef7eb2e8f9f7 115 while ((FCache_Readl(SYS_FCACHE_SR) & FCACHE_CS) != FCACHE_CS_DISABLED);
<> 144:ef7eb2e8f9f7 116 /* Cache Enabled: Set enabled to 0 */
<> 144:ef7eb2e8f9f7 117 enabled = 0;
<> 144:ef7eb2e8f9f7 118 break;
<> 144:ef7eb2e8f9f7 119 case 1:
<> 144:ef7eb2e8f9f7 120 /* Statistic counters enabled, Cache disable,
<> 144:ef7eb2e8f9f7 121 * manual-inval, manual-power control
<> 144:ef7eb2e8f9f7 122 */
<> 144:ef7eb2e8f9f7 123 FCache_Writel(SYS_FCACHE_CCR, (FCACHE_POW_REQ
<> 144:ef7eb2e8f9f7 124 | FCACHE_SET_MAN_POW
<> 144:ef7eb2e8f9f7 125 | FCACHE_SET_MAN_INV
<> 144:ef7eb2e8f9f7 126 | FCACHE_STATISTIC_EN));
<> 144:ef7eb2e8f9f7 127 /* Wait until the cache is disabled */
<> 144:ef7eb2e8f9f7 128 while ((FCache_Readl(SYS_FCACHE_SR) & FCACHE_CS) != FCACHE_CS_DISABLED);
<> 144:ef7eb2e8f9f7 129 /* Cache Enabled: Set enabled to 0 */
<> 144:ef7eb2e8f9f7 130 enabled = 0;
<> 144:ef7eb2e8f9f7 131 break;
<> 144:ef7eb2e8f9f7 132 default:
<> 144:ef7eb2e8f9f7 133 break;
<> 144:ef7eb2e8f9f7 134 }
<> 144:ef7eb2e8f9f7 135 }
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 /*
<> 144:ef7eb2e8f9f7 138 * FCache_Invalidate: to be invalidated the cache needs to be disabled.
<> 144:ef7eb2e8f9f7 139 * return -1: flash cannot be disabled
<> 144:ef7eb2e8f9f7 140 * -2: flash cannot be enabled
<> 144:ef7eb2e8f9f7 141 */
<> 144:ef7eb2e8f9f7 142 int FCache_Invalidate()
<> 144:ef7eb2e8f9f7 143 {
<> 144:ef7eb2e8f9f7 144 /* Manual cache invalidate */
<> 144:ef7eb2e8f9f7 145 if (fcache_mode == 1)
<> 144:ef7eb2e8f9f7 146 {
<> 144:ef7eb2e8f9f7 147 /* Disable Flash Cache */
<> 144:ef7eb2e8f9f7 148 if (enabled == 1)
<> 144:ef7eb2e8f9f7 149 FCache_Disable();
<> 144:ef7eb2e8f9f7 150 else
<> 144:ef7eb2e8f9f7 151 goto error;
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 /* Trigger INV_REQ */
<> 144:ef7eb2e8f9f7 154 FCache_Writel(SYS_FCACHE_CCR, (FCACHE_INV_REQ
<> 144:ef7eb2e8f9f7 155 | FCACHE_POW_REQ
<> 144:ef7eb2e8f9f7 156 | FCACHE_SET_MAN_POW
<> 144:ef7eb2e8f9f7 157 | FCACHE_SET_MAN_INV
<> 144:ef7eb2e8f9f7 158 | FCACHE_STATISTIC_EN));
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 /* Wait until INV_REQ is finished */
<> 144:ef7eb2e8f9f7 161 while ((FCache_Readl(SYS_FCACHE_SR) & FCACHE_CS) != FCACHE_CS_DISABLED);
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 /* Clear Stats */
<> 144:ef7eb2e8f9f7 164 FCache_Writel(SYS_FCACHE_CSHR, 0);
<> 144:ef7eb2e8f9f7 165 FCache_Writel(SYS_FCACHE_CSMR, 0);
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 /* Enable Flash Cache */
<> 144:ef7eb2e8f9f7 168 if (enabled == 0)
<> 144:ef7eb2e8f9f7 169 FCache_Enable(1);
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 error:
<> 144:ef7eb2e8f9f7 172 if (enabled == 0)
<> 144:ef7eb2e8f9f7 173 return -1;
<> 144:ef7eb2e8f9f7 174 else
<> 144:ef7eb2e8f9f7 175 return -2;
<> 144:ef7eb2e8f9f7 176 }
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 return 0;
<> 144:ef7eb2e8f9f7 179 }
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 unsigned int * FCache_GetStats()
<> 144:ef7eb2e8f9f7 182 {
<> 144:ef7eb2e8f9f7 183 static unsigned int stats[2];
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 /* Cache Statistics HIT Register */
<> 144:ef7eb2e8f9f7 186 stats[0] = FCache_Readl(SYS_FCACHE_CSHR);
<> 144:ef7eb2e8f9f7 187 /* Cache Statistics MISS Register */
<> 144:ef7eb2e8f9f7 188 stats[1] = FCache_Readl(SYS_FCACHE_CSMR);
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 return stats;
<> 144:ef7eb2e8f9f7 191 }
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 /*
<> 144:ef7eb2e8f9f7 194 * FCache_isEnabled: returns 1 if FCache is enabled
<> 144:ef7eb2e8f9f7 195 */
<> 144:ef7eb2e8f9f7 196 unsigned int FCache_isEnabled()
<> 144:ef7eb2e8f9f7 197 {
<> 144:ef7eb2e8f9f7 198 return enabled;
<> 144:ef7eb2e8f9f7 199 }