added prescaler for 16 bit pwm in LPC1347 target
Fork of mbed-dev by
targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rmu.c@147:ba84b7dc41a7, 2016-09-10 (annotated)
- Committer:
- JojoS
- Date:
- Sat Sep 10 15:32:04 2016 +0000
- Revision:
- 147:ba84b7dc41a7
- Parent:
- 144:ef7eb2e8f9f7
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 2 | * @file em_rmu.c |
<> | 144:ef7eb2e8f9f7 | 3 | * @brief Reset Management Unit (RMU) peripheral module peripheral API |
<> | 144:ef7eb2e8f9f7 | 4 | * |
<> | 144:ef7eb2e8f9f7 | 5 | * @version 4.2.1 |
<> | 144:ef7eb2e8f9f7 | 6 | ******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 7 | * @section License |
<> | 144:ef7eb2e8f9f7 | 8 | * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b> |
<> | 144:ef7eb2e8f9f7 | 9 | ******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 10 | * |
<> | 144:ef7eb2e8f9f7 | 11 | * Permission is granted to anyone to use this software for any purpose, |
<> | 144:ef7eb2e8f9f7 | 12 | * including commercial applications, and to alter it and redistribute it |
<> | 144:ef7eb2e8f9f7 | 13 | * freely, subject to the following restrictions: |
<> | 144:ef7eb2e8f9f7 | 14 | * |
<> | 144:ef7eb2e8f9f7 | 15 | * 1. The origin of this software must not be misrepresented; you must not |
<> | 144:ef7eb2e8f9f7 | 16 | * claim that you wrote the original software. |
<> | 144:ef7eb2e8f9f7 | 17 | * 2. Altered source versions must be plainly marked as such, and must not be |
<> | 144:ef7eb2e8f9f7 | 18 | * misrepresented as being the original software. |
<> | 144:ef7eb2e8f9f7 | 19 | * 3. This notice may not be removed or altered from any source distribution. |
<> | 144:ef7eb2e8f9f7 | 20 | * |
<> | 144:ef7eb2e8f9f7 | 21 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no |
<> | 144:ef7eb2e8f9f7 | 22 | * obligation to support this Software. Silicon Labs is providing the |
<> | 144:ef7eb2e8f9f7 | 23 | * Software "AS IS", with no express or implied warranties of any kind, |
<> | 144:ef7eb2e8f9f7 | 24 | * including, but not limited to, any implied warranties of merchantability |
<> | 144:ef7eb2e8f9f7 | 25 | * or fitness for any particular purpose or warranties against infringement |
<> | 144:ef7eb2e8f9f7 | 26 | * of any proprietary rights of a third party. |
<> | 144:ef7eb2e8f9f7 | 27 | * |
<> | 144:ef7eb2e8f9f7 | 28 | * Silicon Labs will not be liable for any consequential, incidental, or |
<> | 144:ef7eb2e8f9f7 | 29 | * special damages, or any other relief, or for any claim by any third party, |
<> | 144:ef7eb2e8f9f7 | 30 | * arising from your use of this Software. |
<> | 144:ef7eb2e8f9f7 | 31 | * |
<> | 144:ef7eb2e8f9f7 | 32 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 33 | |
<> | 144:ef7eb2e8f9f7 | 34 | #include "em_rmu.h" |
<> | 144:ef7eb2e8f9f7 | 35 | #if defined(RMU_COUNT) && (RMU_COUNT > 0) |
<> | 144:ef7eb2e8f9f7 | 36 | |
<> | 144:ef7eb2e8f9f7 | 37 | #include "em_common.h" |
<> | 144:ef7eb2e8f9f7 | 38 | #include "em_emu.h" |
<> | 144:ef7eb2e8f9f7 | 39 | #include "em_bus.h" |
<> | 144:ef7eb2e8f9f7 | 40 | |
<> | 144:ef7eb2e8f9f7 | 41 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 42 | * @addtogroup EM_Library |
<> | 144:ef7eb2e8f9f7 | 43 | * @{ |
<> | 144:ef7eb2e8f9f7 | 44 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 45 | |
<> | 144:ef7eb2e8f9f7 | 46 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 47 | * @addtogroup RMU |
<> | 144:ef7eb2e8f9f7 | 48 | * @brief Reset Management Unit (RMU) Peripheral API |
<> | 144:ef7eb2e8f9f7 | 49 | * @{ |
<> | 144:ef7eb2e8f9f7 | 50 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 51 | |
<> | 144:ef7eb2e8f9f7 | 52 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 53 | ***************************** DEFINES ********************************* |
<> | 144:ef7eb2e8f9f7 | 54 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 55 | |
<> | 144:ef7eb2e8f9f7 | 56 | /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ |
<> | 144:ef7eb2e8f9f7 | 57 | |
<> | 144:ef7eb2e8f9f7 | 58 | /* Reset cause "don't care" definitions. |
<> | 144:ef7eb2e8f9f7 | 59 | 1's mark the bits that must be zero, zeros are "don't cares". */ |
<> | 144:ef7eb2e8f9f7 | 60 | #if (_RMU_RSTCAUSE_MASK == 0x0000007FUL) |
<> | 144:ef7eb2e8f9f7 | 61 | #define RMU_RSTCAUSE_PORST_XMASK (0x00000000) /**0b0000000000000000 < Power On Reset */ |
<> | 144:ef7eb2e8f9f7 | 62 | #define RMU_RSTCAUSE_BODUNREGRST_XMASK (0x00000081) /**0b0000000010000001 < Brown Out Detector Unregulated Domain Reset */ |
<> | 144:ef7eb2e8f9f7 | 63 | #define RMU_RSTCAUSE_BODREGRST_XMASK (0x00000091) /**0b0000000010010001 < Brown Out Detector Regulated Domain Reset */ |
<> | 144:ef7eb2e8f9f7 | 64 | #define RMU_RSTCAUSE_EXTRST_XMASK (0x00000001) /**0b0000000000000001 < External Pin Reset */ |
<> | 144:ef7eb2e8f9f7 | 65 | #define RMU_RSTCAUSE_WDOGRST_XMASK (0x00000003) /**0b0000000000000011 < Watchdog Reset */ |
<> | 144:ef7eb2e8f9f7 | 66 | #define RMU_RSTCAUSE_LOCKUPRST_XMASK (0x0000EFDF) /**0b1110111111011111 < LOCKUP Reset */ |
<> | 144:ef7eb2e8f9f7 | 67 | #define RMU_RSTCAUSE_SYSREQRST_XMASK (0x0000EF9F) /**0b1110111110011111 < System Request Reset */ |
<> | 144:ef7eb2e8f9f7 | 68 | #define NUM_RSTCAUSES (7) |
<> | 144:ef7eb2e8f9f7 | 69 | |
<> | 144:ef7eb2e8f9f7 | 70 | #elif (_RMU_RSTCAUSE_MASK == 0x000007FFUL) |
<> | 144:ef7eb2e8f9f7 | 71 | #define RMU_RSTCAUSE_PORST_XMASK (0x00000000) /**0b0000000000000000 < Power On Reset */ |
<> | 144:ef7eb2e8f9f7 | 72 | #define RMU_RSTCAUSE_BODUNREGRST_XMASK (0x00000081) /**0b0000000010000001 < Brown Out Detector Unregulated Domain Reset */ |
<> | 144:ef7eb2e8f9f7 | 73 | #define RMU_RSTCAUSE_BODREGRST_XMASK (0x00000091) /**0b0000000010010001 < Brown Out Detector Regulated Domain Reset */ |
<> | 144:ef7eb2e8f9f7 | 74 | #define RMU_RSTCAUSE_EXTRST_XMASK (0x00000001) /**0b0000000000000001 < External Pin Reset */ |
<> | 144:ef7eb2e8f9f7 | 75 | #define RMU_RSTCAUSE_WDOGRST_XMASK (0x00000003) /**0b0000000000000011 < Watchdog Reset */ |
<> | 144:ef7eb2e8f9f7 | 76 | #define RMU_RSTCAUSE_LOCKUPRST_XMASK (0x0000EFDF) /**0b1110111111011111 < LOCKUP Reset */ |
<> | 144:ef7eb2e8f9f7 | 77 | #define RMU_RSTCAUSE_SYSREQRST_XMASK (0x0000EF9F) /**0b1110111110011111 < System Request Reset */ |
<> | 144:ef7eb2e8f9f7 | 78 | #define RMU_RSTCAUSE_EM4RST_XMASK (0x00000719) /**0b0000011100011001 < EM4 Reset */ |
<> | 144:ef7eb2e8f9f7 | 79 | #define RMU_RSTCAUSE_EM4WURST_XMASK (0x00000619) /**0b0000011000011001 < EM4 Wake-up Reset */ |
<> | 144:ef7eb2e8f9f7 | 80 | #define RMU_RSTCAUSE_BODAVDD0_XMASK (0x0000041F) /**0b0000010000011111 < AVDD0 Bod Reset. */ |
<> | 144:ef7eb2e8f9f7 | 81 | #define RMU_RSTCAUSE_BODAVDD1_XMASK (0x0000021F) /**0b0000001000011111 < AVDD1 Bod Reset. */ |
<> | 144:ef7eb2e8f9f7 | 82 | #define NUM_RSTCAUSES (11) |
<> | 144:ef7eb2e8f9f7 | 83 | |
<> | 144:ef7eb2e8f9f7 | 84 | #elif (_RMU_RSTCAUSE_MASK == 0x0000FFFFUL) |
<> | 144:ef7eb2e8f9f7 | 85 | #define RMU_RSTCAUSE_PORST_XMASK (0x00000000) /**0b0000000000000000 < Power On Reset */ |
<> | 144:ef7eb2e8f9f7 | 86 | #define RMU_RSTCAUSE_BODUNREGRST_XMASK (0x00000081) /**0b0000000010000001 < Brown Out Detector Unregulated Domain Reset */ |
<> | 144:ef7eb2e8f9f7 | 87 | #define RMU_RSTCAUSE_BODREGRST_XMASK (0x00000091) /**0b0000000010010001 < Brown Out Detector Regulated Domain Reset */ |
<> | 144:ef7eb2e8f9f7 | 88 | #define RMU_RSTCAUSE_EXTRST_XMASK (0x00000001) /**0b0000000000000001 < External Pin Reset */ |
<> | 144:ef7eb2e8f9f7 | 89 | #define RMU_RSTCAUSE_WDOGRST_XMASK (0x00000003) /**0b0000000000000011 < Watchdog Reset */ |
<> | 144:ef7eb2e8f9f7 | 90 | #define RMU_RSTCAUSE_LOCKUPRST_XMASK (0x0000EFDF) /**0b1110111111011111 < LOCKUP Reset */ |
<> | 144:ef7eb2e8f9f7 | 91 | #define RMU_RSTCAUSE_SYSREQRST_XMASK (0x0000EF9F) /**0b1110111110011111 < System Request Reset */ |
<> | 144:ef7eb2e8f9f7 | 92 | #define RMU_RSTCAUSE_EM4RST_XMASK (0x00000719) /**0b0000011100011001 < EM4 Reset */ |
<> | 144:ef7eb2e8f9f7 | 93 | #define RMU_RSTCAUSE_EM4WURST_XMASK (0x00000619) /**0b0000011000011001 < EM4 Wake-up Reset */ |
<> | 144:ef7eb2e8f9f7 | 94 | #define RMU_RSTCAUSE_BODAVDD0_XMASK (0x0000041F) /**0b0000010000011111 < AVDD0 Bod Reset */ |
<> | 144:ef7eb2e8f9f7 | 95 | #define RMU_RSTCAUSE_BODAVDD1_XMASK (0x0000021F) /**0b0000001000011111 < AVDD1 Bod Reset */ |
<> | 144:ef7eb2e8f9f7 | 96 | #define RMU_RSTCAUSE_BUBODVDDDREG_XMASK (0x00000001) /**0b0000000000000001 < Backup Brown Out Detector, VDD_DREG */ |
<> | 144:ef7eb2e8f9f7 | 97 | #define RMU_RSTCAUSE_BUBODBUVIN_XMASK (0x00000001) /**0b0000000000000001 < Backup Brown Out Detector, BU_VIN */ |
<> | 144:ef7eb2e8f9f7 | 98 | #define RMU_RSTCAUSE_BUBODUNREG_XMASK (0x00000001) /**0b0000000000000001 < Backup Brown Out Detector Unregulated Domain */ |
<> | 144:ef7eb2e8f9f7 | 99 | #define RMU_RSTCAUSE_BUBODREG_XMASK (0x00000001) /**0b0000000000000001 < Backup Brown Out Detector Regulated Domain */ |
<> | 144:ef7eb2e8f9f7 | 100 | #define RMU_RSTCAUSE_BUMODERST_XMASK (0x00000001) /**0b0000000000000001 < Backup mode reset */ |
<> | 144:ef7eb2e8f9f7 | 101 | #define NUM_RSTCAUSES (16) |
<> | 144:ef7eb2e8f9f7 | 102 | |
<> | 144:ef7eb2e8f9f7 | 103 | #elif ((_RMU_RSTCAUSE_MASK & 0x0FFFFFFF) == 0x00010F1DUL) |
<> | 144:ef7eb2e8f9f7 | 104 | #define RMU_RSTCAUSE_PORST_XMASK (0x00000000) /**0b0000000000000000 < Power On Reset */ |
<> | 144:ef7eb2e8f9f7 | 105 | #define RMU_RSTCAUSE_BODAVDD_XMASK (0x00000001) /**0b0000000000000001 < AVDD Bod Reset */ |
<> | 144:ef7eb2e8f9f7 | 106 | #define RMU_RSTCAUSE_BODDVDD_XMASK (0x00000003) /**0b0000000000000011 < DVDD Bod Reset */ |
<> | 144:ef7eb2e8f9f7 | 107 | #define RMU_RSTCAUSE_BODREGRST_XMASK (0x0000000F) /**0b0000000000001111 < Brown Out Detector Regulated Domain Reset */ |
<> | 144:ef7eb2e8f9f7 | 108 | #define RMU_RSTCAUSE_EXTRST_XMASK (0x0000000F) /**0b0000000000001111 < External Pin Reset */ |
<> | 144:ef7eb2e8f9f7 | 109 | #define RMU_RSTCAUSE_LOCKUPRST_XMASK (0x0000001F) /**0b0000000000011111 < LOCKUP Reset */ |
<> | 144:ef7eb2e8f9f7 | 110 | #define RMU_RSTCAUSE_SYSREQRST_XMASK (0x0000001F) /**0b0000000000011111 < System Request Reset */ |
<> | 144:ef7eb2e8f9f7 | 111 | #define RMU_RSTCAUSE_WDOGRST_XMASK (0x0000001F) /**0b0000000000011111 < Watchdog Reset */ |
<> | 144:ef7eb2e8f9f7 | 112 | #define RMU_RSTCAUSE_EM4RST_XMASK (0x00000003) /**0b0000000000000011 < EM4H/S Reset */ |
<> | 144:ef7eb2e8f9f7 | 113 | #define NUM_RSTCAUSES (9) |
<> | 144:ef7eb2e8f9f7 | 114 | |
<> | 144:ef7eb2e8f9f7 | 115 | #else |
<> | 144:ef7eb2e8f9f7 | 116 | #warning "RMU_RSTCAUSE XMASKs are not defined for this family." |
<> | 144:ef7eb2e8f9f7 | 117 | #endif |
<> | 144:ef7eb2e8f9f7 | 118 | |
<> | 144:ef7eb2e8f9f7 | 119 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 120 | ******************************* STRUCTS *********************************** |
<> | 144:ef7eb2e8f9f7 | 121 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 122 | |
<> | 144:ef7eb2e8f9f7 | 123 | /** Reset cause mask type. */ |
<> | 144:ef7eb2e8f9f7 | 124 | typedef struct |
<> | 144:ef7eb2e8f9f7 | 125 | { |
<> | 144:ef7eb2e8f9f7 | 126 | uint32_t resetCauseMask; |
<> | 144:ef7eb2e8f9f7 | 127 | uint32_t dontCareMask; |
<> | 144:ef7eb2e8f9f7 | 128 | } RMU_ResetCauseMasks_Typedef; |
<> | 144:ef7eb2e8f9f7 | 129 | |
<> | 144:ef7eb2e8f9f7 | 130 | |
<> | 144:ef7eb2e8f9f7 | 131 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 132 | ******************************* TYPEDEFS ********************************** |
<> | 144:ef7eb2e8f9f7 | 133 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 134 | |
<> | 144:ef7eb2e8f9f7 | 135 | /** Reset cause mask table. */ |
<> | 144:ef7eb2e8f9f7 | 136 | static const RMU_ResetCauseMasks_Typedef resetCauseMasks[NUM_RSTCAUSES] = |
<> | 144:ef7eb2e8f9f7 | 137 | { |
<> | 144:ef7eb2e8f9f7 | 138 | { RMU_RSTCAUSE_PORST, RMU_RSTCAUSE_PORST_XMASK }, |
<> | 144:ef7eb2e8f9f7 | 139 | #if defined(RMU_RSTCAUSE_BODUNREGRST) |
<> | 144:ef7eb2e8f9f7 | 140 | { RMU_RSTCAUSE_BODUNREGRST, RMU_RSTCAUSE_BODUNREGRST_XMASK }, |
<> | 144:ef7eb2e8f9f7 | 141 | #endif |
<> | 144:ef7eb2e8f9f7 | 142 | #if defined(RMU_RSTCAUSE_BODREGRST) |
<> | 144:ef7eb2e8f9f7 | 143 | { RMU_RSTCAUSE_BODREGRST, RMU_RSTCAUSE_BODREGRST_XMASK }, |
<> | 144:ef7eb2e8f9f7 | 144 | #endif |
<> | 144:ef7eb2e8f9f7 | 145 | #if defined(RMU_RSTCAUSE_AVDDBOD) |
<> | 144:ef7eb2e8f9f7 | 146 | { RMU_RSTCAUSE_AVDDBOD, RMU_RSTCAUSE_BODAVDD_XMASK }, |
<> | 144:ef7eb2e8f9f7 | 147 | #endif |
<> | 144:ef7eb2e8f9f7 | 148 | #if defined(RMU_RSTCAUSE_DVDDBOD) |
<> | 144:ef7eb2e8f9f7 | 149 | { RMU_RSTCAUSE_DVDDBOD, RMU_RSTCAUSE_BODDVDD_XMASK }, |
<> | 144:ef7eb2e8f9f7 | 150 | #endif |
<> | 144:ef7eb2e8f9f7 | 151 | #if defined(RMU_RSTCAUSE_DECBOD) |
<> | 144:ef7eb2e8f9f7 | 152 | { RMU_RSTCAUSE_DECBOD, RMU_RSTCAUSE_BODREGRST_XMASK }, |
<> | 144:ef7eb2e8f9f7 | 153 | #endif |
<> | 144:ef7eb2e8f9f7 | 154 | { RMU_RSTCAUSE_EXTRST, RMU_RSTCAUSE_EXTRST_XMASK }, |
<> | 144:ef7eb2e8f9f7 | 155 | { RMU_RSTCAUSE_WDOGRST, RMU_RSTCAUSE_WDOGRST_XMASK }, |
<> | 144:ef7eb2e8f9f7 | 156 | { RMU_RSTCAUSE_LOCKUPRST, RMU_RSTCAUSE_LOCKUPRST_XMASK }, |
<> | 144:ef7eb2e8f9f7 | 157 | { RMU_RSTCAUSE_SYSREQRST, RMU_RSTCAUSE_SYSREQRST_XMASK }, |
<> | 144:ef7eb2e8f9f7 | 158 | #if defined(RMU_RSTCAUSE_EM4RST) |
<> | 144:ef7eb2e8f9f7 | 159 | { RMU_RSTCAUSE_EM4RST, RMU_RSTCAUSE_EM4RST_XMASK }, |
<> | 144:ef7eb2e8f9f7 | 160 | #endif |
<> | 144:ef7eb2e8f9f7 | 161 | #if defined(RMU_RSTCAUSE_EM4WURST) |
<> | 144:ef7eb2e8f9f7 | 162 | { RMU_RSTCAUSE_EM4WURST, RMU_RSTCAUSE_EM4WURST_XMASK }, |
<> | 144:ef7eb2e8f9f7 | 163 | #endif |
<> | 144:ef7eb2e8f9f7 | 164 | #if defined(RMU_RSTCAUSE_BODAVDD0) |
<> | 144:ef7eb2e8f9f7 | 165 | { RMU_RSTCAUSE_BODAVDD0, RMU_RSTCAUSE_BODAVDD0_XMASK }, |
<> | 144:ef7eb2e8f9f7 | 166 | #endif |
<> | 144:ef7eb2e8f9f7 | 167 | #if defined(RMU_RSTCAUSE_BODAVDD1) |
<> | 144:ef7eb2e8f9f7 | 168 | { RMU_RSTCAUSE_BODAVDD1, RMU_RSTCAUSE_BODAVDD1_XMASK }, |
<> | 144:ef7eb2e8f9f7 | 169 | #endif |
<> | 144:ef7eb2e8f9f7 | 170 | #if defined(BU_PRESENT) |
<> | 144:ef7eb2e8f9f7 | 171 | { RMU_RSTCAUSE_BUBODVDDDREG, RMU_RSTCAUSE_BUBODVDDDREG_XMASK }, |
<> | 144:ef7eb2e8f9f7 | 172 | { RMU_RSTCAUSE_BUBODBUVIN, RMU_RSTCAUSE_BUBODBUVIN_XMASK }, |
<> | 144:ef7eb2e8f9f7 | 173 | { RMU_RSTCAUSE_BUBODUNREG, RMU_RSTCAUSE_BUBODUNREG_XMASK }, |
<> | 144:ef7eb2e8f9f7 | 174 | { RMU_RSTCAUSE_BUBODREG, RMU_RSTCAUSE_BUBODREG_XMASK }, |
<> | 144:ef7eb2e8f9f7 | 175 | { RMU_RSTCAUSE_BUMODERST, RMU_RSTCAUSE_BUMODERST_XMASK }, |
<> | 144:ef7eb2e8f9f7 | 176 | #endif |
<> | 144:ef7eb2e8f9f7 | 177 | }; |
<> | 144:ef7eb2e8f9f7 | 178 | |
<> | 144:ef7eb2e8f9f7 | 179 | |
<> | 144:ef7eb2e8f9f7 | 180 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 181 | ******************************** TEST ******************************** |
<> | 144:ef7eb2e8f9f7 | 182 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 183 | #if defined(EMLIB_REGRESSION_TEST) |
<> | 144:ef7eb2e8f9f7 | 184 | /* Test variable that replaces the RSTCAUSE cause register when testing |
<> | 144:ef7eb2e8f9f7 | 185 | the RMU_ResetCauseGet function. */ |
<> | 144:ef7eb2e8f9f7 | 186 | extern uint32_t rstCause; |
<> | 144:ef7eb2e8f9f7 | 187 | #endif |
<> | 144:ef7eb2e8f9f7 | 188 | |
<> | 144:ef7eb2e8f9f7 | 189 | |
<> | 144:ef7eb2e8f9f7 | 190 | /** @endcond */ |
<> | 144:ef7eb2e8f9f7 | 191 | |
<> | 144:ef7eb2e8f9f7 | 192 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 193 | ************************** GLOBAL FUNCTIONS ******************************* |
<> | 144:ef7eb2e8f9f7 | 194 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 195 | |
<> | 144:ef7eb2e8f9f7 | 196 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 197 | * @brief |
<> | 144:ef7eb2e8f9f7 | 198 | * Disable/enable reset for various peripherals and signal sources |
<> | 144:ef7eb2e8f9f7 | 199 | * |
<> | 144:ef7eb2e8f9f7 | 200 | * @param[in] reset Reset types to enable/disable |
<> | 144:ef7eb2e8f9f7 | 201 | * |
<> | 144:ef7eb2e8f9f7 | 202 | * @param[in] mode Reset mode |
<> | 144:ef7eb2e8f9f7 | 203 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 204 | void RMU_ResetControl(RMU_Reset_TypeDef reset, RMU_ResetMode_TypeDef mode) |
<> | 144:ef7eb2e8f9f7 | 205 | { |
<> | 144:ef7eb2e8f9f7 | 206 | /* Note that the RMU supports bit-band access, but not peripheral bit-field set/clear */ |
<> | 144:ef7eb2e8f9f7 | 207 | #if defined(_RMU_CTRL_PINRMODE_MASK) |
<> | 144:ef7eb2e8f9f7 | 208 | uint32_t val; |
<> | 144:ef7eb2e8f9f7 | 209 | #endif |
<> | 144:ef7eb2e8f9f7 | 210 | uint32_t shift; |
<> | 144:ef7eb2e8f9f7 | 211 | |
<> | 144:ef7eb2e8f9f7 | 212 | shift = EFM32_CTZ((uint32_t)reset); |
<> | 144:ef7eb2e8f9f7 | 213 | #if defined(_RMU_CTRL_PINRMODE_MASK) |
<> | 144:ef7eb2e8f9f7 | 214 | val = (uint32_t)mode << shift; |
<> | 144:ef7eb2e8f9f7 | 215 | RMU->CTRL = (RMU->CTRL & ~reset) | val; |
<> | 144:ef7eb2e8f9f7 | 216 | #else |
<> | 144:ef7eb2e8f9f7 | 217 | BUS_RegBitWrite(&RMU->CTRL, (uint32_t)shift, mode ? 1 : 0); |
<> | 144:ef7eb2e8f9f7 | 218 | #endif |
<> | 144:ef7eb2e8f9f7 | 219 | } |
<> | 144:ef7eb2e8f9f7 | 220 | |
<> | 144:ef7eb2e8f9f7 | 221 | |
<> | 144:ef7eb2e8f9f7 | 222 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 223 | * @brief |
<> | 144:ef7eb2e8f9f7 | 224 | * Clear the reset cause register. |
<> | 144:ef7eb2e8f9f7 | 225 | * |
<> | 144:ef7eb2e8f9f7 | 226 | * @details |
<> | 144:ef7eb2e8f9f7 | 227 | * This function clears all the reset cause bits of the RSTCAUSE register. |
<> | 144:ef7eb2e8f9f7 | 228 | * The reset cause bits must be cleared by SW before a new reset occurs, |
<> | 144:ef7eb2e8f9f7 | 229 | * otherwise reset causes may accumulate. See @ref RMU_ResetCauseGet(). |
<> | 144:ef7eb2e8f9f7 | 230 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 231 | void RMU_ResetCauseClear(void) |
<> | 144:ef7eb2e8f9f7 | 232 | { |
<> | 144:ef7eb2e8f9f7 | 233 | RMU->CMD = RMU_CMD_RCCLR; |
<> | 144:ef7eb2e8f9f7 | 234 | |
<> | 144:ef7eb2e8f9f7 | 235 | #if defined(EMU_AUXCTRL_HRCCLR) |
<> | 144:ef7eb2e8f9f7 | 236 | { |
<> | 144:ef7eb2e8f9f7 | 237 | uint32_t locked; |
<> | 144:ef7eb2e8f9f7 | 238 | |
<> | 144:ef7eb2e8f9f7 | 239 | /* Clear some reset causes not cleared with RMU CMD register */ |
<> | 144:ef7eb2e8f9f7 | 240 | /* (If EMU registers locked, they must be unlocked first) */ |
<> | 144:ef7eb2e8f9f7 | 241 | locked = EMU->LOCK & EMU_LOCK_LOCKKEY_LOCKED; |
<> | 144:ef7eb2e8f9f7 | 242 | if (locked) |
<> | 144:ef7eb2e8f9f7 | 243 | { |
<> | 144:ef7eb2e8f9f7 | 244 | EMU_Unlock(); |
<> | 144:ef7eb2e8f9f7 | 245 | } |
<> | 144:ef7eb2e8f9f7 | 246 | |
<> | 144:ef7eb2e8f9f7 | 247 | BUS_RegBitWrite(&(EMU->AUXCTRL), _EMU_AUXCTRL_HRCCLR_SHIFT, 1); |
<> | 144:ef7eb2e8f9f7 | 248 | BUS_RegBitWrite(&(EMU->AUXCTRL), _EMU_AUXCTRL_HRCCLR_SHIFT, 0); |
<> | 144:ef7eb2e8f9f7 | 249 | |
<> | 144:ef7eb2e8f9f7 | 250 | if (locked) |
<> | 144:ef7eb2e8f9f7 | 251 | { |
<> | 144:ef7eb2e8f9f7 | 252 | EMU_Lock(); |
<> | 144:ef7eb2e8f9f7 | 253 | } |
<> | 144:ef7eb2e8f9f7 | 254 | } |
<> | 144:ef7eb2e8f9f7 | 255 | #endif |
<> | 144:ef7eb2e8f9f7 | 256 | } |
<> | 144:ef7eb2e8f9f7 | 257 | |
<> | 144:ef7eb2e8f9f7 | 258 | |
<> | 144:ef7eb2e8f9f7 | 259 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 260 | * @brief |
<> | 144:ef7eb2e8f9f7 | 261 | * Get the cause of the last reset. |
<> | 144:ef7eb2e8f9f7 | 262 | * |
<> | 144:ef7eb2e8f9f7 | 263 | * @details |
<> | 144:ef7eb2e8f9f7 | 264 | * In order to be useful, the reset cause must be cleared by software before a new |
<> | 144:ef7eb2e8f9f7 | 265 | * reset occurs, otherwise reset causes may accumulate. See @ref |
<> | 144:ef7eb2e8f9f7 | 266 | * RMU_ResetCauseClear(). This function call will return the main cause for |
<> | 144:ef7eb2e8f9f7 | 267 | * reset, which can be a bit mask (several causes), and clear away "noise". |
<> | 144:ef7eb2e8f9f7 | 268 | * |
<> | 144:ef7eb2e8f9f7 | 269 | * @return |
<> | 144:ef7eb2e8f9f7 | 270 | * Reset cause mask. Please consult the reference manual for description |
<> | 144:ef7eb2e8f9f7 | 271 | * of the reset cause mask. |
<> | 144:ef7eb2e8f9f7 | 272 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 273 | uint32_t RMU_ResetCauseGet(void) |
<> | 144:ef7eb2e8f9f7 | 274 | { |
<> | 144:ef7eb2e8f9f7 | 275 | #if !defined(EMLIB_REGRESSION_TEST) |
<> | 144:ef7eb2e8f9f7 | 276 | uint32_t rstCause = RMU->RSTCAUSE; |
<> | 144:ef7eb2e8f9f7 | 277 | #endif |
<> | 144:ef7eb2e8f9f7 | 278 | uint32_t validRstCause = 0; |
<> | 144:ef7eb2e8f9f7 | 279 | uint32_t i; |
<> | 144:ef7eb2e8f9f7 | 280 | |
<> | 144:ef7eb2e8f9f7 | 281 | for (i = 0; i < NUM_RSTCAUSES; i++) |
<> | 144:ef7eb2e8f9f7 | 282 | { |
<> | 144:ef7eb2e8f9f7 | 283 | /* Checks to see if rstCause matches a RSTCAUSE and is not excluded by the X-mask */ |
<> | 144:ef7eb2e8f9f7 | 284 | if ((rstCause & resetCauseMasks[i].resetCauseMask) |
<> | 144:ef7eb2e8f9f7 | 285 | && !(rstCause & resetCauseMasks[i].dontCareMask)) |
<> | 144:ef7eb2e8f9f7 | 286 | { |
<> | 144:ef7eb2e8f9f7 | 287 | /* Adds the reset-cause to list of real reset-causes */ |
<> | 144:ef7eb2e8f9f7 | 288 | validRstCause |= resetCauseMasks[i].resetCauseMask; |
<> | 144:ef7eb2e8f9f7 | 289 | } |
<> | 144:ef7eb2e8f9f7 | 290 | } |
<> | 144:ef7eb2e8f9f7 | 291 | return validRstCause; |
<> | 144:ef7eb2e8f9f7 | 292 | } |
<> | 144:ef7eb2e8f9f7 | 293 | |
<> | 144:ef7eb2e8f9f7 | 294 | |
<> | 144:ef7eb2e8f9f7 | 295 | /** @} (end addtogroup RMU) */ |
<> | 144:ef7eb2e8f9f7 | 296 | /** @} (end addtogroup EM_Library) */ |
<> | 144:ef7eb2e8f9f7 | 297 | #endif /* defined(RMU_COUNT) && (RMU_COUNT > 0) */ |