Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/Changes_emlib.txt@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 ================ Revision history ============================================
<> 144:ef7eb2e8f9f7 2 4.2.1:
<> 144:ef7eb2e8f9f7 3 - Added errata fix for an issue that may cause BOD resets in EM2 when using
<> 144:ef7eb2e8f9f7 4 DCDC-to-DVDD mode. The fix is implemented in EMU_DCDCInit().
<> 144:ef7eb2e8f9f7 5 - Added function EMU_DCDCPowerOff() for boards with physically disconnected DCDC.
<> 144:ef7eb2e8f9f7 6 - Current consumption is optimized for DCDC bypass mode. This update is
<> 144:ef7eb2e8f9f7 7 implemented in EMU_DCDCInit().
<> 144:ef7eb2e8f9f7 8
<> 144:ef7eb2e8f9f7 9 4.2.0:
<> 144:ef7eb2e8f9f7 10 - Updated I2C clock divider equation for platform 2 parts. Added constraints
<> 144:ef7eb2e8f9f7 11 to HFPER clock frequency in I2C_BusFreqSet().
<> 144:ef7eb2e8f9f7 12 - EMU EMU_EM23VregMode_TypeDef replaced with a bool.
<> 144:ef7eb2e8f9f7 13 - Added support for GPIO alternate drive strength and alternate control modes.
<> 144:ef7eb2e8f9f7 14 - DCDC setup is simplified. More tuning and optimization settings added to
<> 144:ef7eb2e8f9f7 15 EMU_DCDCInit().
<> 144:ef7eb2e8f9f7 16 - Added member pinRetentionMode to EMU_EM4Init_TypeDef.
<> 144:ef7eb2e8f9f7 17 - Added function EMU_UnlatchPinRetention() to support unlatching of pin
<> 144:ef7eb2e8f9f7 18 retention in EM4H/S.
<> 144:ef7eb2e8f9f7 19 - Fixed bug in ADC_InitScan() which caused a overwrite of single conversion
<> 144:ef7eb2e8f9f7 20 mode calibration values.
<> 144:ef7eb2e8f9f7 21 - Added support for CRYPTO module on Pearl and Jade Geckos (em_crypto.c/h)
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 4.1.1:
<> 144:ef7eb2e8f9f7 24 - EMU_DCDCInit() updated with new parameters for EM2 and 3. Current consumption
<> 144:ef7eb2e8f9f7 25 with DCDC at expected levels for EFR32 and EFM32PG revA1, A2 and B0.
<> 144:ef7eb2e8f9f7 26 - EMU_DCDCInit_TypeDef updated with more parameters. EMU_DcdcLpcmpBiasMode_TypeDef
<> 144:ef7eb2e8f9f7 27 is removed.
<> 144:ef7eb2e8f9f7 28 - More assertions added to EMU_DCDCInit().
<> 144:ef7eb2e8f9f7 29 - HFXO default parameters updated.
<> 144:ef7eb2e8f9f7 30 - ADC defaults updated.
<> 144:ef7eb2e8f9f7 31 - RMU pin mode set fixed.
<> 144:ef7eb2e8f9f7 32 - Added missing define for cmuSelect_ULFRCO.
<> 144:ef7eb2e8f9f7 33 - Added missing functions for handling peripheral interrupts.
<> 144:ef7eb2e8f9f7 34 - Added support for VMON.
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 4.1.0:
<> 144:ef7eb2e8f9f7 37 - The typedef EMU_EM23Init_TypeDef which is a parameter to EMU_EM23Init()
<> 144:ef7eb2e8f9f7 38 has got a new definition.
<> 144:ef7eb2e8f9f7 39 - Initial support _SILICON_LABS_32B_PLATFORM_2 devices added
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 4.0.0:
<> 144:ef7eb2e8f9f7 42 - Use ARM CMSIS version 4.2.0.
<> 144:ef7eb2e8f9f7 43 - New style version macros in em_version.h.
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 3.20.14:
<> 144:ef7eb2e8f9f7 46 - USB release only.
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 3.20.13:
<> 144:ef7eb2e8f9f7 49 - Added new style family #defines in em_system.h, including EZR32 families.
<> 144:ef7eb2e8f9f7 50 - Fixed I2C_FREQ_STANDARD_MAX macros.
<> 144:ef7eb2e8f9f7 51 - Fixed bug in MSC_WriteWord which called internal functions that were linked
<> 144:ef7eb2e8f9f7 52 to flash for armgcc. All subsequent calls of MSC_WriteWord should now be
<> 144:ef7eb2e8f9f7 53 linked to RAM for all supported compilers. The internals of MSC_WriteWord
<> 144:ef7eb2e8f9f7 54 will check the global variable SystemCoreClock in order to make sure the
<> 144:ef7eb2e8f9f7 55 frequency is high enough for flash operations. If the core clock frequency
<> 144:ef7eb2e8f9f7 56 is changed, software is responsible for calling MSC_Init or
<> 144:ef7eb2e8f9f7 57 SystemCoreClockGet in order to set the SystemCoreClock variable to the
<> 144:ef7eb2e8f9f7 58 correct value.
<> 144:ef7eb2e8f9f7 59 - Added errata fix IDAC_101.
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 3.20.12:
<> 144:ef7eb2e8f9f7 62 - Added errata fix EMU_108.
<> 144:ef7eb2e8f9f7 63 - #ifdef's now use register defines instead of a mix of register and family defines.
<> 144:ef7eb2e8f9f7 64 - Added a case for when there are only 4 DMA channels available:
<> 144:ef7eb2e8f9f7 65 Alignment was (correctly) defined at 7 bit, but got asserted for 8 bit, leading
<> 144:ef7eb2e8f9f7 66 to unpredictable tripped asserts.
<> 144:ef7eb2e8f9f7 67 - Added USART_INITPRSTRIGGER_DEFAULT defined structure to support HWCONF.
<> 144:ef7eb2e8f9f7 68 - Added support for LFC clock tree.
<> 144:ef7eb2e8f9f7 69 - Added CMU_USHFRCOBandSet() and CMU_USHFRCOBandGet().
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 3.20.10:
<> 144:ef7eb2e8f9f7 72 - Maintenance release, no changes.
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 3.20.9:
<> 144:ef7eb2e8f9f7 75 - Added support for Happy Gecko including support for the new oscillator USHFRCO.
<> 144:ef7eb2e8f9f7 76 - Added MSC_WriteWordFast() function. This flash write function has a similar
<> 144:ef7eb2e8f9f7 77 performance as the old MSC_WriteWord(), but it disables interrupts and
<> 144:ef7eb2e8f9f7 78 requires a core clock frequency of at least 14MHz. The new MSC_WriteWord()
<> 144:ef7eb2e8f9f7 79 is slower, but it does not disable interrupts and may be called with core
<> 144:ef7eb2e8f9f7 80 clock frequencies down to 1MHz.
<> 144:ef7eb2e8f9f7 81 - Fixed a bug in EMU_EnterEM4() that set other EM4 configuration bits to 0
<> 144:ef7eb2e8f9f7 82 on EM4 entry.
<> 144:ef7eb2e8f9f7 83 - Added EMU_EM23Init().
<> 144:ef7eb2e8f9f7 84 - Fixed a bug in CMU_FlashWaitStateControl() where it failed to set the
<> 144:ef7eb2e8f9f7 85 required wait-state configuration if the MSC is locked.
<> 144:ef7eb2e8f9f7 86 - Added EMU interrupt handling functions.
<> 144:ef7eb2e8f9f7 87 - BURTC_Reset() changed to use async reset RMU_CTRL_BURSTEN instead of
<> 144:ef7eb2e8f9f7 88 reset value writeback. This makes the function independent of a selected
<> 144:ef7eb2e8f9f7 89 and enabled clock.
<> 144:ef7eb2e8f9f7 90 - BURTC_Sync() now returns without waiting for BURTC->SYNCBUSY to clear
<> 144:ef7eb2e8f9f7 91 when no clock is selected in BURTC_CTRL_CLKSEL.
<> 144:ef7eb2e8f9f7 92 - Fixed assertion bug in ACMP_ChannelSet() that checked the negSel parameter
<> 144:ef7eb2e8f9f7 93 against the wrong upper bound.
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 3.20.7:
<> 144:ef7eb2e8f9f7 96 - Fixed CMU_MAX_FREQ_HFLE macro for Wonder family.
<> 144:ef7eb2e8f9f7 97 - Fixed MSC_WriteWord() bug.
<> 144:ef7eb2e8f9f7 98 - Added syncbusy wait in RTC_Reset() for Gecko family.
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 3.20.6:
<> 144:ef7eb2e8f9f7 101 - Corrected fix for Errata EMU_E107.
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 3.20.5:
<> 144:ef7eb2e8f9f7 104 - Updated license texts.
<> 144:ef7eb2e8f9f7 105 - Removed unnecessary fix for Wonder Gecko.
<> 144:ef7eb2e8f9f7 106 - Updated LFXO temperature compensation in CHIP_Init().
<> 144:ef7eb2e8f9f7 107 - Changed LESENSE_ScanStart, LESENSE_ScanStop, LESENSE_DecoderStart,
<> 144:ef7eb2e8f9f7 108 LESENSE_ResultBufferClear() and LESENSE_Reset() functions to wait until
<> 144:ef7eb2e8f9f7 109 CMD register writes complete in order to make sure CMD register writes do
<> 144:ef7eb2e8f9f7 110 not break each other, and for register values to be consistent when
<> 144:ef7eb2e8f9f7 111 returning from functions that write to the CMD register.
<> 144:ef7eb2e8f9f7 112 - Added fix for Errata EMU_E107.
<> 144:ef7eb2e8f9f7 113 - Added family to SYSTEM_ChipRevision_TypeDef.
<> 144:ef7eb2e8f9f7 114 - Fixed bug in function AES_OFB128 which failed on Zero Gecko.
<> 144:ef7eb2e8f9f7 115 - Fixed RMU_ResetCauseGet() to return correct reset causes.
<> 144:ef7eb2e8f9f7 116 - Fixed bug in RTC_CounterReset() which failed to reset counter immediately
<> 144:ef7eb2e8f9f7 117 after return on Gecko devices.
<> 144:ef7eb2e8f9f7 118 - Added static inline non-blocking USART receive functions (USART_Rx...).
<> 144:ef7eb2e8f9f7 119 - Added function SYSTEM_GetFamily().
<> 144:ef7eb2e8f9f7 120 - Added function DAC_ChannelOutputSet().
<> 144:ef7eb2e8f9f7 121 - Fixed MSC_WriteWord() to not use WDOUBLE if LPWRITE is set.
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 3.20.2:
<> 144:ef7eb2e8f9f7 124 - Fixed bug regarding when MEMINFO in DEVINFO was introduced.
<> 144:ef7eb2e8f9f7 125 The correct crossover is production revision 18.
<> 144:ef7eb2e8f9f7 126 - Fixed bug in WDOG_Feed() which does not feed the watchdog if the watchdog
<> 144:ef7eb2e8f9f7 127 is disabled. Previously, the watchdog was broken after WDOG_Feed() fed it
<> 144:ef7eb2e8f9f7 128 when it was disabled.
<> 144:ef7eb2e8f9f7 129 - Fixed issue in em_i2c.c, which should set the NACK bit in the I2C CMD
<> 144:ef7eb2e8f9f7 130 register for the next to last byte received. The exception is when only
<> 144:ef7eb2e8f9f7 131 one byte is to be received. Then the NACK bit must be set like the
<> 144:ef7eb2e8f9f7 132 previous code was doing.
<> 144:ef7eb2e8f9f7 133 - Added function BURTC_ClockFreqGet() in order to determine clock frequency
<> 144:ef7eb2e8f9f7 134 of BURTC.
<> 144:ef7eb2e8f9f7 135 - Fixed bug in BURTC_Reset() which made a subsequent call to BURTC_Init hang.
<> 144:ef7eb2e8f9f7 136 - Added support for the IDAC module on the Zero Gecko family, em_idac.c/h.
<> 144:ef7eb2e8f9f7 137 - Fixed bug in DAC_PrescaleCalc() which could return higher values than
<> 144:ef7eb2e8f9f7 138 the maximum prescaler value. The fix makes sure to return the max prescaler
<> 144:ef7eb2e8f9f7 139 value resulting in possible higher DAC frequency than requested.
<> 144:ef7eb2e8f9f7 140 - Fixed I2C_BusFreqSet to use documented values for Nlow and Nhigh values,
<> 144:ef7eb2e8f9f7 141 and do not decrement the div(isor) by one according to the formula because
<> 144:ef7eb2e8f9f7 142 this resulted in higher I2C bus frequencies than desired.
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 3.20.0:
<> 144:ef7eb2e8f9f7 145 - LEUART: Added LEUART_TxDmaInEM2Enable() and LEUART_RxDmaInEM2Enable() for
<> 144:ef7eb2e8f9f7 146 enabling and disabling DMA LEUART RX and Tx in EM2 support.
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 3.0.3:
<> 144:ef7eb2e8f9f7 149 - Internal release for testing Wonder Gecko support.
<> 144:ef7eb2e8f9f7 150 - SYSTEM: Added function to enable/disable FPU access on Wonder parts,
<> 144:ef7eb2e8f9f7 151 SYSTEM_FpuAccessModeSet().
<> 144:ef7eb2e8f9f7 152 - USART: Added USART_SpiTransfer() function.
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 3.0.2:
<> 144:ef7eb2e8f9f7 155 - MSC: In MSC_WriteWord(), added support for double word write cycle support
<> 144:ef7eb2e8f9f7 156 (WDOUBLE) on devices with more than 512KiBytes of Flash memory. This can
<> 144:ef7eb2e8f9f7 157 almost double the speed of the MSC_WriteWord function for large data sizes.
<> 144:ef7eb2e8f9f7 158 - MSC: In MSC_ErasePage(), added support for devices with Flash page size
<> 144:ef7eb2e8f9f7 159 larger than 512 bytes, like Giant and Leopard Gecko.
<> 144:ef7eb2e8f9f7 160 - CMU: Fixed bug in CMU_ClockDivSet(). Clear HFLE and HFCORECLKLEDIV flags when
<> 144:ef7eb2e8f9f7 161 the core runs at frequencies up to 32MHz.
<> 144:ef7eb2e8f9f7 162 - CMU: Fixed bug in CMU_ClockEnable(): Set the HFLE and HFCORECLKLEDIV flags
<> 144:ef7eb2e8f9f7 163 when the CORE clock runs at frequencies higher than 32MHz.
<> 144:ef7eb2e8f9f7 164 - CMU: Fixed bug in CMU_ClockSelectSet(): Set HFLE and DIV4 factor for peripheral
<> 144:ef7eb2e8f9f7 165 clock if HFCORE clock for LE is enabled and the CORE clock runs at
<> 144:ef7eb2e8f9f7 166 frequencies higher than 32MHz.
<> 144:ef7eb2e8f9f7 167 - BITBAND: Added BITBAND_PeripheralRead() and BITBAND_SRAMRead() functions.
<> 144:ef7eb2e8f9f7 168 - DMA: Added #ifndef EXCLUDE_DEFAULT_DMA_IRQ_HANDLER around DMA_IRQHandler in
<> 144:ef7eb2e8f9f7 169 order for the user to implement a custom IRQ handler or run without a DMA
<> 144:ef7eb2e8f9f7 170 IRQ handler by defining EXCLUDE_DEFAULT_DMA_IRQ_HANDLER with the -D compiler
<> 144:ef7eb2e8f9f7 171 option.
<> 144:ef7eb2e8f9f7 172 - BURTC: In functions BURTC_Init() and BURTC_CompareSet(), moved SYNCBUSY
<> 144:ef7eb2e8f9f7 173 loops in front of modifications of registers COMP0 and LPMODE.
<> 144:ef7eb2e8f9f7 174 - MSC: Fixed ram_code section error on Keil toolchain.
<> 144:ef7eb2e8f9f7 175 - MSC: Removed uneeded code from MSC init and deinit which would have no
<> 144:ef7eb2e8f9f7 176 effect (Big thanks to Martin Schreiber for reporting this bug!).
<> 144:ef7eb2e8f9f7 177 - System: Added access functions for reading some values out of the Device
<> 144:ef7eb2e8f9f7 178 Information page.
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 3.0.1:
<> 144:ef7eb2e8f9f7 181 - LFXO fix for Giant family.
<> 144:ef7eb2e8f9f7 182 - USART: Fix for EFM32TG108Fxx which does not have USART0.
<> 144:ef7eb2e8f9f7 183 - EBI: The write to the CTRL register now happens before the ROUTE registers
<> 144:ef7eb2e8f9f7 184 are set. This avoids potential glitches.
<> 144:ef7eb2e8f9f7 185 - LESENSE: Fix issue when using lesenseAltExMapACMP.
<> 144:ef7eb2e8f9f7 186 - TIMER: Fix compilation on devices where ADC is not available.
<> 144:ef7eb2e8f9f7 187 - LCD: Fix bug where Aloc field would not be set to 0.
<> 144:ef7eb2e8f9f7 188 - BURTC: Fix Reset function by adding reset of COMP0 register and removing
<> 144:ef7eb2e8f9f7 189 reset of POWERDOWN register. The POWERDOWN register cannot be used to
<> 144:ef7eb2e8f9f7 190 power up the blocks after it has been powered down.
<> 144:ef7eb2e8f9f7 191 - CMU: Fixed bug where ClockDivSet, ClockDivGet and ClockFreqGet didn't work for
<> 144:ef7eb2e8f9f7 192 cmuClock_LCDpre clock. Also corrected 3 wrongly typed constants.
<> 144:ef7eb2e8f9f7 193 - CMU: Fixed bug where LFBE field in LFCLKSEL was not cleared before setting
<> 144:ef7eb2e8f9f7 194 bit-value.
<> 144:ef7eb2e8f9f7 195 - CMU: Fixed bug with CMU_ClockSelectGet. Did not give correct return value
<> 144:ef7eb2e8f9f7 196 for cmuClock_LFB.
<> 144:ef7eb2e8f9f7 197 - I2C: Fixed bug where I2C_Init would set divisor depending on the previous
<> 144:ef7eb2e8f9f7 198 master/slave configuration, not the one set in the initialization.
<> 144:ef7eb2e8f9f7 199 - I2C: Fixed issue in the function I2C_BusFreqSet (called by I2C_Init). The
<> 144:ef7eb2e8f9f7 200 input parameter 'I2C_ClockHLR_TypeDef type' was not in use. The fix enables
<> 144:ef7eb2e8f9f7 201 the parameter to add support for 'i2cClockHLRAsymetric' and 'i2cClockHLRFast'
<> 144:ef7eb2e8f9f7 202 modes. In order to use 'i2cClockHLRAsymetric' and 'i2cClockHLRFast' the
<> 144:ef7eb2e8f9f7 203 frequency of the HFPER clock may need to be increased.
<> 144:ef7eb2e8f9f7 204 - OPAMP: Fixed bug in the function OPAMP_Enable where an incorrect register
<> 144:ef7eb2e8f9f7 205 was used when setting the OPA2 calibration value.
<> 144:ef7eb2e8f9f7 206 - LEUART: Fixed issue in LEUART_BaudrateSet when a high clock frequency and a
<> 144:ef7eb2e8f9f7 207 low baudrate can overflow the clock divisor register (CLKDIV). The fix uses
<> 144:ef7eb2e8f9f7 208 an assert statement to check whether the calculated clock divisor is out of
<> 144:ef7eb2e8f9f7 209 range.
<> 144:ef7eb2e8f9f7 210 - USART: Fixed issue in USART_BaudrateAsyncSet when a high clock frequency and
<> 144:ef7eb2e8f9f7 211 a low baudrate can overflow the clock divisor register (CLKDIV). The fix uses
<> 144:ef7eb2e8f9f7 212 an assert statement to check whether the calculated clock divisor is out of
<> 144:ef7eb2e8f9f7 213 range.
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 3.0.0:
<> 144:ef7eb2e8f9f7 216 - efm32lib renamed emlib, as it will include support for non-EFM32 devices
<> 144:ef7eb2e8f9f7 217 in the future
<> 144:ef7eb2e8f9f7 218 - Added CMSIS_V3 compatibility fixes, and use of CMSIS_V3 definitions
<> 144:ef7eb2e8f9f7 219 - See Device/Changes-EnergyMicro.txt for detailed path changes
<> 144:ef7eb2e8f9f7 220 - New prefixes of all files, efm32_<peripherqal>.c/h to em_<peripheral>.c/h
<> 144:ef7eb2e8f9f7 221 - New names for readme and changes files
<> 144:ef7eb2e8f9f7 222 - RMU - BUMODERST not masked away when EM4 bits has been set
<> 144:ef7eb2e8f9f7 223 - CMU - CMU_LFClkGet now accounts for ULFRCO bit for Tiny Gecko
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 2.4.1:
<> 144:ef7eb2e8f9f7 226 - New, open source friendly license
<> 144:ef7eb2e8f9f7 227 - Fixed BURTC initialization hang if init->enable was false
<> 144:ef7eb2e8f9f7 228 - Fixed CMU issue with USBC and USB checks not being used correctly
<> 144:ef7eb2e8f9f7 229 - Added CMU feature, missing TIMER3 support
<> 144:ef7eb2e8f9f7 230 - Improved accuracy of SPI mode for USART baudrate calculation
<> 144:ef7eb2e8f9f7 231 - Corrected USBC HFCLKNODIV setting to comply with new header file defines
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 2.4.0:
<> 144:ef7eb2e8f9f7 234 - Added efm32_version.h defining software version number
<> 144:ef7eb2e8f9f7 235 - Added BURTC support for Giant and Leopard Gecko
<> 144:ef7eb2e8f9f7 236 - Added RMU_ResetControl for BU reset flag
<> 144:ef7eb2e8f9f7 237 - Added some missing features to EMU for back up domain and EM4 support
<> 144:ef7eb2e8f9f7 238 - ADC TimebaseCalc(), Giant/Leopard Gecko have max 5 bits in TIMEBASE field
<> 144:ef7eb2e8f9f7 239 - Removed EMU Backup Power Domain threshold setings from EMU_BUPDInit, added
<> 144:ef7eb2e8f9f7 240 EMU_BUThresRangeSet() and EMU_BUThresholdSet() API calls. Threshold values
<> 144:ef7eb2e8f9f7 241 are factory calibrated and should not usually be overridden by the user.
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 2.3.2:
<> 144:ef7eb2e8f9f7 244 - Added Tiny Gecko and Giant Gecko support in RMU for new reset causes
<> 144:ef7eb2e8f9f7 245 - CMU_ClockFreqGet will now report correct clock rates if HFLE is set (/4)
<> 144:ef7eb2e8f9f7 246 - Added Giant Gecko specific MSC_MassErase(), erase entire flash
<> 144:ef7eb2e8f9f7 247 - Added Giant Gecko specific MSC_BusStrategy (inline) function
<> 144:ef7eb2e8f9f7 248 - MSC_Init() will now configure TIMEBASE correctly according to AUXHFRCO clock
<> 144:ef7eb2e8f9f7 249 rate for Tiny Gecko and Giant Gecko
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 2.3.0:
<> 144:ef7eb2e8f9f7 252 - USART - Added USART_InitPrsTrigger to initialize USART PRS triggered
<> 144:ef7eb2e8f9f7 253 transmissions.
<> 144:ef7eb2e8f9f7 254 - CMU - numerous updates, now supports full clock tree of Giant/Tiny Gecko
<> 144:ef7eb2e8f9f7 255 - CMU_ClockDivSet/Get will now use real dividend and not logarithmic values
<> 144:ef7eb2e8f9f7 256 as earlier. Prior enumerated values have been kept for backward compatibility.
<> 144:ef7eb2e8f9f7 257 - Added support for CMU HFLE and DIV4 factor for core clock for LE
<> 144:ef7eb2e8f9f7 258 peripherals
<> 144:ef7eb2e8f9f7 259 - Added support for alternate LCD segment animation range for Giant Gecko
<> 144:ef7eb2e8f9f7 260 - Fixed bug: Don't enable VCMP low power reference until after warm up,
<> 144:ef7eb2e8f9f7 261 allow biasprog value of 0 in VCMP_Init()
<> 144:ef7eb2e8f9f7 262 - Added support for ALTMAP (256MB address map) in EBI_BankAddress()
<> 144:ef7eb2e8f9f7 263 - TIMER_Init() will now reset CNT value
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 2.2.2:
<> 144:ef7eb2e8f9f7 266 - Added DAC0 channel 0 and 1 to ACMP for Tiny and Giant devices
<> 144:ef7eb2e8f9f7 267 - Fixed bug in CMU for MSC WAITSTATE configuration, leading to too high wait
<> 144:ef7eb2e8f9f7 268 states depending on clock rate
<> 144:ef7eb2e8f9f7 269 - Fixed bug in CMU for UART1 clock enable
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 2.2.1:
<> 144:ef7eb2e8f9f7 272 - UART_Reset() and LEUART_Reset() will now reset ROUTE register as well, this
<> 144:ef7eb2e8f9f7 273 will mean GPIO pins will not be driven after this call. Take care to ensure
<> 144:ef7eb2e8f9f7 274 that GPIO ROUTE register is configured after calls to *UART_Init*Sync
<> 144:ef7eb2e8f9f7 275 - Fixed problems with EFM_ASSERT when using UART in USART API
<> 144:ef7eb2e8f9f7 276 - Added Giant Gecko support for EBI (new modes and TFT direct drive)
<> 144:ef7eb2e8f9f7 277 - Added Giant Gecko support for CMU 2 WAIT STATES, and I2C1
<> 144:ef7eb2e8f9f7 278 - Added Giant Gecko support for UART1 in CMU
<> 144:ef7eb2e8f9f7 279 - Added Giant Gecko support for DMA LOOP and 2D Copy operations
<> 144:ef7eb2e8f9f7 280
<> 144:ef7eb2e8f9f7 281 2.1.0:
<> 144:ef7eb2e8f9f7 282 - EMU_Restore will now disable HFRCO if it was not enabled when entering
<> 144:ef7eb2e8f9f7 283 an Energy Mode
<> 144:ef7eb2e8f9f7 284 - Run time changes only applies to Gecko devices, filter out Tiny and Giant
<> 144:ef7eb2e8f9f7 285 for CHIP_Init();
<> 144:ef7eb2e8f9f7 286 - Added const specificers to various initialization structures, to ensure
<> 144:ef7eb2e8f9f7 287 they can reside in flash instead of SRAM
<> 144:ef7eb2e8f9f7 288 - Bugfix in efm32_i2c.c, keep returning i2cTransferInProgress until done
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 2.0.1:
<> 144:ef7eb2e8f9f7 291 - Changed enum OPAMP_PosSel_TypeDef. Enum value opaPosSelOpaIn changed from
<> 144:ef7eb2e8f9f7 292 DAC_OPA0MUX_POSSEL_OPA1IN to DAC_OPA0MUX_POSSEL_OPA0INP.
<> 144:ef7eb2e8f9f7 293 - Bugfix in efm32_lesense.h, LESENSE_ChClk_TypeDef now contains unshifted
<> 144:ef7eb2e8f9f7 294 values, fixed the implementation in efm32_lesense.c where the bug prevented
<> 144:ef7eb2e8f9f7 295 the sampleClk to be set to AUXHFRCO.
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 2.0.0:
<> 144:ef7eb2e8f9f7 298 - USART_Init-functions now calls USART_Reset() which will also disable/reset
<> 144:ef7eb2e8f9f7 299 interrupt
<> 144:ef7eb2e8f9f7 300 - USART_BaudrateSyncSet() now asserts on invalid oversample configuration
<> 144:ef7eb2e8f9f7 301 - Added initialization of parity bit in LEUART_Init()
<> 144:ef7eb2e8f9f7 302 - Added Tiny Gecko support for CMU, ULFRCO, LESENSE clocks and continuous
<> 144:ef7eb2e8f9f7 303 calibration
<> 144:ef7eb2e8f9f7 304 - Added Tiny Gecko support for GPIO, EM4 pin retention and wake up support
<> 144:ef7eb2e8f9f7 305 - Added Tiny Gecko support for I2S, SPI auto TX mode on USART
<> 144:ef7eb2e8f9f7 306 - Added Tiny Gecko support for CACHE mesasurements for MSC module
<> 144:ef7eb2e8f9f7 307 - Added Tiny Gecko support for LCD module (with no HIGH segment registers)
<> 144:ef7eb2e8f9f7 308 - Added Tiny Gecko support for TIMER, PWM 2x, (DT lock not supported)
<> 144:ef7eb2e8f9f7 309 - Added Tiny Gecko support for LESENSE module
<> 144:ef7eb2e8f9f7 310 - Added Tiny Gecko support for PRS input in PCNT
<> 144:ef7eb2e8f9f7 311 - Added Tiny Gecko support for async signals in PRS, PRS_SourceAsyncSignalSet()
<> 144:ef7eb2e8f9f7 312 - Initial support for some Giant Gecko features, where overlapping with Tiny
<> 144:ef7eb2e8f9f7 313 - Removed LPFEN / LPFREQ support from DAC
<> 144:ef7eb2e8f9f7 314 - Fixed comments around interrupt functions, making it clear it is bitwise
<> 144:ef7eb2e8f9f7 315 logical or interrupt flags
<> 144:ef7eb2e8f9f7 316 - Fixed PCNT initialization for external clock configurations, making sure
<> 144:ef7eb2e8f9f7 317 config is synchronized at startup to 3 clocks. Note fix only works for
<> 144:ef7eb2e8f9f7 318 >revC EFM32G devices.
<> 144:ef7eb2e8f9f7 319 - Fixed efm32_cmu.c, EFM_ASSERT statement for LEUART clock div logic was
<> 144:ef7eb2e8f9f7 320 inverted
<> 144:ef7eb2e8f9f7 321 - Fixed ADC_InitScan, PRSSEL shift value corrected
<> 144:ef7eb2e8f9f7 322 - Fixed CMU_ClockFreqGet for devices that do not have I2C
<> 144:ef7eb2e8f9f7 323 - Fixed I2C_TransferInit for devices with more than one I2C-bus (Giant Gecko)
<> 144:ef7eb2e8f9f7 324 - Changed ACMP_Disable() implementation, now only disables the ACMP instance
<> 144:ef7eb2e8f9f7 325 by clearing the EN bit in the CTRL register
<> 144:ef7eb2e8f9f7 326 - Removed ACMP_DisableNoReset() function
<> 144:ef7eb2e8f9f7 327 - Fixed ACMP_Init(), removed automatic enabling, added new structure member
<> 144:ef7eb2e8f9f7 328 "enaReq" for ACMP_Init_TypeDef to control, fixed the EFM_ASSERT of the
<> 144:ef7eb2e8f9f7 329 biasprog parameter
<> 144:ef7eb2e8f9f7 330 - Added default configuration macro ACMP_INIT_DEFAULT for ACMP_Init_TypeDef
<> 144:ef7eb2e8f9f7 331 - Fixed ACMP_CapsenseInit(), removed automatic enabling, added new structure member
<> 144:ef7eb2e8f9f7 332 "enaReq" for ACMP_CapsenseInit_TypeDef to control, fixed the EFM_ASSERT of
<> 144:ef7eb2e8f9f7 333 the biasprog parameter
<> 144:ef7eb2e8f9f7 334 - Changed the name of the default configuration macro for
<> 144:ef7eb2e8f9f7 335 ACMP_CapsenseInit_TypeDef to ACMP_CAPSENSE_INIT_DEFAULT
<> 144:ef7eb2e8f9f7 336 - Added RTC_Reset and RTC_CounterReset functions for RTC
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338 1.3.0:
<> 144:ef7eb2e8f9f7 339 - MSC is automatically enabled/disabled when using the MSC API. This saves
<> 144:ef7eb2e8f9f7 340 power, and reduces errors due to not calling MSC_Init().
<> 144:ef7eb2e8f9f7 341 - Added API for controlling Cortex-M3 MPU (memory protection unit)
<> 144:ef7eb2e8f9f7 342 - Adjusted bit fields to comply with latest CMSIS release, see EFM_CMSIS
<> 144:ef7eb2e8f9f7 343 changes file for details
<> 144:ef7eb2e8f9f7 344 - Fixed issue with bit mask clearing in ACMP
<> 144:ef7eb2e8f9f7 345 - Functions ACMP_Enable and ACMP_DisableNoReset added
<> 144:ef7eb2e8f9f7 346 - Added comment about rev.C chips in PCNT, CMD_LTOPBIM not neccessary any more
<> 144:ef7eb2e8f9f7 347 - Added missing instance validity asserts to peripherals (ACMP, LEUART, USART)
<> 144:ef7eb2e8f9f7 348 - Fixed UART0 check in CMU_ClockFreqGet()
<> 144:ef7eb2e8f9f7 349 - Fixed command sync for PCNT before setting TOPB value during init
<> 144:ef7eb2e8f9f7 350 - Fixed instance validity check macro in PCNT
<> 144:ef7eb2e8f9f7 351 - Fixed TIMER_Reset() removed write to unimplemented timer channel registers
<> 144:ef7eb2e8f9f7 352 - Fixed EFM_ASSERT statements in ACMP, VCMP
<> 144:ef7eb2e8f9f7 353 - General code style update: added missing curly braces, default cases, etc.
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 1.2.1:
<> 144:ef7eb2e8f9f7 356 - Feature complete efm32lib, now also includes peripheral API for modules
<> 144:ef7eb2e8f9f7 357 AES,PCNT,MSC,ACMP,VCMP,LCD,EBI
<> 144:ef7eb2e8f9f7 358 - Fixed _TIMER_CC_CTRL_ICEDGE flags for correct timer configuration
<> 144:ef7eb2e8f9f7 359 - Fixed ADC calibration of Single and Scan mode of operation
<> 144:ef7eb2e8f9f7 360 - Added PCNT (ChipRev A/B PCNT0 errata NOT supported) and AES support
<> 144:ef7eb2e8f9f7 361 - Fixed conditional inclusion in efm32_emu.h
<> 144:ef7eb2e8f9f7 362 - Fixed code for LEUART0 for devices with multiple LEUARTs.
<> 144:ef7eb2e8f9f7 363 - Fixed incorrect setting of DOUT for GPIO configuration
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 1.1.4
<> 144:ef7eb2e8f9f7 366 - Fix for TIMER_INIT_DEFAULT
<> 144:ef7eb2e8f9f7 367
<> 144:ef7eb2e8f9f7 368 1.1.3:
<> 144:ef7eb2e8f9f7 369 - Added ADC, DAC, LETIMER, PRS, TIMER (except DTI) support
<> 144:ef7eb2e8f9f7 370 - Added utility for fetching chip revision (efm32_system.c/h)
<> 144:ef7eb2e8f9f7 371 - Removed RTC instance ref in API, only one RTC will be supported
<> 144:ef7eb2e8f9f7 372 (Affects also define in efm32_cmu.h)
<> 144:ef7eb2e8f9f7 373 - Added default init struct macros for LEUART, USART
<> 144:ef7eb2e8f9f7 374 - Added msbf parameter in USART synchronous init struct, USART_InitSync_TypeDef.
<> 144:ef7eb2e8f9f7 375 - Updated reset for I2C, USART, LEUART to also reset IEN register.
<> 144:ef7eb2e8f9f7 376 - Corrected fault in GPIO_PortOutSet()
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 1.1.2:
<> 144:ef7eb2e8f9f7 379 - Corrected minor issues in EMU, EM3 mode when restoring clocks
<> 144:ef7eb2e8f9f7 380 - Corrected RMU reset cause checking
<> 144:ef7eb2e8f9f7 381 - Changed GPIO enumerator symbols to start with gpio (from GPIO_)
<> 144:ef7eb2e8f9f7 382 - Changed CMU and WDOG enum typedefs to start with CMU_/WDOG_ (from cmu/wdog)
<> 144:ef7eb2e8f9f7 383 - Added USART/UART, LEUART, DMA, I2C support
<> 144:ef7eb2e8f9f7 384
<> 144:ef7eb2e8f9f7 385 1.1.1:
<> 144:ef7eb2e8f9f7 386 - First version including support for CMU, DBG, EMU, GPIO, RTC, WDOG