added prescaler for 16 bit pwm in LPC1347 target
Fork of mbed-dev by
targets/hal/TARGET_ONSEMI/TARGET_NCS36510/architecture.h@147:ba84b7dc41a7, 2016-09-10 (annotated)
- Committer:
- JojoS
- Date:
- Sat Sep 10 15:32:04 2016 +0000
- Revision:
- 147:ba84b7dc41a7
- Parent:
- 144:ef7eb2e8f9f7
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /** |
<> | 144:ef7eb2e8f9f7 | 2 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 3 | * @file architecture.h |
<> | 144:ef7eb2e8f9f7 | 4 | * @brief CM3 architecture specific inclusions and defines. |
<> | 144:ef7eb2e8f9f7 | 5 | * @internal |
<> | 144:ef7eb2e8f9f7 | 6 | * @author ON Semiconductor |
<> | 144:ef7eb2e8f9f7 | 7 | * $Rev: $ |
<> | 144:ef7eb2e8f9f7 | 8 | * $Date: $ |
<> | 144:ef7eb2e8f9f7 | 9 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 10 | * @copyright (c) 2012 ON Semiconductor. All rights reserved. |
<> | 144:ef7eb2e8f9f7 | 11 | * ON Semiconductor is supplying this software for use with ON Semiconductor |
<> | 144:ef7eb2e8f9f7 | 12 | * processor based microcontrollers only. |
<> | 144:ef7eb2e8f9f7 | 13 | * |
<> | 144:ef7eb2e8f9f7 | 14 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
<> | 144:ef7eb2e8f9f7 | 15 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
<> | 144:ef7eb2e8f9f7 | 16 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
<> | 144:ef7eb2e8f9f7 | 17 | * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, |
<> | 144:ef7eb2e8f9f7 | 18 | * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
<> | 144:ef7eb2e8f9f7 | 19 | * @endinternal |
<> | 144:ef7eb2e8f9f7 | 20 | * |
<> | 144:ef7eb2e8f9f7 | 21 | * @ingroup bsp |
<> | 144:ef7eb2e8f9f7 | 22 | */ |
<> | 144:ef7eb2e8f9f7 | 23 | |
<> | 144:ef7eb2e8f9f7 | 24 | #ifndef ARCHITECTURE_H_ |
<> | 144:ef7eb2e8f9f7 | 25 | #define ARCHITECTURE_H_ |
<> | 144:ef7eb2e8f9f7 | 26 | |
<> | 144:ef7eb2e8f9f7 | 27 | /************************************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 28 | * * |
<> | 144:ef7eb2e8f9f7 | 29 | * Header files * |
<> | 144:ef7eb2e8f9f7 | 30 | * * |
<> | 144:ef7eb2e8f9f7 | 31 | *************************************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 32 | |
<> | 144:ef7eb2e8f9f7 | 33 | //#include <ncs36510.h> |
<> | 144:ef7eb2e8f9f7 | 34 | //#include <system_ncs36510.h> |
<> | 144:ef7eb2e8f9f7 | 35 | //#include <core_cm3.h> |
<> | 144:ef7eb2e8f9f7 | 36 | |
<> | 144:ef7eb2e8f9f7 | 37 | #include "NCS36510.h" |
<> | 144:ef7eb2e8f9f7 | 38 | #include "system_NCS36510.h" |
<> | 144:ef7eb2e8f9f7 | 39 | #include "core_cm3.h" |
<> | 144:ef7eb2e8f9f7 | 40 | #include "cmsis.h" |
<> | 144:ef7eb2e8f9f7 | 41 | |
<> | 144:ef7eb2e8f9f7 | 42 | |
<> | 144:ef7eb2e8f9f7 | 43 | /************************************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 44 | * * |
<> | 144:ef7eb2e8f9f7 | 45 | * Symbolic Constants * |
<> | 144:ef7eb2e8f9f7 | 46 | * * |
<> | 144:ef7eb2e8f9f7 | 47 | *************************************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 48 | |
<> | 144:ef7eb2e8f9f7 | 49 | /* Interrupt Control and State Register (0xE000ED04) |
<> | 144:ef7eb2e8f9f7 | 50 | * 31 NMIPENDSET R/W 0 NMI pended |
<> | 144:ef7eb2e8f9f7 | 51 | * 28 PENDSVSET R/W 0 Write 1 to pend system call; Read value |
<> | 144:ef7eb2e8f9f7 | 52 | * indicates pending status |
<> | 144:ef7eb2e8f9f7 | 53 | * 27 PENDSVCLR W 0 Write 1 to clear PendSV pending status |
<> | 144:ef7eb2e8f9f7 | 54 | * 26 PENDSTSET R/W 0 Write 1 to pend Systick exception; Read |
<> | 144:ef7eb2e8f9f7 | 55 | * value indicates pending status |
<> | 144:ef7eb2e8f9f7 | 56 | * 25 PENDSTCLR W 0 Write 1 to clear Systick pending status |
<> | 144:ef7eb2e8f9f7 | 57 | * 23 ISRPREEMPT R 0 Indicate that a pending interrupt is going |
<> | 144:ef7eb2e8f9f7 | 58 | * to be active in next step (for debug) |
<> | 144:ef7eb2e8f9f7 | 59 | * 22 ISRPENDING R 0 External interrupt pending (excluding |
<> | 144:ef7eb2e8f9f7 | 60 | * system exceptions such as NMI for |
<> | 144:ef7eb2e8f9f7 | 61 | * fault) |
<> | 144:ef7eb2e8f9f7 | 62 | * 21:12 VECTPENDING R 0 Pending ISR number |
<> | 144:ef7eb2e8f9f7 | 63 | * 11 RETTOBASE R 0 Set to 1 when the processor is running |
<> | 144:ef7eb2e8f9f7 | 64 | * an exception handler and will return to |
<> | 144:ef7eb2e8f9f7 | 65 | * thread level if interrupt return and no |
<> | 144:ef7eb2e8f9f7 | 66 | * other exceptions pending |
<> | 144:ef7eb2e8f9f7 | 67 | * 9:0 VECTACTIVE R 0 Current running interrupt service routine |
<> | 144:ef7eb2e8f9f7 | 68 | */ |
<> | 144:ef7eb2e8f9f7 | 69 | #define RUNNING_IN_ISR (((SCB->ICSR & 0x3FF) > 0 ) ? 1 : 0) |
<> | 144:ef7eb2e8f9f7 | 70 | |
<> | 144:ef7eb2e8f9f7 | 71 | #endif /* ARCHITECTURE_H_ */ |