Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Maxim/TARGET_MAX32620/spi_api.c@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*******************************************************************************
<> 144:ef7eb2e8f9f7 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 144:ef7eb2e8f9f7 5 * copy of this software and associated documentation files (the "Software"),
<> 144:ef7eb2e8f9f7 6 * to deal in the Software without restriction, including without limitation
<> 144:ef7eb2e8f9f7 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 144:ef7eb2e8f9f7 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 144:ef7eb2e8f9f7 9 * Software is furnished to do so, subject to the following conditions:
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * The above copyright notice and this permission notice shall be included
<> 144:ef7eb2e8f9f7 12 * in all copies or substantial portions of the Software.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 144:ef7eb2e8f9f7 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 144:ef7eb2e8f9f7 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 144:ef7eb2e8f9f7 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 144:ef7eb2e8f9f7 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 144:ef7eb2e8f9f7 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * Except as contained in this notice, the name of Maxim Integrated
<> 144:ef7eb2e8f9f7 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 144:ef7eb2e8f9f7 24 * Products, Inc. Branding Policy.
<> 144:ef7eb2e8f9f7 25 *
<> 144:ef7eb2e8f9f7 26 * The mere transfer of this software does not imply any licenses
<> 144:ef7eb2e8f9f7 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 144:ef7eb2e8f9f7 28 * trademarks, maskwork rights, or any other form of intellectual
<> 144:ef7eb2e8f9f7 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 144:ef7eb2e8f9f7 30 * ownership rights.
<> 144:ef7eb2e8f9f7 31 *******************************************************************************
<> 144:ef7eb2e8f9f7 32 */
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #include <string.h>
<> 144:ef7eb2e8f9f7 35 #include "mbed_assert.h"
<> 144:ef7eb2e8f9f7 36 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 37 #include "spi_api.h"
<> 144:ef7eb2e8f9f7 38 #include "spi_multi_api.h"
<> 144:ef7eb2e8f9f7 39 #include "pinmap.h"
<> 144:ef7eb2e8f9f7 40 #include "ioman_regs.h"
<> 144:ef7eb2e8f9f7 41 #include "clkman_regs.h"
<> 144:ef7eb2e8f9f7 42 #include "PeripheralPins.h"
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 #define DEFAULT_CHAR 8
<> 144:ef7eb2e8f9f7 45 #define DEFAULT_MODE 0
<> 144:ef7eb2e8f9f7 46 #define DEFAULT_FREQ 1000000
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 // BYTE maximums for FIFO and page writes; FIFO depth spec'd as 16-bit words
<> 144:ef7eb2e8f9f7 49 #define SPI_MAX_BYTE_LEN (MXC_CFG_SPI_FIFO_DEPTH * 2)
<> 144:ef7eb2e8f9f7 50 #define SPI_MAX_PAGE_LEN (MXC_CFG_SPI_FIFO_DEPTH * 2)
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 #if DEVICE_SPI_ASYNCH
<> 144:ef7eb2e8f9f7 53 // Instance references for async transactions
<> 144:ef7eb2e8f9f7 54 static struct spi_s *state[MXC_CFG_SPI_INSTANCES] = {NULL};
<> 144:ef7eb2e8f9f7 55 #endif
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 //******************************************************************************
<> 144:ef7eb2e8f9f7 58 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
<> 144:ef7eb2e8f9f7 59 {
<> 144:ef7eb2e8f9f7 60 // Make sure pins are pointing to the same SPI instance
<> 144:ef7eb2e8f9f7 61 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
<> 144:ef7eb2e8f9f7 62 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
<> 144:ef7eb2e8f9f7 63 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
<> 144:ef7eb2e8f9f7 64 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
<> 144:ef7eb2e8f9f7 67 SPIName spi_cntl;
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 // Give the application the option to manually control Slave Select
<> 144:ef7eb2e8f9f7 70 if ((SPIName)spi_ssel != (SPIName)NC) {
<> 144:ef7eb2e8f9f7 71 spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
<> 144:ef7eb2e8f9f7 72 // Slave select is currently limited to slave select zero. If others are
<> 144:ef7eb2e8f9f7 73 // to be supported a function to map PinName to a value suitable for use
<> 144:ef7eb2e8f9f7 74 // in mstr_cfg.slave_sel will be required.
<> 144:ef7eb2e8f9f7 75 obj->spi.ssel = 0;
<> 144:ef7eb2e8f9f7 76 } else {
<> 144:ef7eb2e8f9f7 77 spi_cntl = spi_sclk;
<> 144:ef7eb2e8f9f7 78 obj->spi.ssel = -1;
<> 144:ef7eb2e8f9f7 79 }
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 SPIName spi = (SPIName)pinmap_merge(spi_data, spi_cntl);
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 MBED_ASSERT((SPIName)spi != (SPIName)NC);
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 // Set the obj pointer to the proper SPI Instance
<> 144:ef7eb2e8f9f7 86 obj->spi.spi = (mxc_spi_regs_t*)spi;
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 // Set the SPI index and FIFOs
<> 144:ef7eb2e8f9f7 89 obj->spi.index = MXC_SPI_GET_IDX(obj->spi.spi);
<> 144:ef7eb2e8f9f7 90 obj->spi.fifo = MXC_SPI_GET_SPI_FIFO(obj->spi.index);
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 // Configure the pins
<> 144:ef7eb2e8f9f7 93 pinmap_pinout(mosi, PinMap_SPI_MOSI);
<> 144:ef7eb2e8f9f7 94 pinmap_pinout(miso, PinMap_SPI_MISO);
<> 144:ef7eb2e8f9f7 95 pinmap_pinout(sclk, PinMap_SPI_SCLK);
<> 144:ef7eb2e8f9f7 96 pinmap_pinout(ssel, PinMap_SPI_SSEL);
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 #if DEVICE_SPI_ASYNCH
<> 144:ef7eb2e8f9f7 99 // Configure default page size; size is known to async interface
<> 144:ef7eb2e8f9f7 100 obj->spi.spi->mstr_cfg = (obj->spi.spi->mstr_cfg & ~MXC_F_SPI_MSTR_CFG_PAGE_SIZE) | MXC_S_SPI_MSTR_CFG_PAGE_32B;
<> 144:ef7eb2e8f9f7 101 #endif
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 // Enable SPI and FIFOs
<> 144:ef7eb2e8f9f7 104 obj->spi.spi->gen_ctrl = (MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN |
<> 144:ef7eb2e8f9f7 105 MXC_F_SPI_GEN_CTRL_TX_FIFO_EN |
<> 144:ef7eb2e8f9f7 106 MXC_F_SPI_GEN_CTRL_RX_FIFO_EN );
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 obj->spi.sclk = sclk; // save the sclk PinName in the object as a key for Quad SPI pin mapping lookup
<> 144:ef7eb2e8f9f7 109 spi_master_width(obj, 0); // default this for Single SPI communications
<> 144:ef7eb2e8f9f7 110 }
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 //******************************************************************************
<> 144:ef7eb2e8f9f7 113 void spi_format(spi_t *obj, int bits, int mode, int slave)
<> 144:ef7eb2e8f9f7 114 {
<> 144:ef7eb2e8f9f7 115 // Check the validity of the inputs
<> 144:ef7eb2e8f9f7 116 MBED_ASSERT(((bits >= 1) && (bits <= 32)) && ((mode >= 0) && (mode <= 3)));
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 // Only supports master mode
<> 144:ef7eb2e8f9f7 119 MBED_ASSERT(!slave);
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 // Save formatting data
<> 144:ef7eb2e8f9f7 122 obj->spi.bits = bits;
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 // Set the mode
<> 144:ef7eb2e8f9f7 125 MXC_SET_FIELD(&obj->spi.spi->mstr_cfg, MXC_F_SPI_MSTR_CFG_SPI_MODE, mode << MXC_F_SPI_MSTR_CFG_SPI_MODE_POS);
<> 144:ef7eb2e8f9f7 126 }
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 //******************************************************************************
<> 144:ef7eb2e8f9f7 129 void spi_frequency(spi_t *obj, int hz)
<> 144:ef7eb2e8f9f7 130 {
<> 144:ef7eb2e8f9f7 131 // Maximum frequency is half the system frequency
<> 144:ef7eb2e8f9f7 132 MBED_ASSERT((unsigned int)hz <= (SystemCoreClock / 2));
<> 144:ef7eb2e8f9f7 133 unsigned clocks = ((SystemCoreClock / 2) / hz);
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 // Figure out the divider ratio
<> 144:ef7eb2e8f9f7 136 int clk_div = 1;
<> 144:ef7eb2e8f9f7 137 while (clk_div < 10) {
<> 144:ef7eb2e8f9f7 138 if (clocks < 0x10) {
<> 144:ef7eb2e8f9f7 139 break;
<> 144:ef7eb2e8f9f7 140 }
<> 144:ef7eb2e8f9f7 141 clk_div++;
<> 144:ef7eb2e8f9f7 142 clocks = clocks >> 1;
<> 144:ef7eb2e8f9f7 143 }
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 // Turn on the SPI clock
<> 144:ef7eb2e8f9f7 146 if (obj->spi.index == 0) {
<> 144:ef7eb2e8f9f7 147 MXC_CLKMAN->sys_clk_ctrl_11_spi0 = clk_div;
<> 144:ef7eb2e8f9f7 148 } else if (obj->spi.index == 1) {
<> 144:ef7eb2e8f9f7 149 MXC_CLKMAN->sys_clk_ctrl_12_spi1 = clk_div;
<> 144:ef7eb2e8f9f7 150 } else if (obj->spi.index == 2) {
<> 144:ef7eb2e8f9f7 151 MXC_CLKMAN->sys_clk_ctrl_13_spi2 = clk_div;
<> 144:ef7eb2e8f9f7 152 } else {
<> 144:ef7eb2e8f9f7 153 MBED_ASSERT(0);
<> 144:ef7eb2e8f9f7 154 }
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 // Set the number of clocks to hold sclk high and low
<> 144:ef7eb2e8f9f7 157 MXC_SET_FIELD(&obj->spi.spi->mstr_cfg, (MXC_F_SPI_MSTR_CFG_SCK_HI_CLK | MXC_F_SPI_MSTR_CFG_SCK_LO_CLK),
<> 144:ef7eb2e8f9f7 158 ((clocks << MXC_F_SPI_MSTR_CFG_SCK_HI_CLK_POS) | (clocks << MXC_F_SPI_MSTR_CFG_SCK_LO_CLK_POS)));
<> 144:ef7eb2e8f9f7 159 }
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 //******************************************************************************
<> 144:ef7eb2e8f9f7 162 void spi_master_width(spi_t *obj, SpiWidth width)
<> 144:ef7eb2e8f9f7 163 {
<> 144:ef7eb2e8f9f7 164 // Save the width to be used in the SPI header
<> 144:ef7eb2e8f9f7 165 switch (width) {
<> 144:ef7eb2e8f9f7 166 case WidthSingle:
<> 144:ef7eb2e8f9f7 167 obj->spi.width = MXC_S_SPI_FIFO_WIDTH_SINGLE;
<> 144:ef7eb2e8f9f7 168 break;
<> 144:ef7eb2e8f9f7 169 case WidthDual:
<> 144:ef7eb2e8f9f7 170 obj->spi.width = MXC_S_SPI_FIFO_WIDTH_DUAL;
<> 144:ef7eb2e8f9f7 171 break;
<> 144:ef7eb2e8f9f7 172 case WidthQuad:
<> 144:ef7eb2e8f9f7 173 obj->spi.width = MXC_S_SPI_FIFO_WIDTH_QUAD;
<> 144:ef7eb2e8f9f7 174 // do pin mapping for SDIO[2] and SDIO[3] if Quad SPI is selected
<> 144:ef7eb2e8f9f7 175 pinmap_pinout(obj->spi.sclk, PinMap_SPI_QUAD);
<> 144:ef7eb2e8f9f7 176 break;
<> 144:ef7eb2e8f9f7 177 default:
<> 144:ef7eb2e8f9f7 178 MBED_ASSERT(0);
<> 144:ef7eb2e8f9f7 179 }
<> 144:ef7eb2e8f9f7 180 }
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 //******************************************************************************
<> 144:ef7eb2e8f9f7 183 /** Performs a master write or read transaction
<> 144:ef7eb2e8f9f7 184 *
<> 144:ef7eb2e8f9f7 185 * @param[in] obj The SPI peripheral to use for sending
<> 144:ef7eb2e8f9f7 186 * @param[in] value The value to send
<> 144:ef7eb2e8f9f7 187 * @param[in] direction Direction of the transaction, TX, RX or both
<> 144:ef7eb2e8f9f7 188 * @return Returns the value received during send
<> 144:ef7eb2e8f9f7 189 */
<> 144:ef7eb2e8f9f7 190 static int spi_master_transaction(spi_t *obj, int value, uint32_t direction)
<> 144:ef7eb2e8f9f7 191 {
<> 144:ef7eb2e8f9f7 192 int bits;
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 // Create the header
<> 144:ef7eb2e8f9f7 195 uint16_t header = (direction | // direction based on SPI object
<> 144:ef7eb2e8f9f7 196 MXC_S_SPI_FIFO_UNIT_BITS | // unit size
<> 144:ef7eb2e8f9f7 197 ((obj->spi.bits == 32) ? 0 : obj->spi.bits << MXC_F_SPI_FIFO_SIZE_POS) | // Number of units
<> 144:ef7eb2e8f9f7 198 obj->spi.width | // I/O width
<> 144:ef7eb2e8f9f7 199 ((obj->spi.ssel == -1) ? 0 : 1 << MXC_F_SPI_FIFO_DASS_POS));
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 // Send the message header
<> 144:ef7eb2e8f9f7 202 *obj->spi.fifo->trans_16 = header;
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 // Send the data
<> 144:ef7eb2e8f9f7 205 if (obj->spi.bits < 17) {
<> 144:ef7eb2e8f9f7 206 *obj->spi.fifo->trans_16 = (uint16_t)value;
<> 144:ef7eb2e8f9f7 207 } else {
<> 144:ef7eb2e8f9f7 208 *obj->spi.fifo->trans_32 = (uint32_t)value;
<> 144:ef7eb2e8f9f7 209 }
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 // Get the data
<> 144:ef7eb2e8f9f7 212 bits = obj->spi.bits;
<> 144:ef7eb2e8f9f7 213 int result = 0;
<> 144:ef7eb2e8f9f7 214 int i = 0;
<> 144:ef7eb2e8f9f7 215 while (bits > 0) {
<> 144:ef7eb2e8f9f7 216 // Wait for data
<> 144:ef7eb2e8f9f7 217 while (((obj->spi.spi->fifo_ctrl & MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED)
<> 144:ef7eb2e8f9f7 218 >> MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED_POS) < 1);
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 result |= (*obj->spi.fifo->rslts_8 << (i++*8));
<> 144:ef7eb2e8f9f7 221 bits-=8;
<> 144:ef7eb2e8f9f7 222 }
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 return result;
<> 144:ef7eb2e8f9f7 225 }
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 //******************************************************************************
<> 144:ef7eb2e8f9f7 228 int spi_master_write(spi_t *obj, int value)
<> 144:ef7eb2e8f9f7 229 {
<> 144:ef7eb2e8f9f7 230 // set the fifo direction for full duplex, TX and RX simultaneously
<> 144:ef7eb2e8f9f7 231 return spi_master_transaction(obj, value, MXC_S_SPI_FIFO_DIR_BOTH);
<> 144:ef7eb2e8f9f7 232 }
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 //******************************************************************************
<> 144:ef7eb2e8f9f7 235 int spi_master_read(spi_t *obj)
<> 144:ef7eb2e8f9f7 236 {
<> 144:ef7eb2e8f9f7 237 return spi_master_transaction(obj, 0xFF, MXC_S_SPI_FIFO_DIR_RX);
<> 144:ef7eb2e8f9f7 238 }
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 //******************************************************************************
<> 144:ef7eb2e8f9f7 241 // spi_busy() is part of the synchronous API, it is not used by the asynchronous API.
<> 144:ef7eb2e8f9f7 242 int spi_busy(spi_t *obj)
<> 144:ef7eb2e8f9f7 243 {
<> 144:ef7eb2e8f9f7 244 return !(obj->spi.spi->intfl & MXC_F_SPI_INTFL_TX_READY);
<> 144:ef7eb2e8f9f7 245 }
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 #if DEVICE_SPI_ASYNCH
<> 144:ef7eb2e8f9f7 248 //******************************************************************************
<> 144:ef7eb2e8f9f7 249 static uint32_t spi_master_read_rxfifo(mxc_spi_regs_t *spim, mxc_spi_fifo_regs_t *fifo, uint8_t *data, uint32_t len)
<> 144:ef7eb2e8f9f7 250 {
<> 144:ef7eb2e8f9f7 251 uint32_t num = 0;
<> 144:ef7eb2e8f9f7 252 uint32_t avail = ((spim->fifo_ctrl & MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED) >> MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED_POS);
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 // Get data from the RXFIFO
<> 144:ef7eb2e8f9f7 255 while (avail && (len - num)) {
<> 144:ef7eb2e8f9f7 256 // Save data from the RXFIFO
<> 144:ef7eb2e8f9f7 257 if ((avail >= 4) && ((len - num) >= 4)) {
<> 144:ef7eb2e8f9f7 258 uint32_t temp = *fifo->rslts_32;
<> 144:ef7eb2e8f9f7 259 data[num++] = temp;
<> 144:ef7eb2e8f9f7 260 data[num++] = temp >> 8;
<> 144:ef7eb2e8f9f7 261 data[num++] = temp >> 16;
<> 144:ef7eb2e8f9f7 262 data[num++] = temp >> 24;
<> 144:ef7eb2e8f9f7 263 avail -= 4;
<> 144:ef7eb2e8f9f7 264 } else if ((avail >= 2) && ((len - num) >= 2)) {
<> 144:ef7eb2e8f9f7 265 uint16_t temp = *fifo->rslts_16;
<> 144:ef7eb2e8f9f7 266 data[num++] = temp;
<> 144:ef7eb2e8f9f7 267 data[num++] = temp >> 8;
<> 144:ef7eb2e8f9f7 268 avail -= 2;
<> 144:ef7eb2e8f9f7 269 } else {
<> 144:ef7eb2e8f9f7 270 data[num++] = *fifo->rslts_8;
<> 144:ef7eb2e8f9f7 271 avail--;
<> 144:ef7eb2e8f9f7 272 }
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 // Check to see if there is more data in the FIFO
<> 144:ef7eb2e8f9f7 275 if (avail == 0) {
<> 144:ef7eb2e8f9f7 276 avail = ((spim->fifo_ctrl & MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED) >> MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED_POS);
<> 144:ef7eb2e8f9f7 277 }
<> 144:ef7eb2e8f9f7 278 }
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 return num;
<> 144:ef7eb2e8f9f7 281 }
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 //******************************************************************************
<> 144:ef7eb2e8f9f7 284 static uint32_t spi_master_transfer_handler(spi_t *obj)
<> 144:ef7eb2e8f9f7 285 {
<> 144:ef7eb2e8f9f7 286 uint8_t read;
<> 144:ef7eb2e8f9f7 287 uint8_t write;
<> 144:ef7eb2e8f9f7 288 uint16_t header;
<> 144:ef7eb2e8f9f7 289 uint32_t pages;
<> 144:ef7eb2e8f9f7 290 uint32_t bytes;
<> 144:ef7eb2e8f9f7 291 uint32_t inten;
<> 144:ef7eb2e8f9f7 292 unsigned remain;
<> 144:ef7eb2e8f9f7 293 unsigned bytes_read;
<> 144:ef7eb2e8f9f7 294 unsigned head_rem_temp;
<> 144:ef7eb2e8f9f7 295 unsigned avail;
<> 144:ef7eb2e8f9f7 296 struct spi_s *req = &obj->spi;
<> 144:ef7eb2e8f9f7 297 mxc_spi_regs_t *spim = obj->spi.spi;
<> 144:ef7eb2e8f9f7 298 mxc_spi_fifo_regs_t *fifo = obj->spi.fifo;
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 inten = 0;
<> 144:ef7eb2e8f9f7 301
<> 144:ef7eb2e8f9f7 302 // Figure out if we're reading
<> 144:ef7eb2e8f9f7 303 read = (req->rx_data != NULL) ? 1 : 0;
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 // Figure out if we're writing
<> 144:ef7eb2e8f9f7 306 write = (req->tx_data != NULL) ? 1 : 0;
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 // Read byte from the FIFO if we are reading
<> 144:ef7eb2e8f9f7 309 if (read) {
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 // Read all of the data in the RXFIFO, or until we don't need anymore
<> 144:ef7eb2e8f9f7 312 bytes_read = spi_master_read_rxfifo(spim, fifo, &req->rx_data[req->read_num], (req->len - req->read_num));
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 req->read_num += bytes_read;
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 // Adjust head_rem if we are only reading
<> 144:ef7eb2e8f9f7 317 if (!write && (req->head_rem > 0)) {
<> 144:ef7eb2e8f9f7 318 req->head_rem -= bytes_read;
<> 144:ef7eb2e8f9f7 319 }
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321 // Figure out how many bytes we have left to read
<> 144:ef7eb2e8f9f7 322 if (req->head_rem > 0) {
<> 144:ef7eb2e8f9f7 323 remain = req->head_rem;
<> 144:ef7eb2e8f9f7 324 } else {
<> 144:ef7eb2e8f9f7 325 remain = req->len - req->read_num;
<> 144:ef7eb2e8f9f7 326 }
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 if (remain) {
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 // Set the RX interrupts
<> 144:ef7eb2e8f9f7 331 if (remain > MXC_CFG_SPI_FIFO_DEPTH) {
<> 144:ef7eb2e8f9f7 332 spim->fifo_ctrl = ((spim->fifo_ctrl & ~MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL) |
<> 144:ef7eb2e8f9f7 333 ((MXC_CFG_SPI_FIFO_DEPTH - 2) << MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL_POS));
<> 144:ef7eb2e8f9f7 334 } else {
<> 144:ef7eb2e8f9f7 335 spim->fifo_ctrl = ((spim->fifo_ctrl & ~MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL) |
<> 144:ef7eb2e8f9f7 336 ((remain - 1) << MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL_POS));
<> 144:ef7eb2e8f9f7 337 }
<> 144:ef7eb2e8f9f7 338
<> 144:ef7eb2e8f9f7 339 inten |= MXC_F_SPI_INTEN_RX_FIFO_AF;
<> 144:ef7eb2e8f9f7 340 }
<> 144:ef7eb2e8f9f7 341 }
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343 // Figure out how many bytes we have left to send headers for
<> 144:ef7eb2e8f9f7 344 if (write) {
<> 144:ef7eb2e8f9f7 345 remain = req->len - req->write_num;
<> 144:ef7eb2e8f9f7 346 } else {
<> 144:ef7eb2e8f9f7 347 remain = req->len - req->read_num;
<> 144:ef7eb2e8f9f7 348 }
<> 144:ef7eb2e8f9f7 349
<> 144:ef7eb2e8f9f7 350 // See if we need to send a new header
<> 144:ef7eb2e8f9f7 351 if ((req->head_rem <= 0) && remain) {
<> 144:ef7eb2e8f9f7 352
<> 144:ef7eb2e8f9f7 353 // Set the transaction configuration in the header
<> 144:ef7eb2e8f9f7 354 header = ((write | (read << 1)) << MXC_F_SPI_FIFO_DIR_POS) | (req->width << MXC_F_SPI_FIFO_WIDTH_POS);
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 if (remain >= SPI_MAX_BYTE_LEN) {
<> 144:ef7eb2e8f9f7 357
<> 144:ef7eb2e8f9f7 358 // Send a 32 byte header
<> 144:ef7eb2e8f9f7 359 if (remain == SPI_MAX_BYTE_LEN) {
<> 144:ef7eb2e8f9f7 360
<> 144:ef7eb2e8f9f7 361 header |= (MXC_S_SPI_FIFO_UNIT_BYTES | MXC_F_SPI_FIFO_DASS);
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 // Save the number of bytes we need to write to the FIFO
<> 144:ef7eb2e8f9f7 364 bytes = SPI_MAX_BYTE_LEN;
<> 144:ef7eb2e8f9f7 365
<> 144:ef7eb2e8f9f7 366 } else {
<> 144:ef7eb2e8f9f7 367 // Send in increments of 32 byte pages
<> 144:ef7eb2e8f9f7 368 header |= MXC_S_SPI_FIFO_UNIT_PAGES;
<> 144:ef7eb2e8f9f7 369 pages = remain / SPI_MAX_PAGE_LEN;
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 if (pages >= 32) {
<> 144:ef7eb2e8f9f7 372 // 0 maps to 32 in the header
<> 144:ef7eb2e8f9f7 373 bytes = 32 * SPI_MAX_PAGE_LEN;
<> 144:ef7eb2e8f9f7 374 } else {
<> 144:ef7eb2e8f9f7 375 header |= (pages << MXC_F_SPI_FIFO_SIZE_POS);
<> 144:ef7eb2e8f9f7 376 bytes = pages * SPI_MAX_PAGE_LEN;
<> 144:ef7eb2e8f9f7 377 }
<> 144:ef7eb2e8f9f7 378
<> 144:ef7eb2e8f9f7 379 // Check if this is the last header we will send
<> 144:ef7eb2e8f9f7 380 if ((remain - bytes) == 0) {
<> 144:ef7eb2e8f9f7 381 header |= MXC_F_SPI_FIFO_DASS;
<> 144:ef7eb2e8f9f7 382 }
<> 144:ef7eb2e8f9f7 383 }
<> 144:ef7eb2e8f9f7 384
<> 144:ef7eb2e8f9f7 385 fifo->trans_16[0] = header;
<> 144:ef7eb2e8f9f7 386
<> 144:ef7eb2e8f9f7 387 // Save the number of bytes we need to write to the FIFO
<> 144:ef7eb2e8f9f7 388 req->head_rem = bytes;
<> 144:ef7eb2e8f9f7 389
<> 144:ef7eb2e8f9f7 390 } else {
<> 144:ef7eb2e8f9f7 391 // Send final header with the number of bytes remaining and de-assert the SS at the end of the transaction
<> 144:ef7eb2e8f9f7 392 header |= (MXC_S_SPI_FIFO_UNIT_BYTES | (remain << MXC_F_SPI_FIFO_SIZE_POS) | MXC_F_SPI_FIFO_DASS);
<> 144:ef7eb2e8f9f7 393 fifo->trans_16[0] = header;
<> 144:ef7eb2e8f9f7 394 req->head_rem = remain;
<> 144:ef7eb2e8f9f7 395 }
<> 144:ef7eb2e8f9f7 396 }
<> 144:ef7eb2e8f9f7 397
<> 144:ef7eb2e8f9f7 398 // Put data into the FIFO if we are writing
<> 144:ef7eb2e8f9f7 399 remain = req->len - req->write_num;
<> 144:ef7eb2e8f9f7 400 head_rem_temp = req->head_rem;
<> 144:ef7eb2e8f9f7 401 if (write && head_rem_temp) {
<> 144:ef7eb2e8f9f7 402
<> 144:ef7eb2e8f9f7 403 // Fill the FIFO
<> 144:ef7eb2e8f9f7 404 avail = (MXC_CFG_SPI_FIFO_DEPTH - ((spim->fifo_ctrl & MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED) >> MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED_POS));
<> 144:ef7eb2e8f9f7 405
<> 144:ef7eb2e8f9f7 406 // Use memcpy for everything except the last byte in odd length transactions
<> 144:ef7eb2e8f9f7 407 while ((avail >= 2) && (head_rem_temp >= 2)) {
<> 144:ef7eb2e8f9f7 408
<> 144:ef7eb2e8f9f7 409 unsigned length;
<> 144:ef7eb2e8f9f7 410 if (head_rem_temp < avail) {
<> 144:ef7eb2e8f9f7 411 length = head_rem_temp;
<> 144:ef7eb2e8f9f7 412 } else {
<> 144:ef7eb2e8f9f7 413 length = avail;
<> 144:ef7eb2e8f9f7 414 }
<> 144:ef7eb2e8f9f7 415
<> 144:ef7eb2e8f9f7 416 // Only memcpy even numbers
<> 144:ef7eb2e8f9f7 417 length = ((length / 2) * 2);
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 memcpy((void*)fifo->trans_32, &(req->tx_data[req->write_num]), length);
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 head_rem_temp -= length;
<> 144:ef7eb2e8f9f7 422 req->write_num += length;
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 avail = (MXC_CFG_SPI_FIFO_DEPTH - ((spim->fifo_ctrl & MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED) >> MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED_POS));
<> 144:ef7eb2e8f9f7 425 }
<> 144:ef7eb2e8f9f7 426
<> 144:ef7eb2e8f9f7 427 // Copy the last byte and pad with 0xF0 to not get confused as header
<> 144:ef7eb2e8f9f7 428 if ((avail >= 1) && (head_rem_temp == 1)) {
<> 144:ef7eb2e8f9f7 429
<> 144:ef7eb2e8f9f7 430 // Write the last byte
<> 144:ef7eb2e8f9f7 431 fifo->trans_16[0] = (0xF000 | req->tx_data[req->write_num]);
<> 144:ef7eb2e8f9f7 432
<> 144:ef7eb2e8f9f7 433 avail -= 1;
<> 144:ef7eb2e8f9f7 434 req->write_num += 1;
<> 144:ef7eb2e8f9f7 435 head_rem_temp -= 1;
<> 144:ef7eb2e8f9f7 436 }
<> 144:ef7eb2e8f9f7 437
<> 144:ef7eb2e8f9f7 438 req->head_rem = head_rem_temp;
<> 144:ef7eb2e8f9f7 439 remain = req->len - req->write_num;
<> 144:ef7eb2e8f9f7 440
<> 144:ef7eb2e8f9f7 441 // Set the TX interrupts
<> 144:ef7eb2e8f9f7 442 if (remain) {
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444 // Set the TX FIFO almost empty interrupt if we have to refill
<> 144:ef7eb2e8f9f7 445 spim->fifo_ctrl = ((spim->fifo_ctrl & ~MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL) |
<> 144:ef7eb2e8f9f7 446 ((MXC_CFG_SPI_FIFO_DEPTH - 2) << MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL_POS));
<> 144:ef7eb2e8f9f7 447
<> 144:ef7eb2e8f9f7 448 inten |= MXC_F_SPI_INTEN_TX_FIFO_AE;
<> 144:ef7eb2e8f9f7 449 }
<> 144:ef7eb2e8f9f7 450 }
<> 144:ef7eb2e8f9f7 451
<> 144:ef7eb2e8f9f7 452 // Check to see if we've finished reading and writing
<> 144:ef7eb2e8f9f7 453 if (((read && (req->read_num == req->len)) || !read) &&
<> 144:ef7eb2e8f9f7 454 ((req->write_num == req->len) || !write)) {
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 // Disable interrupts
<> 144:ef7eb2e8f9f7 457 spim->inten = 0;
<> 144:ef7eb2e8f9f7 458 }
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 // Enable the SPIM interrupts
<> 144:ef7eb2e8f9f7 461 return inten;
<> 144:ef7eb2e8f9f7 462 }
<> 144:ef7eb2e8f9f7 463
<> 144:ef7eb2e8f9f7 464 //******************************************************************************
<> 144:ef7eb2e8f9f7 465 void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint)
<> 144:ef7eb2e8f9f7 466 {
<> 144:ef7eb2e8f9f7 467 MBED_ASSERT(tx_length == rx_length);
<> 144:ef7eb2e8f9f7 468 MBED_ASSERT(bit_width == obj->spi.bits);
<> 144:ef7eb2e8f9f7 469
<> 144:ef7eb2e8f9f7 470 // Save object reference for callback
<> 144:ef7eb2e8f9f7 471 state[obj->spi.index] = &obj->spi;
<> 144:ef7eb2e8f9f7 472
<> 144:ef7eb2e8f9f7 473 // Initialize request info
<> 144:ef7eb2e8f9f7 474 obj->spi.tx_data = tx;
<> 144:ef7eb2e8f9f7 475 obj->spi.rx_data = rx;
<> 144:ef7eb2e8f9f7 476 obj->spi.len = tx_length;
<> 144:ef7eb2e8f9f7 477 obj->spi.callback = (void(*)())handler;
<> 144:ef7eb2e8f9f7 478 obj->spi.event = event;
<> 144:ef7eb2e8f9f7 479 // Clear transfer state
<> 144:ef7eb2e8f9f7 480 obj->spi.read_num = 0;
<> 144:ef7eb2e8f9f7 481 obj->spi.write_num = 0;
<> 144:ef7eb2e8f9f7 482 obj->spi.head_rem = 0;
<> 144:ef7eb2e8f9f7 483
<> 144:ef7eb2e8f9f7 484 NVIC_EnableIRQ(MXC_SPI_GET_IRQ(obj->spi.index));
<> 144:ef7eb2e8f9f7 485
<> 144:ef7eb2e8f9f7 486 obj->spi.spi->inten = spi_master_transfer_handler(obj);
<> 144:ef7eb2e8f9f7 487 }
<> 144:ef7eb2e8f9f7 488
<> 144:ef7eb2e8f9f7 489 //******************************************************************************
<> 144:ef7eb2e8f9f7 490 uint32_t spi_irq_handler_asynch(spi_t *obj)
<> 144:ef7eb2e8f9f7 491 {
<> 144:ef7eb2e8f9f7 492 mxc_spi_regs_t *spim = obj->spi.spi;
<> 144:ef7eb2e8f9f7 493 uint32_t flags;
<> 144:ef7eb2e8f9f7 494
<> 144:ef7eb2e8f9f7 495 // Clear the interrupt flags
<> 144:ef7eb2e8f9f7 496 spim->inten = 0;
<> 144:ef7eb2e8f9f7 497 flags = spim->intfl;
<> 144:ef7eb2e8f9f7 498 spim->intfl = flags;
<> 144:ef7eb2e8f9f7 499
<> 144:ef7eb2e8f9f7 500 // Figure out if this SPIM has an active request
<> 144:ef7eb2e8f9f7 501 if (flags) {
<> 144:ef7eb2e8f9f7 502 if ((spim->inten = spi_master_transfer_handler(obj)) != 0) {
<> 144:ef7eb2e8f9f7 503 return 0;
<> 144:ef7eb2e8f9f7 504 }
<> 144:ef7eb2e8f9f7 505 }
<> 144:ef7eb2e8f9f7 506
<> 144:ef7eb2e8f9f7 507 state[obj->spi.index] = NULL;
<> 144:ef7eb2e8f9f7 508
<> 144:ef7eb2e8f9f7 509 return SPI_EVENT_COMPLETE;
<> 144:ef7eb2e8f9f7 510 }
<> 144:ef7eb2e8f9f7 511
<> 144:ef7eb2e8f9f7 512 //******************************************************************************
<> 144:ef7eb2e8f9f7 513 uint8_t spi_active(spi_t *obj)
<> 144:ef7eb2e8f9f7 514 {
<> 144:ef7eb2e8f9f7 515 mxc_spi_regs_t *spim = obj->spi.spi;
<> 144:ef7eb2e8f9f7 516
<> 144:ef7eb2e8f9f7 517 // Check to see if there are any ongoing transactions
<> 144:ef7eb2e8f9f7 518 if ((state[obj->spi.index] == NULL) &&
<> 144:ef7eb2e8f9f7 519 !(spim->fifo_ctrl & MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED)) {
<> 144:ef7eb2e8f9f7 520 return 0;
<> 144:ef7eb2e8f9f7 521 }
<> 144:ef7eb2e8f9f7 522
<> 144:ef7eb2e8f9f7 523 return 1;
<> 144:ef7eb2e8f9f7 524 }
<> 144:ef7eb2e8f9f7 525
<> 144:ef7eb2e8f9f7 526 //******************************************************************************
<> 144:ef7eb2e8f9f7 527 void spi_abort_asynch(spi_t *obj)
<> 144:ef7eb2e8f9f7 528 {
<> 144:ef7eb2e8f9f7 529 mxc_spi_regs_t *spim = obj->spi.spi;
<> 144:ef7eb2e8f9f7 530
<> 144:ef7eb2e8f9f7 531 // Disable interrupts, clear the flags
<> 144:ef7eb2e8f9f7 532 spim->inten = 0;
<> 144:ef7eb2e8f9f7 533 spim->intfl = spim->intfl;
<> 144:ef7eb2e8f9f7 534
<> 144:ef7eb2e8f9f7 535 // Reset the SPIM to cancel the on ongoing transaction
<> 144:ef7eb2e8f9f7 536 spim->gen_ctrl &= ~(MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN);
<> 144:ef7eb2e8f9f7 537 spim->gen_ctrl |= (MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN);
<> 144:ef7eb2e8f9f7 538
<> 144:ef7eb2e8f9f7 539 state[obj->spi.index] = NULL;
<> 144:ef7eb2e8f9f7 540 }
<> 144:ef7eb2e8f9f7 541
<> 144:ef7eb2e8f9f7 542 //******************************************************************************
<> 144:ef7eb2e8f9f7 543 static void SPI_IRQHandler(int spim_num)
<> 144:ef7eb2e8f9f7 544 {
<> 144:ef7eb2e8f9f7 545 if (state[spim_num] != NULL) {
<> 144:ef7eb2e8f9f7 546 if (state[spim_num]->callback != NULL) {
<> 144:ef7eb2e8f9f7 547 state[spim_num]->callback();
<> 144:ef7eb2e8f9f7 548 return;
<> 144:ef7eb2e8f9f7 549 }
<> 144:ef7eb2e8f9f7 550 }
<> 144:ef7eb2e8f9f7 551 mxc_spi_regs_t *spim = MXC_SPI_GET_SPI(spim_num);
<> 144:ef7eb2e8f9f7 552 spim->inten = 0;
<> 144:ef7eb2e8f9f7 553 }
<> 144:ef7eb2e8f9f7 554
<> 144:ef7eb2e8f9f7 555 //******************************************************************************
<> 144:ef7eb2e8f9f7 556 void SPI0_IRQHandler(void) { SPI_IRQHandler(0); }
<> 144:ef7eb2e8f9f7 557 void SPI1_IRQHandler(void) { SPI_IRQHandler(1); }
<> 144:ef7eb2e8f9f7 558 void SPI2_IRQHandler(void) { SPI_IRQHandler(2); }
<> 144:ef7eb2e8f9f7 559
<> 144:ef7eb2e8f9f7 560 #endif