Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Maxim/TARGET_MAX32620/serial_api.c@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*******************************************************************************
<> 144:ef7eb2e8f9f7 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 144:ef7eb2e8f9f7 5 * copy of this software and associated documentation files (the "Software"),
<> 144:ef7eb2e8f9f7 6 * to deal in the Software without restriction, including without limitation
<> 144:ef7eb2e8f9f7 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 144:ef7eb2e8f9f7 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 144:ef7eb2e8f9f7 9 * Software is furnished to do so, subject to the following conditions:
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * The above copyright notice and this permission notice shall be included
<> 144:ef7eb2e8f9f7 12 * in all copies or substantial portions of the Software.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 144:ef7eb2e8f9f7 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 144:ef7eb2e8f9f7 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 144:ef7eb2e8f9f7 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 144:ef7eb2e8f9f7 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 144:ef7eb2e8f9f7 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * Except as contained in this notice, the name of Maxim Integrated
<> 144:ef7eb2e8f9f7 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 144:ef7eb2e8f9f7 24 * Products, Inc. Branding Policy.
<> 144:ef7eb2e8f9f7 25 *
<> 144:ef7eb2e8f9f7 26 * The mere transfer of this software does not imply any licenses
<> 144:ef7eb2e8f9f7 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 144:ef7eb2e8f9f7 28 * trademarks, maskwork rights, or any other form of intellectual
<> 144:ef7eb2e8f9f7 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 144:ef7eb2e8f9f7 30 * ownership rights.
<> 144:ef7eb2e8f9f7 31 *******************************************************************************
<> 144:ef7eb2e8f9f7 32 */
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #include <string.h>
<> 144:ef7eb2e8f9f7 35 #include "mbed_assert.h"
<> 144:ef7eb2e8f9f7 36 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 37 #include "serial_api.h"
<> 144:ef7eb2e8f9f7 38 #include "uart_regs.h"
<> 144:ef7eb2e8f9f7 39 #include "ioman_regs.h"
<> 144:ef7eb2e8f9f7 40 #include "gpio_api.h"
<> 144:ef7eb2e8f9f7 41 #include "clkman_regs.h"
<> 144:ef7eb2e8f9f7 42 #include "PeripheralPins.h"
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 #define DEFAULT_BAUD 9600
<> 144:ef7eb2e8f9f7 45 #define DEFAULT_STOP 1
<> 144:ef7eb2e8f9f7 46 #define DEFAULT_PARITY ParityNone
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 #define UART_ERRORS (MXC_F_UART_INTFL_RX_FRAMING_ERR | \
<> 144:ef7eb2e8f9f7 49 MXC_F_UART_INTFL_RX_PARITY_ERR | \
<> 144:ef7eb2e8f9f7 50 MXC_F_UART_INTFL_RX_FIFO_OVERFLOW)
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 // Variables for managing the stdio UART
<> 144:ef7eb2e8f9f7 53 int stdio_uart_inited;
<> 144:ef7eb2e8f9f7 54 serial_t stdio_uart;
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 // Variables for interrupt driven
<> 144:ef7eb2e8f9f7 57 static uart_irq_handler irq_handler;
<> 144:ef7eb2e8f9f7 58 static uint32_t serial_irq_ids[MXC_CFG_UART_INSTANCES];
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 //******************************************************************************
<> 144:ef7eb2e8f9f7 61 void serial_init(serial_t *obj, PinName tx, PinName rx)
<> 144:ef7eb2e8f9f7 62 {
<> 144:ef7eb2e8f9f7 63 // Determine which uart is associated with each pin
<> 144:ef7eb2e8f9f7 64 UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
<> 144:ef7eb2e8f9f7 65 UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
<> 144:ef7eb2e8f9f7 66 UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 // Make sure that both pins are pointing to the same uart
<> 144:ef7eb2e8f9f7 69 MBED_ASSERT(uart != (UARTName)NC);
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 // Ensure that the UART clock is enabled
<> 144:ef7eb2e8f9f7 72 switch (uart) {
<> 144:ef7eb2e8f9f7 73 case UART_0:
<> 144:ef7eb2e8f9f7 74 MXC_CLKMAN->clk_gate_ctrl1 |= MXC_F_CLKMAN_CLK_GATE_CTRL1_UART0_CLK_GATER;
<> 144:ef7eb2e8f9f7 75 break;
<> 144:ef7eb2e8f9f7 76 case UART_1:
<> 144:ef7eb2e8f9f7 77 MXC_CLKMAN->clk_gate_ctrl1 |= MXC_F_CLKMAN_CLK_GATE_CTRL1_UART1_CLK_GATER;
<> 144:ef7eb2e8f9f7 78 break;
<> 144:ef7eb2e8f9f7 79 case UART_2:
<> 144:ef7eb2e8f9f7 80 MXC_CLKMAN->clk_gate_ctrl1 |= MXC_F_CLKMAN_CLK_GATE_CTRL1_UART2_CLK_GATER;
<> 144:ef7eb2e8f9f7 81 break;
<> 144:ef7eb2e8f9f7 82 case UART_3:
<> 144:ef7eb2e8f9f7 83 MXC_CLKMAN->clk_gate_ctrl1 |= MXC_F_CLKMAN_CLK_GATE_CTRL1_UART3_CLK_GATER;
<> 144:ef7eb2e8f9f7 84 break;
<> 144:ef7eb2e8f9f7 85 default:
<> 144:ef7eb2e8f9f7 86 break;
<> 144:ef7eb2e8f9f7 87 }
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 // Ensure that the UART clock is enabled
<> 144:ef7eb2e8f9f7 90 // But don't override the scaler
<> 144:ef7eb2e8f9f7 91 //
<> 144:ef7eb2e8f9f7 92 // To support the most common baud rates, 9600 and 115200, we need to
<> 144:ef7eb2e8f9f7 93 // scale down the uart input clock.
<> 144:ef7eb2e8f9f7 94 if (!(MXC_CLKMAN->sys_clk_ctrl_8_uart & MXC_F_CLKMAN_SYS_CLK_CTRL_8_UART_UART_CLK_SCALE)) {
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 switch (SystemCoreClock) {
<> 144:ef7eb2e8f9f7 97 case RO_FREQ:
<> 144:ef7eb2e8f9f7 98 MXC_CLKMAN->sys_clk_ctrl_8_uart = MXC_S_CLKMAN_CLK_SCALE_DIV_4;
<> 144:ef7eb2e8f9f7 99 break;
<> 144:ef7eb2e8f9f7 100 case (RO_FREQ / 2):
<> 144:ef7eb2e8f9f7 101 MXC_CLKMAN->sys_clk_ctrl_8_uart = MXC_S_CLKMAN_CLK_SCALE_DIV_2;
<> 144:ef7eb2e8f9f7 102 break;
<> 144:ef7eb2e8f9f7 103 default:
<> 144:ef7eb2e8f9f7 104 MXC_CLKMAN->sys_clk_ctrl_8_uart = MXC_S_CLKMAN_CLK_SCALE_DIV_4;
<> 144:ef7eb2e8f9f7 105 break;
<> 144:ef7eb2e8f9f7 106 }
<> 144:ef7eb2e8f9f7 107 }
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 // Set the obj pointer to the proper uart
<> 144:ef7eb2e8f9f7 110 obj->uart = (mxc_uart_regs_t*)uart;
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 // Set the uart index
<> 144:ef7eb2e8f9f7 113 obj->index = MXC_UART_GET_IDX(obj->uart);
<> 144:ef7eb2e8f9f7 114 obj->fifo = (mxc_uart_fifo_regs_t*)MXC_UART_GET_BASE_FIFO(obj->index);
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 // Configure the pins
<> 144:ef7eb2e8f9f7 117 pinmap_pinout(tx, PinMap_UART_TX);
<> 144:ef7eb2e8f9f7 118 pinmap_pinout(rx, PinMap_UART_RX);
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120 // Flush the RX and TX FIFOs, clear the settings
<> 144:ef7eb2e8f9f7 121 obj->uart->ctrl &= ~(MXC_F_UART_CTRL_RX_FIFO_EN | MXC_F_UART_CTRL_TX_FIFO_EN);
<> 144:ef7eb2e8f9f7 122 obj->uart->ctrl |= (MXC_F_UART_CTRL_RX_FIFO_EN | MXC_F_UART_CTRL_TX_FIFO_EN);
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 // Disable interrupts
<> 144:ef7eb2e8f9f7 125 obj->uart->inten = 0;
<> 144:ef7eb2e8f9f7 126 obj->uart->intfl = obj->uart->intfl;
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 // Configure to default settings
<> 144:ef7eb2e8f9f7 129 serial_baud(obj, DEFAULT_BAUD);
<> 144:ef7eb2e8f9f7 130 serial_format(obj, 8, ParityNone, 1);
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 // Manage stdio UART
<> 144:ef7eb2e8f9f7 133 if (uart == STDIO_UART) {
<> 144:ef7eb2e8f9f7 134 stdio_uart_inited = 1;
<> 144:ef7eb2e8f9f7 135 memcpy(&stdio_uart, obj, sizeof(serial_t));
<> 144:ef7eb2e8f9f7 136 }
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 // Enable UART
<> 144:ef7eb2e8f9f7 139 obj->uart->ctrl |= MXC_F_UART_CTRL_UART_EN;
<> 144:ef7eb2e8f9f7 140 }
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 //******************************************************************************
<> 144:ef7eb2e8f9f7 143 void serial_baud(serial_t *obj, int baudrate)
<> 144:ef7eb2e8f9f7 144 {
<> 144:ef7eb2e8f9f7 145 uint32_t baud_setting = 0;
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 MBED_ASSERT(MXC_CLKMAN->sys_clk_ctrl_8_uart > MXC_S_CLKMAN_CLK_SCALE_DISABLED);
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 // Calculate the integer and decimal portions
<> 144:ef7eb2e8f9f7 150 baud_setting = SystemCoreClock / (1<<(MXC_CLKMAN->sys_clk_ctrl_8_uart-1));
<> 144:ef7eb2e8f9f7 151 baud_setting = baud_setting / (baudrate * 16);
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 // If the result doesn't fit in the register
<> 144:ef7eb2e8f9f7 154 MBED_ASSERT(baud_setting <= UINT8_MAX);
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 obj->uart->baud = baud_setting;
<> 144:ef7eb2e8f9f7 157 }
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 //******************************************************************************
<> 144:ef7eb2e8f9f7 160 void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
<> 144:ef7eb2e8f9f7 161 {
<> 144:ef7eb2e8f9f7 162 // Check the validity of the inputs
<> 144:ef7eb2e8f9f7 163 MBED_ASSERT((data_bits > 4) && (data_bits < 9));
<> 144:ef7eb2e8f9f7 164 MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) ||
<> 144:ef7eb2e8f9f7 165 (parity == ParityEven) || (parity == ParityForced1) ||
<> 144:ef7eb2e8f9f7 166 (parity == ParityForced0));
<> 144:ef7eb2e8f9f7 167 MBED_ASSERT((stop_bits == 1) || (stop_bits == 2));
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 // Adjust the stop and data bits
<> 144:ef7eb2e8f9f7 170 stop_bits -= 1;
<> 144:ef7eb2e8f9f7 171 data_bits -= 5;
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 // Adjust the parity setting
<> 144:ef7eb2e8f9f7 174 int mode = 0;
<> 144:ef7eb2e8f9f7 175 switch (parity) {
<> 144:ef7eb2e8f9f7 176 case ParityNone:
<> 144:ef7eb2e8f9f7 177 mode = 0;
<> 144:ef7eb2e8f9f7 178 break;
<> 144:ef7eb2e8f9f7 179 case ParityOdd :
<> 144:ef7eb2e8f9f7 180 mode = 1;
<> 144:ef7eb2e8f9f7 181 break;
<> 144:ef7eb2e8f9f7 182 case ParityEven:
<> 144:ef7eb2e8f9f7 183 mode = 2;
<> 144:ef7eb2e8f9f7 184 break;
<> 144:ef7eb2e8f9f7 185 case ParityForced1:
<> 144:ef7eb2e8f9f7 186 // Hardware does not support forced parity
<> 144:ef7eb2e8f9f7 187 MBED_ASSERT(0);
<> 144:ef7eb2e8f9f7 188 break;
<> 144:ef7eb2e8f9f7 189 case ParityForced0:
<> 144:ef7eb2e8f9f7 190 // Hardware does not support forced parity
<> 144:ef7eb2e8f9f7 191 MBED_ASSERT(0);
<> 144:ef7eb2e8f9f7 192 break;
<> 144:ef7eb2e8f9f7 193 default:
<> 144:ef7eb2e8f9f7 194 mode = 0;
<> 144:ef7eb2e8f9f7 195 break;
<> 144:ef7eb2e8f9f7 196 }
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 int temp = obj->uart->ctrl;
<> 144:ef7eb2e8f9f7 199 temp &= ~(MXC_F_UART_CTRL_DATA_SIZE | MXC_F_UART_CTRL_EXTRA_STOP | MXC_F_UART_CTRL_PARITY);
<> 144:ef7eb2e8f9f7 200 temp |= (data_bits << MXC_F_UART_CTRL_DATA_SIZE_POS);
<> 144:ef7eb2e8f9f7 201 temp |= (stop_bits << MXC_F_UART_CTRL_EXTRA_STOP_POS);
<> 144:ef7eb2e8f9f7 202 temp |= (mode << MXC_F_UART_CTRL_PARITY_POS);
<> 144:ef7eb2e8f9f7 203 obj->uart->ctrl = temp;
<> 144:ef7eb2e8f9f7 204 }
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 //******************************************************************************
<> 144:ef7eb2e8f9f7 207 void uart_handler(mxc_uart_regs_t* uart, int id)
<> 144:ef7eb2e8f9f7 208 {
<> 144:ef7eb2e8f9f7 209 // Check for errors or RX Threshold
<> 144:ef7eb2e8f9f7 210 if (uart->intfl & (MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY | UART_ERRORS)) {
<> 144:ef7eb2e8f9f7 211 if (serial_irq_ids[id]) {
<> 144:ef7eb2e8f9f7 212 irq_handler(serial_irq_ids[id], RxIrq);
<> 144:ef7eb2e8f9f7 213 }
<> 144:ef7eb2e8f9f7 214 uart->intfl = (MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY | UART_ERRORS);
<> 144:ef7eb2e8f9f7 215 }
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 // Check for TX Threshold
<> 144:ef7eb2e8f9f7 218 if (uart->intfl & MXC_F_UART_INTFL_TX_FIFO_AE) {
<> 144:ef7eb2e8f9f7 219 if (serial_irq_ids[id]) {
<> 144:ef7eb2e8f9f7 220 irq_handler(serial_irq_ids[id], TxIrq);
<> 144:ef7eb2e8f9f7 221 }
<> 144:ef7eb2e8f9f7 222 uart->intfl = MXC_F_UART_INTFL_TX_FIFO_AE;
<> 144:ef7eb2e8f9f7 223 }
<> 144:ef7eb2e8f9f7 224 }
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 void uart0_handler(void) { uart_handler(MXC_UART0, 0); }
<> 144:ef7eb2e8f9f7 227 void uart1_handler(void) { uart_handler(MXC_UART1, 1); }
<> 144:ef7eb2e8f9f7 228 void uart2_handler(void) { uart_handler(MXC_UART2, 2); }
<> 144:ef7eb2e8f9f7 229 void uart3_handler(void) { uart_handler(MXC_UART3, 3); }
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 //******************************************************************************
<> 144:ef7eb2e8f9f7 232 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
<> 144:ef7eb2e8f9f7 233 {
<> 144:ef7eb2e8f9f7 234 irq_handler = handler;
<> 144:ef7eb2e8f9f7 235 serial_irq_ids[obj->index] = id;
<> 144:ef7eb2e8f9f7 236 }
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 //******************************************************************************
<> 144:ef7eb2e8f9f7 239 void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
<> 144:ef7eb2e8f9f7 240 {
<> 144:ef7eb2e8f9f7 241 switch (obj->index) {
<> 144:ef7eb2e8f9f7 242 case 0:
<> 144:ef7eb2e8f9f7 243 NVIC_SetVector(UART0_IRQn, (uint32_t)uart0_handler);
<> 144:ef7eb2e8f9f7 244 NVIC_EnableIRQ(UART0_IRQn);
<> 144:ef7eb2e8f9f7 245 break;
<> 144:ef7eb2e8f9f7 246 case 1:
<> 144:ef7eb2e8f9f7 247 NVIC_SetVector(UART1_IRQn, (uint32_t)uart1_handler);
<> 144:ef7eb2e8f9f7 248 NVIC_EnableIRQ(UART1_IRQn);
<> 144:ef7eb2e8f9f7 249 break;
<> 144:ef7eb2e8f9f7 250 case 2:
<> 144:ef7eb2e8f9f7 251 NVIC_SetVector(UART2_IRQn, (uint32_t)uart2_handler);
<> 144:ef7eb2e8f9f7 252 NVIC_EnableIRQ(UART2_IRQn);
<> 144:ef7eb2e8f9f7 253 break;
<> 144:ef7eb2e8f9f7 254 case 3:
<> 144:ef7eb2e8f9f7 255 NVIC_SetVector(UART3_IRQn, (uint32_t)uart3_handler);
<> 144:ef7eb2e8f9f7 256 NVIC_EnableIRQ(UART3_IRQn);
<> 144:ef7eb2e8f9f7 257 break;
<> 144:ef7eb2e8f9f7 258 default:
<> 144:ef7eb2e8f9f7 259 MBED_ASSERT(0);
<> 144:ef7eb2e8f9f7 260 }
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 if (irq == RxIrq) {
<> 144:ef7eb2e8f9f7 263 // Enable RX FIFO Threshold Interrupt
<> 144:ef7eb2e8f9f7 264 if (enable) {
<> 144:ef7eb2e8f9f7 265 // Clear pending interrupts
<> 144:ef7eb2e8f9f7 266 obj->uart->intfl = obj->uart->intfl;
<> 144:ef7eb2e8f9f7 267 obj->uart->inten |= (MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY | UART_ERRORS);
<> 144:ef7eb2e8f9f7 268 } else {
<> 144:ef7eb2e8f9f7 269 // Clear pending interrupts
<> 144:ef7eb2e8f9f7 270 obj->uart->intfl = obj->uart->intfl;
<> 144:ef7eb2e8f9f7 271 obj->uart->inten &= ~(MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY | UART_ERRORS);
<> 144:ef7eb2e8f9f7 272 }
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 } else if (irq == TxIrq) {
<> 144:ef7eb2e8f9f7 275 // Set TX Almost Empty level to interrupt when empty
<> 144:ef7eb2e8f9f7 276 MXC_SET_FIELD(&obj->uart->tx_fifo_ctrl, MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL,
<> 144:ef7eb2e8f9f7 277 (MXC_UART_FIFO_DEPTH - 1) << MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL_POS);
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 // Enable TX Almost Empty Interrupt
<> 144:ef7eb2e8f9f7 280 if (enable) {
<> 144:ef7eb2e8f9f7 281 // Clear pending interrupts
<> 144:ef7eb2e8f9f7 282 obj->uart->intfl = obj->uart->intfl;
<> 144:ef7eb2e8f9f7 283 obj->uart->inten |= MXC_F_UART_INTFL_TX_FIFO_AE;
<> 144:ef7eb2e8f9f7 284 } else {
<> 144:ef7eb2e8f9f7 285 // Clear pending interrupts
<> 144:ef7eb2e8f9f7 286 obj->uart->intfl = obj->uart->intfl;
<> 144:ef7eb2e8f9f7 287 obj->uart->inten &= ~MXC_F_UART_INTFL_TX_FIFO_AE;
<> 144:ef7eb2e8f9f7 288 }
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 } else {
<> 144:ef7eb2e8f9f7 291 MBED_ASSERT(0);
<> 144:ef7eb2e8f9f7 292 }
<> 144:ef7eb2e8f9f7 293 }
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295
<> 144:ef7eb2e8f9f7 296 //******************************************************************************
<> 144:ef7eb2e8f9f7 297 int serial_getc(serial_t *obj)
<> 144:ef7eb2e8f9f7 298 {
<> 144:ef7eb2e8f9f7 299 int c;
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 // Wait for data to be available
<> 144:ef7eb2e8f9f7 302 while ((obj->uart->rx_fifo_ctrl & MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY) == 0);
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304 c = *obj->fifo->rx_8;
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306 // Echo characters for stdio
<> 144:ef7eb2e8f9f7 307 if (obj->uart == (mxc_uart_regs_t*)STDIO_UART) {
<> 144:ef7eb2e8f9f7 308 *obj->fifo->tx_8 = (uint8_t)c;
<> 144:ef7eb2e8f9f7 309 }
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 return c;
<> 144:ef7eb2e8f9f7 312 }
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 //******************************************************************************
<> 144:ef7eb2e8f9f7 315 void serial_putc(serial_t *obj, int c)
<> 144:ef7eb2e8f9f7 316 {
<> 144:ef7eb2e8f9f7 317 // Append a carriage return for stdio
<> 144:ef7eb2e8f9f7 318 if ((c == (int)'\n') && (obj->uart == (mxc_uart_regs_t*)STDIO_UART)) {
<> 144:ef7eb2e8f9f7 319 while ( ((obj->uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY)
<> 144:ef7eb2e8f9f7 320 >> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS)
<> 144:ef7eb2e8f9f7 321 >= MXC_UART_FIFO_DEPTH );
<> 144:ef7eb2e8f9f7 322
<> 144:ef7eb2e8f9f7 323 // Must clear before every write to the buffer to know that the fifo
<> 144:ef7eb2e8f9f7 324 // is empty when the TX DONE bit is set
<> 144:ef7eb2e8f9f7 325 obj->uart->intfl = MXC_F_UART_INTFL_TX_DONE;
<> 144:ef7eb2e8f9f7 326 *obj->fifo->tx_8 = (uint8_t)'\r';
<> 144:ef7eb2e8f9f7 327 }
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 // Wait for TXFIFO to not be full
<> 144:ef7eb2e8f9f7 330 while ( ((obj->uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY)
<> 144:ef7eb2e8f9f7 331 >> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS)
<> 144:ef7eb2e8f9f7 332 >= MXC_UART_FIFO_DEPTH );
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 // Must clear before every write to the buffer to know that the fifo
<> 144:ef7eb2e8f9f7 335 // is empty when the TX DONE bit is set
<> 144:ef7eb2e8f9f7 336 obj->uart->intfl = MXC_F_UART_INTFL_TX_DONE;
<> 144:ef7eb2e8f9f7 337 *obj->fifo->tx_8 = (uint8_t)c;
<> 144:ef7eb2e8f9f7 338 }
<> 144:ef7eb2e8f9f7 339
<> 144:ef7eb2e8f9f7 340 //******************************************************************************
<> 144:ef7eb2e8f9f7 341 int serial_readable(serial_t *obj)
<> 144:ef7eb2e8f9f7 342 {
<> 144:ef7eb2e8f9f7 343 return (obj->uart->intfl & MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY);
<> 144:ef7eb2e8f9f7 344 }
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 //******************************************************************************
<> 144:ef7eb2e8f9f7 347 int serial_writable(serial_t *obj)
<> 144:ef7eb2e8f9f7 348 {
<> 144:ef7eb2e8f9f7 349 return ( ((obj->uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY)
<> 144:ef7eb2e8f9f7 350 >> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS)
<> 144:ef7eb2e8f9f7 351 < MXC_UART_FIFO_DEPTH );
<> 144:ef7eb2e8f9f7 352 }
<> 144:ef7eb2e8f9f7 353
<> 144:ef7eb2e8f9f7 354 //******************************************************************************
<> 144:ef7eb2e8f9f7 355 void serial_clear(serial_t *obj)
<> 144:ef7eb2e8f9f7 356 {
<> 144:ef7eb2e8f9f7 357 // Clear the rx and tx fifos
<> 144:ef7eb2e8f9f7 358 obj->uart->ctrl &= ~(MXC_F_UART_CTRL_RX_FIFO_EN | MXC_F_UART_CTRL_TX_FIFO_EN);
<> 144:ef7eb2e8f9f7 359 obj->uart->ctrl |= (MXC_F_UART_CTRL_RX_FIFO_EN | MXC_F_UART_CTRL_TX_FIFO_EN);
<> 144:ef7eb2e8f9f7 360 }
<> 144:ef7eb2e8f9f7 361
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 //******************************************************************************
<> 144:ef7eb2e8f9f7 364 void serial_break_set(serial_t *obj)
<> 144:ef7eb2e8f9f7 365 {
<> 144:ef7eb2e8f9f7 366 // Make sure that nothing is being sent
<> 144:ef7eb2e8f9f7 367 while ( ((obj->uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY)
<> 144:ef7eb2e8f9f7 368 >> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS) > 0);
<> 144:ef7eb2e8f9f7 369 while (!(obj->uart->intfl & MXC_F_UART_INTFL_TX_DONE));
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 // Configure the GPIO to output 0
<> 144:ef7eb2e8f9f7 372 gpio_t tx_gpio;
<> 144:ef7eb2e8f9f7 373 switch (((UARTName)(obj->uart))) {
<> 144:ef7eb2e8f9f7 374 case UART_0:
<> 144:ef7eb2e8f9f7 375 gpio_init_out(&tx_gpio, UART0_TX);
<> 144:ef7eb2e8f9f7 376 break;
<> 144:ef7eb2e8f9f7 377 case UART_1:
<> 144:ef7eb2e8f9f7 378 gpio_init_out(&tx_gpio, UART1_TX);
<> 144:ef7eb2e8f9f7 379 break;
<> 144:ef7eb2e8f9f7 380 case UART_2:
<> 144:ef7eb2e8f9f7 381 gpio_init_out(&tx_gpio, UART2_TX);
<> 144:ef7eb2e8f9f7 382 break;
<> 144:ef7eb2e8f9f7 383 case UART_3:
<> 144:ef7eb2e8f9f7 384 gpio_init_out(&tx_gpio, UART3_TX);
<> 144:ef7eb2e8f9f7 385 break;
<> 144:ef7eb2e8f9f7 386 default:
<> 144:ef7eb2e8f9f7 387 gpio_init_out(&tx_gpio, (PinName)NC);
<> 144:ef7eb2e8f9f7 388 break;
<> 144:ef7eb2e8f9f7 389 }
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 gpio_write(&tx_gpio, 0);
<> 144:ef7eb2e8f9f7 392
<> 144:ef7eb2e8f9f7 393 // GPIO is setup now, but we need to map GPIO to the pin
<> 144:ef7eb2e8f9f7 394 switch (((UARTName)(obj->uart))) {
<> 144:ef7eb2e8f9f7 395 case UART_0:
<> 144:ef7eb2e8f9f7 396 MXC_IOMAN->uart0_req &= ~MXC_F_IOMAN_UART_REQ_IO_REQ;
<> 144:ef7eb2e8f9f7 397 MBED_ASSERT((MXC_IOMAN->uart0_ack & (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)) == 0);
<> 144:ef7eb2e8f9f7 398 break;
<> 144:ef7eb2e8f9f7 399 case UART_1:
<> 144:ef7eb2e8f9f7 400 MXC_IOMAN->uart1_req &= ~MXC_F_IOMAN_UART_REQ_IO_REQ;
<> 144:ef7eb2e8f9f7 401 MBED_ASSERT((MXC_IOMAN->uart1_ack & (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)) == 0);
<> 144:ef7eb2e8f9f7 402 break;
<> 144:ef7eb2e8f9f7 403 case UART_2:
<> 144:ef7eb2e8f9f7 404 MXC_IOMAN->uart2_req &= ~MXC_F_IOMAN_UART_REQ_IO_REQ;
<> 144:ef7eb2e8f9f7 405 MBED_ASSERT((MXC_IOMAN->uart2_ack & (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)) == 0);
<> 144:ef7eb2e8f9f7 406 break;
<> 144:ef7eb2e8f9f7 407 case UART_3:
<> 144:ef7eb2e8f9f7 408 MXC_IOMAN->uart3_req &= ~MXC_F_IOMAN_UART_REQ_IO_REQ;
<> 144:ef7eb2e8f9f7 409 MBED_ASSERT((MXC_IOMAN->uart3_ack & (MXC_F_IOMAN_UART_ACK_IO_MAP | MXC_F_IOMAN_UART_ACK_IO_ACK)) == 0);
<> 144:ef7eb2e8f9f7 410 break;
<> 144:ef7eb2e8f9f7 411 default:
<> 144:ef7eb2e8f9f7 412 break;
<> 144:ef7eb2e8f9f7 413 }
<> 144:ef7eb2e8f9f7 414 }
<> 144:ef7eb2e8f9f7 415
<> 144:ef7eb2e8f9f7 416 //******************************************************************************
<> 144:ef7eb2e8f9f7 417 void serial_break_clear(serial_t *obj)
<> 144:ef7eb2e8f9f7 418 {
<> 144:ef7eb2e8f9f7 419 // Configure the GPIO to output 1
<> 144:ef7eb2e8f9f7 420 gpio_t tx_gpio;
<> 144:ef7eb2e8f9f7 421 switch (((UARTName)(obj->uart))) {
<> 144:ef7eb2e8f9f7 422 case UART_0:
<> 144:ef7eb2e8f9f7 423 gpio_init_out(&tx_gpio, UART0_TX);
<> 144:ef7eb2e8f9f7 424 break;
<> 144:ef7eb2e8f9f7 425 case UART_1:
<> 144:ef7eb2e8f9f7 426 gpio_init_out(&tx_gpio, UART1_TX);
<> 144:ef7eb2e8f9f7 427 break;
<> 144:ef7eb2e8f9f7 428 case UART_2:
<> 144:ef7eb2e8f9f7 429 gpio_init_out(&tx_gpio, UART2_TX);
<> 144:ef7eb2e8f9f7 430 break;
<> 144:ef7eb2e8f9f7 431 case UART_3:
<> 144:ef7eb2e8f9f7 432 gpio_init_out(&tx_gpio, UART3_TX);
<> 144:ef7eb2e8f9f7 433 break;
<> 144:ef7eb2e8f9f7 434 default:
<> 144:ef7eb2e8f9f7 435 gpio_init_out(&tx_gpio, (PinName)NC);
<> 144:ef7eb2e8f9f7 436 break;
<> 144:ef7eb2e8f9f7 437 }
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 gpio_write(&tx_gpio, 1);
<> 144:ef7eb2e8f9f7 440
<> 144:ef7eb2e8f9f7 441 // Renable UART
<> 144:ef7eb2e8f9f7 442 switch (((UARTName)(obj->uart))) {
<> 144:ef7eb2e8f9f7 443 case UART_0:
<> 144:ef7eb2e8f9f7 444 serial_pinout_tx(UART0_TX);
<> 144:ef7eb2e8f9f7 445 break;
<> 144:ef7eb2e8f9f7 446 case UART_1:
<> 144:ef7eb2e8f9f7 447 serial_pinout_tx(UART1_TX);
<> 144:ef7eb2e8f9f7 448 break;
<> 144:ef7eb2e8f9f7 449 case UART_2:
<> 144:ef7eb2e8f9f7 450 serial_pinout_tx(UART2_TX);
<> 144:ef7eb2e8f9f7 451 break;
<> 144:ef7eb2e8f9f7 452 case UART_3:
<> 144:ef7eb2e8f9f7 453 serial_pinout_tx(UART3_TX);
<> 144:ef7eb2e8f9f7 454 break;
<> 144:ef7eb2e8f9f7 455 default:
<> 144:ef7eb2e8f9f7 456 serial_pinout_tx((PinName)NC);
<> 144:ef7eb2e8f9f7 457 break;
<> 144:ef7eb2e8f9f7 458 }
<> 144:ef7eb2e8f9f7 459 }
<> 144:ef7eb2e8f9f7 460
<> 144:ef7eb2e8f9f7 461 //******************************************************************************
<> 144:ef7eb2e8f9f7 462 void serial_pinout_tx(PinName tx)
<> 144:ef7eb2e8f9f7 463 {
<> 144:ef7eb2e8f9f7 464 pinmap_pinout(tx, PinMap_UART_TX);
<> 144:ef7eb2e8f9f7 465 }
<> 144:ef7eb2e8f9f7 466
<> 144:ef7eb2e8f9f7 467 //******************************************************************************
<> 144:ef7eb2e8f9f7 468 void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
<> 144:ef7eb2e8f9f7 469 {
<> 144:ef7eb2e8f9f7 470 uint32_t ctrl = obj->uart->ctrl;
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 // Disable hardware flow control
<> 144:ef7eb2e8f9f7 473 ctrl &= ~(MXC_F_UART_CTRL_RTS_EN | MXC_F_UART_CTRL_CTS_EN);
<> 144:ef7eb2e8f9f7 474
<> 144:ef7eb2e8f9f7 475 if (FlowControlNone != type) {
<> 144:ef7eb2e8f9f7 476 // Check to see if we can use HW flow control
<> 144:ef7eb2e8f9f7 477 UARTName uart_cts = (UARTName)pinmap_peripheral(txflow, PinMap_UART_CTS);
<> 144:ef7eb2e8f9f7 478 UARTName uart_rts = (UARTName)pinmap_peripheral(rxflow, PinMap_UART_RTS);
<> 144:ef7eb2e8f9f7 479 UARTName uart = (UARTName)pinmap_merge(uart_cts, uart_rts);
<> 144:ef7eb2e8f9f7 480
<> 144:ef7eb2e8f9f7 481 // Make sure that the pins are pointing to the same UART
<> 144:ef7eb2e8f9f7 482 MBED_ASSERT(uart != (UARTName)NC);
<> 144:ef7eb2e8f9f7 483
<> 144:ef7eb2e8f9f7 484 if ((FlowControlCTS == type) || (FlowControlRTSCTS == type)) {
<> 144:ef7eb2e8f9f7 485 // Make sure pin is in the PinMap
<> 144:ef7eb2e8f9f7 486 MBED_ASSERT(uart_cts != (UARTName)NC);
<> 144:ef7eb2e8f9f7 487
<> 144:ef7eb2e8f9f7 488 // Enable the pin for CTS function
<> 144:ef7eb2e8f9f7 489 pinmap_pinout(txflow, PinMap_UART_CTS);
<> 144:ef7eb2e8f9f7 490
<> 144:ef7eb2e8f9f7 491 // Enable active-low hardware flow control
<> 144:ef7eb2e8f9f7 492 ctrl |= (MXC_F_UART_CTRL_CTS_EN | MXC_F_UART_CTRL_CTS_POLARITY);
<> 144:ef7eb2e8f9f7 493 }
<> 144:ef7eb2e8f9f7 494
<> 144:ef7eb2e8f9f7 495 if ((FlowControlRTS == type) || (FlowControlRTSCTS == type)) {
<> 144:ef7eb2e8f9f7 496 // Make sure pin is in the PinMap
<> 144:ef7eb2e8f9f7 497 MBED_ASSERT(uart_rts != (UARTName)NC);
<> 144:ef7eb2e8f9f7 498
<> 144:ef7eb2e8f9f7 499 // Enable the pin for RTS function
<> 144:ef7eb2e8f9f7 500 pinmap_pinout(rxflow, PinMap_UART_RTS);
<> 144:ef7eb2e8f9f7 501
<> 144:ef7eb2e8f9f7 502 // Enable active-low hardware flow control
<> 144:ef7eb2e8f9f7 503 ctrl |= (MXC_F_UART_CTRL_RTS_EN | MXC_F_UART_CTRL_RTS_POLARITY);
<> 144:ef7eb2e8f9f7 504 }
<> 144:ef7eb2e8f9f7 505 }
<> 144:ef7eb2e8f9f7 506
<> 144:ef7eb2e8f9f7 507 obj->uart->ctrl = ctrl;
<> 144:ef7eb2e8f9f7 508 }