Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/drivers/fsl_uart.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 144:ef7eb2e8f9f7 3 * All rights reserved.
<> 144:ef7eb2e8f9f7 4 *
<> 144:ef7eb2e8f9f7 5 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 6 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 144:ef7eb2e8f9f7 9 * of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 144:ef7eb2e8f9f7 12 * list of conditions and the following disclaimer in the documentation and/or
<> 144:ef7eb2e8f9f7 13 * other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 144:ef7eb2e8f9f7 16 * contributors may be used to endorse or promote products derived from this
<> 144:ef7eb2e8f9f7 17 * software without specific prior written permission.
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 29 */
<> 144:ef7eb2e8f9f7 30 #ifndef _FSL_UART_H_
<> 144:ef7eb2e8f9f7 31 #define _FSL_UART_H_
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 #include "fsl_common.h"
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 /*!
<> 144:ef7eb2e8f9f7 36 * @addtogroup uart_driver
<> 144:ef7eb2e8f9f7 37 * @{
<> 144:ef7eb2e8f9f7 38 */
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 /*! @file */
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 /*******************************************************************************
<> 144:ef7eb2e8f9f7 43 * Definitions
<> 144:ef7eb2e8f9f7 44 ******************************************************************************/
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /*! @name Driver version */
<> 144:ef7eb2e8f9f7 47 /*@{*/
<> 144:ef7eb2e8f9f7 48 /*! @brief UART driver version 2.1.0. */
<> 144:ef7eb2e8f9f7 49 #define FSL_UART_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
<> 144:ef7eb2e8f9f7 50 /*@}*/
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 /*! @brief Error codes for the UART driver. */
<> 144:ef7eb2e8f9f7 53 enum _uart_status
<> 144:ef7eb2e8f9f7 54 {
<> 144:ef7eb2e8f9f7 55 kStatus_UART_TxBusy = MAKE_STATUS(kStatusGroup_UART, 0), /*!< Transmitter is busy. */
<> 144:ef7eb2e8f9f7 56 kStatus_UART_RxBusy = MAKE_STATUS(kStatusGroup_UART, 1), /*!< Receiver is busy. */
<> 144:ef7eb2e8f9f7 57 kStatus_UART_TxIdle = MAKE_STATUS(kStatusGroup_UART, 2), /*!< UART transmitter is idle. */
<> 144:ef7eb2e8f9f7 58 kStatus_UART_RxIdle = MAKE_STATUS(kStatusGroup_UART, 3), /*!< UART receiver is idle. */
<> 144:ef7eb2e8f9f7 59 kStatus_UART_TxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_UART, 4), /*!< TX FIFO watermark too large */
<> 144:ef7eb2e8f9f7 60 kStatus_UART_RxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_UART, 5), /*!< RX FIFO watermark too large */
<> 144:ef7eb2e8f9f7 61 kStatus_UART_FlagCannotClearManually =
<> 144:ef7eb2e8f9f7 62 MAKE_STATUS(kStatusGroup_UART, 6), /*!< UART flag can't be manually cleared. */
<> 144:ef7eb2e8f9f7 63 kStatus_UART_Error = MAKE_STATUS(kStatusGroup_UART, 7), /*!< Error happens on UART. */
<> 144:ef7eb2e8f9f7 64 kStatus_UART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_UART, 8), /*!< UART RX software ring buffer overrun. */
<> 144:ef7eb2e8f9f7 65 kStatus_UART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_UART, 9), /*!< UART RX receiver overrun. */
<> 144:ef7eb2e8f9f7 66 kStatus_UART_NoiseError = MAKE_STATUS(kStatusGroup_UART, 10), /*!< UART noise error. */
<> 144:ef7eb2e8f9f7 67 kStatus_UART_FramingError = MAKE_STATUS(kStatusGroup_UART, 11), /*!< UART framing error. */
<> 144:ef7eb2e8f9f7 68 kStatus_UART_ParityError = MAKE_STATUS(kStatusGroup_UART, 12), /*!< UART parity error. */
<> 144:ef7eb2e8f9f7 69 };
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 /*! @brief UART parity mode. */
<> 144:ef7eb2e8f9f7 72 typedef enum _uart_parity_mode
<> 144:ef7eb2e8f9f7 73 {
<> 144:ef7eb2e8f9f7 74 kUART_ParityDisabled = 0x0U, /*!< Parity disabled */
<> 144:ef7eb2e8f9f7 75 kUART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */
<> 144:ef7eb2e8f9f7 76 kUART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */
<> 144:ef7eb2e8f9f7 77 } uart_parity_mode_t;
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 /*! @brief UART stop bit count. */
<> 144:ef7eb2e8f9f7 80 typedef enum _uart_stop_bit_count
<> 144:ef7eb2e8f9f7 81 {
<> 144:ef7eb2e8f9f7 82 kUART_OneStopBit = 0U, /*!< One stop bit */
<> 144:ef7eb2e8f9f7 83 kUART_TwoStopBit = 1U, /*!< Two stop bits */
<> 144:ef7eb2e8f9f7 84 } uart_stop_bit_count_t;
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 /*!
<> 144:ef7eb2e8f9f7 87 * @brief UART interrupt configuration structure, default settings all disabled.
<> 144:ef7eb2e8f9f7 88 *
<> 144:ef7eb2e8f9f7 89 * This structure contains the settings for all of the UART interrupt configurations.
<> 144:ef7eb2e8f9f7 90 */
<> 144:ef7eb2e8f9f7 91 enum _uart_interrupt_enable
<> 144:ef7eb2e8f9f7 92 {
<> 144:ef7eb2e8f9f7 93 #if defined(FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT
<> 144:ef7eb2e8f9f7 94 kUART_LinBreakInterruptEnable = (UART_BDH_LBKDIE_MASK), /*!< LIN break detect interrupt. */
<> 144:ef7eb2e8f9f7 95 #endif
<> 144:ef7eb2e8f9f7 96 kUART_RxActiveEdgeInterruptEnable = (UART_BDH_RXEDGIE_MASK), /*!< RX active edge interrupt. */
<> 144:ef7eb2e8f9f7 97 kUART_TxDataRegEmptyInterruptEnable = (UART_C2_TIE_MASK << 8), /*!< Transmit data register empty interrupt. */
<> 144:ef7eb2e8f9f7 98 kUART_TransmissionCompleteInterruptEnable = (UART_C2_TCIE_MASK << 8), /*!< Transmission complete interrupt. */
<> 144:ef7eb2e8f9f7 99 kUART_RxDataRegFullInterruptEnable = (UART_C2_RIE_MASK << 8), /*!< Receiver data register full interrupt. */
<> 144:ef7eb2e8f9f7 100 kUART_IdleLineInterruptEnable = (UART_C2_ILIE_MASK << 8), /*!< Idle line interrupt. */
<> 144:ef7eb2e8f9f7 101 kUART_RxOverrunInterruptEnable = (UART_C3_ORIE_MASK << 16), /*!< Receiver overrun interrupt. */
<> 144:ef7eb2e8f9f7 102 kUART_NoiseErrorInterruptEnable = (UART_C3_NEIE_MASK << 16), /*!< Noise error flag interrupt. */
<> 144:ef7eb2e8f9f7 103 kUART_FramingErrorInterruptEnable = (UART_C3_FEIE_MASK << 16), /*!< Framing error flag interrupt. */
<> 144:ef7eb2e8f9f7 104 kUART_ParityErrorInterruptEnable = (UART_C3_PEIE_MASK << 16), /*!< Parity error flag interrupt. */
<> 144:ef7eb2e8f9f7 105 #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
<> 144:ef7eb2e8f9f7 106 kUART_RxFifoOverflowInterruptEnable = (UART_CFIFO_TXOFE_MASK << 24), /*!< TX FIFO overflow interrupt. */
<> 144:ef7eb2e8f9f7 107 kUART_TxFifoOverflowInterruptEnable = (UART_CFIFO_RXUFE_MASK << 24), /*!< RX FIFO underflow interrupt. */
<> 144:ef7eb2e8f9f7 108 kUART_RxFifoUnderflowInterruptEnable = (UART_CFIFO_RXUFE_MASK << 24), /*!< RX FIFO underflow interrupt. */
<> 144:ef7eb2e8f9f7 109 #endif
<> 144:ef7eb2e8f9f7 110 };
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 /*!
<> 144:ef7eb2e8f9f7 113 * @brief UART status flags.
<> 144:ef7eb2e8f9f7 114 *
<> 144:ef7eb2e8f9f7 115 * This provides constants for the UART status flags for use in the UART functions.
<> 144:ef7eb2e8f9f7 116 */
<> 144:ef7eb2e8f9f7 117 enum _uart_flags
<> 144:ef7eb2e8f9f7 118 {
<> 144:ef7eb2e8f9f7 119 kUART_TxDataRegEmptyFlag = (UART_S1_TDRE_MASK), /*!< TX data register empty flag. */
<> 144:ef7eb2e8f9f7 120 kUART_TransmissionCompleteFlag = (UART_S1_TC_MASK), /*!< Transmission complete flag. */
<> 144:ef7eb2e8f9f7 121 kUART_RxDataRegFullFlag = (UART_S1_RDRF_MASK), /*!< RX data register full flag. */
<> 144:ef7eb2e8f9f7 122 kUART_IdleLineFlag = (UART_S1_IDLE_MASK), /*!< Idle line detect flag. */
<> 144:ef7eb2e8f9f7 123 kUART_RxOverrunFlag = (UART_S1_OR_MASK), /*!< RX overrun flag. */
<> 144:ef7eb2e8f9f7 124 kUART_NoiseErrorFlag = (UART_S1_NF_MASK), /*!< RX takes 3 samples of each received bit.
<> 144:ef7eb2e8f9f7 125 If any of these samples differ, noise flag sets */
<> 144:ef7eb2e8f9f7 126 kUART_FramingErrorFlag = (UART_S1_FE_MASK), /*!< Frame error flag, sets if logic 0 was detected
<> 144:ef7eb2e8f9f7 127 where stop bit expected */
<> 144:ef7eb2e8f9f7 128 kUART_ParityErrorFlag = (UART_S1_PF_MASK), /*!< If parity enabled, sets upon parity error detection */
<> 144:ef7eb2e8f9f7 129 #if defined(FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT
<> 144:ef7eb2e8f9f7 130 kUART_LinBreakFlag =
<> 144:ef7eb2e8f9f7 131 (UART_S2_LBKDIF_MASK << 8), /*!< LIN break detect interrupt flag, sets when
<> 144:ef7eb2e8f9f7 132 LIN break char detected and LIN circuit enabled */
<> 144:ef7eb2e8f9f7 133 #endif
<> 144:ef7eb2e8f9f7 134 kUART_RxActiveEdgeFlag = (UART_S2_RXEDGIF_MASK << 8), /*!< RX pin active edge interrupt flag,
<> 144:ef7eb2e8f9f7 135 sets when active edge detected */
<> 144:ef7eb2e8f9f7 136 kUART_RxActiveFlag = (UART_S2_RAF_MASK << 8), /*!< Receiver Active Flag (RAF),
<> 144:ef7eb2e8f9f7 137 sets at beginning of valid start bit */
<> 144:ef7eb2e8f9f7 138 #if defined(FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS) && FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS
<> 144:ef7eb2e8f9f7 139 kUART_NoiseErrorInRxDataRegFlag = (UART_ED_NOISY_MASK << 16), /*!< Noisy bit, sets if noise detected. */
<> 144:ef7eb2e8f9f7 140 kUART_ParityErrorInRxDataRegFlag = (UART_ED_PARITYE_MASK << 16), /*!< Paritye bit, sets if parity error detected. */
<> 144:ef7eb2e8f9f7 141 #endif
<> 144:ef7eb2e8f9f7 142 #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
<> 144:ef7eb2e8f9f7 143 kUART_TxFifoEmptyFlag = (UART_SFIFO_TXEMPT_MASK << 24), /*!< TXEMPT bit, sets if TX buffer is empty */
<> 144:ef7eb2e8f9f7 144 kUART_RxFifoEmptyFlag = (UART_SFIFO_RXEMPT_MASK << 24), /*!< RXEMPT bit, sets if RX buffer is empty */
<> 144:ef7eb2e8f9f7 145 kUART_TxFifoOverflowFlag = (UART_SFIFO_TXOF_MASK << 24), /*!< TXOF bit, sets if TX buffer overflow occurred */
<> 144:ef7eb2e8f9f7 146 kUART_RxFifoOverflowFlag = (UART_SFIFO_RXOF_MASK << 24), /*!< RXOF bit, sets if receive buffer overflow */
<> 144:ef7eb2e8f9f7 147 kUART_RxFifoUnderflowFlag = (UART_SFIFO_RXUF_MASK << 24), /*!< RXUF bit, sets if receive buffer underflow */
<> 144:ef7eb2e8f9f7 148 #endif
<> 144:ef7eb2e8f9f7 149 };
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 /*! @brief UART configuration structure. */
<> 144:ef7eb2e8f9f7 152 typedef struct _uart_config
<> 144:ef7eb2e8f9f7 153 {
<> 144:ef7eb2e8f9f7 154 uint32_t baudRate_Bps; /*!< UART baud rate */
<> 144:ef7eb2e8f9f7 155 uart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */
<> 144:ef7eb2e8f9f7 156 #if defined(FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT
<> 144:ef7eb2e8f9f7 157 uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */
<> 144:ef7eb2e8f9f7 158 #endif
<> 144:ef7eb2e8f9f7 159 #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
<> 144:ef7eb2e8f9f7 160 uint8_t txFifoWatermark; /*!< TX FIFO watermark */
<> 144:ef7eb2e8f9f7 161 uint8_t rxFifoWatermark; /*!< RX FIFO watermark */
<> 144:ef7eb2e8f9f7 162 #endif
<> 144:ef7eb2e8f9f7 163 bool enableTx; /*!< Enable TX */
<> 144:ef7eb2e8f9f7 164 bool enableRx; /*!< Enable RX */
<> 144:ef7eb2e8f9f7 165 } uart_config_t;
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 /*! @brief UART transfer structure. */
<> 144:ef7eb2e8f9f7 168 typedef struct _uart_transfer
<> 144:ef7eb2e8f9f7 169 {
<> 144:ef7eb2e8f9f7 170 uint8_t *data; /*!< The buffer of data to be transfer.*/
<> 144:ef7eb2e8f9f7 171 size_t dataSize; /*!< The byte count to be transfer. */
<> 144:ef7eb2e8f9f7 172 } uart_transfer_t;
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 /* Forward declaration of the handle typedef. */
<> 144:ef7eb2e8f9f7 175 typedef struct _uart_handle uart_handle_t;
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 /*! @brief UART transfer callback function. */
<> 144:ef7eb2e8f9f7 178 typedef void (*uart_transfer_callback_t)(UART_Type *base, uart_handle_t *handle, status_t status, void *userData);
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 /*! @brief UART handle structure. */
<> 144:ef7eb2e8f9f7 181 struct _uart_handle
<> 144:ef7eb2e8f9f7 182 {
<> 144:ef7eb2e8f9f7 183 uint8_t *volatile txData; /*!< Address of remaining data to send. */
<> 144:ef7eb2e8f9f7 184 volatile size_t txDataSize; /*!< Size of the remaining data to send. */
<> 144:ef7eb2e8f9f7 185 size_t txDataSizeAll; /*!< Size of the data to send out. */
<> 144:ef7eb2e8f9f7 186 uint8_t *volatile rxData; /*!< Address of remaining data to receive. */
<> 144:ef7eb2e8f9f7 187 volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */
<> 144:ef7eb2e8f9f7 188 size_t rxDataSizeAll; /*!< Size of the data to receive. */
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */
<> 144:ef7eb2e8f9f7 191 size_t rxRingBufferSize; /*!< Size of the ring buffer. */
<> 144:ef7eb2e8f9f7 192 volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */
<> 144:ef7eb2e8f9f7 193 volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 uart_transfer_callback_t callback; /*!< Callback function. */
<> 144:ef7eb2e8f9f7 196 void *userData; /*!< UART callback function parameter.*/
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 volatile uint8_t txState; /*!< TX transfer state. */
<> 144:ef7eb2e8f9f7 199 volatile uint8_t rxState; /*!< RX transfer state */
<> 144:ef7eb2e8f9f7 200 };
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 /*******************************************************************************
<> 144:ef7eb2e8f9f7 203 * API
<> 144:ef7eb2e8f9f7 204 ******************************************************************************/
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 #if defined(__cplusplus)
<> 144:ef7eb2e8f9f7 207 extern "C" {
<> 144:ef7eb2e8f9f7 208 #endif /* _cplusplus */
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 /*!
<> 144:ef7eb2e8f9f7 211 * @name Initialization and deinitialization
<> 144:ef7eb2e8f9f7 212 * @{
<> 144:ef7eb2e8f9f7 213 */
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 /*!
<> 144:ef7eb2e8f9f7 216 * @brief Initializes a UART instance with user configuration structure and peripheral clock.
<> 144:ef7eb2e8f9f7 217 *
<> 144:ef7eb2e8f9f7 218 * This function configures the UART module with the user-defined settings. The user can configure the configuration
<> 144:ef7eb2e8f9f7 219 * structure and also get the default configuration by using the UART_GetDefaultConfig() function.
<> 144:ef7eb2e8f9f7 220 * Example below shows how to use this API to configure UART.
<> 144:ef7eb2e8f9f7 221 * @code
<> 144:ef7eb2e8f9f7 222 * uart_config_t uartConfig;
<> 144:ef7eb2e8f9f7 223 * uartConfig.baudRate_Bps = 115200U;
<> 144:ef7eb2e8f9f7 224 * uartConfig.parityMode = kUART_ParityDisabled;
<> 144:ef7eb2e8f9f7 225 * uartConfig.stopBitCount = kUART_OneStopBit;
<> 144:ef7eb2e8f9f7 226 * uartConfig.txFifoWatermark = 0;
<> 144:ef7eb2e8f9f7 227 * uartConfig.rxFifoWatermark = 1;
<> 144:ef7eb2e8f9f7 228 * UART_Init(UART1, &uartConfig, 20000000U);
<> 144:ef7eb2e8f9f7 229 * @endcode
<> 144:ef7eb2e8f9f7 230 *
<> 144:ef7eb2e8f9f7 231 * @param base UART peripheral base address.
<> 144:ef7eb2e8f9f7 232 * @param config Pointer to user-defined configuration structure.
<> 144:ef7eb2e8f9f7 233 * @param srcClock_Hz UART clock source frequency in HZ.
<> 144:ef7eb2e8f9f7 234 */
<> 144:ef7eb2e8f9f7 235 void UART_Init(UART_Type *base, const uart_config_t *config, uint32_t srcClock_Hz);
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 /*!
<> 144:ef7eb2e8f9f7 238 * @brief Deinitializes a UART instance.
<> 144:ef7eb2e8f9f7 239 *
<> 144:ef7eb2e8f9f7 240 * This function waits for TX complete, disables TX and RX, and disables the UART clock.
<> 144:ef7eb2e8f9f7 241 *
<> 144:ef7eb2e8f9f7 242 * @param base UART peripheral base address.
<> 144:ef7eb2e8f9f7 243 */
<> 144:ef7eb2e8f9f7 244 void UART_Deinit(UART_Type *base);
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 /*!
<> 144:ef7eb2e8f9f7 247 * @brief Gets the default configuration structure.
<> 144:ef7eb2e8f9f7 248 *
<> 144:ef7eb2e8f9f7 249 * This function initializes the UART configuration structure to a default value. The default
<> 144:ef7eb2e8f9f7 250 * values are:
<> 144:ef7eb2e8f9f7 251 * uartConfig->baudRate_Bps = 115200U;
<> 144:ef7eb2e8f9f7 252 * uartConfig->bitCountPerChar = kUART_8BitsPerChar;
<> 144:ef7eb2e8f9f7 253 * uartConfig->parityMode = kUART_ParityDisabled;
<> 144:ef7eb2e8f9f7 254 * uartConfig->stopBitCount = kUART_OneStopBit;
<> 144:ef7eb2e8f9f7 255 * uartConfig->txFifoWatermark = 0;
<> 144:ef7eb2e8f9f7 256 * uartConfig->rxFifoWatermark = 1;
<> 144:ef7eb2e8f9f7 257 * uartConfig->enableTx = false;
<> 144:ef7eb2e8f9f7 258 * uartConfig->enableRx = false;
<> 144:ef7eb2e8f9f7 259 *
<> 144:ef7eb2e8f9f7 260 * @param config Pointer to configuration structure.
<> 144:ef7eb2e8f9f7 261 */
<> 144:ef7eb2e8f9f7 262 void UART_GetDefaultConfig(uart_config_t *config);
<> 144:ef7eb2e8f9f7 263
<> 144:ef7eb2e8f9f7 264 /*!
<> 144:ef7eb2e8f9f7 265 * @brief Sets the UART instance baud rate.
<> 144:ef7eb2e8f9f7 266 *
<> 144:ef7eb2e8f9f7 267 * This function configures the UART module baud rate. This function is used to update
<> 144:ef7eb2e8f9f7 268 * the UART module baud rate after the UART module is initialized by the UART_Init.
<> 144:ef7eb2e8f9f7 269 * @code
<> 144:ef7eb2e8f9f7 270 * UART_SetBaudRate(UART1, 115200U, 20000000U);
<> 144:ef7eb2e8f9f7 271 * @endcode
<> 144:ef7eb2e8f9f7 272 *
<> 144:ef7eb2e8f9f7 273 * @param base UART peripheral base address.
<> 144:ef7eb2e8f9f7 274 * @param baudRate_Bps UART baudrate to be set.
<> 144:ef7eb2e8f9f7 275 * @param srcClock_Hz UART clock source freqency in HZ.
<> 144:ef7eb2e8f9f7 276 */
<> 144:ef7eb2e8f9f7 277 void UART_SetBaudRate(UART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz);
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 /* @} */
<> 144:ef7eb2e8f9f7 280
<> 144:ef7eb2e8f9f7 281 /*!
<> 144:ef7eb2e8f9f7 282 * @name Status
<> 144:ef7eb2e8f9f7 283 * @{
<> 144:ef7eb2e8f9f7 284 */
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 /*!
<> 144:ef7eb2e8f9f7 287 * @brief Get UART status flags.
<> 144:ef7eb2e8f9f7 288 *
<> 144:ef7eb2e8f9f7 289 * This function get all UART status flags, the flags are returned as the logical
<> 144:ef7eb2e8f9f7 290 * OR value of the enumerators @ref _uart_flags. To check specific status,
<> 144:ef7eb2e8f9f7 291 * compare the return value with enumerators in @ref _uart_flags.
<> 144:ef7eb2e8f9f7 292 * For example, to check whether the TX is empty:
<> 144:ef7eb2e8f9f7 293 * @code
<> 144:ef7eb2e8f9f7 294 * if (kUART_TxDataRegEmptyFlag & UART_GetStatusFlags(UART1))
<> 144:ef7eb2e8f9f7 295 * {
<> 144:ef7eb2e8f9f7 296 * ...
<> 144:ef7eb2e8f9f7 297 * }
<> 144:ef7eb2e8f9f7 298 * @endcode
<> 144:ef7eb2e8f9f7 299 *
<> 144:ef7eb2e8f9f7 300 * @param base UART peripheral base address.
<> 144:ef7eb2e8f9f7 301 * @return UART status flags which are ORed by the enumerators in the _uart_flags.
<> 144:ef7eb2e8f9f7 302 */
<> 144:ef7eb2e8f9f7 303 uint32_t UART_GetStatusFlags(UART_Type *base);
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 /*!
<> 144:ef7eb2e8f9f7 306 * @brief Clears status flags with the provided mask.
<> 144:ef7eb2e8f9f7 307 *
<> 144:ef7eb2e8f9f7 308 * This function clears UART status flags with a provided mask. Automatically cleared flag
<> 144:ef7eb2e8f9f7 309 * can't be cleared by this function.
<> 144:ef7eb2e8f9f7 310 * Some flags can only be cleared or set by hardware itself. These flags are:
<> 144:ef7eb2e8f9f7 311 * kUART_TxDataRegEmptyFlag, kUART_TransmissionCompleteFlag, kUART_RxDataRegFullFlag,
<> 144:ef7eb2e8f9f7 312 * kUART_RxActiveFlag, kUART_NoiseErrorInRxDataRegFlag, kUART_ParityErrorInRxDataRegFlag,
<> 144:ef7eb2e8f9f7 313 * kUART_TxFifoEmptyFlag,kUART_RxFifoEmptyFlag
<> 144:ef7eb2e8f9f7 314 * Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects.
<> 144:ef7eb2e8f9f7 315 *
<> 144:ef7eb2e8f9f7 316 * @param base UART peripheral base address.
<> 144:ef7eb2e8f9f7 317 * @param mask The status flags to be cleared, it is logical OR value of @ref _uart_flags.
<> 144:ef7eb2e8f9f7 318 * @retval kStatus_UART_FlagCannotClearManually The flag can't be cleared by this function but
<> 144:ef7eb2e8f9f7 319 * it is cleared automatically by hardware.
<> 144:ef7eb2e8f9f7 320 * @retval kStatus_Success Status in the mask are cleared.
<> 144:ef7eb2e8f9f7 321 */
<> 144:ef7eb2e8f9f7 322 status_t UART_ClearStatusFlags(UART_Type *base, uint32_t mask);
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 /* @} */
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 /*!
<> 144:ef7eb2e8f9f7 327 * @name Interrupts
<> 144:ef7eb2e8f9f7 328 * @{
<> 144:ef7eb2e8f9f7 329 */
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 /*!
<> 144:ef7eb2e8f9f7 332 * @brief Enables UART interrupts according to the provided mask.
<> 144:ef7eb2e8f9f7 333 *
<> 144:ef7eb2e8f9f7 334 * This function enables the UART interrupts according to the provided mask. The mask
<> 144:ef7eb2e8f9f7 335 * is a logical OR of enumeration members. See @ref _uart_interrupt_enable.
<> 144:ef7eb2e8f9f7 336 * For example, to enable TX empty interrupt and RX full interrupt:
<> 144:ef7eb2e8f9f7 337 * @code
<> 144:ef7eb2e8f9f7 338 * UART_EnableInterrupts(UART1,kUART_TxDataRegEmptyInterruptEnable | kUART_RxDataRegFullInterruptEnable);
<> 144:ef7eb2e8f9f7 339 * @endcode
<> 144:ef7eb2e8f9f7 340 *
<> 144:ef7eb2e8f9f7 341 * @param base UART peripheral base address.
<> 144:ef7eb2e8f9f7 342 * @param mask The interrupts to enable. Logical OR of @ref _uart_interrupt_enable.
<> 144:ef7eb2e8f9f7 343 */
<> 144:ef7eb2e8f9f7 344 void UART_EnableInterrupts(UART_Type *base, uint32_t mask);
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 /*!
<> 144:ef7eb2e8f9f7 347 * @brief Disables the UART interrupts according to the provided mask.
<> 144:ef7eb2e8f9f7 348 *
<> 144:ef7eb2e8f9f7 349 * This function disables the UART interrupts according to the provided mask. The mask
<> 144:ef7eb2e8f9f7 350 * is a logical OR of enumeration members. See @ref _uart_interrupt_enable.
<> 144:ef7eb2e8f9f7 351 * For example, to disable TX empty interrupt and RX full interrupt:
<> 144:ef7eb2e8f9f7 352 * @code
<> 144:ef7eb2e8f9f7 353 * UART_DisableInterrupts(UART1,kUART_TxDataRegEmptyInterruptEnable | kUART_RxDataRegFullInterruptEnable);
<> 144:ef7eb2e8f9f7 354 * @endcode
<> 144:ef7eb2e8f9f7 355 *
<> 144:ef7eb2e8f9f7 356 * @param base UART peripheral base address.
<> 144:ef7eb2e8f9f7 357 * @param mask The interrupts to disable. Logical OR of @ref _uart_interrupt_enable.
<> 144:ef7eb2e8f9f7 358 */
<> 144:ef7eb2e8f9f7 359 void UART_DisableInterrupts(UART_Type *base, uint32_t mask);
<> 144:ef7eb2e8f9f7 360
<> 144:ef7eb2e8f9f7 361 /*!
<> 144:ef7eb2e8f9f7 362 * @brief Gets the enabled UART interrupts.
<> 144:ef7eb2e8f9f7 363 *
<> 144:ef7eb2e8f9f7 364 * This function gets the enabled UART interrupts. The enabled interrupts are returned
<> 144:ef7eb2e8f9f7 365 * as the logical OR value of the enumerators @ref _uart_interrupt_enable. To check
<> 144:ef7eb2e8f9f7 366 * specific interrupts enable status, compare the return value with enumerators
<> 144:ef7eb2e8f9f7 367 * in @ref _uart_interrupt_enable.
<> 144:ef7eb2e8f9f7 368 * For example, to check whether TX empty interrupt is enabled:
<> 144:ef7eb2e8f9f7 369 * @code
<> 144:ef7eb2e8f9f7 370 * uint32_t enabledInterrupts = UART_GetEnabledInterrupts(UART1);
<> 144:ef7eb2e8f9f7 371 *
<> 144:ef7eb2e8f9f7 372 * if (kUART_TxDataRegEmptyInterruptEnable & enabledInterrupts)
<> 144:ef7eb2e8f9f7 373 * {
<> 144:ef7eb2e8f9f7 374 * ...
<> 144:ef7eb2e8f9f7 375 * }
<> 144:ef7eb2e8f9f7 376 * @endcode
<> 144:ef7eb2e8f9f7 377 *
<> 144:ef7eb2e8f9f7 378 * @param base UART peripheral base address.
<> 144:ef7eb2e8f9f7 379 * @return UART interrupt flags which are logical OR of the enumerators in @ref _uart_interrupt_enable.
<> 144:ef7eb2e8f9f7 380 */
<> 144:ef7eb2e8f9f7 381 uint32_t UART_GetEnabledInterrupts(UART_Type *base);
<> 144:ef7eb2e8f9f7 382
<> 144:ef7eb2e8f9f7 383 /* @} */
<> 144:ef7eb2e8f9f7 384
<> 144:ef7eb2e8f9f7 385 #if defined(FSL_FEATURE_UART_HAS_DMA_SELECT) && FSL_FEATURE_UART_HAS_DMA_SELECT
<> 144:ef7eb2e8f9f7 386 /*!
<> 144:ef7eb2e8f9f7 387 * @name DMA Control
<> 144:ef7eb2e8f9f7 388 * @{
<> 144:ef7eb2e8f9f7 389 */
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 /*!
<> 144:ef7eb2e8f9f7 392 * @brief Gets the UART data register address.
<> 144:ef7eb2e8f9f7 393 *
<> 144:ef7eb2e8f9f7 394 * This function returns the UART data register address, which is mainly used by DMA/eDMA.
<> 144:ef7eb2e8f9f7 395 *
<> 144:ef7eb2e8f9f7 396 * @param base UART peripheral base address.
<> 144:ef7eb2e8f9f7 397 * @return UART data register address which are used both by transmitter and receiver.
<> 144:ef7eb2e8f9f7 398 */
<> 144:ef7eb2e8f9f7 399 static inline uint32_t UART_GetDataRegisterAddress(UART_Type *base)
<> 144:ef7eb2e8f9f7 400 {
<> 144:ef7eb2e8f9f7 401 return (uint32_t) & (base->D);
<> 144:ef7eb2e8f9f7 402 }
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404 /*!
<> 144:ef7eb2e8f9f7 405 * @brief Enables or disables the UART transmitter DMA request.
<> 144:ef7eb2e8f9f7 406 *
<> 144:ef7eb2e8f9f7 407 * This function enables or disables the transmit data register empty flag, S1[TDRE], to generate the DMA requests.
<> 144:ef7eb2e8f9f7 408 *
<> 144:ef7eb2e8f9f7 409 * @param base UART peripheral base address.
<> 144:ef7eb2e8f9f7 410 * @param enable True to enable, false to disable.
<> 144:ef7eb2e8f9f7 411 */
<> 144:ef7eb2e8f9f7 412 static inline void UART_EnableTxDMA(UART_Type *base, bool enable)
<> 144:ef7eb2e8f9f7 413 {
<> 144:ef7eb2e8f9f7 414 if (enable)
<> 144:ef7eb2e8f9f7 415 {
<> 144:ef7eb2e8f9f7 416 #if (defined(FSL_FEATURE_UART_IS_SCI) && FSL_FEATURE_UART_IS_SCI)
<> 144:ef7eb2e8f9f7 417 base->C4 |= UART_C4_TDMAS_MASK;
<> 144:ef7eb2e8f9f7 418 #else
<> 144:ef7eb2e8f9f7 419 base->C5 |= UART_C5_TDMAS_MASK;
<> 144:ef7eb2e8f9f7 420 #endif
<> 144:ef7eb2e8f9f7 421 base->C2 |= UART_C2_TIE_MASK;
<> 144:ef7eb2e8f9f7 422 }
<> 144:ef7eb2e8f9f7 423 else
<> 144:ef7eb2e8f9f7 424 {
<> 144:ef7eb2e8f9f7 425 #if (defined(FSL_FEATURE_UART_IS_SCI) && FSL_FEATURE_UART_IS_SCI)
<> 144:ef7eb2e8f9f7 426 base->C4 &= ~UART_C4_TDMAS_MASK;
<> 144:ef7eb2e8f9f7 427 #else
<> 144:ef7eb2e8f9f7 428 base->C5 &= ~UART_C5_TDMAS_MASK;
<> 144:ef7eb2e8f9f7 429 #endif
<> 144:ef7eb2e8f9f7 430 base->C2 &= ~UART_C2_TIE_MASK;
<> 144:ef7eb2e8f9f7 431 }
<> 144:ef7eb2e8f9f7 432 }
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434 /*!
<> 144:ef7eb2e8f9f7 435 * @brief Enables or disables the UART receiver DMA.
<> 144:ef7eb2e8f9f7 436 *
<> 144:ef7eb2e8f9f7 437 * This function enables or disables the receiver data register full flag, S1[RDRF], to generate DMA requests.
<> 144:ef7eb2e8f9f7 438 *
<> 144:ef7eb2e8f9f7 439 * @param base UART peripheral base address.
<> 144:ef7eb2e8f9f7 440 * @param enable True to enable, false to disable.
<> 144:ef7eb2e8f9f7 441 */
<> 144:ef7eb2e8f9f7 442 static inline void UART_EnableRxDMA(UART_Type *base, bool enable)
<> 144:ef7eb2e8f9f7 443 {
<> 144:ef7eb2e8f9f7 444 if (enable)
<> 144:ef7eb2e8f9f7 445 {
<> 144:ef7eb2e8f9f7 446 #if (defined(FSL_FEATURE_UART_IS_SCI) && FSL_FEATURE_UART_IS_SCI)
<> 144:ef7eb2e8f9f7 447 base->C4 |= UART_C4_RDMAS_MASK;
<> 144:ef7eb2e8f9f7 448 #else
<> 144:ef7eb2e8f9f7 449 base->C5 |= UART_C5_RDMAS_MASK;
<> 144:ef7eb2e8f9f7 450 #endif
<> 144:ef7eb2e8f9f7 451 base->C2 |= UART_C2_RIE_MASK;
<> 144:ef7eb2e8f9f7 452 }
<> 144:ef7eb2e8f9f7 453 else
<> 144:ef7eb2e8f9f7 454 {
<> 144:ef7eb2e8f9f7 455 #if (defined(FSL_FEATURE_UART_IS_SCI) && FSL_FEATURE_UART_IS_SCI)
<> 144:ef7eb2e8f9f7 456 base->C4 &= ~UART_C4_RDMAS_MASK;
<> 144:ef7eb2e8f9f7 457 #else
<> 144:ef7eb2e8f9f7 458 base->C5 &= ~UART_C5_RDMAS_MASK;
<> 144:ef7eb2e8f9f7 459 #endif
<> 144:ef7eb2e8f9f7 460 base->C2 &= ~UART_C2_RIE_MASK;
<> 144:ef7eb2e8f9f7 461 }
<> 144:ef7eb2e8f9f7 462 }
<> 144:ef7eb2e8f9f7 463
<> 144:ef7eb2e8f9f7 464 /* @} */
<> 144:ef7eb2e8f9f7 465 #endif /* FSL_FEATURE_UART_HAS_DMA_SELECT */
<> 144:ef7eb2e8f9f7 466
<> 144:ef7eb2e8f9f7 467 /*!
<> 144:ef7eb2e8f9f7 468 * @name Bus Operations
<> 144:ef7eb2e8f9f7 469 * @{
<> 144:ef7eb2e8f9f7 470 */
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 /*!
<> 144:ef7eb2e8f9f7 473 * @brief Enables or disables the UART transmitter.
<> 144:ef7eb2e8f9f7 474 *
<> 144:ef7eb2e8f9f7 475 * This function enables or disables the UART transmitter.
<> 144:ef7eb2e8f9f7 476 *
<> 144:ef7eb2e8f9f7 477 * @param base UART peripheral base address.
<> 144:ef7eb2e8f9f7 478 * @param enable True to enable, false to disable.
<> 144:ef7eb2e8f9f7 479 */
<> 144:ef7eb2e8f9f7 480 static inline void UART_EnableTx(UART_Type *base, bool enable)
<> 144:ef7eb2e8f9f7 481 {
<> 144:ef7eb2e8f9f7 482 if (enable)
<> 144:ef7eb2e8f9f7 483 {
<> 144:ef7eb2e8f9f7 484 base->C2 |= UART_C2_TE_MASK;
<> 144:ef7eb2e8f9f7 485 }
<> 144:ef7eb2e8f9f7 486 else
<> 144:ef7eb2e8f9f7 487 {
<> 144:ef7eb2e8f9f7 488 base->C2 &= ~UART_C2_TE_MASK;
<> 144:ef7eb2e8f9f7 489 }
<> 144:ef7eb2e8f9f7 490 }
<> 144:ef7eb2e8f9f7 491
<> 144:ef7eb2e8f9f7 492 /*!
<> 144:ef7eb2e8f9f7 493 * @brief Enables or disables the UART receiver.
<> 144:ef7eb2e8f9f7 494 *
<> 144:ef7eb2e8f9f7 495 * This function enables or disables the UART receiver.
<> 144:ef7eb2e8f9f7 496 *
<> 144:ef7eb2e8f9f7 497 * @param base UART peripheral base address.
<> 144:ef7eb2e8f9f7 498 * @param enable True to enable, false to disable.
<> 144:ef7eb2e8f9f7 499 */
<> 144:ef7eb2e8f9f7 500 static inline void UART_EnableRx(UART_Type *base, bool enable)
<> 144:ef7eb2e8f9f7 501 {
<> 144:ef7eb2e8f9f7 502 if (enable)
<> 144:ef7eb2e8f9f7 503 {
<> 144:ef7eb2e8f9f7 504 base->C2 |= UART_C2_RE_MASK;
<> 144:ef7eb2e8f9f7 505 }
<> 144:ef7eb2e8f9f7 506 else
<> 144:ef7eb2e8f9f7 507 {
<> 144:ef7eb2e8f9f7 508 base->C2 &= ~UART_C2_RE_MASK;
<> 144:ef7eb2e8f9f7 509 }
<> 144:ef7eb2e8f9f7 510 }
<> 144:ef7eb2e8f9f7 511
<> 144:ef7eb2e8f9f7 512 /*!
<> 144:ef7eb2e8f9f7 513 * @brief Writes to the TX register.
<> 144:ef7eb2e8f9f7 514 *
<> 144:ef7eb2e8f9f7 515 * This function writes data to the TX register directly. The upper layer must ensure
<> 144:ef7eb2e8f9f7 516 * that the TX register is empty or TX FIFO has empty room before calling this function.
<> 144:ef7eb2e8f9f7 517 *
<> 144:ef7eb2e8f9f7 518 * @param base UART peripheral base address.
<> 144:ef7eb2e8f9f7 519 * @param data The byte to write.
<> 144:ef7eb2e8f9f7 520 */
<> 144:ef7eb2e8f9f7 521 static inline void UART_WriteByte(UART_Type *base, uint8_t data)
<> 144:ef7eb2e8f9f7 522 {
<> 144:ef7eb2e8f9f7 523 base->D = data;
<> 144:ef7eb2e8f9f7 524 }
<> 144:ef7eb2e8f9f7 525
<> 144:ef7eb2e8f9f7 526 /*!
<> 144:ef7eb2e8f9f7 527 * @brief Reads the RX register directly.
<> 144:ef7eb2e8f9f7 528 *
<> 144:ef7eb2e8f9f7 529 * This function reads data from the TX register directly. The upper layer must
<> 144:ef7eb2e8f9f7 530 * ensure that the RX register is full or that the TX FIFO has data before calling this function.
<> 144:ef7eb2e8f9f7 531 *
<> 144:ef7eb2e8f9f7 532 * @param base UART peripheral base address.
<> 144:ef7eb2e8f9f7 533 * @return The byte read from UART data register.
<> 144:ef7eb2e8f9f7 534 */
<> 144:ef7eb2e8f9f7 535 static inline uint8_t UART_ReadByte(UART_Type *base)
<> 144:ef7eb2e8f9f7 536 {
<> 144:ef7eb2e8f9f7 537 return base->D;
<> 144:ef7eb2e8f9f7 538 }
<> 144:ef7eb2e8f9f7 539
<> 144:ef7eb2e8f9f7 540 /*!
<> 144:ef7eb2e8f9f7 541 * @brief Writes to the TX register using a blocking method.
<> 144:ef7eb2e8f9f7 542 *
<> 144:ef7eb2e8f9f7 543 * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO
<> 144:ef7eb2e8f9f7 544 * to have room and writes data to the TX buffer.
<> 144:ef7eb2e8f9f7 545 *
<> 144:ef7eb2e8f9f7 546 * @note This function does not check whether all the data has been sent out to the bus.
<> 144:ef7eb2e8f9f7 547 * Before disabling the TX, check kUART_TransmissionCompleteFlag to ensure that the TX is
<> 144:ef7eb2e8f9f7 548 * finished.
<> 144:ef7eb2e8f9f7 549 *
<> 144:ef7eb2e8f9f7 550 * @param base UART peripheral base address.
<> 144:ef7eb2e8f9f7 551 * @param data Start address of the data to write.
<> 144:ef7eb2e8f9f7 552 * @param length Size of the data to write.
<> 144:ef7eb2e8f9f7 553 */
<> 144:ef7eb2e8f9f7 554 void UART_WriteBlocking(UART_Type *base, const uint8_t *data, size_t length);
<> 144:ef7eb2e8f9f7 555
<> 144:ef7eb2e8f9f7 556 /*!
<> 144:ef7eb2e8f9f7 557 * @brief Read RX data register using a blocking method.
<> 144:ef7eb2e8f9f7 558 *
<> 144:ef7eb2e8f9f7 559 * This function polls the RX register, waits for the RX register to be full or for RX FIFO to
<> 144:ef7eb2e8f9f7 560 * have data and read data from the TX register.
<> 144:ef7eb2e8f9f7 561 *
<> 144:ef7eb2e8f9f7 562 * @param base UART peripheral base address.
<> 144:ef7eb2e8f9f7 563 * @param data Start address of the buffer to store the received data.
<> 144:ef7eb2e8f9f7 564 * @param length Size of the buffer.
<> 144:ef7eb2e8f9f7 565 * @retval kStatus_UART_RxHardwareOverrun Receiver overrun happened while receiving data.
<> 144:ef7eb2e8f9f7 566 * @retval kStatus_UART_NoiseError Noise error happened while receiving data.
<> 144:ef7eb2e8f9f7 567 * @retval kStatus_UART_FramingError Framing error happened while receiving data.
<> 144:ef7eb2e8f9f7 568 * @retval kStatus_UART_ParityError Parity error happened while receiving data.
<> 144:ef7eb2e8f9f7 569 * @retval kStatus_Success Successfully received all data.
<> 144:ef7eb2e8f9f7 570 */
<> 144:ef7eb2e8f9f7 571 status_t UART_ReadBlocking(UART_Type *base, uint8_t *data, size_t length);
<> 144:ef7eb2e8f9f7 572
<> 144:ef7eb2e8f9f7 573 /* @} */
<> 144:ef7eb2e8f9f7 574
<> 144:ef7eb2e8f9f7 575 /*!
<> 144:ef7eb2e8f9f7 576 * @name Transactional
<> 144:ef7eb2e8f9f7 577 * @{
<> 144:ef7eb2e8f9f7 578 */
<> 144:ef7eb2e8f9f7 579
<> 144:ef7eb2e8f9f7 580 /*!
<> 144:ef7eb2e8f9f7 581 * @brief Initializes the UART handle.
<> 144:ef7eb2e8f9f7 582 *
<> 144:ef7eb2e8f9f7 583 * This function initializes the UART handle which can be used for other UART
<> 144:ef7eb2e8f9f7 584 * transactional APIs. Usually, for a specified UART instance,
<> 144:ef7eb2e8f9f7 585 * call this API once to get the initialized handle.
<> 144:ef7eb2e8f9f7 586 *
<> 144:ef7eb2e8f9f7 587 * @param base UART peripheral base address.
<> 144:ef7eb2e8f9f7 588 * @param handle UART handle pointer.
<> 144:ef7eb2e8f9f7 589 * @param callback The callback function.
<> 144:ef7eb2e8f9f7 590 * @param userData The parameter of the callback function.
<> 144:ef7eb2e8f9f7 591 */
<> 144:ef7eb2e8f9f7 592 void UART_TransferCreateHandle(UART_Type *base,
<> 144:ef7eb2e8f9f7 593 uart_handle_t *handle,
<> 144:ef7eb2e8f9f7 594 uart_transfer_callback_t callback,
<> 144:ef7eb2e8f9f7 595 void *userData);
<> 144:ef7eb2e8f9f7 596
<> 144:ef7eb2e8f9f7 597 /*!
<> 144:ef7eb2e8f9f7 598 * @brief Sets up the RX ring buffer.
<> 144:ef7eb2e8f9f7 599 *
<> 144:ef7eb2e8f9f7 600 * This function sets up the RX ring buffer to a specific UART handle.
<> 144:ef7eb2e8f9f7 601 *
<> 144:ef7eb2e8f9f7 602 * When the RX ring buffer is used, data received are stored into the ring buffer even when the
<> 144:ef7eb2e8f9f7 603 * user doesn't call the UART_TransferReceiveNonBlocking() API. If there is already data received
<> 144:ef7eb2e8f9f7 604 * in the ring buffer, the user can get the received data from the ring buffer directly.
<> 144:ef7eb2e8f9f7 605 *
<> 144:ef7eb2e8f9f7 606 * @note When using the RX ring buffer, one byte is reserved for internal use. In other
<> 144:ef7eb2e8f9f7 607 * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data.
<> 144:ef7eb2e8f9f7 608 *
<> 144:ef7eb2e8f9f7 609 * @param base UART peripheral base address.
<> 144:ef7eb2e8f9f7 610 * @param handle UART handle pointer.
<> 144:ef7eb2e8f9f7 611 * @param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer.
<> 144:ef7eb2e8f9f7 612 * @param ringBufferSize size of the ring buffer.
<> 144:ef7eb2e8f9f7 613 */
<> 144:ef7eb2e8f9f7 614 void UART_TransferStartRingBuffer(UART_Type *base, uart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize);
<> 144:ef7eb2e8f9f7 615
<> 144:ef7eb2e8f9f7 616 /*!
<> 144:ef7eb2e8f9f7 617 * @brief Aborts the background transfer and uninstalls the ring buffer.
<> 144:ef7eb2e8f9f7 618 *
<> 144:ef7eb2e8f9f7 619 * This function aborts the background transfer and uninstalls the ring buffer.
<> 144:ef7eb2e8f9f7 620 *
<> 144:ef7eb2e8f9f7 621 * @param base UART peripheral base address.
<> 144:ef7eb2e8f9f7 622 * @param handle UART handle pointer.
<> 144:ef7eb2e8f9f7 623 */
<> 144:ef7eb2e8f9f7 624 void UART_TransferStopRingBuffer(UART_Type *base, uart_handle_t *handle);
<> 144:ef7eb2e8f9f7 625
<> 144:ef7eb2e8f9f7 626 /*!
<> 144:ef7eb2e8f9f7 627 * @brief Transmits a buffer of data using the interrupt method.
<> 144:ef7eb2e8f9f7 628 *
<> 144:ef7eb2e8f9f7 629 * This function sends data using an interrupt method. This is a non-blocking function, which
<> 144:ef7eb2e8f9f7 630 * returns directly without waiting for all data to be written to the TX register. When
<> 144:ef7eb2e8f9f7 631 * all data is written to the TX register in the ISR, the UART driver calls the callback
<> 144:ef7eb2e8f9f7 632 * function and passes the @ref kStatus_UART_TxIdle as status parameter.
<> 144:ef7eb2e8f9f7 633 *
<> 144:ef7eb2e8f9f7 634 * @note The kStatus_UART_TxIdle is passed to the upper layer when all data is written
<> 144:ef7eb2e8f9f7 635 * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX,
<> 144:ef7eb2e8f9f7 636 * check the kUART_TransmissionCompleteFlag to ensure that the TX is finished.
<> 144:ef7eb2e8f9f7 637 *
<> 144:ef7eb2e8f9f7 638 * @param base UART peripheral base address.
<> 144:ef7eb2e8f9f7 639 * @param handle UART handle pointer.
<> 144:ef7eb2e8f9f7 640 * @param xfer UART transfer structure. See #uart_transfer_t.
<> 144:ef7eb2e8f9f7 641 * @retval kStatus_Success Successfully start the data transmission.
<> 144:ef7eb2e8f9f7 642 * @retval kStatus_UART_TxBusy Previous transmission still not finished, data not all written to TX register yet.
<> 144:ef7eb2e8f9f7 643 * @retval kStatus_InvalidArgument Invalid argument.
<> 144:ef7eb2e8f9f7 644 */
<> 144:ef7eb2e8f9f7 645 status_t UART_TransferSendNonBlocking(UART_Type *base, uart_handle_t *handle, uart_transfer_t *xfer);
<> 144:ef7eb2e8f9f7 646
<> 144:ef7eb2e8f9f7 647 /*!
<> 144:ef7eb2e8f9f7 648 * @brief Aborts the interrupt driven data transmit.
<> 144:ef7eb2e8f9f7 649 *
<> 144:ef7eb2e8f9f7 650 * This function aborts the interrupt driven data sending. The user can get the remainBytes to find out
<> 144:ef7eb2e8f9f7 651 * how many bytes are still not sent out.
<> 144:ef7eb2e8f9f7 652 *
<> 144:ef7eb2e8f9f7 653 * @param base UART peripheral base address.
<> 144:ef7eb2e8f9f7 654 * @param handle UART handle pointer.
<> 144:ef7eb2e8f9f7 655 */
<> 144:ef7eb2e8f9f7 656 void UART_TransferAbortSend(UART_Type *base, uart_handle_t *handle);
<> 144:ef7eb2e8f9f7 657
<> 144:ef7eb2e8f9f7 658 /*!
<> 144:ef7eb2e8f9f7 659 * @brief Get the number of bytes that have been written to UART TX register.
<> 144:ef7eb2e8f9f7 660 *
<> 144:ef7eb2e8f9f7 661 * This function gets the number of bytes that have been written to UART TX
<> 144:ef7eb2e8f9f7 662 * register by interrupt method.
<> 144:ef7eb2e8f9f7 663 *
<> 144:ef7eb2e8f9f7 664 * @param base UART peripheral base address.
<> 144:ef7eb2e8f9f7 665 * @param handle UART handle pointer.
<> 144:ef7eb2e8f9f7 666 * @param count Send bytes count.
<> 144:ef7eb2e8f9f7 667 * @retval kStatus_NoTransferInProgress No send in progress.
<> 144:ef7eb2e8f9f7 668 * @retval kStatus_InvalidArgument Parameter is invalid.
<> 144:ef7eb2e8f9f7 669 * @retval kStatus_Success Get successfully through the parameter \p count;
<> 144:ef7eb2e8f9f7 670 */
<> 144:ef7eb2e8f9f7 671 status_t UART_TransferGetSendCount(UART_Type *base, uart_handle_t *handle, uint32_t *count);
<> 144:ef7eb2e8f9f7 672
<> 144:ef7eb2e8f9f7 673 /*!
<> 144:ef7eb2e8f9f7 674 * @brief Receives a buffer of data using an interrupt method.
<> 144:ef7eb2e8f9f7 675 *
<> 144:ef7eb2e8f9f7 676 * This function receives data using an interrupt method. This is a non-blocking function, which
<> 144:ef7eb2e8f9f7 677 * returns without waiting for all data to be received.
<> 144:ef7eb2e8f9f7 678 * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and
<> 144:ef7eb2e8f9f7 679 * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer.
<> 144:ef7eb2e8f9f7 680 * After copying, if the data in the ring buffer is not enough to read, the receive
<> 144:ef7eb2e8f9f7 681 * request is saved by the UART driver. When the new data arrives, the receive request
<> 144:ef7eb2e8f9f7 682 * is serviced first. When all data is received, the UART driver notifies the upper layer
<> 144:ef7eb2e8f9f7 683 * through a callback function and passes the status parameter @ref kStatus_UART_RxIdle.
<> 144:ef7eb2e8f9f7 684 * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer.
<> 144:ef7eb2e8f9f7 685 * The 5 bytes are copied to the xfer->data and this function returns with the
<> 144:ef7eb2e8f9f7 686 * parameter @p receivedBytes set to 5. For the left 5 bytes, newly arrived data is
<> 144:ef7eb2e8f9f7 687 * saved from the xfer->data[5]. When 5 bytes are received, the UART driver notifies the upper layer.
<> 144:ef7eb2e8f9f7 688 * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt
<> 144:ef7eb2e8f9f7 689 * to receive data to the xfer->data. When all data is received, the upper layer is notified.
<> 144:ef7eb2e8f9f7 690 *
<> 144:ef7eb2e8f9f7 691 * @param base UART peripheral base address.
<> 144:ef7eb2e8f9f7 692 * @param handle UART handle pointer.
<> 144:ef7eb2e8f9f7 693 * @param xfer UART transfer structure, refer to #uart_transfer_t.
<> 144:ef7eb2e8f9f7 694 * @param receivedBytes Bytes received from the ring buffer directly.
<> 144:ef7eb2e8f9f7 695 * @retval kStatus_Success Successfully queue the transfer into transmit queue.
<> 144:ef7eb2e8f9f7 696 * @retval kStatus_UART_RxBusy Previous receive request is not finished.
<> 144:ef7eb2e8f9f7 697 * @retval kStatus_InvalidArgument Invalid argument.
<> 144:ef7eb2e8f9f7 698 */
<> 144:ef7eb2e8f9f7 699 status_t UART_TransferReceiveNonBlocking(UART_Type *base,
<> 144:ef7eb2e8f9f7 700 uart_handle_t *handle,
<> 144:ef7eb2e8f9f7 701 uart_transfer_t *xfer,
<> 144:ef7eb2e8f9f7 702 size_t *receivedBytes);
<> 144:ef7eb2e8f9f7 703
<> 144:ef7eb2e8f9f7 704 /*!
<> 144:ef7eb2e8f9f7 705 * @brief Aborts the interrupt-driven data receiving.
<> 144:ef7eb2e8f9f7 706 *
<> 144:ef7eb2e8f9f7 707 * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know
<> 144:ef7eb2e8f9f7 708 * how many bytes not received yet.
<> 144:ef7eb2e8f9f7 709 *
<> 144:ef7eb2e8f9f7 710 * @param base UART peripheral base address.
<> 144:ef7eb2e8f9f7 711 * @param handle UART handle pointer.
<> 144:ef7eb2e8f9f7 712 */
<> 144:ef7eb2e8f9f7 713 void UART_TransferAbortReceive(UART_Type *base, uart_handle_t *handle);
<> 144:ef7eb2e8f9f7 714
<> 144:ef7eb2e8f9f7 715 /*!
<> 144:ef7eb2e8f9f7 716 * @brief Get the number of bytes that have been received.
<> 144:ef7eb2e8f9f7 717 *
<> 144:ef7eb2e8f9f7 718 * This function gets the number of bytes that have been received.
<> 144:ef7eb2e8f9f7 719 *
<> 144:ef7eb2e8f9f7 720 * @param base UART peripheral base address.
<> 144:ef7eb2e8f9f7 721 * @param handle UART handle pointer.
<> 144:ef7eb2e8f9f7 722 * @param count Receive bytes count.
<> 144:ef7eb2e8f9f7 723 * @retval kStatus_NoTransferInProgress No receive in progress.
<> 144:ef7eb2e8f9f7 724 * @retval kStatus_InvalidArgument Parameter is invalid.
<> 144:ef7eb2e8f9f7 725 * @retval kStatus_Success Get successfully through the parameter \p count;
<> 144:ef7eb2e8f9f7 726 */
<> 144:ef7eb2e8f9f7 727 status_t UART_TransferGetReceiveCount(UART_Type *base, uart_handle_t *handle, uint32_t *count);
<> 144:ef7eb2e8f9f7 728
<> 144:ef7eb2e8f9f7 729 /*!
<> 144:ef7eb2e8f9f7 730 * @brief UART IRQ handle function.
<> 144:ef7eb2e8f9f7 731 *
<> 144:ef7eb2e8f9f7 732 * This function handles the UART transmit and receive IRQ request.
<> 144:ef7eb2e8f9f7 733 *
<> 144:ef7eb2e8f9f7 734 * @param base UART peripheral base address.
<> 144:ef7eb2e8f9f7 735 * @param handle UART handle pointer.
<> 144:ef7eb2e8f9f7 736 */
<> 144:ef7eb2e8f9f7 737 void UART_TransferHandleIRQ(UART_Type *base, uart_handle_t *handle);
<> 144:ef7eb2e8f9f7 738
<> 144:ef7eb2e8f9f7 739 /*!
<> 144:ef7eb2e8f9f7 740 * @brief UART Error IRQ handle function.
<> 144:ef7eb2e8f9f7 741 *
<> 144:ef7eb2e8f9f7 742 * This function handle the UART error IRQ request.
<> 144:ef7eb2e8f9f7 743 *
<> 144:ef7eb2e8f9f7 744 * @param base UART peripheral base address.
<> 144:ef7eb2e8f9f7 745 * @param handle UART handle pointer.
<> 144:ef7eb2e8f9f7 746 */
<> 144:ef7eb2e8f9f7 747 void UART_TransferHandleErrorIRQ(UART_Type *base, uart_handle_t *handle);
<> 144:ef7eb2e8f9f7 748
<> 144:ef7eb2e8f9f7 749 /* @} */
<> 144:ef7eb2e8f9f7 750
<> 144:ef7eb2e8f9f7 751 #if defined(__cplusplus)
<> 144:ef7eb2e8f9f7 752 }
<> 144:ef7eb2e8f9f7 753 #endif
<> 144:ef7eb2e8f9f7 754
<> 144:ef7eb2e8f9f7 755 /*! @}*/
<> 144:ef7eb2e8f9f7 756
<> 144:ef7eb2e8f9f7 757 #endif /* _FSL_UART_H_ */