Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/drivers/fsl_tpm.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 144:ef7eb2e8f9f7 3 * All rights reserved.
<> 144:ef7eb2e8f9f7 4 *
<> 144:ef7eb2e8f9f7 5 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 6 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 144:ef7eb2e8f9f7 9 * of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 144:ef7eb2e8f9f7 12 * list of conditions and the following disclaimer in the documentation and/or
<> 144:ef7eb2e8f9f7 13 * other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 144:ef7eb2e8f9f7 16 * contributors may be used to endorse or promote products derived from this
<> 144:ef7eb2e8f9f7 17 * software without specific prior written permission.
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 29 */
<> 144:ef7eb2e8f9f7 30 #ifndef _FSL_TPM_H_
<> 144:ef7eb2e8f9f7 31 #define _FSL_TPM_H_
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 #include "fsl_common.h"
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 /*!
<> 144:ef7eb2e8f9f7 36 * @addtogroup tpm
<> 144:ef7eb2e8f9f7 37 * @{
<> 144:ef7eb2e8f9f7 38 */
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 /*! @file */
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 /*******************************************************************************
<> 144:ef7eb2e8f9f7 43 * Definitions
<> 144:ef7eb2e8f9f7 44 ******************************************************************************/
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /*! @name Driver version */
<> 144:ef7eb2e8f9f7 47 /*@{*/
<> 144:ef7eb2e8f9f7 48 #define FSL_TPM_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version 2.0.2 */
<> 144:ef7eb2e8f9f7 49 /*@}*/
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 /*!
<> 144:ef7eb2e8f9f7 52 * @brief List of TPM channels.
<> 144:ef7eb2e8f9f7 53 * @note Actual number of available channels is SoC dependent
<> 144:ef7eb2e8f9f7 54 */
<> 144:ef7eb2e8f9f7 55 typedef enum _tpm_chnl
<> 144:ef7eb2e8f9f7 56 {
<> 144:ef7eb2e8f9f7 57 kTPM_Chnl_0 = 0U, /*!< TPM channel number 0*/
<> 144:ef7eb2e8f9f7 58 kTPM_Chnl_1, /*!< TPM channel number 1 */
<> 144:ef7eb2e8f9f7 59 kTPM_Chnl_2, /*!< TPM channel number 2 */
<> 144:ef7eb2e8f9f7 60 kTPM_Chnl_3, /*!< TPM channel number 3 */
<> 144:ef7eb2e8f9f7 61 kTPM_Chnl_4, /*!< TPM channel number 4 */
<> 144:ef7eb2e8f9f7 62 kTPM_Chnl_5, /*!< TPM channel number 5 */
<> 144:ef7eb2e8f9f7 63 kTPM_Chnl_6, /*!< TPM channel number 6 */
<> 144:ef7eb2e8f9f7 64 kTPM_Chnl_7 /*!< TPM channel number 7 */
<> 144:ef7eb2e8f9f7 65 } tpm_chnl_t;
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 /*! @brief TPM PWM operation modes */
<> 144:ef7eb2e8f9f7 68 typedef enum _tpm_pwm_mode
<> 144:ef7eb2e8f9f7 69 {
<> 144:ef7eb2e8f9f7 70 kTPM_EdgeAlignedPwm = 0U, /*!< Edge aligned PWM */
<> 144:ef7eb2e8f9f7 71 kTPM_CenterAlignedPwm, /*!< Center aligned PWM */
<> 144:ef7eb2e8f9f7 72 #if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE
<> 144:ef7eb2e8f9f7 73 kTPM_CombinedPwm /*!< Combined PWM */
<> 144:ef7eb2e8f9f7 74 #endif
<> 144:ef7eb2e8f9f7 75 } tpm_pwm_mode_t;
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 /*! @brief TPM PWM output pulse mode: high-true, low-true or no output */
<> 144:ef7eb2e8f9f7 78 typedef enum _tpm_pwm_level_select
<> 144:ef7eb2e8f9f7 79 {
<> 144:ef7eb2e8f9f7 80 kTPM_NoPwmSignal = 0U, /*!< No PWM output on pin */
<> 144:ef7eb2e8f9f7 81 kTPM_LowTrue, /*!< Low true pulses */
<> 144:ef7eb2e8f9f7 82 kTPM_HighTrue /*!< High true pulses */
<> 144:ef7eb2e8f9f7 83 } tpm_pwm_level_select_t;
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 /*! @brief Options to configure a TPM channel's PWM signal */
<> 144:ef7eb2e8f9f7 86 typedef struct _tpm_chnl_pwm_signal_param
<> 144:ef7eb2e8f9f7 87 {
<> 144:ef7eb2e8f9f7 88 tpm_chnl_t chnlNumber; /*!< TPM channel to configure.
<> 144:ef7eb2e8f9f7 89 In combined mode (available in some SoC's, this represents the
<> 144:ef7eb2e8f9f7 90 channel pair number */
<> 144:ef7eb2e8f9f7 91 tpm_pwm_level_select_t level; /*!< PWM output active level select */
<> 144:ef7eb2e8f9f7 92 uint8_t dutyCyclePercent; /*!< PWM pulse width, value should be between 0 to 100
<> 144:ef7eb2e8f9f7 93 0=inactive signal(0% duty cycle)...
<> 144:ef7eb2e8f9f7 94 100=always active signal (100% duty cycle)*/
<> 144:ef7eb2e8f9f7 95 #if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE
<> 144:ef7eb2e8f9f7 96 uint8_t firstEdgeDelayPercent; /*!< Used only in combined PWM mode to generate asymmetrical PWM.
<> 144:ef7eb2e8f9f7 97 Specifies the delay to the first edge in a PWM period.
<> 144:ef7eb2e8f9f7 98 If unsure, leave as 0; Should be specified as
<> 144:ef7eb2e8f9f7 99 percentage of the PWM period */
<> 144:ef7eb2e8f9f7 100 #endif
<> 144:ef7eb2e8f9f7 101 } tpm_chnl_pwm_signal_param_t;
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 /*!
<> 144:ef7eb2e8f9f7 104 * @brief Trigger options available.
<> 144:ef7eb2e8f9f7 105 *
<> 144:ef7eb2e8f9f7 106 * This is used for both internal & external trigger sources (external option available in certain SoC's)
<> 144:ef7eb2e8f9f7 107 *
<> 144:ef7eb2e8f9f7 108 * @note The actual trigger options available is SoC-specific.
<> 144:ef7eb2e8f9f7 109 */
<> 144:ef7eb2e8f9f7 110 typedef enum _tpm_trigger_select
<> 144:ef7eb2e8f9f7 111 {
<> 144:ef7eb2e8f9f7 112 kTPM_Trigger_Select_0 = 0U,
<> 144:ef7eb2e8f9f7 113 kTPM_Trigger_Select_1,
<> 144:ef7eb2e8f9f7 114 kTPM_Trigger_Select_2,
<> 144:ef7eb2e8f9f7 115 kTPM_Trigger_Select_3,
<> 144:ef7eb2e8f9f7 116 kTPM_Trigger_Select_4,
<> 144:ef7eb2e8f9f7 117 kTPM_Trigger_Select_5,
<> 144:ef7eb2e8f9f7 118 kTPM_Trigger_Select_6,
<> 144:ef7eb2e8f9f7 119 kTPM_Trigger_Select_7,
<> 144:ef7eb2e8f9f7 120 kTPM_Trigger_Select_8,
<> 144:ef7eb2e8f9f7 121 kTPM_Trigger_Select_9,
<> 144:ef7eb2e8f9f7 122 kTPM_Trigger_Select_10,
<> 144:ef7eb2e8f9f7 123 kTPM_Trigger_Select_11,
<> 144:ef7eb2e8f9f7 124 kTPM_Trigger_Select_12,
<> 144:ef7eb2e8f9f7 125 kTPM_Trigger_Select_13,
<> 144:ef7eb2e8f9f7 126 kTPM_Trigger_Select_14,
<> 144:ef7eb2e8f9f7 127 kTPM_Trigger_Select_15
<> 144:ef7eb2e8f9f7 128 } tpm_trigger_select_t;
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 #if defined(FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION) && FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION
<> 144:ef7eb2e8f9f7 131 /*!
<> 144:ef7eb2e8f9f7 132 * @brief Trigger source options available
<> 144:ef7eb2e8f9f7 133 *
<> 144:ef7eb2e8f9f7 134 * @note This selection is available only on some SoC's. For SoC's without this selection, the only
<> 144:ef7eb2e8f9f7 135 * trigger source available is internal triger.
<> 144:ef7eb2e8f9f7 136 */
<> 144:ef7eb2e8f9f7 137 typedef enum _tpm_trigger_source
<> 144:ef7eb2e8f9f7 138 {
<> 144:ef7eb2e8f9f7 139 kTPM_TriggerSource_External = 0U, /*!< Use external trigger input */
<> 144:ef7eb2e8f9f7 140 kTPM_TriggerSource_Internal /*!< Use internal trigger */
<> 144:ef7eb2e8f9f7 141 } tpm_trigger_source_t;
<> 144:ef7eb2e8f9f7 142 #endif
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 /*! @brief TPM output compare modes */
<> 144:ef7eb2e8f9f7 145 typedef enum _tpm_output_compare_mode
<> 144:ef7eb2e8f9f7 146 {
<> 144:ef7eb2e8f9f7 147 kTPM_NoOutputSignal = (1U << TPM_CnSC_MSA_SHIFT), /*!< No channel output when counter reaches CnV */
<> 144:ef7eb2e8f9f7 148 kTPM_ToggleOnMatch = ((1U << TPM_CnSC_MSA_SHIFT) | (1U << TPM_CnSC_ELSA_SHIFT)), /*!< Toggle output */
<> 144:ef7eb2e8f9f7 149 kTPM_ClearOnMatch = ((1U << TPM_CnSC_MSA_SHIFT) | (2U << TPM_CnSC_ELSA_SHIFT)), /*!< Clear output */
<> 144:ef7eb2e8f9f7 150 kTPM_SetOnMatch = ((1U << TPM_CnSC_MSA_SHIFT) | (3U << TPM_CnSC_ELSA_SHIFT)), /*!< Set output */
<> 144:ef7eb2e8f9f7 151 kTPM_HighPulseOutput = ((3U << TPM_CnSC_MSA_SHIFT) | (1U << TPM_CnSC_ELSA_SHIFT)), /*!< Pulse output high */
<> 144:ef7eb2e8f9f7 152 kTPM_LowPulseOutput = ((3U << TPM_CnSC_MSA_SHIFT) | (2U << TPM_CnSC_ELSA_SHIFT)) /*!< Pulse output low */
<> 144:ef7eb2e8f9f7 153 } tpm_output_compare_mode_t;
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 /*! @brief TPM input capture edge */
<> 144:ef7eb2e8f9f7 156 typedef enum _tpm_input_capture_edge
<> 144:ef7eb2e8f9f7 157 {
<> 144:ef7eb2e8f9f7 158 kTPM_RisingEdge = (1U << TPM_CnSC_ELSA_SHIFT), /*!< Capture on rising edge only */
<> 144:ef7eb2e8f9f7 159 kTPM_FallingEdge = (2U << TPM_CnSC_ELSA_SHIFT), /*!< Capture on falling edge only */
<> 144:ef7eb2e8f9f7 160 kTPM_RiseAndFallEdge = (3U << TPM_CnSC_ELSA_SHIFT) /*!< Capture on rising or falling edge */
<> 144:ef7eb2e8f9f7 161 } tpm_input_capture_edge_t;
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 #if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE
<> 144:ef7eb2e8f9f7 164 /*!
<> 144:ef7eb2e8f9f7 165 * @brief TPM dual edge capture parameters
<> 144:ef7eb2e8f9f7 166 *
<> 144:ef7eb2e8f9f7 167 * @note This mode is available only on some SoC's.
<> 144:ef7eb2e8f9f7 168 */
<> 144:ef7eb2e8f9f7 169 typedef struct _tpm_dual_edge_capture_param
<> 144:ef7eb2e8f9f7 170 {
<> 144:ef7eb2e8f9f7 171 bool enableSwap; /*!< true: Use channel n+1 input, channel n input is ignored;
<> 144:ef7eb2e8f9f7 172 false: Use channel n input, channel n+1 input is ignored */
<> 144:ef7eb2e8f9f7 173 tpm_input_capture_edge_t currChanEdgeMode; /*!< Input capture edge select for channel n */
<> 144:ef7eb2e8f9f7 174 tpm_input_capture_edge_t nextChanEdgeMode; /*!< Input capture edge select for channel n+1 */
<> 144:ef7eb2e8f9f7 175 } tpm_dual_edge_capture_param_t;
<> 144:ef7eb2e8f9f7 176 #endif
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 #if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL
<> 144:ef7eb2e8f9f7 179 /*!
<> 144:ef7eb2e8f9f7 180 * @brief TPM quadrature decode modes
<> 144:ef7eb2e8f9f7 181 *
<> 144:ef7eb2e8f9f7 182 * @note This mode is available only on some SoC's.
<> 144:ef7eb2e8f9f7 183 */
<> 144:ef7eb2e8f9f7 184 typedef enum _tpm_quad_decode_mode
<> 144:ef7eb2e8f9f7 185 {
<> 144:ef7eb2e8f9f7 186 kTPM_QuadPhaseEncode = 0U, /*!< Phase A and Phase B encoding mode */
<> 144:ef7eb2e8f9f7 187 kTPM_QuadCountAndDir /*!< Count and direction encoding mode */
<> 144:ef7eb2e8f9f7 188 } tpm_quad_decode_mode_t;
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 /*! @brief TPM quadrature phase polarities */
<> 144:ef7eb2e8f9f7 191 typedef enum _tpm_phase_polarity
<> 144:ef7eb2e8f9f7 192 {
<> 144:ef7eb2e8f9f7 193 kTPM_QuadPhaseNormal = 0U, /*!< Phase input signal is not inverted */
<> 144:ef7eb2e8f9f7 194 kTPM_QuadPhaseInvert /*!< Phase input signal is inverted */
<> 144:ef7eb2e8f9f7 195 } tpm_phase_polarity_t;
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 /*! @brief TPM quadrature decode phase parameters */
<> 144:ef7eb2e8f9f7 198 typedef struct _tpm_phase_param
<> 144:ef7eb2e8f9f7 199 {
<> 144:ef7eb2e8f9f7 200 uint32_t phaseFilterVal; /*!< Filter value, filter is disabled when the value is zero */
<> 144:ef7eb2e8f9f7 201 tpm_phase_polarity_t phasePolarity; /*!< Phase polarity */
<> 144:ef7eb2e8f9f7 202 } tpm_phase_params_t;
<> 144:ef7eb2e8f9f7 203 #endif
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 /*! @brief TPM clock source selection*/
<> 144:ef7eb2e8f9f7 206 typedef enum _tpm_clock_source
<> 144:ef7eb2e8f9f7 207 {
<> 144:ef7eb2e8f9f7 208 kTPM_SystemClock = 1U, /*!< System clock */
<> 144:ef7eb2e8f9f7 209 kTPM_ExternalClock /*!< External clock */
<> 144:ef7eb2e8f9f7 210 } tpm_clock_source_t;
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 /*! @brief TPM prescale value selection for the clock source*/
<> 144:ef7eb2e8f9f7 213 typedef enum _tpm_clock_prescale
<> 144:ef7eb2e8f9f7 214 {
<> 144:ef7eb2e8f9f7 215 kTPM_Prescale_Divide_1 = 0U, /*!< Divide by 1 */
<> 144:ef7eb2e8f9f7 216 kTPM_Prescale_Divide_2, /*!< Divide by 2 */
<> 144:ef7eb2e8f9f7 217 kTPM_Prescale_Divide_4, /*!< Divide by 4 */
<> 144:ef7eb2e8f9f7 218 kTPM_Prescale_Divide_8, /*!< Divide by 8 */
<> 144:ef7eb2e8f9f7 219 kTPM_Prescale_Divide_16, /*!< Divide by 16 */
<> 144:ef7eb2e8f9f7 220 kTPM_Prescale_Divide_32, /*!< Divide by 32 */
<> 144:ef7eb2e8f9f7 221 kTPM_Prescale_Divide_64, /*!< Divide by 64 */
<> 144:ef7eb2e8f9f7 222 kTPM_Prescale_Divide_128 /*!< Divide by 128 */
<> 144:ef7eb2e8f9f7 223 } tpm_clock_prescale_t;
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 /*!
<> 144:ef7eb2e8f9f7 226 * @brief TPM config structure
<> 144:ef7eb2e8f9f7 227 *
<> 144:ef7eb2e8f9f7 228 * This structure holds the configuration settings for the TPM peripheral. To initialize this
<> 144:ef7eb2e8f9f7 229 * structure to reasonable defaults, call the TPM_GetDefaultConfig() function and pass a
<> 144:ef7eb2e8f9f7 230 * pointer to your config structure instance.
<> 144:ef7eb2e8f9f7 231 *
<> 144:ef7eb2e8f9f7 232 * The config struct can be made const so it resides in flash
<> 144:ef7eb2e8f9f7 233 */
<> 144:ef7eb2e8f9f7 234 typedef struct _tpm_config
<> 144:ef7eb2e8f9f7 235 {
<> 144:ef7eb2e8f9f7 236 tpm_clock_prescale_t prescale; /*!< Select TPM clock prescale value */
<> 144:ef7eb2e8f9f7 237 bool useGlobalTimeBase; /*!< true: Use of an external global time base is enabled;
<> 144:ef7eb2e8f9f7 238 false: disabled */
<> 144:ef7eb2e8f9f7 239 tpm_trigger_select_t triggerSelect; /*!< Input trigger to use for controlling the counter operation */
<> 144:ef7eb2e8f9f7 240 #if defined(FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION) && FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION
<> 144:ef7eb2e8f9f7 241 tpm_trigger_source_t triggerSource; /*!< Decides if we use external or internal trigger. */
<> 144:ef7eb2e8f9f7 242 #endif
<> 144:ef7eb2e8f9f7 243 bool enableDoze; /*!< true: TPM counter is paused in doze mode;
<> 144:ef7eb2e8f9f7 244 false: TPM counter continues in doze mode */
<> 144:ef7eb2e8f9f7 245 bool enableDebugMode; /*!< true: TPM counter continues in debug mode;
<> 144:ef7eb2e8f9f7 246 false: TPM counter is paused in debug mode */
<> 144:ef7eb2e8f9f7 247 bool enableReloadOnTrigger; /*!< true: TPM counter is reloaded on trigger;
<> 144:ef7eb2e8f9f7 248 false: TPM counter not reloaded */
<> 144:ef7eb2e8f9f7 249 bool enableStopOnOverflow; /*!< true: TPM counter stops after overflow;
<> 144:ef7eb2e8f9f7 250 false: TPM counter continues running after overflow */
<> 144:ef7eb2e8f9f7 251 bool enableStartOnTrigger; /*!< true: TPM counter only starts when a trigger is detected;
<> 144:ef7eb2e8f9f7 252 false: TPM counter starts immediately */
<> 144:ef7eb2e8f9f7 253 #if defined(FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER) && FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER
<> 144:ef7eb2e8f9f7 254 bool enablePauseOnTrigger; /*!< true: TPM counter will pause while trigger remains asserted;
<> 144:ef7eb2e8f9f7 255 false: TPM counter continues running */
<> 144:ef7eb2e8f9f7 256 #endif
<> 144:ef7eb2e8f9f7 257 } tpm_config_t;
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 /*! @brief List of TPM interrupts */
<> 144:ef7eb2e8f9f7 260 typedef enum _tpm_interrupt_enable
<> 144:ef7eb2e8f9f7 261 {
<> 144:ef7eb2e8f9f7 262 kTPM_Chnl0InterruptEnable = (1U << 0), /*!< Channel 0 interrupt.*/
<> 144:ef7eb2e8f9f7 263 kTPM_Chnl1InterruptEnable = (1U << 1), /*!< Channel 1 interrupt.*/
<> 144:ef7eb2e8f9f7 264 kTPM_Chnl2InterruptEnable = (1U << 2), /*!< Channel 2 interrupt.*/
<> 144:ef7eb2e8f9f7 265 kTPM_Chnl3InterruptEnable = (1U << 3), /*!< Channel 3 interrupt.*/
<> 144:ef7eb2e8f9f7 266 kTPM_Chnl4InterruptEnable = (1U << 4), /*!< Channel 4 interrupt.*/
<> 144:ef7eb2e8f9f7 267 kTPM_Chnl5InterruptEnable = (1U << 5), /*!< Channel 5 interrupt.*/
<> 144:ef7eb2e8f9f7 268 kTPM_Chnl6InterruptEnable = (1U << 6), /*!< Channel 6 interrupt.*/
<> 144:ef7eb2e8f9f7 269 kTPM_Chnl7InterruptEnable = (1U << 7), /*!< Channel 7 interrupt.*/
<> 144:ef7eb2e8f9f7 270 kTPM_TimeOverflowInterruptEnable = (1U << 8) /*!< Time overflow interrupt.*/
<> 144:ef7eb2e8f9f7 271 } tpm_interrupt_enable_t;
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 /*! @brief List of TPM flags */
<> 144:ef7eb2e8f9f7 274 typedef enum _tpm_status_flags
<> 144:ef7eb2e8f9f7 275 {
<> 144:ef7eb2e8f9f7 276 kTPM_Chnl0Flag = (1U << 0), /*!< Channel 0 flag */
<> 144:ef7eb2e8f9f7 277 kTPM_Chnl1Flag = (1U << 1), /*!< Channel 1 flag */
<> 144:ef7eb2e8f9f7 278 kTPM_Chnl2Flag = (1U << 2), /*!< Channel 2 flag */
<> 144:ef7eb2e8f9f7 279 kTPM_Chnl3Flag = (1U << 3), /*!< Channel 3 flag */
<> 144:ef7eb2e8f9f7 280 kTPM_Chnl4Flag = (1U << 4), /*!< Channel 4 flag */
<> 144:ef7eb2e8f9f7 281 kTPM_Chnl5Flag = (1U << 5), /*!< Channel 5 flag */
<> 144:ef7eb2e8f9f7 282 kTPM_Chnl6Flag = (1U << 6), /*!< Channel 6 flag */
<> 144:ef7eb2e8f9f7 283 kTPM_Chnl7Flag = (1U << 7), /*!< Channel 7 flag */
<> 144:ef7eb2e8f9f7 284 kTPM_TimeOverflowFlag = (1U << 8) /*!< Time overflow flag */
<> 144:ef7eb2e8f9f7 285 } tpm_status_flags_t;
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 /*******************************************************************************
<> 144:ef7eb2e8f9f7 288 * API
<> 144:ef7eb2e8f9f7 289 ******************************************************************************/
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 #if defined(__cplusplus)
<> 144:ef7eb2e8f9f7 292 extern "C" {
<> 144:ef7eb2e8f9f7 293 #endif
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295 /*!
<> 144:ef7eb2e8f9f7 296 * @name Initialization and deinitialization
<> 144:ef7eb2e8f9f7 297 * @{
<> 144:ef7eb2e8f9f7 298 */
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 /*!
<> 144:ef7eb2e8f9f7 301 * @brief Ungates the TPM clock and configures the peripheral for basic operation.
<> 144:ef7eb2e8f9f7 302 *
<> 144:ef7eb2e8f9f7 303 * @note This API should be called at the beginning of the application using the TPM driver.
<> 144:ef7eb2e8f9f7 304 *
<> 144:ef7eb2e8f9f7 305 * @param base TPM peripheral base address
<> 144:ef7eb2e8f9f7 306 * @param config Pointer to user's TPM config structure.
<> 144:ef7eb2e8f9f7 307 */
<> 144:ef7eb2e8f9f7 308 void TPM_Init(TPM_Type *base, const tpm_config_t *config);
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 /*!
<> 144:ef7eb2e8f9f7 311 * @brief Stops the counter and gates the TPM clock
<> 144:ef7eb2e8f9f7 312 *
<> 144:ef7eb2e8f9f7 313 * @param base TPM peripheral base address
<> 144:ef7eb2e8f9f7 314 */
<> 144:ef7eb2e8f9f7 315 void TPM_Deinit(TPM_Type *base);
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 /*!
<> 144:ef7eb2e8f9f7 318 * @brief Fill in the TPM config struct with the default settings
<> 144:ef7eb2e8f9f7 319 *
<> 144:ef7eb2e8f9f7 320 * The default values are:
<> 144:ef7eb2e8f9f7 321 * @code
<> 144:ef7eb2e8f9f7 322 * config->prescale = kTPM_Prescale_Divide_1;
<> 144:ef7eb2e8f9f7 323 * config->useGlobalTimeBase = false;
<> 144:ef7eb2e8f9f7 324 * config->dozeEnable = false;
<> 144:ef7eb2e8f9f7 325 * config->dbgMode = false;
<> 144:ef7eb2e8f9f7 326 * config->enableReloadOnTrigger = false;
<> 144:ef7eb2e8f9f7 327 * config->enableStopOnOverflow = false;
<> 144:ef7eb2e8f9f7 328 * config->enableStartOnTrigger = false;
<> 144:ef7eb2e8f9f7 329 *#if FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER
<> 144:ef7eb2e8f9f7 330 * config->enablePauseOnTrigger = false;
<> 144:ef7eb2e8f9f7 331 *#endif
<> 144:ef7eb2e8f9f7 332 * config->triggerSelect = kTPM_Trigger_Select_0;
<> 144:ef7eb2e8f9f7 333 *#if FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION
<> 144:ef7eb2e8f9f7 334 * config->triggerSource = kTPM_TriggerSource_External;
<> 144:ef7eb2e8f9f7 335 *#endif
<> 144:ef7eb2e8f9f7 336 * @endcode
<> 144:ef7eb2e8f9f7 337 * @param config Pointer to user's TPM config structure.
<> 144:ef7eb2e8f9f7 338 */
<> 144:ef7eb2e8f9f7 339 void TPM_GetDefaultConfig(tpm_config_t *config);
<> 144:ef7eb2e8f9f7 340
<> 144:ef7eb2e8f9f7 341 /*! @}*/
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343 /*!
<> 144:ef7eb2e8f9f7 344 * @name Channel mode operations
<> 144:ef7eb2e8f9f7 345 * @{
<> 144:ef7eb2e8f9f7 346 */
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348 /*!
<> 144:ef7eb2e8f9f7 349 * @brief Configures the PWM signal parameters
<> 144:ef7eb2e8f9f7 350 *
<> 144:ef7eb2e8f9f7 351 * User calls this function to configure the PWM signals period, mode, dutycycle and edge. Use this
<> 144:ef7eb2e8f9f7 352 * function to configure all the TPM channels that will be used to output a PWM signal
<> 144:ef7eb2e8f9f7 353 *
<> 144:ef7eb2e8f9f7 354 * @param base TPM peripheral base address
<> 144:ef7eb2e8f9f7 355 * @param chnlParams Array of PWM channel parameters to configure the channel(s)
<> 144:ef7eb2e8f9f7 356 * @param numOfChnls Number of channels to configure, this should be the size of the array passed in
<> 144:ef7eb2e8f9f7 357 * @param mode PWM operation mode, options available in enumeration ::tpm_pwm_mode_t
<> 144:ef7eb2e8f9f7 358 * @param pwmFreq_Hz PWM signal frequency in Hz
<> 144:ef7eb2e8f9f7 359 * @param srcClock_Hz TPM counter clock in Hz
<> 144:ef7eb2e8f9f7 360 *
<> 144:ef7eb2e8f9f7 361 * @return kStatus_Success if the PWM setup was successful,
<> 144:ef7eb2e8f9f7 362 * kStatus_Error on failure
<> 144:ef7eb2e8f9f7 363 */
<> 144:ef7eb2e8f9f7 364 status_t TPM_SetupPwm(TPM_Type *base,
<> 144:ef7eb2e8f9f7 365 const tpm_chnl_pwm_signal_param_t *chnlParams,
<> 144:ef7eb2e8f9f7 366 uint8_t numOfChnls,
<> 144:ef7eb2e8f9f7 367 tpm_pwm_mode_t mode,
<> 144:ef7eb2e8f9f7 368 uint32_t pwmFreq_Hz,
<> 144:ef7eb2e8f9f7 369 uint32_t srcClock_Hz);
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 /*!
<> 144:ef7eb2e8f9f7 372 * @brief Update the duty cycle of an active PWM signal
<> 144:ef7eb2e8f9f7 373 *
<> 144:ef7eb2e8f9f7 374 * @param base TPM peripheral base address
<> 144:ef7eb2e8f9f7 375 * @param chnlNumber The channel number. In combined mode, this represents
<> 144:ef7eb2e8f9f7 376 * the channel pair number
<> 144:ef7eb2e8f9f7 377 * @param currentPwmMode The current PWM mode set during PWM setup
<> 144:ef7eb2e8f9f7 378 * @param dutyCyclePercent New PWM pulse width, value should be between 0 to 100
<> 144:ef7eb2e8f9f7 379 * 0=inactive signal(0% duty cycle)...
<> 144:ef7eb2e8f9f7 380 * 100=active signal (100% duty cycle)
<> 144:ef7eb2e8f9f7 381 */
<> 144:ef7eb2e8f9f7 382 void TPM_UpdatePwmDutycycle(TPM_Type *base,
<> 144:ef7eb2e8f9f7 383 tpm_chnl_t chnlNumber,
<> 144:ef7eb2e8f9f7 384 tpm_pwm_mode_t currentPwmMode,
<> 144:ef7eb2e8f9f7 385 uint8_t dutyCyclePercent);
<> 144:ef7eb2e8f9f7 386
<> 144:ef7eb2e8f9f7 387 /*!
<> 144:ef7eb2e8f9f7 388 * @brief Update the edge level selection for a channel
<> 144:ef7eb2e8f9f7 389 *
<> 144:ef7eb2e8f9f7 390 * @param base TPM peripheral base address
<> 144:ef7eb2e8f9f7 391 * @param chnlNumber The channel number
<> 144:ef7eb2e8f9f7 392 * @param level The level to be set to the ELSnB:ELSnA field; valid values are 00, 01, 10, 11.
<> 144:ef7eb2e8f9f7 393 * See the appropriate SoC reference manual for details about this field.
<> 144:ef7eb2e8f9f7 394 */
<> 144:ef7eb2e8f9f7 395 void TPM_UpdateChnlEdgeLevelSelect(TPM_Type *base, tpm_chnl_t chnlNumber, uint8_t level);
<> 144:ef7eb2e8f9f7 396
<> 144:ef7eb2e8f9f7 397 /*!
<> 144:ef7eb2e8f9f7 398 * @brief Enables capturing an input signal on the channel using the function parameters.
<> 144:ef7eb2e8f9f7 399 *
<> 144:ef7eb2e8f9f7 400 * When the edge specified in the captureMode argument occurs on the channel, the TPM counter is captured into
<> 144:ef7eb2e8f9f7 401 * the CnV register. The user has to read the CnV register separately to get this value.
<> 144:ef7eb2e8f9f7 402 *
<> 144:ef7eb2e8f9f7 403 * @param base TPM peripheral base address
<> 144:ef7eb2e8f9f7 404 * @param chnlNumber The channel number
<> 144:ef7eb2e8f9f7 405 * @param captureMode Specifies which edge to capture
<> 144:ef7eb2e8f9f7 406 */
<> 144:ef7eb2e8f9f7 407 void TPM_SetupInputCapture(TPM_Type *base, tpm_chnl_t chnlNumber, tpm_input_capture_edge_t captureMode);
<> 144:ef7eb2e8f9f7 408
<> 144:ef7eb2e8f9f7 409 /*!
<> 144:ef7eb2e8f9f7 410 * @brief Configures the TPM to generate timed pulses.
<> 144:ef7eb2e8f9f7 411 *
<> 144:ef7eb2e8f9f7 412 * When the TPM counter matches the value of compareVal argument (this is written into CnV reg), the channel
<> 144:ef7eb2e8f9f7 413 * output is changed based on what is specified in the compareMode argument.
<> 144:ef7eb2e8f9f7 414 *
<> 144:ef7eb2e8f9f7 415 * @param base TPM peripheral base address
<> 144:ef7eb2e8f9f7 416 * @param chnlNumber The channel number
<> 144:ef7eb2e8f9f7 417 * @param compareMode Action to take on the channel output when the compare condition is met
<> 144:ef7eb2e8f9f7 418 * @param compareValue Value to be programmed in the CnV register.
<> 144:ef7eb2e8f9f7 419 */
<> 144:ef7eb2e8f9f7 420 void TPM_SetupOutputCompare(TPM_Type *base,
<> 144:ef7eb2e8f9f7 421 tpm_chnl_t chnlNumber,
<> 144:ef7eb2e8f9f7 422 tpm_output_compare_mode_t compareMode,
<> 144:ef7eb2e8f9f7 423 uint32_t compareValue);
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425 #if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE
<> 144:ef7eb2e8f9f7 426 /*!
<> 144:ef7eb2e8f9f7 427 * @brief Configures the dual edge capture mode of the TPM.
<> 144:ef7eb2e8f9f7 428 *
<> 144:ef7eb2e8f9f7 429 * This function allows to measure a pulse width of the signal on the input of channel of a
<> 144:ef7eb2e8f9f7 430 * channel pair. The filter function is disabled if the filterVal argument passed is zero.
<> 144:ef7eb2e8f9f7 431 *
<> 144:ef7eb2e8f9f7 432 * @param base TPM peripheral base address
<> 144:ef7eb2e8f9f7 433 * @param chnlPairNumber The TPM channel pair number; options are 0, 1, 2, 3
<> 144:ef7eb2e8f9f7 434 * @param edgeParam Sets up the dual edge capture function
<> 144:ef7eb2e8f9f7 435 * @param filterValue Filter value, specify 0 to disable filter.
<> 144:ef7eb2e8f9f7 436 */
<> 144:ef7eb2e8f9f7 437 void TPM_SetupDualEdgeCapture(TPM_Type *base,
<> 144:ef7eb2e8f9f7 438 tpm_chnl_t chnlPairNumber,
<> 144:ef7eb2e8f9f7 439 const tpm_dual_edge_capture_param_t *edgeParam,
<> 144:ef7eb2e8f9f7 440 uint32_t filterValue);
<> 144:ef7eb2e8f9f7 441 #endif
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443 #if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL
<> 144:ef7eb2e8f9f7 444 /*!
<> 144:ef7eb2e8f9f7 445 * @brief Configures the parameters and activates the quadrature decode mode.
<> 144:ef7eb2e8f9f7 446 *
<> 144:ef7eb2e8f9f7 447 * @param base TPM peripheral base address
<> 144:ef7eb2e8f9f7 448 * @param phaseAParams Phase A configuration parameters
<> 144:ef7eb2e8f9f7 449 * @param phaseBParams Phase B configuration parameters
<> 144:ef7eb2e8f9f7 450 * @param quadMode Selects encoding mode used in quadrature decoder mode
<> 144:ef7eb2e8f9f7 451 */
<> 144:ef7eb2e8f9f7 452 void TPM_SetupQuadDecode(TPM_Type *base,
<> 144:ef7eb2e8f9f7 453 const tpm_phase_params_t *phaseAParams,
<> 144:ef7eb2e8f9f7 454 const tpm_phase_params_t *phaseBParams,
<> 144:ef7eb2e8f9f7 455 tpm_quad_decode_mode_t quadMode);
<> 144:ef7eb2e8f9f7 456 #endif
<> 144:ef7eb2e8f9f7 457
<> 144:ef7eb2e8f9f7 458 /*! @}*/
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 /*!
<> 144:ef7eb2e8f9f7 461 * @name Interrupt Interface
<> 144:ef7eb2e8f9f7 462 * @{
<> 144:ef7eb2e8f9f7 463 */
<> 144:ef7eb2e8f9f7 464
<> 144:ef7eb2e8f9f7 465 /*!
<> 144:ef7eb2e8f9f7 466 * @brief Enables the selected TPM interrupts.
<> 144:ef7eb2e8f9f7 467 *
<> 144:ef7eb2e8f9f7 468 * @param base TPM peripheral base address
<> 144:ef7eb2e8f9f7 469 * @param mask The interrupts to enable. This is a logical OR of members of the
<> 144:ef7eb2e8f9f7 470 * enumeration ::tpm_interrupt_enable_t
<> 144:ef7eb2e8f9f7 471 */
<> 144:ef7eb2e8f9f7 472 void TPM_EnableInterrupts(TPM_Type *base, uint32_t mask);
<> 144:ef7eb2e8f9f7 473
<> 144:ef7eb2e8f9f7 474 /*!
<> 144:ef7eb2e8f9f7 475 * @brief Disables the selected TPM interrupts.
<> 144:ef7eb2e8f9f7 476 *
<> 144:ef7eb2e8f9f7 477 * @param base TPM peripheral base address
<> 144:ef7eb2e8f9f7 478 * @param mask The interrupts to disable. This is a logical OR of members of the
<> 144:ef7eb2e8f9f7 479 * enumeration ::tpm_interrupt_enable_t
<> 144:ef7eb2e8f9f7 480 */
<> 144:ef7eb2e8f9f7 481 void TPM_DisableInterrupts(TPM_Type *base, uint32_t mask);
<> 144:ef7eb2e8f9f7 482
<> 144:ef7eb2e8f9f7 483 /*!
<> 144:ef7eb2e8f9f7 484 * @brief Gets the enabled TPM interrupts.
<> 144:ef7eb2e8f9f7 485 *
<> 144:ef7eb2e8f9f7 486 * @param base TPM peripheral base address
<> 144:ef7eb2e8f9f7 487 *
<> 144:ef7eb2e8f9f7 488 * @return The enabled interrupts. This is the logical OR of members of the
<> 144:ef7eb2e8f9f7 489 * enumeration ::tpm_interrupt_enable_t
<> 144:ef7eb2e8f9f7 490 */
<> 144:ef7eb2e8f9f7 491 uint32_t TPM_GetEnabledInterrupts(TPM_Type *base);
<> 144:ef7eb2e8f9f7 492
<> 144:ef7eb2e8f9f7 493 /*! @}*/
<> 144:ef7eb2e8f9f7 494
<> 144:ef7eb2e8f9f7 495 /*!
<> 144:ef7eb2e8f9f7 496 * @name Status Interface
<> 144:ef7eb2e8f9f7 497 * @{
<> 144:ef7eb2e8f9f7 498 */
<> 144:ef7eb2e8f9f7 499
<> 144:ef7eb2e8f9f7 500 /*!
<> 144:ef7eb2e8f9f7 501 * @brief Gets the TPM status flags
<> 144:ef7eb2e8f9f7 502 *
<> 144:ef7eb2e8f9f7 503 * @param base TPM peripheral base address
<> 144:ef7eb2e8f9f7 504 *
<> 144:ef7eb2e8f9f7 505 * @return The status flags. This is the logical OR of members of the
<> 144:ef7eb2e8f9f7 506 * enumeration ::tpm_status_flags_t
<> 144:ef7eb2e8f9f7 507 */
<> 144:ef7eb2e8f9f7 508 static inline uint32_t TPM_GetStatusFlags(TPM_Type *base)
<> 144:ef7eb2e8f9f7 509 {
<> 144:ef7eb2e8f9f7 510 return base->STATUS;
<> 144:ef7eb2e8f9f7 511 }
<> 144:ef7eb2e8f9f7 512
<> 144:ef7eb2e8f9f7 513 /*!
<> 144:ef7eb2e8f9f7 514 * @brief Clears the TPM status flags
<> 144:ef7eb2e8f9f7 515 *
<> 144:ef7eb2e8f9f7 516 * @param base TPM peripheral base address
<> 144:ef7eb2e8f9f7 517 * @param mask The status flags to clear. This is a logical OR of members of the
<> 144:ef7eb2e8f9f7 518 * enumeration ::tpm_status_flags_t
<> 144:ef7eb2e8f9f7 519 */
<> 144:ef7eb2e8f9f7 520 static inline void TPM_ClearStatusFlags(TPM_Type *base, uint32_t mask)
<> 144:ef7eb2e8f9f7 521 {
<> 144:ef7eb2e8f9f7 522 /* Clear the status flags */
<> 144:ef7eb2e8f9f7 523 base->STATUS = mask;
<> 144:ef7eb2e8f9f7 524 }
<> 144:ef7eb2e8f9f7 525
<> 144:ef7eb2e8f9f7 526 /*! @}*/
<> 144:ef7eb2e8f9f7 527
<> 144:ef7eb2e8f9f7 528 /*!
<> 144:ef7eb2e8f9f7 529 * @name Timer Start and Stop
<> 144:ef7eb2e8f9f7 530 * @{
<> 144:ef7eb2e8f9f7 531 */
<> 144:ef7eb2e8f9f7 532
<> 144:ef7eb2e8f9f7 533 /*!
<> 144:ef7eb2e8f9f7 534 * @brief Starts the TPM counter.
<> 144:ef7eb2e8f9f7 535 *
<> 144:ef7eb2e8f9f7 536 *
<> 144:ef7eb2e8f9f7 537 * @param base TPM peripheral base address
<> 144:ef7eb2e8f9f7 538 * @param clockSource TPM clock source; once clock source is set the counter will start running
<> 144:ef7eb2e8f9f7 539 */
<> 144:ef7eb2e8f9f7 540 static inline void TPM_StartTimer(TPM_Type *base, tpm_clock_source_t clockSource)
<> 144:ef7eb2e8f9f7 541 {
<> 144:ef7eb2e8f9f7 542 uint32_t reg = base->SC;
<> 144:ef7eb2e8f9f7 543
<> 144:ef7eb2e8f9f7 544 reg &= ~(TPM_SC_CMOD_MASK);
<> 144:ef7eb2e8f9f7 545 reg |= TPM_SC_CMOD(clockSource);
<> 144:ef7eb2e8f9f7 546 base->SC = reg;
<> 144:ef7eb2e8f9f7 547 }
<> 144:ef7eb2e8f9f7 548
<> 144:ef7eb2e8f9f7 549 /*!
<> 144:ef7eb2e8f9f7 550 * @brief Stops the TPM counter.
<> 144:ef7eb2e8f9f7 551 *
<> 144:ef7eb2e8f9f7 552 * @param base TPM peripheral base address
<> 144:ef7eb2e8f9f7 553 */
<> 144:ef7eb2e8f9f7 554 static inline void TPM_StopTimer(TPM_Type *base)
<> 144:ef7eb2e8f9f7 555 {
<> 144:ef7eb2e8f9f7 556 /* Set clock source to none to disable counter */
<> 144:ef7eb2e8f9f7 557 base->SC &= ~(TPM_SC_CMOD_MASK);
<> 144:ef7eb2e8f9f7 558
<> 144:ef7eb2e8f9f7 559 /* Wait till this reads as zero acknowledging the counter is disabled */
<> 144:ef7eb2e8f9f7 560 while (base->SC & TPM_SC_CMOD_MASK)
<> 144:ef7eb2e8f9f7 561 {
<> 144:ef7eb2e8f9f7 562 }
<> 144:ef7eb2e8f9f7 563 }
<> 144:ef7eb2e8f9f7 564
<> 144:ef7eb2e8f9f7 565 /*! @}*/
<> 144:ef7eb2e8f9f7 566
<> 144:ef7eb2e8f9f7 567 #if defined(FSL_FEATURE_TPM_HAS_GLOBAL) && FSL_FEATURE_TPM_HAS_GLOBAL
<> 144:ef7eb2e8f9f7 568 /*!
<> 144:ef7eb2e8f9f7 569 * @brief Performs a software reset on the TPM module.
<> 144:ef7eb2e8f9f7 570 *
<> 144:ef7eb2e8f9f7 571 * Reset all internal logic and registers, except the Global Register. Remains set until cleared by software..
<> 144:ef7eb2e8f9f7 572 *
<> 144:ef7eb2e8f9f7 573 * @note TPM software reset is available on certain SoC's only
<> 144:ef7eb2e8f9f7 574 *
<> 144:ef7eb2e8f9f7 575 * @param base TPM peripheral base address
<> 144:ef7eb2e8f9f7 576 */
<> 144:ef7eb2e8f9f7 577 static inline void TPM_Reset(TPM_Type *base)
<> 144:ef7eb2e8f9f7 578 {
<> 144:ef7eb2e8f9f7 579 base->GLOBAL |= TPM_GLOBAL_RST_MASK;
<> 144:ef7eb2e8f9f7 580 base->GLOBAL &= ~TPM_GLOBAL_RST_MASK;
<> 144:ef7eb2e8f9f7 581 }
<> 144:ef7eb2e8f9f7 582 #endif
<> 144:ef7eb2e8f9f7 583
<> 144:ef7eb2e8f9f7 584 #if defined(__cplusplus)
<> 144:ef7eb2e8f9f7 585 }
<> 144:ef7eb2e8f9f7 586 #endif
<> 144:ef7eb2e8f9f7 587
<> 144:ef7eb2e8f9f7 588 /*! @}*/
<> 144:ef7eb2e8f9f7 589
<> 144:ef7eb2e8f9f7 590 #endif /* _FSL_TPM_H_ */