added prescaler for 16 bit pwm in LPC1347 target
Fork of mbed-dev by
targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/drivers/fsl_rcm.h@147:ba84b7dc41a7, 2016-09-10 (annotated)
- Committer:
- JojoS
- Date:
- Sat Sep 10 15:32:04 2016 +0000
- Revision:
- 147:ba84b7dc41a7
- Parent:
- 144:ef7eb2e8f9f7
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /* |
<> | 144:ef7eb2e8f9f7 | 2 | * Copyright (c) 2015, Freescale Semiconductor, Inc. |
<> | 144:ef7eb2e8f9f7 | 3 | * All rights reserved. |
<> | 144:ef7eb2e8f9f7 | 4 | * |
<> | 144:ef7eb2e8f9f7 | 5 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 144:ef7eb2e8f9f7 | 6 | * are permitted provided that the following conditions are met: |
<> | 144:ef7eb2e8f9f7 | 7 | * |
<> | 144:ef7eb2e8f9f7 | 8 | * o Redistributions of source code must retain the above copyright notice, this list |
<> | 144:ef7eb2e8f9f7 | 9 | * of conditions and the following disclaimer. |
<> | 144:ef7eb2e8f9f7 | 10 | * |
<> | 144:ef7eb2e8f9f7 | 11 | * o Redistributions in binary form must reproduce the above copyright notice, this |
<> | 144:ef7eb2e8f9f7 | 12 | * list of conditions and the following disclaimer in the documentation and/or |
<> | 144:ef7eb2e8f9f7 | 13 | * other materials provided with the distribution. |
<> | 144:ef7eb2e8f9f7 | 14 | * |
<> | 144:ef7eb2e8f9f7 | 15 | * o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
<> | 144:ef7eb2e8f9f7 | 16 | * contributors may be used to endorse or promote products derived from this |
<> | 144:ef7eb2e8f9f7 | 17 | * software without specific prior written permission. |
<> | 144:ef7eb2e8f9f7 | 18 | * |
<> | 144:ef7eb2e8f9f7 | 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
<> | 144:ef7eb2e8f9f7 | 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
<> | 144:ef7eb2e8f9f7 | 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 144:ef7eb2e8f9f7 | 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
<> | 144:ef7eb2e8f9f7 | 23 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
<> | 144:ef7eb2e8f9f7 | 24 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
<> | 144:ef7eb2e8f9f7 | 25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
<> | 144:ef7eb2e8f9f7 | 26 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
<> | 144:ef7eb2e8f9f7 | 27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
<> | 144:ef7eb2e8f9f7 | 28 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 144:ef7eb2e8f9f7 | 29 | */ |
<> | 144:ef7eb2e8f9f7 | 30 | #ifndef _FSL_RCM_H_ |
<> | 144:ef7eb2e8f9f7 | 31 | #define _FSL_RCM_H_ |
<> | 144:ef7eb2e8f9f7 | 32 | |
<> | 144:ef7eb2e8f9f7 | 33 | #include "fsl_common.h" |
<> | 144:ef7eb2e8f9f7 | 34 | |
<> | 144:ef7eb2e8f9f7 | 35 | /*! @addtogroup rcm */ |
<> | 144:ef7eb2e8f9f7 | 36 | /*! @{*/ |
<> | 144:ef7eb2e8f9f7 | 37 | |
<> | 144:ef7eb2e8f9f7 | 38 | /*! @file */ |
<> | 144:ef7eb2e8f9f7 | 39 | |
<> | 144:ef7eb2e8f9f7 | 40 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 41 | * Definitions |
<> | 144:ef7eb2e8f9f7 | 42 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 43 | |
<> | 144:ef7eb2e8f9f7 | 44 | /*! @name Driver version */ |
<> | 144:ef7eb2e8f9f7 | 45 | /*@{*/ |
<> | 144:ef7eb2e8f9f7 | 46 | /*! @brief RCM driver version 2.0.0. */ |
<> | 144:ef7eb2e8f9f7 | 47 | #define FSL_RCM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) |
<> | 144:ef7eb2e8f9f7 | 48 | /*@}*/ |
<> | 144:ef7eb2e8f9f7 | 49 | |
<> | 144:ef7eb2e8f9f7 | 50 | /*! |
<> | 144:ef7eb2e8f9f7 | 51 | * @brief System Reset Source Name definitions |
<> | 144:ef7eb2e8f9f7 | 52 | */ |
<> | 144:ef7eb2e8f9f7 | 53 | typedef enum _rcm_reset_source |
<> | 144:ef7eb2e8f9f7 | 54 | { |
<> | 144:ef7eb2e8f9f7 | 55 | #if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32)) |
<> | 144:ef7eb2e8f9f7 | 56 | /* RCM register bit width is 32. */ |
<> | 144:ef7eb2e8f9f7 | 57 | #if (defined(FSL_FEATURE_RCM_HAS_WAKEUP) && FSL_FEATURE_RCM_HAS_WAKEUP) |
<> | 144:ef7eb2e8f9f7 | 58 | kRCM_SourceWakeup = RCM_SRS_WAKEUP_MASK, /*!< Low-leakage wakeup reset */ |
<> | 144:ef7eb2e8f9f7 | 59 | #endif |
<> | 144:ef7eb2e8f9f7 | 60 | kRCM_SourceLvd = RCM_SRS_LVD_MASK, /*!< low voltage detect reset */ |
<> | 144:ef7eb2e8f9f7 | 61 | #if (defined(FSL_FEATURE_RCM_HAS_LOC) && FSL_FEATURE_RCM_HAS_LOC) |
<> | 144:ef7eb2e8f9f7 | 62 | kRCM_SourceLoc = RCM_SRS_LOC_MASK, /*!< Loss of clock reset */ |
<> | 144:ef7eb2e8f9f7 | 63 | #endif /* FSL_FEATURE_RCM_HAS_LOC */ |
<> | 144:ef7eb2e8f9f7 | 64 | #if (defined(FSL_FEATURE_RCM_HAS_LOL) && FSL_FEATURE_RCM_HAS_LOL) |
<> | 144:ef7eb2e8f9f7 | 65 | kRCM_SourceLol = RCM_SRS_LOL_MASK, /*!< Loss of lock reset */ |
<> | 144:ef7eb2e8f9f7 | 66 | #endif /* FSL_FEATURE_RCM_HAS_LOL */ |
<> | 144:ef7eb2e8f9f7 | 67 | kRCM_SourceWdog = RCM_SRS_WDOG_MASK, /*!< Watchdog reset */ |
<> | 144:ef7eb2e8f9f7 | 68 | kRCM_SourcePin = RCM_SRS_PIN_MASK, /*!< External pin reset */ |
<> | 144:ef7eb2e8f9f7 | 69 | kRCM_SourcePor = RCM_SRS_POR_MASK, /*!< Power on reset */ |
<> | 144:ef7eb2e8f9f7 | 70 | #if (defined(FSL_FEATURE_RCM_HAS_JTAG) && FSL_FEATURE_RCM_HAS_JTAG) |
<> | 144:ef7eb2e8f9f7 | 71 | kRCM_SourceJtag = RCM_SRS_JTAG_MASK, /*!< JTAG generated reset */ |
<> | 144:ef7eb2e8f9f7 | 72 | #endif /* FSL_FEATURE_RCM_HAS_JTAG */ |
<> | 144:ef7eb2e8f9f7 | 73 | kRCM_SourceLockup = RCM_SRS_LOCKUP_MASK, /*!< Core lock up reset */ |
<> | 144:ef7eb2e8f9f7 | 74 | kRCM_SourceSw = RCM_SRS_SW_MASK, /*!< Software reset */ |
<> | 144:ef7eb2e8f9f7 | 75 | #if (defined(FSL_FEATURE_RCM_HAS_MDM_AP) && FSL_FEATURE_RCM_HAS_MDM_AP) |
<> | 144:ef7eb2e8f9f7 | 76 | kRCM_SourceMdmap = RCM_SRS_MDM_AP_MASK, /*!< MDM-AP system reset */ |
<> | 144:ef7eb2e8f9f7 | 77 | #endif /* FSL_FEATURE_RCM_HAS_MDM_AP */ |
<> | 144:ef7eb2e8f9f7 | 78 | #if (defined(FSL_FEATURE_RCM_HAS_EZPORT) && FSL_FEATURE_RCM_HAS_EZPORT) |
<> | 144:ef7eb2e8f9f7 | 79 | kRCM_SourceEzpt = RCM_SRS_EZPT_MASK, /*!< EzPort reset */ |
<> | 144:ef7eb2e8f9f7 | 80 | #endif /* FSL_FEATURE_RCM_HAS_EZPORT */ |
<> | 144:ef7eb2e8f9f7 | 81 | kRCM_SourceSackerr = RCM_SRS_SACKERR_MASK, /*!< Parameter could get all reset flags */ |
<> | 144:ef7eb2e8f9f7 | 82 | |
<> | 144:ef7eb2e8f9f7 | 83 | #else /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */ |
<> | 144:ef7eb2e8f9f7 | 84 | /* RCM register bit width is 8. */ |
<> | 144:ef7eb2e8f9f7 | 85 | #if (defined(FSL_FEATURE_RCM_HAS_WAKEUP) && FSL_FEATURE_RCM_HAS_WAKEUP) |
<> | 144:ef7eb2e8f9f7 | 86 | kRCM_SourceWakeup = RCM_SRS0_WAKEUP_MASK, /*!< Low-leakage wakeup reset */ |
<> | 144:ef7eb2e8f9f7 | 87 | #endif |
<> | 144:ef7eb2e8f9f7 | 88 | kRCM_SourceLvd = RCM_SRS0_LVD_MASK, /*!< low voltage detect reset */ |
<> | 144:ef7eb2e8f9f7 | 89 | #if (defined(FSL_FEATURE_RCM_HAS_LOC) && FSL_FEATURE_RCM_HAS_LOC) |
<> | 144:ef7eb2e8f9f7 | 90 | kRCM_SourceLoc = RCM_SRS0_LOC_MASK, /*!< Loss of clock reset */ |
<> | 144:ef7eb2e8f9f7 | 91 | #endif /* FSL_FEATURE_RCM_HAS_LOC */ |
<> | 144:ef7eb2e8f9f7 | 92 | #if (defined(FSL_FEATURE_RCM_HAS_LOL) && FSL_FEATURE_RCM_HAS_LOL) |
<> | 144:ef7eb2e8f9f7 | 93 | kRCM_SourceLol = RCM_SRS0_LOL_MASK, /*!< Loss of lock reset */ |
<> | 144:ef7eb2e8f9f7 | 94 | #endif /* FSL_FEATURE_RCM_HAS_LOL */ |
<> | 144:ef7eb2e8f9f7 | 95 | kRCM_SourceWdog = RCM_SRS0_WDOG_MASK, /*!< Watchdog reset */ |
<> | 144:ef7eb2e8f9f7 | 96 | kRCM_SourcePin = RCM_SRS0_PIN_MASK, /*!< External pin reset */ |
<> | 144:ef7eb2e8f9f7 | 97 | kRCM_SourcePor = RCM_SRS0_POR_MASK, /*!< Power on reset */ |
<> | 144:ef7eb2e8f9f7 | 98 | #if (defined(FSL_FEATURE_RCM_HAS_JTAG) && FSL_FEATURE_RCM_HAS_JTAG) |
<> | 144:ef7eb2e8f9f7 | 99 | kRCM_SourceJtag = RCM_SRS1_JTAG_MASK << 8U, /*!< JTAG generated reset */ |
<> | 144:ef7eb2e8f9f7 | 100 | #endif /* FSL_FEATURE_RCM_HAS_JTAG */ |
<> | 144:ef7eb2e8f9f7 | 101 | kRCM_SourceLockup = RCM_SRS1_LOCKUP_MASK << 8U, /*!< Core lock up reset */ |
<> | 144:ef7eb2e8f9f7 | 102 | kRCM_SourceSw = RCM_SRS1_SW_MASK, /*!< Software reset */ |
<> | 144:ef7eb2e8f9f7 | 103 | #if (defined(FSL_FEATURE_RCM_HAS_MDM_AP) && FSL_FEATURE_RCM_HAS_MDM_AP) |
<> | 144:ef7eb2e8f9f7 | 104 | kRCM_SourceMdmap = RCM_SRS1_MDM_AP_MASK << 8U, /*!< MDM-AP system reset */ |
<> | 144:ef7eb2e8f9f7 | 105 | #endif /* FSL_FEATURE_RCM_HAS_MDM_AP */ |
<> | 144:ef7eb2e8f9f7 | 106 | #if (defined(FSL_FEATURE_RCM_HAS_EZPORT) && FSL_FEATURE_RCM_HAS_EZPORT) |
<> | 144:ef7eb2e8f9f7 | 107 | kRCM_SourceEzpt = RCM_SRS1_EZPT_MASK << 8U, /*!< EzPort reset */ |
<> | 144:ef7eb2e8f9f7 | 108 | #endif /* FSL_FEATURE_RCM_HAS_EZPORT */ |
<> | 144:ef7eb2e8f9f7 | 109 | kRCM_SourceSackerr = RCM_SRS1_SACKERR_MASK << 8U, /*!< Parameter could get all reset flags */ |
<> | 144:ef7eb2e8f9f7 | 110 | #endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */ |
<> | 144:ef7eb2e8f9f7 | 111 | kRCM_SourceAll = 0xffffffffU, |
<> | 144:ef7eb2e8f9f7 | 112 | } rcm_reset_source_t; |
<> | 144:ef7eb2e8f9f7 | 113 | |
<> | 144:ef7eb2e8f9f7 | 114 | /*! |
<> | 144:ef7eb2e8f9f7 | 115 | * @brief Reset pin filter select in Run and Wait modes |
<> | 144:ef7eb2e8f9f7 | 116 | */ |
<> | 144:ef7eb2e8f9f7 | 117 | typedef enum _rcm_run_wait_filter_mode |
<> | 144:ef7eb2e8f9f7 | 118 | { |
<> | 144:ef7eb2e8f9f7 | 119 | kRCM_FilterDisable = 0U, /*!< All filtering disabled */ |
<> | 144:ef7eb2e8f9f7 | 120 | kRCM_FilterBusClock = 1U, /*!< Bus clock filter enabled */ |
<> | 144:ef7eb2e8f9f7 | 121 | kRCM_FilterLpoClock = 2U /*!< LPO clock filter enabled */ |
<> | 144:ef7eb2e8f9f7 | 122 | } rcm_run_wait_filter_mode_t; |
<> | 144:ef7eb2e8f9f7 | 123 | |
<> | 144:ef7eb2e8f9f7 | 124 | #if (defined(FSL_FEATURE_RCM_HAS_BOOTROM) && FSL_FEATURE_RCM_HAS_BOOTROM) |
<> | 144:ef7eb2e8f9f7 | 125 | /*! |
<> | 144:ef7eb2e8f9f7 | 126 | * @brief Boot from ROM configuration. |
<> | 144:ef7eb2e8f9f7 | 127 | */ |
<> | 144:ef7eb2e8f9f7 | 128 | typedef enum _rcm_boot_rom_config |
<> | 144:ef7eb2e8f9f7 | 129 | { |
<> | 144:ef7eb2e8f9f7 | 130 | kRCM_BootFlash = 0U, /*!< Boot from flash */ |
<> | 144:ef7eb2e8f9f7 | 131 | kRCM_BootRomCfg0 = 1U, /*!< Boot from boot ROM due to BOOTCFG0 */ |
<> | 144:ef7eb2e8f9f7 | 132 | kRCM_BootRomFopt = 2U, /*!< Boot from boot ROM due to FOPT[7] */ |
<> | 144:ef7eb2e8f9f7 | 133 | kRCM_BootRomBoth = 3U /*!< Boot from boot ROM due to both BOOTCFG0 and FOPT[7] */ |
<> | 144:ef7eb2e8f9f7 | 134 | } rcm_boot_rom_config_t; |
<> | 144:ef7eb2e8f9f7 | 135 | #endif /* FSL_FEATURE_RCM_HAS_BOOTROM */ |
<> | 144:ef7eb2e8f9f7 | 136 | |
<> | 144:ef7eb2e8f9f7 | 137 | #if (defined(FSL_FEATURE_RCM_HAS_SRIE) && FSL_FEATURE_RCM_HAS_SRIE) |
<> | 144:ef7eb2e8f9f7 | 138 | /*! |
<> | 144:ef7eb2e8f9f7 | 139 | * @brief Max delay time from interrupt asserts to system reset. |
<> | 144:ef7eb2e8f9f7 | 140 | */ |
<> | 144:ef7eb2e8f9f7 | 141 | typedef enum _rcm_reset_delay |
<> | 144:ef7eb2e8f9f7 | 142 | { |
<> | 144:ef7eb2e8f9f7 | 143 | kRCM_ResetDelay8Lpo = 0U, /*!< Delay 8 LPO cycles. */ |
<> | 144:ef7eb2e8f9f7 | 144 | kRCM_ResetDelay32Lpo = 1U, /*!< Delay 32 LPO cycles. */ |
<> | 144:ef7eb2e8f9f7 | 145 | kRCM_ResetDelay128Lpo = 2U, /*!< Delay 128 LPO cycles. */ |
<> | 144:ef7eb2e8f9f7 | 146 | kRCM_ResetDelay512Lpo = 3U /*!< Delay 512 LPO cycles. */ |
<> | 144:ef7eb2e8f9f7 | 147 | } rcm_reset_delay_t; |
<> | 144:ef7eb2e8f9f7 | 148 | |
<> | 144:ef7eb2e8f9f7 | 149 | /*! |
<> | 144:ef7eb2e8f9f7 | 150 | * @brief System reset interrupt enable bit definitions. |
<> | 144:ef7eb2e8f9f7 | 151 | */ |
<> | 144:ef7eb2e8f9f7 | 152 | typedef enum _rcm_interrupt_enable |
<> | 144:ef7eb2e8f9f7 | 153 | { |
<> | 144:ef7eb2e8f9f7 | 154 | kRCM_IntNone = 0U, /*!< No interrupt enabled. */ |
<> | 144:ef7eb2e8f9f7 | 155 | kRCM_IntLossOfClk = RCM_SRIE_LOC_MASK, /*!< Loss of clock interrupt. */ |
<> | 144:ef7eb2e8f9f7 | 156 | kRCM_IntLossOfLock = RCM_SRIE_LOL_MASK, /*!< Loss of lock interrupt. */ |
<> | 144:ef7eb2e8f9f7 | 157 | kRCM_IntWatchDog = RCM_SRIE_WDOG_MASK, /*!< Watch dog interrupt. */ |
<> | 144:ef7eb2e8f9f7 | 158 | kRCM_IntExternalPin = RCM_SRIE_PIN_MASK, /*!< External pin interrupt. */ |
<> | 144:ef7eb2e8f9f7 | 159 | kRCM_IntGlobal = RCM_SRIE_GIE_MASK, /*!< Global interrupts. */ |
<> | 144:ef7eb2e8f9f7 | 160 | kRCM_IntCoreLockup = RCM_SRIE_LOCKUP_MASK, /*!< Core lock up interrupt */ |
<> | 144:ef7eb2e8f9f7 | 161 | kRCM_IntSoftware = RCM_SRIE_SW_MASK, /*!< software interrupt */ |
<> | 144:ef7eb2e8f9f7 | 162 | kRCM_IntStopModeAckErr = RCM_SRIE_SACKERR_MASK, /*!< Stop mode ACK error interrupt. */ |
<> | 144:ef7eb2e8f9f7 | 163 | #if (defined(FSL_FEATURE_RCM_HAS_CORE1) && FSL_FEATURE_RCM_HAS_CORE1) |
<> | 144:ef7eb2e8f9f7 | 164 | kRCM_IntCore1 = RCM_SRIE_CORE1_MASK, /*!< Core 1 interrupt. */ |
<> | 144:ef7eb2e8f9f7 | 165 | #endif |
<> | 144:ef7eb2e8f9f7 | 166 | kRCM_IntAll = RCM_SRIE_LOC_MASK /*!< Enable all interrupts. */ |
<> | 144:ef7eb2e8f9f7 | 167 | | |
<> | 144:ef7eb2e8f9f7 | 168 | RCM_SRIE_LOL_MASK | RCM_SRIE_WDOG_MASK | RCM_SRIE_PIN_MASK | RCM_SRIE_GIE_MASK | |
<> | 144:ef7eb2e8f9f7 | 169 | RCM_SRIE_LOCKUP_MASK | RCM_SRIE_SW_MASK | RCM_SRIE_SACKERR_MASK |
<> | 144:ef7eb2e8f9f7 | 170 | #if (defined(FSL_FEATURE_RCM_HAS_CORE1) && FSL_FEATURE_RCM_HAS_CORE1) |
<> | 144:ef7eb2e8f9f7 | 171 | | |
<> | 144:ef7eb2e8f9f7 | 172 | RCM_SRIE_CORE1_MASK |
<> | 144:ef7eb2e8f9f7 | 173 | #endif |
<> | 144:ef7eb2e8f9f7 | 174 | } rcm_interrupt_enable_t; |
<> | 144:ef7eb2e8f9f7 | 175 | #endif /* FSL_FEATURE_RCM_HAS_SRIE */ |
<> | 144:ef7eb2e8f9f7 | 176 | |
<> | 144:ef7eb2e8f9f7 | 177 | #if (defined(FSL_FEATURE_RCM_HAS_VERID) && FSL_FEATURE_RCM_HAS_VERID) |
<> | 144:ef7eb2e8f9f7 | 178 | /*! |
<> | 144:ef7eb2e8f9f7 | 179 | * @brief IP version ID definition. |
<> | 144:ef7eb2e8f9f7 | 180 | */ |
<> | 144:ef7eb2e8f9f7 | 181 | typedef struct _rcm_version_id |
<> | 144:ef7eb2e8f9f7 | 182 | { |
<> | 144:ef7eb2e8f9f7 | 183 | uint16_t feature; /*!< Feature Specification Number. */ |
<> | 144:ef7eb2e8f9f7 | 184 | uint8_t minor; /*!< Minor version number. */ |
<> | 144:ef7eb2e8f9f7 | 185 | uint8_t major; /*!< Major version number. */ |
<> | 144:ef7eb2e8f9f7 | 186 | } rcm_version_id_t; |
<> | 144:ef7eb2e8f9f7 | 187 | #endif |
<> | 144:ef7eb2e8f9f7 | 188 | |
<> | 144:ef7eb2e8f9f7 | 189 | /*! |
<> | 144:ef7eb2e8f9f7 | 190 | * @brief Reset pin filter configuration |
<> | 144:ef7eb2e8f9f7 | 191 | */ |
<> | 144:ef7eb2e8f9f7 | 192 | typedef struct _rcm_reset_pin_filter_config |
<> | 144:ef7eb2e8f9f7 | 193 | { |
<> | 144:ef7eb2e8f9f7 | 194 | bool enableFilterInStop; /*!< Reset pin filter select in stop mode. */ |
<> | 144:ef7eb2e8f9f7 | 195 | rcm_run_wait_filter_mode_t filterInRunWait; /*!< Reset pin filter in run/wait mode. */ |
<> | 144:ef7eb2e8f9f7 | 196 | uint8_t busClockFilterCount; /*!< Reset pin bus clock filter width. */ |
<> | 144:ef7eb2e8f9f7 | 197 | } rcm_reset_pin_filter_config_t; |
<> | 144:ef7eb2e8f9f7 | 198 | |
<> | 144:ef7eb2e8f9f7 | 199 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 200 | * API |
<> | 144:ef7eb2e8f9f7 | 201 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 202 | #if defined(__cplusplus) |
<> | 144:ef7eb2e8f9f7 | 203 | extern "C" { |
<> | 144:ef7eb2e8f9f7 | 204 | #endif /* __cplusplus*/ |
<> | 144:ef7eb2e8f9f7 | 205 | |
<> | 144:ef7eb2e8f9f7 | 206 | /*! @name Reset Control Module APIs*/ |
<> | 144:ef7eb2e8f9f7 | 207 | /*@{*/ |
<> | 144:ef7eb2e8f9f7 | 208 | |
<> | 144:ef7eb2e8f9f7 | 209 | #if (defined(FSL_FEATURE_RCM_HAS_VERID) && FSL_FEATURE_RCM_HAS_VERID) |
<> | 144:ef7eb2e8f9f7 | 210 | /*! |
<> | 144:ef7eb2e8f9f7 | 211 | * @brief Gets the RCM version ID. |
<> | 144:ef7eb2e8f9f7 | 212 | * |
<> | 144:ef7eb2e8f9f7 | 213 | * This function gets the RCM version ID including the major version number, |
<> | 144:ef7eb2e8f9f7 | 214 | * the minor version number, and the feature specification number. |
<> | 144:ef7eb2e8f9f7 | 215 | * |
<> | 144:ef7eb2e8f9f7 | 216 | * @param base RCM peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 217 | * @param versionId Pointer to version ID structure. |
<> | 144:ef7eb2e8f9f7 | 218 | */ |
<> | 144:ef7eb2e8f9f7 | 219 | static inline void RCM_GetVersionId(RCM_Type *base, rcm_version_id_t *versionId) |
<> | 144:ef7eb2e8f9f7 | 220 | { |
<> | 144:ef7eb2e8f9f7 | 221 | *((uint32_t *)versionId) = base->VERID; |
<> | 144:ef7eb2e8f9f7 | 222 | } |
<> | 144:ef7eb2e8f9f7 | 223 | #endif |
<> | 144:ef7eb2e8f9f7 | 224 | |
<> | 144:ef7eb2e8f9f7 | 225 | #if (defined(FSL_FEATURE_RCM_HAS_PARAM) && FSL_FEATURE_RCM_HAS_PARAM) |
<> | 144:ef7eb2e8f9f7 | 226 | /*! |
<> | 144:ef7eb2e8f9f7 | 227 | * @brief Gets the reset source implemented status. |
<> | 144:ef7eb2e8f9f7 | 228 | * |
<> | 144:ef7eb2e8f9f7 | 229 | * This function gets the RCM parameter that indicates whether the corresponding reset source is implemented. |
<> | 144:ef7eb2e8f9f7 | 230 | * Use source masks defined in the rcm_reset_source_t to get the desired source status. |
<> | 144:ef7eb2e8f9f7 | 231 | * |
<> | 144:ef7eb2e8f9f7 | 232 | * Example: |
<> | 144:ef7eb2e8f9f7 | 233 | @code |
<> | 144:ef7eb2e8f9f7 | 234 | uint32_t status; |
<> | 144:ef7eb2e8f9f7 | 235 | |
<> | 144:ef7eb2e8f9f7 | 236 | // To test whether the MCU is reset using Watchdog. |
<> | 144:ef7eb2e8f9f7 | 237 | status = RCM_GetResetSourceImplementedStatus(RCM) & (kRCM_SourceWdog | kRCM_SourcePin); |
<> | 144:ef7eb2e8f9f7 | 238 | @endcode |
<> | 144:ef7eb2e8f9f7 | 239 | * |
<> | 144:ef7eb2e8f9f7 | 240 | * @param base RCM peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 241 | * @return All reset source implemented status bit map. |
<> | 144:ef7eb2e8f9f7 | 242 | */ |
<> | 144:ef7eb2e8f9f7 | 243 | static inline uint32_t RCM_GetResetSourceImplementedStatus(RCM_Type *base) |
<> | 144:ef7eb2e8f9f7 | 244 | { |
<> | 144:ef7eb2e8f9f7 | 245 | return base->PARAM; |
<> | 144:ef7eb2e8f9f7 | 246 | } |
<> | 144:ef7eb2e8f9f7 | 247 | #endif /* FSL_FEATURE_RCM_HAS_PARAM */ |
<> | 144:ef7eb2e8f9f7 | 248 | |
<> | 144:ef7eb2e8f9f7 | 249 | /*! |
<> | 144:ef7eb2e8f9f7 | 250 | * @brief Gets the reset source status which caused a previous reset. |
<> | 144:ef7eb2e8f9f7 | 251 | * |
<> | 144:ef7eb2e8f9f7 | 252 | * This function gets the current reset source status. Use source masks |
<> | 144:ef7eb2e8f9f7 | 253 | * defined in the rcm_reset_source_t to get the desired source status. |
<> | 144:ef7eb2e8f9f7 | 254 | * |
<> | 144:ef7eb2e8f9f7 | 255 | * Example: |
<> | 144:ef7eb2e8f9f7 | 256 | @code |
<> | 144:ef7eb2e8f9f7 | 257 | uint32_t resetStatus; |
<> | 144:ef7eb2e8f9f7 | 258 | |
<> | 144:ef7eb2e8f9f7 | 259 | // To get all reset source statuses. |
<> | 144:ef7eb2e8f9f7 | 260 | resetStatus = RCM_GetPreviousResetSources(RCM) & kRCM_SourceAll; |
<> | 144:ef7eb2e8f9f7 | 261 | |
<> | 144:ef7eb2e8f9f7 | 262 | // To test whether the MCU is reset using Watchdog. |
<> | 144:ef7eb2e8f9f7 | 263 | resetStatus = RCM_GetPreviousResetSources(RCM) & kRCM_SourceWdog; |
<> | 144:ef7eb2e8f9f7 | 264 | |
<> | 144:ef7eb2e8f9f7 | 265 | // To test multiple reset sources. |
<> | 144:ef7eb2e8f9f7 | 266 | resetStatus = RCM_GetPreviousResetSources(RCM) & (kRCM_SourceWdog | kRCM_SourcePin); |
<> | 144:ef7eb2e8f9f7 | 267 | @endcode |
<> | 144:ef7eb2e8f9f7 | 268 | * |
<> | 144:ef7eb2e8f9f7 | 269 | * @param base RCM peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 270 | * @return All reset source status bit map. |
<> | 144:ef7eb2e8f9f7 | 271 | */ |
<> | 144:ef7eb2e8f9f7 | 272 | static inline uint32_t RCM_GetPreviousResetSources(RCM_Type *base) |
<> | 144:ef7eb2e8f9f7 | 273 | { |
<> | 144:ef7eb2e8f9f7 | 274 | #if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32)) |
<> | 144:ef7eb2e8f9f7 | 275 | return base->SRS; |
<> | 144:ef7eb2e8f9f7 | 276 | #else |
<> | 144:ef7eb2e8f9f7 | 277 | return (uint32_t)((uint32_t)base->SRS0 | ((uint32_t)base->SRS1 << 8U)); |
<> | 144:ef7eb2e8f9f7 | 278 | #endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */ |
<> | 144:ef7eb2e8f9f7 | 279 | } |
<> | 144:ef7eb2e8f9f7 | 280 | |
<> | 144:ef7eb2e8f9f7 | 281 | #if (defined(FSL_FEATURE_RCM_HAS_SSRS) && FSL_FEATURE_RCM_HAS_SSRS) |
<> | 144:ef7eb2e8f9f7 | 282 | /*! |
<> | 144:ef7eb2e8f9f7 | 283 | * @brief Gets the sticky reset source status. |
<> | 144:ef7eb2e8f9f7 | 284 | * |
<> | 144:ef7eb2e8f9f7 | 285 | * This function gets the current reset source status that has not been cleared |
<> | 144:ef7eb2e8f9f7 | 286 | * by software for some specific source. |
<> | 144:ef7eb2e8f9f7 | 287 | * |
<> | 144:ef7eb2e8f9f7 | 288 | * Example: |
<> | 144:ef7eb2e8f9f7 | 289 | @code |
<> | 144:ef7eb2e8f9f7 | 290 | uint32_t resetStatus; |
<> | 144:ef7eb2e8f9f7 | 291 | |
<> | 144:ef7eb2e8f9f7 | 292 | // To get all reset source statuses. |
<> | 144:ef7eb2e8f9f7 | 293 | resetStatus = RCM_GetStickyResetSources(RCM) & kRCM_SourceAll; |
<> | 144:ef7eb2e8f9f7 | 294 | |
<> | 144:ef7eb2e8f9f7 | 295 | // To test whether the MCU is reset using Watchdog. |
<> | 144:ef7eb2e8f9f7 | 296 | resetStatus = RCM_GetStickyResetSources(RCM) & kRCM_SourceWdog; |
<> | 144:ef7eb2e8f9f7 | 297 | |
<> | 144:ef7eb2e8f9f7 | 298 | // To test multiple reset sources. |
<> | 144:ef7eb2e8f9f7 | 299 | resetStatus = RCM_GetStickyResetSources(RCM) & (kRCM_SourceWdog | kRCM_SourcePin); |
<> | 144:ef7eb2e8f9f7 | 300 | @endcode |
<> | 144:ef7eb2e8f9f7 | 301 | * |
<> | 144:ef7eb2e8f9f7 | 302 | * @param base RCM peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 303 | * @return All reset source status bit map. |
<> | 144:ef7eb2e8f9f7 | 304 | */ |
<> | 144:ef7eb2e8f9f7 | 305 | static inline uint32_t RCM_GetStickyResetSources(RCM_Type *base) |
<> | 144:ef7eb2e8f9f7 | 306 | { |
<> | 144:ef7eb2e8f9f7 | 307 | #if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32)) |
<> | 144:ef7eb2e8f9f7 | 308 | return base->SSRS; |
<> | 144:ef7eb2e8f9f7 | 309 | #else |
<> | 144:ef7eb2e8f9f7 | 310 | return (base->SSRS0 | ((uint32_t)base->SSRS1 << 8U)); |
<> | 144:ef7eb2e8f9f7 | 311 | #endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */ |
<> | 144:ef7eb2e8f9f7 | 312 | } |
<> | 144:ef7eb2e8f9f7 | 313 | |
<> | 144:ef7eb2e8f9f7 | 314 | /*! |
<> | 144:ef7eb2e8f9f7 | 315 | * @brief Clears the sticky reset source status. |
<> | 144:ef7eb2e8f9f7 | 316 | * |
<> | 144:ef7eb2e8f9f7 | 317 | * This function clears the sticky system reset flags indicated by source masks. |
<> | 144:ef7eb2e8f9f7 | 318 | * |
<> | 144:ef7eb2e8f9f7 | 319 | * Example: |
<> | 144:ef7eb2e8f9f7 | 320 | @code |
<> | 144:ef7eb2e8f9f7 | 321 | // Clears multiple reset sources. |
<> | 144:ef7eb2e8f9f7 | 322 | RCM_ClearStickyResetSources(kRCM_SourceWdog | kRCM_SourcePin); |
<> | 144:ef7eb2e8f9f7 | 323 | @endcode |
<> | 144:ef7eb2e8f9f7 | 324 | * |
<> | 144:ef7eb2e8f9f7 | 325 | * @param base RCM peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 326 | * @param sourceMasks reset source status bit map |
<> | 144:ef7eb2e8f9f7 | 327 | */ |
<> | 144:ef7eb2e8f9f7 | 328 | static inline void RCM_ClearStickyResetSources(RCM_Type *base, uint32_t sourceMasks) |
<> | 144:ef7eb2e8f9f7 | 329 | { |
<> | 144:ef7eb2e8f9f7 | 330 | #if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32)) |
<> | 144:ef7eb2e8f9f7 | 331 | base->SSRS = sourceMasks; |
<> | 144:ef7eb2e8f9f7 | 332 | #else |
<> | 144:ef7eb2e8f9f7 | 333 | base->SSRS0 = (sourceMasks & 0xffU); |
<> | 144:ef7eb2e8f9f7 | 334 | base->SSRS1 = ((sourceMasks >> 8U) & 0xffU); |
<> | 144:ef7eb2e8f9f7 | 335 | #endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */ |
<> | 144:ef7eb2e8f9f7 | 336 | } |
<> | 144:ef7eb2e8f9f7 | 337 | #endif /* FSL_FEATURE_RCM_HAS_SSRS */ |
<> | 144:ef7eb2e8f9f7 | 338 | |
<> | 144:ef7eb2e8f9f7 | 339 | /*! |
<> | 144:ef7eb2e8f9f7 | 340 | * @brief Configures the reset pin filter. |
<> | 144:ef7eb2e8f9f7 | 341 | * |
<> | 144:ef7eb2e8f9f7 | 342 | * This function sets the reset pin filter including the filter source, filter |
<> | 144:ef7eb2e8f9f7 | 343 | * width, and so on. |
<> | 144:ef7eb2e8f9f7 | 344 | * |
<> | 144:ef7eb2e8f9f7 | 345 | * @param base RCM peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 346 | * @param config Pointer to the configuration structure. |
<> | 144:ef7eb2e8f9f7 | 347 | */ |
<> | 144:ef7eb2e8f9f7 | 348 | void RCM_ConfigureResetPinFilter(RCM_Type *base, const rcm_reset_pin_filter_config_t *config); |
<> | 144:ef7eb2e8f9f7 | 349 | |
<> | 144:ef7eb2e8f9f7 | 350 | #if (defined(FSL_FEATURE_RCM_HAS_EZPMS) && FSL_FEATURE_RCM_HAS_EZPMS) |
<> | 144:ef7eb2e8f9f7 | 351 | /*! |
<> | 144:ef7eb2e8f9f7 | 352 | * @brief Gets the EZP_MS_B pin assert status. |
<> | 144:ef7eb2e8f9f7 | 353 | * |
<> | 144:ef7eb2e8f9f7 | 354 | * This function gets the easy port mode status (EZP_MS_B) pin assert status. |
<> | 144:ef7eb2e8f9f7 | 355 | * |
<> | 144:ef7eb2e8f9f7 | 356 | * @param base RCM peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 357 | * @return status true - asserted, false - reasserted |
<> | 144:ef7eb2e8f9f7 | 358 | */ |
<> | 144:ef7eb2e8f9f7 | 359 | static inline bool RCM_GetEasyPortModePinStatus(RCM_Type *base) |
<> | 144:ef7eb2e8f9f7 | 360 | { |
<> | 144:ef7eb2e8f9f7 | 361 | return (bool)(base->MR & RCM_MR_EZP_MS_MASK); |
<> | 144:ef7eb2e8f9f7 | 362 | } |
<> | 144:ef7eb2e8f9f7 | 363 | #endif /* FSL_FEATURE_RCM_HAS_EZPMS */ |
<> | 144:ef7eb2e8f9f7 | 364 | |
<> | 144:ef7eb2e8f9f7 | 365 | #if (defined(FSL_FEATURE_RCM_HAS_BOOTROM) && FSL_FEATURE_RCM_HAS_BOOTROM) |
<> | 144:ef7eb2e8f9f7 | 366 | /*! |
<> | 144:ef7eb2e8f9f7 | 367 | * @brief Gets the ROM boot source. |
<> | 144:ef7eb2e8f9f7 | 368 | * |
<> | 144:ef7eb2e8f9f7 | 369 | * This function gets the ROM boot source during the last chip reset. |
<> | 144:ef7eb2e8f9f7 | 370 | * |
<> | 144:ef7eb2e8f9f7 | 371 | * @param base RCM peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 372 | * @return The ROM boot source. |
<> | 144:ef7eb2e8f9f7 | 373 | */ |
<> | 144:ef7eb2e8f9f7 | 374 | static inline rcm_boot_rom_config_t RCM_GetBootRomSource(RCM_Type *base) |
<> | 144:ef7eb2e8f9f7 | 375 | { |
<> | 144:ef7eb2e8f9f7 | 376 | return (rcm_boot_rom_config_t)((base->MR & RCM_MR_BOOTROM_MASK) >> RCM_MR_BOOTROM_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 377 | } |
<> | 144:ef7eb2e8f9f7 | 378 | |
<> | 144:ef7eb2e8f9f7 | 379 | /*! |
<> | 144:ef7eb2e8f9f7 | 380 | * @brief Clears the ROM boot source flag. |
<> | 144:ef7eb2e8f9f7 | 381 | * |
<> | 144:ef7eb2e8f9f7 | 382 | * This function clears the ROM boot source flag. |
<> | 144:ef7eb2e8f9f7 | 383 | * |
<> | 144:ef7eb2e8f9f7 | 384 | * @param base Register base address of RCM |
<> | 144:ef7eb2e8f9f7 | 385 | */ |
<> | 144:ef7eb2e8f9f7 | 386 | static inline void RCM_ClearBootRomSource(RCM_Type *base) |
<> | 144:ef7eb2e8f9f7 | 387 | { |
<> | 144:ef7eb2e8f9f7 | 388 | base->MR |= RCM_MR_BOOTROM_MASK; |
<> | 144:ef7eb2e8f9f7 | 389 | } |
<> | 144:ef7eb2e8f9f7 | 390 | |
<> | 144:ef7eb2e8f9f7 | 391 | /*! |
<> | 144:ef7eb2e8f9f7 | 392 | * @brief Forces the boot from ROM. |
<> | 144:ef7eb2e8f9f7 | 393 | * |
<> | 144:ef7eb2e8f9f7 | 394 | * This function forces booting from ROM during all subsequent system resets. |
<> | 144:ef7eb2e8f9f7 | 395 | * |
<> | 144:ef7eb2e8f9f7 | 396 | * @param base RCM peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 397 | * @param config Boot configuration. |
<> | 144:ef7eb2e8f9f7 | 398 | */ |
<> | 144:ef7eb2e8f9f7 | 399 | void RCM_SetForceBootRomSource(RCM_Type *base, rcm_boot_rom_config_t config); |
<> | 144:ef7eb2e8f9f7 | 400 | #endif /* FSL_FEATURE_RCM_HAS_BOOTROM */ |
<> | 144:ef7eb2e8f9f7 | 401 | |
<> | 144:ef7eb2e8f9f7 | 402 | #if (defined(FSL_FEATURE_RCM_HAS_SRIE) && FSL_FEATURE_RCM_HAS_SRIE) |
<> | 144:ef7eb2e8f9f7 | 403 | /*! |
<> | 144:ef7eb2e8f9f7 | 404 | * @brief Sets the system reset interrupt configuration. |
<> | 144:ef7eb2e8f9f7 | 405 | * |
<> | 144:ef7eb2e8f9f7 | 406 | * For graceful shutdown, the RCM supports delaying the assertion of the system |
<> | 144:ef7eb2e8f9f7 | 407 | * reset for a period of time when the reset interrupt is generated. This function |
<> | 144:ef7eb2e8f9f7 | 408 | * can be used to enable the interrupt and the delay period. The interrupts |
<> | 144:ef7eb2e8f9f7 | 409 | * are passed in as bit mask. See rcm_int_t for details. For example, to |
<> | 144:ef7eb2e8f9f7 | 410 | * delay a reset for 512 LPO cycles after the WDOG timeout or loss-of-clock occurs, |
<> | 144:ef7eb2e8f9f7 | 411 | * configure as follows: |
<> | 144:ef7eb2e8f9f7 | 412 | * RCM_SetSystemResetInterruptConfig(kRCM_IntWatchDog | kRCM_IntLossOfClk, kRCM_ResetDelay512Lpo); |
<> | 144:ef7eb2e8f9f7 | 413 | * |
<> | 144:ef7eb2e8f9f7 | 414 | * @param base RCM peripheral base address. |
<> | 144:ef7eb2e8f9f7 | 415 | * @param intMask Bit mask of the system reset interrupts to enable. See |
<> | 144:ef7eb2e8f9f7 | 416 | * rcm_interrupt_enable_t for details. |
<> | 144:ef7eb2e8f9f7 | 417 | * @param Delay Bit mask of the system reset interrupts to enable. |
<> | 144:ef7eb2e8f9f7 | 418 | */ |
<> | 144:ef7eb2e8f9f7 | 419 | static inline void RCM_SetSystemResetInterruptConfig(RCM_Type *base, uint32_t intMask, rcm_reset_delay_t delay) |
<> | 144:ef7eb2e8f9f7 | 420 | { |
<> | 144:ef7eb2e8f9f7 | 421 | base->SRIE = (intMask | delay); |
<> | 144:ef7eb2e8f9f7 | 422 | } |
<> | 144:ef7eb2e8f9f7 | 423 | #endif /* FSL_FEATURE_RCM_HAS_SRIE */ |
<> | 144:ef7eb2e8f9f7 | 424 | /*@}*/ |
<> | 144:ef7eb2e8f9f7 | 425 | |
<> | 144:ef7eb2e8f9f7 | 426 | #if defined(__cplusplus) |
<> | 144:ef7eb2e8f9f7 | 427 | } |
<> | 144:ef7eb2e8f9f7 | 428 | #endif /* __cplusplus*/ |
<> | 144:ef7eb2e8f9f7 | 429 | |
<> | 144:ef7eb2e8f9f7 | 430 | /*! @}*/ |
<> | 144:ef7eb2e8f9f7 | 431 | |
<> | 144:ef7eb2e8f9f7 | 432 | #endif /* _FSL_RCM_H_ */ |