Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/drivers/fsl_i2c.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 144:ef7eb2e8f9f7 3 * All rights reserved.
<> 144:ef7eb2e8f9f7 4 *
<> 144:ef7eb2e8f9f7 5 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 6 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 144:ef7eb2e8f9f7 9 * of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 144:ef7eb2e8f9f7 12 * list of conditions and the following disclaimer in the documentation and/or
<> 144:ef7eb2e8f9f7 13 * other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 144:ef7eb2e8f9f7 16 * contributors may be used to endorse or promote products derived from this
<> 144:ef7eb2e8f9f7 17 * software without specific prior written permission.
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 29 */
<> 144:ef7eb2e8f9f7 30 #ifndef _FSL_I2C_H_
<> 144:ef7eb2e8f9f7 31 #define _FSL_I2C_H_
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 #include "fsl_common.h"
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 /*!
<> 144:ef7eb2e8f9f7 36 * @addtogroup i2c_driver
<> 144:ef7eb2e8f9f7 37 * @{
<> 144:ef7eb2e8f9f7 38 */
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 /*! @file */
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 /*******************************************************************************
<> 144:ef7eb2e8f9f7 43 * Definitions
<> 144:ef7eb2e8f9f7 44 ******************************************************************************/
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /*! @name Driver version */
<> 144:ef7eb2e8f9f7 47 /*@{*/
<> 144:ef7eb2e8f9f7 48 /*! @brief I2C driver version 2.0.0. */
<> 144:ef7eb2e8f9f7 49 #define FSL_I2C_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
<> 144:ef7eb2e8f9f7 50 /*@}*/
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 #if (defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT || \
<> 144:ef7eb2e8f9f7 53 defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT)
<> 144:ef7eb2e8f9f7 54 #define I2C_HAS_STOP_DETECT
<> 144:ef7eb2e8f9f7 55 #endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT / FSL_FEATURE_I2C_HAS_STOP_DETECT */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /*! @brief I2C status return codes. */
<> 144:ef7eb2e8f9f7 58 enum _i2c_status
<> 144:ef7eb2e8f9f7 59 {
<> 144:ef7eb2e8f9f7 60 kStatus_I2C_Busy = MAKE_STATUS(kStatusGroup_I2C, 0), /*!< I2C is busy with current transfer. */
<> 144:ef7eb2e8f9f7 61 kStatus_I2C_Idle = MAKE_STATUS(kStatusGroup_I2C, 1), /*!< Bus is Idle. */
<> 144:ef7eb2e8f9f7 62 kStatus_I2C_Nak = MAKE_STATUS(kStatusGroup_I2C, 2), /*!< NAK received during transfer. */
<> 144:ef7eb2e8f9f7 63 kStatus_I2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_I2C, 3), /*!< Arbitration lost during transfer. */
<> 144:ef7eb2e8f9f7 64 kStatus_I2C_Timeout = MAKE_STATUS(kStatusGroup_I2C, 4), /*!< Wait event timeout. */
<> 144:ef7eb2e8f9f7 65 };
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 /*!
<> 144:ef7eb2e8f9f7 68 * @brief I2C peripheral flags
<> 144:ef7eb2e8f9f7 69 *
<> 144:ef7eb2e8f9f7 70 * The following status register flags can be cleared:
<> 144:ef7eb2e8f9f7 71 * - #kI2C_ArbitrationLostFlag
<> 144:ef7eb2e8f9f7 72 * - #kI2C_IntPendingFlag
<> 144:ef7eb2e8f9f7 73 * - #kI2C_StartDetectFlag
<> 144:ef7eb2e8f9f7 74 * - #kI2C_StopDetectFlag
<> 144:ef7eb2e8f9f7 75 *
<> 144:ef7eb2e8f9f7 76 * @note These enumerations are meant to be OR'd together to form a bit mask.
<> 144:ef7eb2e8f9f7 77 *
<> 144:ef7eb2e8f9f7 78 */
<> 144:ef7eb2e8f9f7 79 enum _i2c_flags
<> 144:ef7eb2e8f9f7 80 {
<> 144:ef7eb2e8f9f7 81 kI2C_ReceiveNakFlag = I2C_S_RXAK_MASK, /*!< I2C receive NAK flag. */
<> 144:ef7eb2e8f9f7 82 kI2C_IntPendingFlag = I2C_S_IICIF_MASK, /*!< I2C interrupt pending flag. */
<> 144:ef7eb2e8f9f7 83 kI2C_TransferDirectionFlag = I2C_S_SRW_MASK, /*!< I2C transfer direction flag. */
<> 144:ef7eb2e8f9f7 84 kI2C_RangeAddressMatchFlag = I2C_S_RAM_MASK, /*!< I2C range address match flag. */
<> 144:ef7eb2e8f9f7 85 kI2C_ArbitrationLostFlag = I2C_S_ARBL_MASK, /*!< I2C arbitration lost flag. */
<> 144:ef7eb2e8f9f7 86 kI2C_BusBusyFlag = I2C_S_BUSY_MASK, /*!< I2C bus busy flag. */
<> 144:ef7eb2e8f9f7 87 kI2C_AddressMatchFlag = I2C_S_IAAS_MASK, /*!< I2C address match flag. */
<> 144:ef7eb2e8f9f7 88 kI2C_TransferCompleteFlag = I2C_S_TCF_MASK, /*!< I2C transfer complete flag. */
<> 144:ef7eb2e8f9f7 89 #ifdef I2C_HAS_STOP_DETECT
<> 144:ef7eb2e8f9f7 90 kI2C_StopDetectFlag = I2C_FLT_STOPF_MASK << 8, /*!< I2C stop detect flag. */
<> 144:ef7eb2e8f9f7 91 #endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT / FSL_FEATURE_I2C_HAS_STOP_DETECT */
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 #if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
<> 144:ef7eb2e8f9f7 94 kI2C_StartDetectFlag = I2C_FLT_STARTF_MASK << 8, /*!< I2C start detect flag. */
<> 144:ef7eb2e8f9f7 95 #endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */
<> 144:ef7eb2e8f9f7 96 };
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 /*! @brief I2C feature interrupt source. */
<> 144:ef7eb2e8f9f7 99 enum _i2c_interrupt_enable
<> 144:ef7eb2e8f9f7 100 {
<> 144:ef7eb2e8f9f7 101 kI2C_GlobalInterruptEnable = I2C_C1_IICIE_MASK, /*!< I2C global interrupt. */
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 #if defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT
<> 144:ef7eb2e8f9f7 104 kI2C_StopDetectInterruptEnable = I2C_FLT_STOPIE_MASK, /*!< I2C stop detect interrupt. */
<> 144:ef7eb2e8f9f7 105 #endif /* FSL_FEATURE_I2C_HAS_STOP_DETECT */
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 #if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
<> 144:ef7eb2e8f9f7 108 kI2C_StartStopDetectInterruptEnable = I2C_FLT_SSIE_MASK, /*!< I2C start&stop detect interrupt. */
<> 144:ef7eb2e8f9f7 109 #endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */
<> 144:ef7eb2e8f9f7 110 };
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 /*! @brief Direction of master and slave transfers. */
<> 144:ef7eb2e8f9f7 113 typedef enum _i2c_direction
<> 144:ef7eb2e8f9f7 114 {
<> 144:ef7eb2e8f9f7 115 kI2C_Write = 0x0U, /*!< Master transmit to slave. */
<> 144:ef7eb2e8f9f7 116 kI2C_Read = 0x1U, /*!< Master receive from slave. */
<> 144:ef7eb2e8f9f7 117 } i2c_direction_t;
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 /*! @brief Addressing mode. */
<> 144:ef7eb2e8f9f7 120 typedef enum _i2c_slave_address_mode
<> 144:ef7eb2e8f9f7 121 {
<> 144:ef7eb2e8f9f7 122 kI2C_Address7bit = 0x0U, /*!< 7-bit addressing mode. */
<> 144:ef7eb2e8f9f7 123 kI2C_RangeMatch = 0X2U, /*!< Range address match addressing mode. */
<> 144:ef7eb2e8f9f7 124 } i2c_slave_address_mode_t;
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 /*! @brief I2C transfer control flag. */
<> 144:ef7eb2e8f9f7 127 enum _i2c_master_transfer_flags
<> 144:ef7eb2e8f9f7 128 {
<> 144:ef7eb2e8f9f7 129 kI2C_TransferDefaultFlag = 0x0U, /*!< Transfer starts with a start signal, stops with a stop signal. */
<> 144:ef7eb2e8f9f7 130 kI2C_TransferNoStartFlag = 0x1U, /*!< Transfer starts without a start signal. */
<> 144:ef7eb2e8f9f7 131 kI2C_TransferRepeatedStartFlag = 0x2U, /*!< Transfer starts with a repeated start signal. */
<> 144:ef7eb2e8f9f7 132 kI2C_TransferNoStopFlag = 0x4U, /*!< Transfer ends without a stop signal. */
<> 144:ef7eb2e8f9f7 133 };
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 /*!
<> 144:ef7eb2e8f9f7 136 * @brief Set of events sent to the callback for nonblocking slave transfers.
<> 144:ef7eb2e8f9f7 137 *
<> 144:ef7eb2e8f9f7 138 * These event enumerations are used for two related purposes. First, a bit mask created by OR'ing together
<> 144:ef7eb2e8f9f7 139 * events is passed to I2C_SlaveTransferNonBlocking() in order to specify which events to enable.
<> 144:ef7eb2e8f9f7 140 * Then, when the slave callback is invoked, it is passed the current event through its @a transfer
<> 144:ef7eb2e8f9f7 141 * parameter.
<> 144:ef7eb2e8f9f7 142 *
<> 144:ef7eb2e8f9f7 143 * @note These enumerations are meant to be OR'd together to form a bit mask of events.
<> 144:ef7eb2e8f9f7 144 */
<> 144:ef7eb2e8f9f7 145 typedef enum _i2c_slave_transfer_event
<> 144:ef7eb2e8f9f7 146 {
<> 144:ef7eb2e8f9f7 147 kI2C_SlaveAddressMatchEvent = 0x01U, /*!< Received the slave address after a start or repeated start. */
<> 144:ef7eb2e8f9f7 148 kI2C_SlaveTransmitEvent = 0x02U, /*!< Callback is requested to provide data to transmit
<> 144:ef7eb2e8f9f7 149 (slave-transmitter role). */
<> 144:ef7eb2e8f9f7 150 kI2C_SlaveReceiveEvent = 0x04U, /*!< Callback is requested to provide a buffer in which to place received
<> 144:ef7eb2e8f9f7 151 data (slave-receiver role). */
<> 144:ef7eb2e8f9f7 152 kI2C_SlaveTransmitAckEvent = 0x08U, /*!< Callback needs to either transmit an ACK or NACK. */
<> 144:ef7eb2e8f9f7 153 #if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
<> 144:ef7eb2e8f9f7 154 kI2C_SlaveRepeatedStartEvent = 0x10U, /*!< A repeated start was detected. */
<> 144:ef7eb2e8f9f7 155 #endif
<> 144:ef7eb2e8f9f7 156 kI2C_SlaveCompletionEvent = 0x20U, /*!< A stop was detected or finished transfer, completing the transfer. */
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 /*! Bit mask of all available events. */
<> 144:ef7eb2e8f9f7 159 kI2C_SlaveAllEvents = kI2C_SlaveAddressMatchEvent | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent |
<> 144:ef7eb2e8f9f7 160 #if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
<> 144:ef7eb2e8f9f7 161 kI2C_SlaveRepeatedStartEvent |
<> 144:ef7eb2e8f9f7 162 #endif
<> 144:ef7eb2e8f9f7 163 kI2C_SlaveCompletionEvent,
<> 144:ef7eb2e8f9f7 164 } i2c_slave_transfer_event_t;
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 /*! @brief I2C master user configuration. */
<> 144:ef7eb2e8f9f7 167 typedef struct _i2c_master_config
<> 144:ef7eb2e8f9f7 168 {
<> 144:ef7eb2e8f9f7 169 bool enableMaster; /*!< Enables the I2C peripheral at initialization time. */
<> 144:ef7eb2e8f9f7 170 #if defined(FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION) && FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION
<> 144:ef7eb2e8f9f7 171 bool enableHighDrive; /*!< Controls the drive capability of the I2C pads. */
<> 144:ef7eb2e8f9f7 172 #endif
<> 144:ef7eb2e8f9f7 173 #if defined(FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF) && FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF
<> 144:ef7eb2e8f9f7 174 bool enableStopHold; /*!< Controls the stop hold enable. */
<> 144:ef7eb2e8f9f7 175 #endif
<> 144:ef7eb2e8f9f7 176 uint32_t baudRate_Bps; /*!< Baud rate configuration of I2C peripheral. */
<> 144:ef7eb2e8f9f7 177 uint8_t glitchFilterWidth; /*!< Controls the width of the glitch. */
<> 144:ef7eb2e8f9f7 178 } i2c_master_config_t;
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 /*! @brief I2C slave user configuration. */
<> 144:ef7eb2e8f9f7 181 typedef struct _i2c_slave_config
<> 144:ef7eb2e8f9f7 182 {
<> 144:ef7eb2e8f9f7 183 bool enableSlave; /*!< Enables the I2C peripheral at initialization time. */
<> 144:ef7eb2e8f9f7 184 bool enableGeneralCall; /*!< Enable general call addressing mode. */
<> 144:ef7eb2e8f9f7 185 bool enableWakeUp; /*!< Enables/disables waking up MCU from low power mode. */
<> 144:ef7eb2e8f9f7 186 #if defined(FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION) && FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION
<> 144:ef7eb2e8f9f7 187 bool enableHighDrive; /*!< Controls the drive capability of the I2C pads. */
<> 144:ef7eb2e8f9f7 188 #endif
<> 144:ef7eb2e8f9f7 189 bool enableBaudRateCtl; /*!< Enables/disables independent slave baud rate on SCL in very fast I2C modes. */
<> 144:ef7eb2e8f9f7 190 uint16_t slaveAddress; /*!< Slave address configuration. */
<> 144:ef7eb2e8f9f7 191 uint16_t upperAddress; /*!< Maximum boundary slave address used in range matching mode. */
<> 144:ef7eb2e8f9f7 192 i2c_slave_address_mode_t addressingMode; /*!< Addressing mode configuration of i2c_slave_address_mode_config_t. */
<> 144:ef7eb2e8f9f7 193 } i2c_slave_config_t;
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 /*! @brief I2C master handle typedef. */
<> 144:ef7eb2e8f9f7 196 typedef struct _i2c_master_handle i2c_master_handle_t;
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 /*! @brief I2C master transfer callback typedef. */
<> 144:ef7eb2e8f9f7 199 typedef void (*i2c_master_transfer_callback_t)(I2C_Type *base,
<> 144:ef7eb2e8f9f7 200 i2c_master_handle_t *handle,
<> 144:ef7eb2e8f9f7 201 status_t status,
<> 144:ef7eb2e8f9f7 202 void *userData);
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 /*! @brief I2C slave handle typedef. */
<> 144:ef7eb2e8f9f7 205 typedef struct _i2c_slave_handle i2c_slave_handle_t;
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 /*! @brief I2C master transfer structure. */
<> 144:ef7eb2e8f9f7 208 typedef struct _i2c_master_transfer
<> 144:ef7eb2e8f9f7 209 {
<> 144:ef7eb2e8f9f7 210 uint32_t flags; /*!< Transfer flag which controls the transfer. */
<> 144:ef7eb2e8f9f7 211 uint8_t slaveAddress; /*!< 7-bit slave address. */
<> 144:ef7eb2e8f9f7 212 i2c_direction_t direction; /*!< Transfer direction, read or write. */
<> 144:ef7eb2e8f9f7 213 uint32_t subaddress; /*!< Sub address. Transferred MSB first. */
<> 144:ef7eb2e8f9f7 214 uint8_t subaddressSize; /*!< Size of command buffer. */
<> 144:ef7eb2e8f9f7 215 uint8_t *volatile data; /*!< Transfer buffer. */
<> 144:ef7eb2e8f9f7 216 volatile size_t dataSize; /*!< Transfer size. */
<> 144:ef7eb2e8f9f7 217 } i2c_master_transfer_t;
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 /*! @brief I2C master handle structure. */
<> 144:ef7eb2e8f9f7 220 struct _i2c_master_handle
<> 144:ef7eb2e8f9f7 221 {
<> 144:ef7eb2e8f9f7 222 i2c_master_transfer_t transfer; /*!< I2C master transfer copy. */
<> 144:ef7eb2e8f9f7 223 size_t transferSize; /*!< Total bytes to be transferred. */
<> 144:ef7eb2e8f9f7 224 uint8_t state; /*!< Transfer state maintained during transfer. */
<> 144:ef7eb2e8f9f7 225 i2c_master_transfer_callback_t completionCallback; /*!< Callback function called when transfer finished. */
<> 144:ef7eb2e8f9f7 226 void *userData; /*!< Callback parameter passed to callback function. */
<> 144:ef7eb2e8f9f7 227 };
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 /*! @brief I2C slave transfer structure. */
<> 144:ef7eb2e8f9f7 230 typedef struct _i2c_slave_transfer
<> 144:ef7eb2e8f9f7 231 {
<> 144:ef7eb2e8f9f7 232 i2c_slave_transfer_event_t event; /*!< Reason the callback is being invoked. */
<> 144:ef7eb2e8f9f7 233 uint8_t *volatile data; /*!< Transfer buffer. */
<> 144:ef7eb2e8f9f7 234 volatile size_t dataSize; /*!< Transfer size. */
<> 144:ef7eb2e8f9f7 235 status_t completionStatus; /*!< Success or error code describing how the transfer completed. Only applies for
<> 144:ef7eb2e8f9f7 236 #kI2C_SlaveCompletionEvent. */
<> 144:ef7eb2e8f9f7 237 size_t transferredCount; /*!< Number of bytes actually transferred since start or last repeated start. */
<> 144:ef7eb2e8f9f7 238 } i2c_slave_transfer_t;
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 /*! @brief I2C slave transfer callback typedef. */
<> 144:ef7eb2e8f9f7 241 typedef void (*i2c_slave_transfer_callback_t)(I2C_Type *base, i2c_slave_transfer_t *xfer, void *userData);
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 /*! @brief I2C slave handle structure. */
<> 144:ef7eb2e8f9f7 244 struct _i2c_slave_handle
<> 144:ef7eb2e8f9f7 245 {
<> 144:ef7eb2e8f9f7 246 bool isBusy; /*!< Whether transfer is busy. */
<> 144:ef7eb2e8f9f7 247 i2c_slave_transfer_t transfer; /*!< I2C slave transfer copy. */
<> 144:ef7eb2e8f9f7 248 uint32_t eventMask; /*!< Mask of enabled events. */
<> 144:ef7eb2e8f9f7 249 i2c_slave_transfer_callback_t callback; /*!< Callback function called at transfer event. */
<> 144:ef7eb2e8f9f7 250 void *userData; /*!< Callback parameter passed to callback. */
<> 144:ef7eb2e8f9f7 251 };
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 /*******************************************************************************
<> 144:ef7eb2e8f9f7 254 * API
<> 144:ef7eb2e8f9f7 255 ******************************************************************************/
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 #if defined(__cplusplus)
<> 144:ef7eb2e8f9f7 258 extern "C" {
<> 144:ef7eb2e8f9f7 259 #endif /*_cplusplus. */
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 /*!
<> 144:ef7eb2e8f9f7 262 * @name Initialization and deinitialization
<> 144:ef7eb2e8f9f7 263 * @{
<> 144:ef7eb2e8f9f7 264 */
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266 /*!
<> 144:ef7eb2e8f9f7 267 * @brief Initializes the I2C peripheral. Call this API to ungate the I2C clock
<> 144:ef7eb2e8f9f7 268 * and configure the I2C with master configuration.
<> 144:ef7eb2e8f9f7 269 *
<> 144:ef7eb2e8f9f7 270 * @note This API should be called at the beginning of the application to use
<> 144:ef7eb2e8f9f7 271 * the I2C driver, or any operation to the I2C module could cause hard fault
<> 144:ef7eb2e8f9f7 272 * because clock is not enabled. The configuration structure can be filled by user
<> 144:ef7eb2e8f9f7 273 * from scratch, or be set with default values by I2C_MasterGetDefaultConfig().
<> 144:ef7eb2e8f9f7 274 * After calling this API, the master is ready to transfer.
<> 144:ef7eb2e8f9f7 275 * Example:
<> 144:ef7eb2e8f9f7 276 * @code
<> 144:ef7eb2e8f9f7 277 * i2c_master_config_t config = {
<> 144:ef7eb2e8f9f7 278 * .enableMaster = true,
<> 144:ef7eb2e8f9f7 279 * .enableStopHold = false,
<> 144:ef7eb2e8f9f7 280 * .highDrive = false,
<> 144:ef7eb2e8f9f7 281 * .baudRate_Bps = 100000,
<> 144:ef7eb2e8f9f7 282 * .glitchFilterWidth = 0
<> 144:ef7eb2e8f9f7 283 * };
<> 144:ef7eb2e8f9f7 284 * I2C_MasterInit(I2C0, &config, 12000000U);
<> 144:ef7eb2e8f9f7 285 * @endcode
<> 144:ef7eb2e8f9f7 286 *
<> 144:ef7eb2e8f9f7 287 * @param base I2C base pointer
<> 144:ef7eb2e8f9f7 288 * @param masterConfig pointer to master configuration structure
<> 144:ef7eb2e8f9f7 289 * @param srcClock_Hz I2C peripheral clock frequency in Hz
<> 144:ef7eb2e8f9f7 290 */
<> 144:ef7eb2e8f9f7 291 void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz);
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 /*!
<> 144:ef7eb2e8f9f7 294 * @brief Initializes the I2C peripheral. Call this API to ungate the I2C clock
<> 144:ef7eb2e8f9f7 295 * and initializes the I2C with slave configuration.
<> 144:ef7eb2e8f9f7 296 *
<> 144:ef7eb2e8f9f7 297 * @note This API should be called at the beginning of the application to use
<> 144:ef7eb2e8f9f7 298 * the I2C driver, or any operation to the I2C module can cause a hard fault
<> 144:ef7eb2e8f9f7 299 * because the clock is not enabled. The configuration structure can partly be set
<> 144:ef7eb2e8f9f7 300 * with default values by I2C_SlaveGetDefaultConfig(), or can be filled by the user.
<> 144:ef7eb2e8f9f7 301 * Example
<> 144:ef7eb2e8f9f7 302 * @code
<> 144:ef7eb2e8f9f7 303 * i2c_slave_config_t config = {
<> 144:ef7eb2e8f9f7 304 * .enableSlave = true,
<> 144:ef7eb2e8f9f7 305 * .enableGeneralCall = false,
<> 144:ef7eb2e8f9f7 306 * .addressingMode = kI2C_Address7bit,
<> 144:ef7eb2e8f9f7 307 * .slaveAddress = 0x1DU,
<> 144:ef7eb2e8f9f7 308 * .enableWakeUp = false,
<> 144:ef7eb2e8f9f7 309 * .enablehighDrive = false,
<> 144:ef7eb2e8f9f7 310 * .enableBaudRateCtl = false
<> 144:ef7eb2e8f9f7 311 * };
<> 144:ef7eb2e8f9f7 312 * I2C_SlaveInit(I2C0, &config);
<> 144:ef7eb2e8f9f7 313 * @endcode
<> 144:ef7eb2e8f9f7 314 *
<> 144:ef7eb2e8f9f7 315 * @param base I2C base pointer
<> 144:ef7eb2e8f9f7 316 * @param slaveConfig pointer to slave configuration structure
<> 144:ef7eb2e8f9f7 317 */
<> 144:ef7eb2e8f9f7 318 void I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig);
<> 144:ef7eb2e8f9f7 319
<> 144:ef7eb2e8f9f7 320 /*!
<> 144:ef7eb2e8f9f7 321 * @brief De-initializes the I2C master peripheral. Call this API to gate the I2C clock.
<> 144:ef7eb2e8f9f7 322 * The I2C master module can't work unless the I2C_MasterInit is called.
<> 144:ef7eb2e8f9f7 323 * @param base I2C base pointer
<> 144:ef7eb2e8f9f7 324 */
<> 144:ef7eb2e8f9f7 325 void I2C_MasterDeinit(I2C_Type *base);
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327 /*!
<> 144:ef7eb2e8f9f7 328 * @brief De-initializes the I2C slave peripheral. Calling this API gates the I2C clock.
<> 144:ef7eb2e8f9f7 329 * The I2C slave module can't work unless the I2C_SlaveInit is called to enable the clock.
<> 144:ef7eb2e8f9f7 330 * @param base I2C base pointer
<> 144:ef7eb2e8f9f7 331 */
<> 144:ef7eb2e8f9f7 332 void I2C_SlaveDeinit(I2C_Type *base);
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 /*!
<> 144:ef7eb2e8f9f7 335 * @brief Sets the I2C master configuration structure to default values.
<> 144:ef7eb2e8f9f7 336 *
<> 144:ef7eb2e8f9f7 337 * The purpose of this API is to get the configuration structure initialized for use in the I2C_MasterConfigure().
<> 144:ef7eb2e8f9f7 338 * Use the initialized structure unchanged in I2C_MasterConfigure(), or modify some fields of
<> 144:ef7eb2e8f9f7 339 * the structure before calling I2C_MasterConfigure().
<> 144:ef7eb2e8f9f7 340 * Example:
<> 144:ef7eb2e8f9f7 341 * @code
<> 144:ef7eb2e8f9f7 342 * i2c_master_config_t config;
<> 144:ef7eb2e8f9f7 343 * I2C_MasterGetDefaultConfig(&config);
<> 144:ef7eb2e8f9f7 344 * @endcode
<> 144:ef7eb2e8f9f7 345 * @param masterConfig Pointer to the master configuration structure.
<> 144:ef7eb2e8f9f7 346 */
<> 144:ef7eb2e8f9f7 347 void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig);
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 /*!
<> 144:ef7eb2e8f9f7 350 * @brief Sets the I2C slave configuration structure to default values.
<> 144:ef7eb2e8f9f7 351 *
<> 144:ef7eb2e8f9f7 352 * The purpose of this API is to get the configuration structure initialized for use in I2C_SlaveConfigure().
<> 144:ef7eb2e8f9f7 353 * Modify fields of the structure before calling the I2C_SlaveConfigure().
<> 144:ef7eb2e8f9f7 354 * Example:
<> 144:ef7eb2e8f9f7 355 * @code
<> 144:ef7eb2e8f9f7 356 * i2c_slave_config_t config;
<> 144:ef7eb2e8f9f7 357 * I2C_SlaveGetDefaultConfig(&config);
<> 144:ef7eb2e8f9f7 358 * @endcode
<> 144:ef7eb2e8f9f7 359 * @param slaveConfig Pointer to the slave configuration structure.
<> 144:ef7eb2e8f9f7 360 */
<> 144:ef7eb2e8f9f7 361 void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig);
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 /*!
<> 144:ef7eb2e8f9f7 364 * @brief Enables or disabless the I2C peripheral operation.
<> 144:ef7eb2e8f9f7 365 *
<> 144:ef7eb2e8f9f7 366 * @param base I2C base pointer
<> 144:ef7eb2e8f9f7 367 * @param enable pass true to enable module, false to disable module
<> 144:ef7eb2e8f9f7 368 */
<> 144:ef7eb2e8f9f7 369 static inline void I2C_Enable(I2C_Type *base, bool enable)
<> 144:ef7eb2e8f9f7 370 {
<> 144:ef7eb2e8f9f7 371 if (enable)
<> 144:ef7eb2e8f9f7 372 {
<> 144:ef7eb2e8f9f7 373 base->C1 |= I2C_C1_IICEN_MASK;
<> 144:ef7eb2e8f9f7 374 }
<> 144:ef7eb2e8f9f7 375 else
<> 144:ef7eb2e8f9f7 376 {
<> 144:ef7eb2e8f9f7 377 base->C1 &= ~I2C_C1_IICEN_MASK;
<> 144:ef7eb2e8f9f7 378 }
<> 144:ef7eb2e8f9f7 379 }
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 /* @} */
<> 144:ef7eb2e8f9f7 382
<> 144:ef7eb2e8f9f7 383 /*!
<> 144:ef7eb2e8f9f7 384 * @name Status
<> 144:ef7eb2e8f9f7 385 * @{
<> 144:ef7eb2e8f9f7 386 */
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388 /*!
<> 144:ef7eb2e8f9f7 389 * @brief Gets the I2C status flags.
<> 144:ef7eb2e8f9f7 390 *
<> 144:ef7eb2e8f9f7 391 * @param base I2C base pointer
<> 144:ef7eb2e8f9f7 392 * @return status flag, use status flag to AND #_i2c_flags could get the related status.
<> 144:ef7eb2e8f9f7 393 */
<> 144:ef7eb2e8f9f7 394 uint32_t I2C_MasterGetStatusFlags(I2C_Type *base);
<> 144:ef7eb2e8f9f7 395
<> 144:ef7eb2e8f9f7 396 /*!
<> 144:ef7eb2e8f9f7 397 * @brief Gets the I2C status flags.
<> 144:ef7eb2e8f9f7 398 *
<> 144:ef7eb2e8f9f7 399 * @param base I2C base pointer
<> 144:ef7eb2e8f9f7 400 * @return status flag, use status flag to AND #_i2c_flags could get the related status.
<> 144:ef7eb2e8f9f7 401 */
<> 144:ef7eb2e8f9f7 402 static inline uint32_t I2C_SlaveGetStatusFlags(I2C_Type *base)
<> 144:ef7eb2e8f9f7 403 {
<> 144:ef7eb2e8f9f7 404 return I2C_MasterGetStatusFlags(base);
<> 144:ef7eb2e8f9f7 405 }
<> 144:ef7eb2e8f9f7 406
<> 144:ef7eb2e8f9f7 407 /*!
<> 144:ef7eb2e8f9f7 408 * @brief Clears the I2C status flag state.
<> 144:ef7eb2e8f9f7 409 *
<> 144:ef7eb2e8f9f7 410 * The following status register flags can be cleared: kI2C_ArbitrationLostFlag and kI2C_IntPendingFlag
<> 144:ef7eb2e8f9f7 411 *
<> 144:ef7eb2e8f9f7 412 * @param base I2C base pointer
<> 144:ef7eb2e8f9f7 413 * @param statusMask The status flag mask, defined in type i2c_status_flag_t.
<> 144:ef7eb2e8f9f7 414 * The parameter could be any combination of the following values:
<> 144:ef7eb2e8f9f7 415 * @arg kI2C_StartDetectFlag (if available)
<> 144:ef7eb2e8f9f7 416 * @arg kI2C_StopDetectFlag (if available)
<> 144:ef7eb2e8f9f7 417 * @arg kI2C_ArbitrationLostFlag
<> 144:ef7eb2e8f9f7 418 * @arg kI2C_IntPendingFlagFlag
<> 144:ef7eb2e8f9f7 419 */
<> 144:ef7eb2e8f9f7 420 static inline void I2C_MasterClearStatusFlags(I2C_Type *base, uint32_t statusMask)
<> 144:ef7eb2e8f9f7 421 {
<> 144:ef7eb2e8f9f7 422 /* Must clear the STARTF / STOPF bits prior to clearing IICIF */
<> 144:ef7eb2e8f9f7 423 #if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
<> 144:ef7eb2e8f9f7 424 if (statusMask & kI2C_StartDetectFlag)
<> 144:ef7eb2e8f9f7 425 {
<> 144:ef7eb2e8f9f7 426 /* Shift the odd-ball flags back into place. */
<> 144:ef7eb2e8f9f7 427 base->FLT |= (uint8_t)(statusMask >> 8U);
<> 144:ef7eb2e8f9f7 428 }
<> 144:ef7eb2e8f9f7 429 #endif
<> 144:ef7eb2e8f9f7 430
<> 144:ef7eb2e8f9f7 431 #ifdef I2C_HAS_STOP_DETECT
<> 144:ef7eb2e8f9f7 432 if (statusMask & kI2C_StopDetectFlag)
<> 144:ef7eb2e8f9f7 433 {
<> 144:ef7eb2e8f9f7 434 /* Shift the odd-ball flags back into place. */
<> 144:ef7eb2e8f9f7 435 base->FLT |= (uint8_t)(statusMask >> 8U);
<> 144:ef7eb2e8f9f7 436 }
<> 144:ef7eb2e8f9f7 437 #endif
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 base->S = (uint8_t)statusMask;
<> 144:ef7eb2e8f9f7 440 }
<> 144:ef7eb2e8f9f7 441
<> 144:ef7eb2e8f9f7 442 /*!
<> 144:ef7eb2e8f9f7 443 * @brief Clears the I2C status flag state.
<> 144:ef7eb2e8f9f7 444 *
<> 144:ef7eb2e8f9f7 445 * The following status register flags can be cleared: kI2C_ArbitrationLostFlag and kI2C_IntPendingFlag
<> 144:ef7eb2e8f9f7 446 *
<> 144:ef7eb2e8f9f7 447 * @param base I2C base pointer
<> 144:ef7eb2e8f9f7 448 * @param statusMask The status flag mask, defined in type i2c_status_flag_t.
<> 144:ef7eb2e8f9f7 449 * The parameter could be any combination of the following values:
<> 144:ef7eb2e8f9f7 450 * @arg kI2C_StartDetectFlag (if available)
<> 144:ef7eb2e8f9f7 451 * @arg kI2C_StopDetectFlag (if available)
<> 144:ef7eb2e8f9f7 452 * @arg kI2C_ArbitrationLostFlag
<> 144:ef7eb2e8f9f7 453 * @arg kI2C_IntPendingFlagFlag
<> 144:ef7eb2e8f9f7 454 */
<> 144:ef7eb2e8f9f7 455 static inline void I2C_SlaveClearStatusFlags(I2C_Type *base, uint32_t statusMask)
<> 144:ef7eb2e8f9f7 456 {
<> 144:ef7eb2e8f9f7 457 I2C_MasterClearStatusFlags(base, statusMask);
<> 144:ef7eb2e8f9f7 458 }
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 /* @} */
<> 144:ef7eb2e8f9f7 461
<> 144:ef7eb2e8f9f7 462 /*!
<> 144:ef7eb2e8f9f7 463 * @name Interrupts
<> 144:ef7eb2e8f9f7 464 * @{
<> 144:ef7eb2e8f9f7 465 */
<> 144:ef7eb2e8f9f7 466
<> 144:ef7eb2e8f9f7 467 /*!
<> 144:ef7eb2e8f9f7 468 * @brief Enables I2C interrupt requests.
<> 144:ef7eb2e8f9f7 469 *
<> 144:ef7eb2e8f9f7 470 * @param base I2C base pointer
<> 144:ef7eb2e8f9f7 471 * @param mask interrupt source
<> 144:ef7eb2e8f9f7 472 * The parameter can be combination of the following source if defined:
<> 144:ef7eb2e8f9f7 473 * @arg kI2C_GlobalInterruptEnable
<> 144:ef7eb2e8f9f7 474 * @arg kI2C_StopDetectInterruptEnable/kI2C_StartDetectInterruptEnable
<> 144:ef7eb2e8f9f7 475 * @arg kI2C_SdaTimeoutInterruptEnable
<> 144:ef7eb2e8f9f7 476 */
<> 144:ef7eb2e8f9f7 477 void I2C_EnableInterrupts(I2C_Type *base, uint32_t mask);
<> 144:ef7eb2e8f9f7 478
<> 144:ef7eb2e8f9f7 479 /*!
<> 144:ef7eb2e8f9f7 480 * @brief Disables I2C interrupt requests.
<> 144:ef7eb2e8f9f7 481 *
<> 144:ef7eb2e8f9f7 482 * @param base I2C base pointer
<> 144:ef7eb2e8f9f7 483 * @param mask interrupt source
<> 144:ef7eb2e8f9f7 484 * The parameter can be combination of the following source if defined:
<> 144:ef7eb2e8f9f7 485 * @arg kI2C_GlobalInterruptEnable
<> 144:ef7eb2e8f9f7 486 * @arg kI2C_StopDetectInterruptEnable/kI2C_StartDetectInterruptEnable
<> 144:ef7eb2e8f9f7 487 * @arg kI2C_SdaTimeoutInterruptEnable
<> 144:ef7eb2e8f9f7 488 */
<> 144:ef7eb2e8f9f7 489 void I2C_DisableInterrupts(I2C_Type *base, uint32_t mask);
<> 144:ef7eb2e8f9f7 490
<> 144:ef7eb2e8f9f7 491 /*!
<> 144:ef7eb2e8f9f7 492 * @name DMA Control
<> 144:ef7eb2e8f9f7 493 * @{
<> 144:ef7eb2e8f9f7 494 */
<> 144:ef7eb2e8f9f7 495 #if defined(FSL_FEATURE_I2C_HAS_DMA_SUPPORT) && FSL_FEATURE_I2C_HAS_DMA_SUPPORT
<> 144:ef7eb2e8f9f7 496 /*!
<> 144:ef7eb2e8f9f7 497 * @brief Enables/disables the I2C DMA interrupt.
<> 144:ef7eb2e8f9f7 498 *
<> 144:ef7eb2e8f9f7 499 * @param base I2C base pointer
<> 144:ef7eb2e8f9f7 500 * @param enable true to enable, false to disable
<> 144:ef7eb2e8f9f7 501 */
<> 144:ef7eb2e8f9f7 502 static inline void I2C_EnableDMA(I2C_Type *base, bool enable)
<> 144:ef7eb2e8f9f7 503 {
<> 144:ef7eb2e8f9f7 504 if (enable)
<> 144:ef7eb2e8f9f7 505 {
<> 144:ef7eb2e8f9f7 506 base->C1 |= I2C_C1_DMAEN_MASK;
<> 144:ef7eb2e8f9f7 507 }
<> 144:ef7eb2e8f9f7 508 else
<> 144:ef7eb2e8f9f7 509 {
<> 144:ef7eb2e8f9f7 510 base->C1 &= ~I2C_C1_DMAEN_MASK;
<> 144:ef7eb2e8f9f7 511 }
<> 144:ef7eb2e8f9f7 512 }
<> 144:ef7eb2e8f9f7 513
<> 144:ef7eb2e8f9f7 514 #endif /* FSL_FEATURE_I2C_HAS_DMA_SUPPORT */
<> 144:ef7eb2e8f9f7 515
<> 144:ef7eb2e8f9f7 516 /*!
<> 144:ef7eb2e8f9f7 517 * @brief Gets the I2C tx/rx data register address. This API is used to provide a transfer address
<> 144:ef7eb2e8f9f7 518 * for I2C DMA transfer configuration.
<> 144:ef7eb2e8f9f7 519 *
<> 144:ef7eb2e8f9f7 520 * @param base I2C base pointer
<> 144:ef7eb2e8f9f7 521 * @return data register address
<> 144:ef7eb2e8f9f7 522 */
<> 144:ef7eb2e8f9f7 523 static inline uint32_t I2C_GetDataRegAddr(I2C_Type *base)
<> 144:ef7eb2e8f9f7 524 {
<> 144:ef7eb2e8f9f7 525 return (uint32_t)(&(base->D));
<> 144:ef7eb2e8f9f7 526 }
<> 144:ef7eb2e8f9f7 527
<> 144:ef7eb2e8f9f7 528 /* @} */
<> 144:ef7eb2e8f9f7 529 /*!
<> 144:ef7eb2e8f9f7 530 * @name Bus Operations
<> 144:ef7eb2e8f9f7 531 * @{
<> 144:ef7eb2e8f9f7 532 */
<> 144:ef7eb2e8f9f7 533
<> 144:ef7eb2e8f9f7 534 /*!
<> 144:ef7eb2e8f9f7 535 * @brief Sets the I2C master transfer baud rate.
<> 144:ef7eb2e8f9f7 536 *
<> 144:ef7eb2e8f9f7 537 * @param base I2C base pointer
<> 144:ef7eb2e8f9f7 538 * @param baudRate_Bps the baud rate value in bps
<> 144:ef7eb2e8f9f7 539 * @param srcClock_Hz Source clock
<> 144:ef7eb2e8f9f7 540 */
<> 144:ef7eb2e8f9f7 541 void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz);
<> 144:ef7eb2e8f9f7 542
<> 144:ef7eb2e8f9f7 543 /*!
<> 144:ef7eb2e8f9f7 544 * @brief Sends a START on the I2C bus.
<> 144:ef7eb2e8f9f7 545 *
<> 144:ef7eb2e8f9f7 546 * This function is used to initiate a new master mode transfer by sending the START signal.
<> 144:ef7eb2e8f9f7 547 * The slave address is sent following the I2C START signal.
<> 144:ef7eb2e8f9f7 548 *
<> 144:ef7eb2e8f9f7 549 * @param base I2C peripheral base pointer
<> 144:ef7eb2e8f9f7 550 * @param address 7-bit slave device address.
<> 144:ef7eb2e8f9f7 551 * @param direction Master transfer directions(transmit/receive).
<> 144:ef7eb2e8f9f7 552 * @retval kStatus_Success Successfully send the start signal.
<> 144:ef7eb2e8f9f7 553 * @retval kStatus_I2C_Busy Current bus is busy.
<> 144:ef7eb2e8f9f7 554 */
<> 144:ef7eb2e8f9f7 555 status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction);
<> 144:ef7eb2e8f9f7 556
<> 144:ef7eb2e8f9f7 557 /*!
<> 144:ef7eb2e8f9f7 558 * @brief Sends a STOP signal on the I2C bus.
<> 144:ef7eb2e8f9f7 559 *
<> 144:ef7eb2e8f9f7 560 * @retval kStatus_Success Successfully send the stop signal.
<> 144:ef7eb2e8f9f7 561 * @retval kStatus_I2C_Timeout Send stop signal failed, timeout.
<> 144:ef7eb2e8f9f7 562 */
<> 144:ef7eb2e8f9f7 563 status_t I2C_MasterStop(I2C_Type *base);
<> 144:ef7eb2e8f9f7 564
<> 144:ef7eb2e8f9f7 565 /*!
<> 144:ef7eb2e8f9f7 566 * @brief Sends a REPEATED START on the I2C bus.
<> 144:ef7eb2e8f9f7 567 *
<> 144:ef7eb2e8f9f7 568 * @param base I2C peripheral base pointer
<> 144:ef7eb2e8f9f7 569 * @param address 7-bit slave device address.
<> 144:ef7eb2e8f9f7 570 * @param direction Master transfer directions(transmit/receive).
<> 144:ef7eb2e8f9f7 571 * @retval kStatus_Success Successfully send the start signal.
<> 144:ef7eb2e8f9f7 572 * @retval kStatus_I2C_Busy Current bus is busy but not occupied by current I2C master.
<> 144:ef7eb2e8f9f7 573 */
<> 144:ef7eb2e8f9f7 574 status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction);
<> 144:ef7eb2e8f9f7 575
<> 144:ef7eb2e8f9f7 576 /*!
<> 144:ef7eb2e8f9f7 577 * @brief Performs a polling send transaction on the I2C bus without a STOP signal.
<> 144:ef7eb2e8f9f7 578 *
<> 144:ef7eb2e8f9f7 579 * @param base The I2C peripheral base pointer.
<> 144:ef7eb2e8f9f7 580 * @param txBuff The pointer to the data to be transferred.
<> 144:ef7eb2e8f9f7 581 * @param txSize The length in bytes of the data to be transferred.
<> 144:ef7eb2e8f9f7 582 * @retval kStatus_Success Successfully complete the data transmission.
<> 144:ef7eb2e8f9f7 583 * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
<> 144:ef7eb2e8f9f7 584 * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer.
<> 144:ef7eb2e8f9f7 585 */
<> 144:ef7eb2e8f9f7 586 status_t I2C_MasterWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize);
<> 144:ef7eb2e8f9f7 587
<> 144:ef7eb2e8f9f7 588 /*!
<> 144:ef7eb2e8f9f7 589 * @brief Performs a polling receive transaction on the I2C bus with a STOP signal.
<> 144:ef7eb2e8f9f7 590 *
<> 144:ef7eb2e8f9f7 591 * @note The I2C_MasterReadBlocking function stops the bus before reading the final byte.
<> 144:ef7eb2e8f9f7 592 * Without stopping the bus prior for the final read, the bus issues another read, resulting
<> 144:ef7eb2e8f9f7 593 * in garbage data being read into the data register.
<> 144:ef7eb2e8f9f7 594 *
<> 144:ef7eb2e8f9f7 595 * @param base I2C peripheral base pointer.
<> 144:ef7eb2e8f9f7 596 * @param rxBuff The pointer to the data to store the received data.
<> 144:ef7eb2e8f9f7 597 * @param rxSize The length in bytes of the data to be received.
<> 144:ef7eb2e8f9f7 598 * @retval kStatus_Success Successfully complete the data transmission.
<> 144:ef7eb2e8f9f7 599 * @retval kStatus_I2C_Timeout Send stop signal failed, timeout.
<> 144:ef7eb2e8f9f7 600 */
<> 144:ef7eb2e8f9f7 601 status_t I2C_MasterReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize);
<> 144:ef7eb2e8f9f7 602
<> 144:ef7eb2e8f9f7 603 /*!
<> 144:ef7eb2e8f9f7 604 * @brief Performs a polling send transaction on the I2C bus.
<> 144:ef7eb2e8f9f7 605 *
<> 144:ef7eb2e8f9f7 606 * @param base The I2C peripheral base pointer.
<> 144:ef7eb2e8f9f7 607 * @param txBuff The pointer to the data to be transferred.
<> 144:ef7eb2e8f9f7 608 * @param txSize The length in bytes of the data to be transferred.
<> 144:ef7eb2e8f9f7 609 * @retval kStatus_Success Successfully complete the data transmission.
<> 144:ef7eb2e8f9f7 610 * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
<> 144:ef7eb2e8f9f7 611 * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer.
<> 144:ef7eb2e8f9f7 612 */
<> 144:ef7eb2e8f9f7 613 status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize);
<> 144:ef7eb2e8f9f7 614
<> 144:ef7eb2e8f9f7 615 /*!
<> 144:ef7eb2e8f9f7 616 * @brief Performs a polling receive transaction on the I2C bus.
<> 144:ef7eb2e8f9f7 617 *
<> 144:ef7eb2e8f9f7 618 * @param base I2C peripheral base pointer.
<> 144:ef7eb2e8f9f7 619 * @param rxBuff The pointer to the data to store the received data.
<> 144:ef7eb2e8f9f7 620 * @param rxSize The length in bytes of the data to be received.
<> 144:ef7eb2e8f9f7 621 */
<> 144:ef7eb2e8f9f7 622 void I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize);
<> 144:ef7eb2e8f9f7 623
<> 144:ef7eb2e8f9f7 624 /*!
<> 144:ef7eb2e8f9f7 625 * @brief Performs a master polling transfer on the I2C bus.
<> 144:ef7eb2e8f9f7 626 *
<> 144:ef7eb2e8f9f7 627 * @note The API does not return until the transfer succeeds or fails due
<> 144:ef7eb2e8f9f7 628 * to arbitration lost or receiving a NAK.
<> 144:ef7eb2e8f9f7 629 *
<> 144:ef7eb2e8f9f7 630 * @param base I2C peripheral base address.
<> 144:ef7eb2e8f9f7 631 * @param xfer Pointer to the transfer structure.
<> 144:ef7eb2e8f9f7 632 * @retval kStatus_Success Successfully complete the data transmission.
<> 144:ef7eb2e8f9f7 633 * @retval kStatus_I2C_Busy Previous transmission still not finished.
<> 144:ef7eb2e8f9f7 634 * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout.
<> 144:ef7eb2e8f9f7 635 * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
<> 144:ef7eb2e8f9f7 636 * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer.
<> 144:ef7eb2e8f9f7 637 */
<> 144:ef7eb2e8f9f7 638 status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer);
<> 144:ef7eb2e8f9f7 639
<> 144:ef7eb2e8f9f7 640 /* @} */
<> 144:ef7eb2e8f9f7 641
<> 144:ef7eb2e8f9f7 642 /*!
<> 144:ef7eb2e8f9f7 643 * @name Transactional
<> 144:ef7eb2e8f9f7 644 * @{
<> 144:ef7eb2e8f9f7 645 */
<> 144:ef7eb2e8f9f7 646
<> 144:ef7eb2e8f9f7 647 /*!
<> 144:ef7eb2e8f9f7 648 * @brief Initializes the I2C handle which is used in transactional functions.
<> 144:ef7eb2e8f9f7 649 *
<> 144:ef7eb2e8f9f7 650 * @param base I2C base pointer.
<> 144:ef7eb2e8f9f7 651 * @param handle pointer to i2c_master_handle_t structure to store the transfer state.
<> 144:ef7eb2e8f9f7 652 * @param callback pointer to user callback function.
<> 144:ef7eb2e8f9f7 653 * @param userData user paramater passed to the callback function.
<> 144:ef7eb2e8f9f7 654 */
<> 144:ef7eb2e8f9f7 655 void I2C_MasterTransferCreateHandle(I2C_Type *base,
<> 144:ef7eb2e8f9f7 656 i2c_master_handle_t *handle,
<> 144:ef7eb2e8f9f7 657 i2c_master_transfer_callback_t callback,
<> 144:ef7eb2e8f9f7 658 void *userData);
<> 144:ef7eb2e8f9f7 659
<> 144:ef7eb2e8f9f7 660 /*!
<> 144:ef7eb2e8f9f7 661 * @brief Performs a master interrupt non-blocking transfer on the I2C bus.
<> 144:ef7eb2e8f9f7 662 *
<> 144:ef7eb2e8f9f7 663 * @note Calling the API will return immediately after transfer initiates, user needs
<> 144:ef7eb2e8f9f7 664 * to call I2C_MasterGetTransferCount to poll the transfer status to check whether
<> 144:ef7eb2e8f9f7 665 * the transfer is finished, if the return status is not kStatus_I2C_Busy, the transfer
<> 144:ef7eb2e8f9f7 666 * is finished.
<> 144:ef7eb2e8f9f7 667 *
<> 144:ef7eb2e8f9f7 668 * @param base I2C base pointer.
<> 144:ef7eb2e8f9f7 669 * @param handle pointer to i2c_master_handle_t structure which stores the transfer state.
<> 144:ef7eb2e8f9f7 670 * @param xfer pointer to i2c_master_transfer_t structure.
<> 144:ef7eb2e8f9f7 671 * @retval kStatus_Success Sucessully start the data transmission.
<> 144:ef7eb2e8f9f7 672 * @retval kStatus_I2C_Busy Previous transmission still not finished.
<> 144:ef7eb2e8f9f7 673 * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout.
<> 144:ef7eb2e8f9f7 674 */
<> 144:ef7eb2e8f9f7 675 status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer);
<> 144:ef7eb2e8f9f7 676
<> 144:ef7eb2e8f9f7 677 /*!
<> 144:ef7eb2e8f9f7 678 * @brief Gets the master transfer status during a interrupt non-blocking transfer.
<> 144:ef7eb2e8f9f7 679 *
<> 144:ef7eb2e8f9f7 680 * @param base I2C base pointer.
<> 144:ef7eb2e8f9f7 681 * @param handle pointer to i2c_master_handle_t structure which stores the transfer state.
<> 144:ef7eb2e8f9f7 682 * @param count Number of bytes transferred so far by the non-blocking transaction.
<> 144:ef7eb2e8f9f7 683 * @retval kStatus_InvalidArgument count is Invalid.
<> 144:ef7eb2e8f9f7 684 * @retval kStatus_Success Successfully return the count.
<> 144:ef7eb2e8f9f7 685 */
<> 144:ef7eb2e8f9f7 686 status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count);
<> 144:ef7eb2e8f9f7 687
<> 144:ef7eb2e8f9f7 688 /*!
<> 144:ef7eb2e8f9f7 689 * @brief Aborts an interrupt non-blocking transfer early.
<> 144:ef7eb2e8f9f7 690 *
<> 144:ef7eb2e8f9f7 691 * @note This API can be called at any time when an interrupt non-blocking transfer initiates
<> 144:ef7eb2e8f9f7 692 * to abort the transfer early.
<> 144:ef7eb2e8f9f7 693 *
<> 144:ef7eb2e8f9f7 694 * @param base I2C base pointer.
<> 144:ef7eb2e8f9f7 695 * @param handle pointer to i2c_master_handle_t structure which stores the transfer state
<> 144:ef7eb2e8f9f7 696 */
<> 144:ef7eb2e8f9f7 697 void I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle);
<> 144:ef7eb2e8f9f7 698
<> 144:ef7eb2e8f9f7 699 /*!
<> 144:ef7eb2e8f9f7 700 * @brief Master interrupt handler.
<> 144:ef7eb2e8f9f7 701 *
<> 144:ef7eb2e8f9f7 702 * @param base I2C base pointer.
<> 144:ef7eb2e8f9f7 703 * @param i2cHandle pointer to i2c_master_handle_t structure.
<> 144:ef7eb2e8f9f7 704 */
<> 144:ef7eb2e8f9f7 705 void I2C_MasterTransferHandleIRQ(I2C_Type *base, void *i2cHandle);
<> 144:ef7eb2e8f9f7 706
<> 144:ef7eb2e8f9f7 707 /*!
<> 144:ef7eb2e8f9f7 708 * @brief Initializes the I2C handle which is used in transactional functions.
<> 144:ef7eb2e8f9f7 709 *
<> 144:ef7eb2e8f9f7 710 * @param base I2C base pointer.
<> 144:ef7eb2e8f9f7 711 * @param handle pointer to i2c_slave_handle_t structure to store the transfer state.
<> 144:ef7eb2e8f9f7 712 * @param callback pointer to user callback function.
<> 144:ef7eb2e8f9f7 713 * @param userData user parameter passed to the callback function.
<> 144:ef7eb2e8f9f7 714 */
<> 144:ef7eb2e8f9f7 715 void I2C_SlaveTransferCreateHandle(I2C_Type *base,
<> 144:ef7eb2e8f9f7 716 i2c_slave_handle_t *handle,
<> 144:ef7eb2e8f9f7 717 i2c_slave_transfer_callback_t callback,
<> 144:ef7eb2e8f9f7 718 void *userData);
<> 144:ef7eb2e8f9f7 719
<> 144:ef7eb2e8f9f7 720 /*!
<> 144:ef7eb2e8f9f7 721 * @brief Starts accepting slave transfers.
<> 144:ef7eb2e8f9f7 722 *
<> 144:ef7eb2e8f9f7 723 * Call this API after calling the I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing
<> 144:ef7eb2e8f9f7 724 * transactions driven by an I2C master. The slave monitors the I2C bus and passes events to the
<> 144:ef7eb2e8f9f7 725 * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked
<> 144:ef7eb2e8f9f7 726 * from the interrupt context.
<> 144:ef7eb2e8f9f7 727 *
<> 144:ef7eb2e8f9f7 728 * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to
<> 144:ef7eb2e8f9f7 729 * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive.
<> 144:ef7eb2e8f9f7 730 * The #kI2C_SlaveTransmitEvent and #kLPI2C_SlaveReceiveEvent events are always enabled and do not need
<> 144:ef7eb2e8f9f7 731 * to be included in the mask. Alternatively, pass 0 to get a default set of only the transmit and
<> 144:ef7eb2e8f9f7 732 * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as
<> 144:ef7eb2e8f9f7 733 * a convenient way to enable all events.
<> 144:ef7eb2e8f9f7 734 *
<> 144:ef7eb2e8f9f7 735 * @param base The I2C peripheral base address.
<> 144:ef7eb2e8f9f7 736 * @param handle Pointer to #i2c_slave_handle_t structure which stores the transfer state.
<> 144:ef7eb2e8f9f7 737 * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify
<> 144:ef7eb2e8f9f7 738 * which events to send to the callback. Other accepted values are 0 to get a default set of
<> 144:ef7eb2e8f9f7 739 * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events.
<> 144:ef7eb2e8f9f7 740 *
<> 144:ef7eb2e8f9f7 741 * @retval #kStatus_Success Slave transfers were successfully started.
<> 144:ef7eb2e8f9f7 742 * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle.
<> 144:ef7eb2e8f9f7 743 */
<> 144:ef7eb2e8f9f7 744 status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask);
<> 144:ef7eb2e8f9f7 745
<> 144:ef7eb2e8f9f7 746 /*!
<> 144:ef7eb2e8f9f7 747 * @brief Aborts the slave transfer.
<> 144:ef7eb2e8f9f7 748 *
<> 144:ef7eb2e8f9f7 749 * @note This API can be called at any time to stop slave for handling the bus events.
<> 144:ef7eb2e8f9f7 750 *
<> 144:ef7eb2e8f9f7 751 * @param base I2C base pointer.
<> 144:ef7eb2e8f9f7 752 * @param handle pointer to i2c_slave_handle_t structure which stores the transfer state.
<> 144:ef7eb2e8f9f7 753 */
<> 144:ef7eb2e8f9f7 754 void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle);
<> 144:ef7eb2e8f9f7 755
<> 144:ef7eb2e8f9f7 756 /*!
<> 144:ef7eb2e8f9f7 757 * @brief Gets the slave transfer remaining bytes during a interrupt non-blocking transfer.
<> 144:ef7eb2e8f9f7 758 *
<> 144:ef7eb2e8f9f7 759 * @param base I2C base pointer.
<> 144:ef7eb2e8f9f7 760 * @param handle pointer to i2c_slave_handle_t structure.
<> 144:ef7eb2e8f9f7 761 * @param count Number of bytes transferred so far by the non-blocking transaction.
<> 144:ef7eb2e8f9f7 762 * @retval kStatus_InvalidArgument count is Invalid.
<> 144:ef7eb2e8f9f7 763 * @retval kStatus_Success Successfully return the count.
<> 144:ef7eb2e8f9f7 764 */
<> 144:ef7eb2e8f9f7 765 status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count);
<> 144:ef7eb2e8f9f7 766
<> 144:ef7eb2e8f9f7 767 /*!
<> 144:ef7eb2e8f9f7 768 * @brief Slave interrupt handler.
<> 144:ef7eb2e8f9f7 769 *
<> 144:ef7eb2e8f9f7 770 * @param base I2C base pointer.
<> 144:ef7eb2e8f9f7 771 * @param i2cHandle pointer to i2c_slave_handle_t structure which stores the transfer state
<> 144:ef7eb2e8f9f7 772 */
<> 144:ef7eb2e8f9f7 773 void I2C_SlaveTransferHandleIRQ(I2C_Type *base, void *i2cHandle);
<> 144:ef7eb2e8f9f7 774
<> 144:ef7eb2e8f9f7 775 /* @} */
<> 144:ef7eb2e8f9f7 776 #if defined(__cplusplus)
<> 144:ef7eb2e8f9f7 777 }
<> 144:ef7eb2e8f9f7 778 #endif /*_cplusplus. */
<> 144:ef7eb2e8f9f7 779 /*@}*/
<> 144:ef7eb2e8f9f7 780
<> 144:ef7eb2e8f9f7 781 #endif /* _FSL_I2C_H_*/