added prescaler for 16 bit pwm in LPC1347 target
Fork of mbed-dev by
targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/drivers/fsl_gpio.h@147:ba84b7dc41a7, 2016-09-10 (annotated)
- Committer:
- JojoS
- Date:
- Sat Sep 10 15:32:04 2016 +0000
- Revision:
- 147:ba84b7dc41a7
- Parent:
- 144:ef7eb2e8f9f7
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /* |
<> | 144:ef7eb2e8f9f7 | 2 | * Copyright (c) 2015, Freescale Semiconductor, Inc. |
<> | 144:ef7eb2e8f9f7 | 3 | * All rights reserved. |
<> | 144:ef7eb2e8f9f7 | 4 | * |
<> | 144:ef7eb2e8f9f7 | 5 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 144:ef7eb2e8f9f7 | 6 | * are permitted provided that the following conditions are met: |
<> | 144:ef7eb2e8f9f7 | 7 | * |
<> | 144:ef7eb2e8f9f7 | 8 | * o Redistributions of source code must retain the above copyright notice, this list |
<> | 144:ef7eb2e8f9f7 | 9 | * of conditions and the following disclaimer. |
<> | 144:ef7eb2e8f9f7 | 10 | * |
<> | 144:ef7eb2e8f9f7 | 11 | * o Redistributions in binary form must reproduce the above copyright notice, this |
<> | 144:ef7eb2e8f9f7 | 12 | * list of conditions and the following disclaimer in the documentation and/or |
<> | 144:ef7eb2e8f9f7 | 13 | * other materials provided with the distribution. |
<> | 144:ef7eb2e8f9f7 | 14 | * |
<> | 144:ef7eb2e8f9f7 | 15 | * o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
<> | 144:ef7eb2e8f9f7 | 16 | * contributors may be used to endorse or promote products derived from this |
<> | 144:ef7eb2e8f9f7 | 17 | * software without specific prior written permission. |
<> | 144:ef7eb2e8f9f7 | 18 | * |
<> | 144:ef7eb2e8f9f7 | 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
<> | 144:ef7eb2e8f9f7 | 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
<> | 144:ef7eb2e8f9f7 | 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 144:ef7eb2e8f9f7 | 22 | * DISCLAIMED. IN NO EVENT SDRVL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
<> | 144:ef7eb2e8f9f7 | 23 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
<> | 144:ef7eb2e8f9f7 | 24 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
<> | 144:ef7eb2e8f9f7 | 25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
<> | 144:ef7eb2e8f9f7 | 26 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
<> | 144:ef7eb2e8f9f7 | 27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
<> | 144:ef7eb2e8f9f7 | 28 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 144:ef7eb2e8f9f7 | 29 | */ |
<> | 144:ef7eb2e8f9f7 | 30 | |
<> | 144:ef7eb2e8f9f7 | 31 | #ifndef _FSL_GPIO_H_ |
<> | 144:ef7eb2e8f9f7 | 32 | #define _FSL_GPIO_H_ |
<> | 144:ef7eb2e8f9f7 | 33 | |
<> | 144:ef7eb2e8f9f7 | 34 | #include "fsl_common.h" |
<> | 144:ef7eb2e8f9f7 | 35 | |
<> | 144:ef7eb2e8f9f7 | 36 | /*! |
<> | 144:ef7eb2e8f9f7 | 37 | * @addtogroup gpio |
<> | 144:ef7eb2e8f9f7 | 38 | * @{ |
<> | 144:ef7eb2e8f9f7 | 39 | */ |
<> | 144:ef7eb2e8f9f7 | 40 | |
<> | 144:ef7eb2e8f9f7 | 41 | /*! @file */ |
<> | 144:ef7eb2e8f9f7 | 42 | |
<> | 144:ef7eb2e8f9f7 | 43 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 44 | * Definitions |
<> | 144:ef7eb2e8f9f7 | 45 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 46 | |
<> | 144:ef7eb2e8f9f7 | 47 | /*! @name Driver version */ |
<> | 144:ef7eb2e8f9f7 | 48 | /*@{*/ |
<> | 144:ef7eb2e8f9f7 | 49 | /*! @brief GPIO driver version 2.1.0. */ |
<> | 144:ef7eb2e8f9f7 | 50 | #define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) |
<> | 144:ef7eb2e8f9f7 | 51 | /*@}*/ |
<> | 144:ef7eb2e8f9f7 | 52 | |
<> | 144:ef7eb2e8f9f7 | 53 | /*! @brief GPIO direction definition*/ |
<> | 144:ef7eb2e8f9f7 | 54 | typedef enum _gpio_pin_direction |
<> | 144:ef7eb2e8f9f7 | 55 | { |
<> | 144:ef7eb2e8f9f7 | 56 | kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/ |
<> | 144:ef7eb2e8f9f7 | 57 | kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/ |
<> | 144:ef7eb2e8f9f7 | 58 | } gpio_pin_direction_t; |
<> | 144:ef7eb2e8f9f7 | 59 | |
<> | 144:ef7eb2e8f9f7 | 60 | /*! |
<> | 144:ef7eb2e8f9f7 | 61 | * @brief The GPIO pin configuration structure. |
<> | 144:ef7eb2e8f9f7 | 62 | * |
<> | 144:ef7eb2e8f9f7 | 63 | * Every pin can only be configured as either output pin or input pin at a time. |
<> | 144:ef7eb2e8f9f7 | 64 | * If configured as a input pin, then leave the outputConfig unused |
<> | 144:ef7eb2e8f9f7 | 65 | * Note : In some cases, the corresponding port property should be configured in advance |
<> | 144:ef7eb2e8f9f7 | 66 | * with the PORT_SetPinConfig() |
<> | 144:ef7eb2e8f9f7 | 67 | */ |
<> | 144:ef7eb2e8f9f7 | 68 | typedef struct _gpio_pin_config |
<> | 144:ef7eb2e8f9f7 | 69 | { |
<> | 144:ef7eb2e8f9f7 | 70 | gpio_pin_direction_t pinDirection; /*!< gpio direction, input or output */ |
<> | 144:ef7eb2e8f9f7 | 71 | /* Output configurations, please ignore if configured as a input one */ |
<> | 144:ef7eb2e8f9f7 | 72 | uint8_t outputLogic; /*!< Set default output logic, no use in input */ |
<> | 144:ef7eb2e8f9f7 | 73 | } gpio_pin_config_t; |
<> | 144:ef7eb2e8f9f7 | 74 | |
<> | 144:ef7eb2e8f9f7 | 75 | /*! @} */ |
<> | 144:ef7eb2e8f9f7 | 76 | |
<> | 144:ef7eb2e8f9f7 | 77 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 78 | * API |
<> | 144:ef7eb2e8f9f7 | 79 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 80 | |
<> | 144:ef7eb2e8f9f7 | 81 | #if defined(__cplusplus) |
<> | 144:ef7eb2e8f9f7 | 82 | extern "C" { |
<> | 144:ef7eb2e8f9f7 | 83 | #endif |
<> | 144:ef7eb2e8f9f7 | 84 | |
<> | 144:ef7eb2e8f9f7 | 85 | /*! |
<> | 144:ef7eb2e8f9f7 | 86 | * @addtogroup gpio_driver |
<> | 144:ef7eb2e8f9f7 | 87 | * @{ |
<> | 144:ef7eb2e8f9f7 | 88 | */ |
<> | 144:ef7eb2e8f9f7 | 89 | |
<> | 144:ef7eb2e8f9f7 | 90 | /*! @name GPIO Configuration */ |
<> | 144:ef7eb2e8f9f7 | 91 | /*@{*/ |
<> | 144:ef7eb2e8f9f7 | 92 | |
<> | 144:ef7eb2e8f9f7 | 93 | /*! |
<> | 144:ef7eb2e8f9f7 | 94 | * @brief Initializes a GPIO pin used by the board. |
<> | 144:ef7eb2e8f9f7 | 95 | * |
<> | 144:ef7eb2e8f9f7 | 96 | * To initialize the GPIO, define a pin configuration, either input or output, in the user file. |
<> | 144:ef7eb2e8f9f7 | 97 | * Then, call the GPIO_PinInit() function. |
<> | 144:ef7eb2e8f9f7 | 98 | * |
<> | 144:ef7eb2e8f9f7 | 99 | * This is an example to define an input pin or output pin configuration: |
<> | 144:ef7eb2e8f9f7 | 100 | * @code |
<> | 144:ef7eb2e8f9f7 | 101 | * // Define a digital input pin configuration, |
<> | 144:ef7eb2e8f9f7 | 102 | * gpio_pin_config_t config = |
<> | 144:ef7eb2e8f9f7 | 103 | * { |
<> | 144:ef7eb2e8f9f7 | 104 | * kGPIO_DigitalInput, |
<> | 144:ef7eb2e8f9f7 | 105 | * 0, |
<> | 144:ef7eb2e8f9f7 | 106 | * } |
<> | 144:ef7eb2e8f9f7 | 107 | * //Define a digital output pin configuration, |
<> | 144:ef7eb2e8f9f7 | 108 | * gpio_pin_config_t config = |
<> | 144:ef7eb2e8f9f7 | 109 | * { |
<> | 144:ef7eb2e8f9f7 | 110 | * kGPIO_DigitalOutput, |
<> | 144:ef7eb2e8f9f7 | 111 | * 0, |
<> | 144:ef7eb2e8f9f7 | 112 | * } |
<> | 144:ef7eb2e8f9f7 | 113 | * @endcode |
<> | 144:ef7eb2e8f9f7 | 114 | * |
<> | 144:ef7eb2e8f9f7 | 115 | * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) |
<> | 144:ef7eb2e8f9f7 | 116 | * @param pin GPIO port pin number |
<> | 144:ef7eb2e8f9f7 | 117 | * @param config GPIO pin configuration pointer |
<> | 144:ef7eb2e8f9f7 | 118 | */ |
<> | 144:ef7eb2e8f9f7 | 119 | void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config); |
<> | 144:ef7eb2e8f9f7 | 120 | |
<> | 144:ef7eb2e8f9f7 | 121 | /*@}*/ |
<> | 144:ef7eb2e8f9f7 | 122 | |
<> | 144:ef7eb2e8f9f7 | 123 | /*! @name GPIO Output Operations */ |
<> | 144:ef7eb2e8f9f7 | 124 | /*@{*/ |
<> | 144:ef7eb2e8f9f7 | 125 | |
<> | 144:ef7eb2e8f9f7 | 126 | /*! |
<> | 144:ef7eb2e8f9f7 | 127 | * @brief Sets the output level of the multiple GPIO pins to the logic 1 or 0. |
<> | 144:ef7eb2e8f9f7 | 128 | * |
<> | 144:ef7eb2e8f9f7 | 129 | * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) |
<> | 144:ef7eb2e8f9f7 | 130 | * @param pin GPIO pin's number |
<> | 144:ef7eb2e8f9f7 | 131 | * @param output GPIO pin output logic level. |
<> | 144:ef7eb2e8f9f7 | 132 | * - 0: corresponding pin output low logic level. |
<> | 144:ef7eb2e8f9f7 | 133 | * - 1: corresponding pin output high logic level. |
<> | 144:ef7eb2e8f9f7 | 134 | */ |
<> | 144:ef7eb2e8f9f7 | 135 | static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t pin, uint8_t output) |
<> | 144:ef7eb2e8f9f7 | 136 | { |
<> | 144:ef7eb2e8f9f7 | 137 | if (output == 0U) |
<> | 144:ef7eb2e8f9f7 | 138 | { |
<> | 144:ef7eb2e8f9f7 | 139 | base->PCOR = 1 << pin; |
<> | 144:ef7eb2e8f9f7 | 140 | } |
<> | 144:ef7eb2e8f9f7 | 141 | else |
<> | 144:ef7eb2e8f9f7 | 142 | { |
<> | 144:ef7eb2e8f9f7 | 143 | base->PSOR = 1 << pin; |
<> | 144:ef7eb2e8f9f7 | 144 | } |
<> | 144:ef7eb2e8f9f7 | 145 | } |
<> | 144:ef7eb2e8f9f7 | 146 | |
<> | 144:ef7eb2e8f9f7 | 147 | /*! |
<> | 144:ef7eb2e8f9f7 | 148 | * @brief Sets the output level of the multiple GPIO pins to the logic 1. |
<> | 144:ef7eb2e8f9f7 | 149 | * |
<> | 144:ef7eb2e8f9f7 | 150 | * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) |
<> | 144:ef7eb2e8f9f7 | 151 | * @param mask GPIO pins' numbers macro |
<> | 144:ef7eb2e8f9f7 | 152 | */ |
<> | 144:ef7eb2e8f9f7 | 153 | static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t mask) |
<> | 144:ef7eb2e8f9f7 | 154 | { |
<> | 144:ef7eb2e8f9f7 | 155 | base->PSOR = mask; |
<> | 144:ef7eb2e8f9f7 | 156 | } |
<> | 144:ef7eb2e8f9f7 | 157 | |
<> | 144:ef7eb2e8f9f7 | 158 | /*! |
<> | 144:ef7eb2e8f9f7 | 159 | * @brief Sets the output level of the multiple GPIO pins to the logic 0. |
<> | 144:ef7eb2e8f9f7 | 160 | * |
<> | 144:ef7eb2e8f9f7 | 161 | * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) |
<> | 144:ef7eb2e8f9f7 | 162 | * @param mask GPIO pins' numbers macro |
<> | 144:ef7eb2e8f9f7 | 163 | */ |
<> | 144:ef7eb2e8f9f7 | 164 | static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t mask) |
<> | 144:ef7eb2e8f9f7 | 165 | { |
<> | 144:ef7eb2e8f9f7 | 166 | base->PCOR = mask; |
<> | 144:ef7eb2e8f9f7 | 167 | } |
<> | 144:ef7eb2e8f9f7 | 168 | |
<> | 144:ef7eb2e8f9f7 | 169 | /*! |
<> | 144:ef7eb2e8f9f7 | 170 | * @brief Reverses current output logic of the multiple GPIO pins. |
<> | 144:ef7eb2e8f9f7 | 171 | * |
<> | 144:ef7eb2e8f9f7 | 172 | * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) |
<> | 144:ef7eb2e8f9f7 | 173 | * @param mask GPIO pins' numbers macro |
<> | 144:ef7eb2e8f9f7 | 174 | */ |
<> | 144:ef7eb2e8f9f7 | 175 | static inline void GPIO_TogglePinsOutput(GPIO_Type *base, uint32_t mask) |
<> | 144:ef7eb2e8f9f7 | 176 | { |
<> | 144:ef7eb2e8f9f7 | 177 | base->PTOR = mask; |
<> | 144:ef7eb2e8f9f7 | 178 | } |
<> | 144:ef7eb2e8f9f7 | 179 | /*@}*/ |
<> | 144:ef7eb2e8f9f7 | 180 | |
<> | 144:ef7eb2e8f9f7 | 181 | /*! @name GPIO Input Operations */ |
<> | 144:ef7eb2e8f9f7 | 182 | /*@{*/ |
<> | 144:ef7eb2e8f9f7 | 183 | |
<> | 144:ef7eb2e8f9f7 | 184 | /*! |
<> | 144:ef7eb2e8f9f7 | 185 | * @brief Reads the current input value of the whole GPIO port. |
<> | 144:ef7eb2e8f9f7 | 186 | * |
<> | 144:ef7eb2e8f9f7 | 187 | * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) |
<> | 144:ef7eb2e8f9f7 | 188 | * @param pin GPIO pin's number |
<> | 144:ef7eb2e8f9f7 | 189 | * @retval GPIO port input value |
<> | 144:ef7eb2e8f9f7 | 190 | * - 0: corresponding pin input low logic level. |
<> | 144:ef7eb2e8f9f7 | 191 | * - 1: corresponding pin input high logic level. |
<> | 144:ef7eb2e8f9f7 | 192 | */ |
<> | 144:ef7eb2e8f9f7 | 193 | static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t pin) |
<> | 144:ef7eb2e8f9f7 | 194 | { |
<> | 144:ef7eb2e8f9f7 | 195 | return (((base->PDIR) >> pin) & 0x01U); |
<> | 144:ef7eb2e8f9f7 | 196 | } |
<> | 144:ef7eb2e8f9f7 | 197 | /*@}*/ |
<> | 144:ef7eb2e8f9f7 | 198 | |
<> | 144:ef7eb2e8f9f7 | 199 | /*! @name GPIO Interrupt */ |
<> | 144:ef7eb2e8f9f7 | 200 | /*@{*/ |
<> | 144:ef7eb2e8f9f7 | 201 | |
<> | 144:ef7eb2e8f9f7 | 202 | /*! |
<> | 144:ef7eb2e8f9f7 | 203 | * @brief Reads whole GPIO port interrupt status flag. |
<> | 144:ef7eb2e8f9f7 | 204 | * |
<> | 144:ef7eb2e8f9f7 | 205 | * If a pin is configured to generate the DMA request, the corresponding flag |
<> | 144:ef7eb2e8f9f7 | 206 | * is cleared automatically at the completion of the requested DMA transfer. |
<> | 144:ef7eb2e8f9f7 | 207 | * Otherwise, the flag remains set until a logic one is written to that flag. |
<> | 144:ef7eb2e8f9f7 | 208 | * If configured for a level sensitive interrupt that remains asserted, the flag |
<> | 144:ef7eb2e8f9f7 | 209 | * is set again immediately. |
<> | 144:ef7eb2e8f9f7 | 210 | * |
<> | 144:ef7eb2e8f9f7 | 211 | * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) |
<> | 144:ef7eb2e8f9f7 | 212 | * @retval Current GPIO port interrupt status flag, for example, 0x00010001 means the |
<> | 144:ef7eb2e8f9f7 | 213 | * pin 0 and 17 have the interrupt. |
<> | 144:ef7eb2e8f9f7 | 214 | */ |
<> | 144:ef7eb2e8f9f7 | 215 | uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base); |
<> | 144:ef7eb2e8f9f7 | 216 | |
<> | 144:ef7eb2e8f9f7 | 217 | /*! |
<> | 144:ef7eb2e8f9f7 | 218 | * @brief Clears multiple GPIO pins' interrupt status flag. |
<> | 144:ef7eb2e8f9f7 | 219 | * |
<> | 144:ef7eb2e8f9f7 | 220 | * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) |
<> | 144:ef7eb2e8f9f7 | 221 | * @param mask GPIO pins' numbers macro |
<> | 144:ef7eb2e8f9f7 | 222 | */ |
<> | 144:ef7eb2e8f9f7 | 223 | void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask); |
<> | 144:ef7eb2e8f9f7 | 224 | |
<> | 144:ef7eb2e8f9f7 | 225 | /*@}*/ |
<> | 144:ef7eb2e8f9f7 | 226 | /*! @} */ |
<> | 144:ef7eb2e8f9f7 | 227 | |
<> | 144:ef7eb2e8f9f7 | 228 | /*! |
<> | 144:ef7eb2e8f9f7 | 229 | * @addtogroup fgpio_driver |
<> | 144:ef7eb2e8f9f7 | 230 | * @{ |
<> | 144:ef7eb2e8f9f7 | 231 | */ |
<> | 144:ef7eb2e8f9f7 | 232 | |
<> | 144:ef7eb2e8f9f7 | 233 | /* |
<> | 144:ef7eb2e8f9f7 | 234 | * Introduce the FGPIO feature. |
<> | 144:ef7eb2e8f9f7 | 235 | * |
<> | 144:ef7eb2e8f9f7 | 236 | * The FGPIO features are only support on some of Kinetis chips. The FGPIO registers are aliased to the IOPORT |
<> | 144:ef7eb2e8f9f7 | 237 | * interface. Accesses via the IOPORT interface occur in parallel with any instruction fetches and will therefore |
<> | 144:ef7eb2e8f9f7 | 238 | * complete in a single cycle. This aliased Fast GPIO memory map is called FGPIO. |
<> | 144:ef7eb2e8f9f7 | 239 | */ |
<> | 144:ef7eb2e8f9f7 | 240 | |
<> | 144:ef7eb2e8f9f7 | 241 | #if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT |
<> | 144:ef7eb2e8f9f7 | 242 | |
<> | 144:ef7eb2e8f9f7 | 243 | /*! @name FGPIO Configuration */ |
<> | 144:ef7eb2e8f9f7 | 244 | /*@{*/ |
<> | 144:ef7eb2e8f9f7 | 245 | |
<> | 144:ef7eb2e8f9f7 | 246 | /*! |
<> | 144:ef7eb2e8f9f7 | 247 | * @brief Initializes a FGPIO pin used by the board. |
<> | 144:ef7eb2e8f9f7 | 248 | * |
<> | 144:ef7eb2e8f9f7 | 249 | * To initialize the FGPIO driver, define a pin configuration, either input or output, in the user file. |
<> | 144:ef7eb2e8f9f7 | 250 | * Then, call the FGPIO_PinInit() function. |
<> | 144:ef7eb2e8f9f7 | 251 | * |
<> | 144:ef7eb2e8f9f7 | 252 | * This is an example to define an input pin or output pin configuration: |
<> | 144:ef7eb2e8f9f7 | 253 | * @code |
<> | 144:ef7eb2e8f9f7 | 254 | * // Define a digital input pin configuration, |
<> | 144:ef7eb2e8f9f7 | 255 | * gpio_pin_config_t config = |
<> | 144:ef7eb2e8f9f7 | 256 | * { |
<> | 144:ef7eb2e8f9f7 | 257 | * kGPIO_DigitalInput, |
<> | 144:ef7eb2e8f9f7 | 258 | * 0, |
<> | 144:ef7eb2e8f9f7 | 259 | * } |
<> | 144:ef7eb2e8f9f7 | 260 | * //Define a digital output pin configuration, |
<> | 144:ef7eb2e8f9f7 | 261 | * gpio_pin_config_t config = |
<> | 144:ef7eb2e8f9f7 | 262 | * { |
<> | 144:ef7eb2e8f9f7 | 263 | * kGPIO_DigitalOutput, |
<> | 144:ef7eb2e8f9f7 | 264 | * 0, |
<> | 144:ef7eb2e8f9f7 | 265 | * } |
<> | 144:ef7eb2e8f9f7 | 266 | * @endcode |
<> | 144:ef7eb2e8f9f7 | 267 | * |
<> | 144:ef7eb2e8f9f7 | 268 | * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) |
<> | 144:ef7eb2e8f9f7 | 269 | * @param pin FGPIO port pin number |
<> | 144:ef7eb2e8f9f7 | 270 | * @param config FGPIO pin configuration pointer |
<> | 144:ef7eb2e8f9f7 | 271 | */ |
<> | 144:ef7eb2e8f9f7 | 272 | void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config); |
<> | 144:ef7eb2e8f9f7 | 273 | |
<> | 144:ef7eb2e8f9f7 | 274 | /*@}*/ |
<> | 144:ef7eb2e8f9f7 | 275 | |
<> | 144:ef7eb2e8f9f7 | 276 | /*! @name FGPIO Output Operations */ |
<> | 144:ef7eb2e8f9f7 | 277 | /*@{*/ |
<> | 144:ef7eb2e8f9f7 | 278 | |
<> | 144:ef7eb2e8f9f7 | 279 | /*! |
<> | 144:ef7eb2e8f9f7 | 280 | * @brief Sets the output level of the multiple FGPIO pins to the logic 1 or 0. |
<> | 144:ef7eb2e8f9f7 | 281 | * |
<> | 144:ef7eb2e8f9f7 | 282 | * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) |
<> | 144:ef7eb2e8f9f7 | 283 | * @param pin FGPIO pin's number |
<> | 144:ef7eb2e8f9f7 | 284 | * @param output FGPIOpin output logic level. |
<> | 144:ef7eb2e8f9f7 | 285 | * - 0: corresponding pin output low logic level. |
<> | 144:ef7eb2e8f9f7 | 286 | * - 1: corresponding pin output high logic level. |
<> | 144:ef7eb2e8f9f7 | 287 | */ |
<> | 144:ef7eb2e8f9f7 | 288 | static inline void FGPIO_WritePinOutput(FGPIO_Type *base, uint32_t pin, uint8_t output) |
<> | 144:ef7eb2e8f9f7 | 289 | { |
<> | 144:ef7eb2e8f9f7 | 290 | if (output == 0U) |
<> | 144:ef7eb2e8f9f7 | 291 | { |
<> | 144:ef7eb2e8f9f7 | 292 | base->PCOR = 1 << pin; |
<> | 144:ef7eb2e8f9f7 | 293 | } |
<> | 144:ef7eb2e8f9f7 | 294 | else |
<> | 144:ef7eb2e8f9f7 | 295 | { |
<> | 144:ef7eb2e8f9f7 | 296 | base->PSOR = 1 << pin; |
<> | 144:ef7eb2e8f9f7 | 297 | } |
<> | 144:ef7eb2e8f9f7 | 298 | } |
<> | 144:ef7eb2e8f9f7 | 299 | |
<> | 144:ef7eb2e8f9f7 | 300 | /*! |
<> | 144:ef7eb2e8f9f7 | 301 | * @brief Sets the output level of the multiple FGPIO pins to the logic 1. |
<> | 144:ef7eb2e8f9f7 | 302 | * |
<> | 144:ef7eb2e8f9f7 | 303 | * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) |
<> | 144:ef7eb2e8f9f7 | 304 | * @param mask FGPIO pins' numbers macro |
<> | 144:ef7eb2e8f9f7 | 305 | */ |
<> | 144:ef7eb2e8f9f7 | 306 | static inline void FGPIO_SetPinsOutput(FGPIO_Type *base, uint32_t mask) |
<> | 144:ef7eb2e8f9f7 | 307 | { |
<> | 144:ef7eb2e8f9f7 | 308 | base->PSOR = mask; |
<> | 144:ef7eb2e8f9f7 | 309 | } |
<> | 144:ef7eb2e8f9f7 | 310 | |
<> | 144:ef7eb2e8f9f7 | 311 | /*! |
<> | 144:ef7eb2e8f9f7 | 312 | * @brief Sets the output level of the multiple FGPIO pins to the logic 0. |
<> | 144:ef7eb2e8f9f7 | 313 | * |
<> | 144:ef7eb2e8f9f7 | 314 | * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) |
<> | 144:ef7eb2e8f9f7 | 315 | * @param mask FGPIO pins' numbers macro |
<> | 144:ef7eb2e8f9f7 | 316 | */ |
<> | 144:ef7eb2e8f9f7 | 317 | static inline void FGPIO_ClearPinsOutput(FGPIO_Type *base, uint32_t mask) |
<> | 144:ef7eb2e8f9f7 | 318 | { |
<> | 144:ef7eb2e8f9f7 | 319 | base->PCOR = mask; |
<> | 144:ef7eb2e8f9f7 | 320 | } |
<> | 144:ef7eb2e8f9f7 | 321 | |
<> | 144:ef7eb2e8f9f7 | 322 | /*! |
<> | 144:ef7eb2e8f9f7 | 323 | * @brief Reverses current output logic of the multiple FGPIO pins. |
<> | 144:ef7eb2e8f9f7 | 324 | * |
<> | 144:ef7eb2e8f9f7 | 325 | * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) |
<> | 144:ef7eb2e8f9f7 | 326 | * @param mask FGPIO pins' numbers macro |
<> | 144:ef7eb2e8f9f7 | 327 | */ |
<> | 144:ef7eb2e8f9f7 | 328 | static inline void FGPIO_TogglePinsOutput(FGPIO_Type *base, uint32_t mask) |
<> | 144:ef7eb2e8f9f7 | 329 | { |
<> | 144:ef7eb2e8f9f7 | 330 | base->PTOR = mask; |
<> | 144:ef7eb2e8f9f7 | 331 | } |
<> | 144:ef7eb2e8f9f7 | 332 | /*@}*/ |
<> | 144:ef7eb2e8f9f7 | 333 | |
<> | 144:ef7eb2e8f9f7 | 334 | /*! @name FGPIO Input Operations */ |
<> | 144:ef7eb2e8f9f7 | 335 | /*@{*/ |
<> | 144:ef7eb2e8f9f7 | 336 | |
<> | 144:ef7eb2e8f9f7 | 337 | /*! |
<> | 144:ef7eb2e8f9f7 | 338 | * @brief Reads the current input value of the whole FGPIO port. |
<> | 144:ef7eb2e8f9f7 | 339 | * |
<> | 144:ef7eb2e8f9f7 | 340 | * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) |
<> | 144:ef7eb2e8f9f7 | 341 | * @param pin FGPIO pin's number |
<> | 144:ef7eb2e8f9f7 | 342 | * @retval FGPIO port input value |
<> | 144:ef7eb2e8f9f7 | 343 | * - 0: corresponding pin input low logic level. |
<> | 144:ef7eb2e8f9f7 | 344 | * - 1: corresponding pin input high logic level. |
<> | 144:ef7eb2e8f9f7 | 345 | */ |
<> | 144:ef7eb2e8f9f7 | 346 | static inline uint32_t FGPIO_ReadPinInput(FGPIO_Type *base, uint32_t pin) |
<> | 144:ef7eb2e8f9f7 | 347 | { |
<> | 144:ef7eb2e8f9f7 | 348 | return (((base->PDIR) >> pin) & 0x01U); |
<> | 144:ef7eb2e8f9f7 | 349 | } |
<> | 144:ef7eb2e8f9f7 | 350 | /*@}*/ |
<> | 144:ef7eb2e8f9f7 | 351 | |
<> | 144:ef7eb2e8f9f7 | 352 | /*! @name FGPIO Interrupt */ |
<> | 144:ef7eb2e8f9f7 | 353 | /*@{*/ |
<> | 144:ef7eb2e8f9f7 | 354 | |
<> | 144:ef7eb2e8f9f7 | 355 | /*! |
<> | 144:ef7eb2e8f9f7 | 356 | * @brief Reads the whole FGPIO port interrupt status flag. |
<> | 144:ef7eb2e8f9f7 | 357 | * |
<> | 144:ef7eb2e8f9f7 | 358 | * If a pin is configured to generate the DMA request, the corresponding flag |
<> | 144:ef7eb2e8f9f7 | 359 | * is cleared automatically at the completion of the requested DMA transfer. |
<> | 144:ef7eb2e8f9f7 | 360 | * Otherwise, the flag remains set until a logic one is written to that flag. |
<> | 144:ef7eb2e8f9f7 | 361 | * If configured for a level sensitive interrupt that remains asserted, the flag |
<> | 144:ef7eb2e8f9f7 | 362 | * is set again immediately. |
<> | 144:ef7eb2e8f9f7 | 363 | * |
<> | 144:ef7eb2e8f9f7 | 364 | * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) |
<> | 144:ef7eb2e8f9f7 | 365 | * @retval Current FGPIO port interrupt status flags, for example, 0x00010001 means the |
<> | 144:ef7eb2e8f9f7 | 366 | * pin 0 and 17 have the interrupt. |
<> | 144:ef7eb2e8f9f7 | 367 | */ |
<> | 144:ef7eb2e8f9f7 | 368 | uint32_t FGPIO_GetPinsInterruptFlags(FGPIO_Type *base); |
<> | 144:ef7eb2e8f9f7 | 369 | |
<> | 144:ef7eb2e8f9f7 | 370 | /*! |
<> | 144:ef7eb2e8f9f7 | 371 | * @brief Clears the multiple FGPIO pins' interrupt status flag. |
<> | 144:ef7eb2e8f9f7 | 372 | * |
<> | 144:ef7eb2e8f9f7 | 373 | * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.) |
<> | 144:ef7eb2e8f9f7 | 374 | * @param mask FGPIO pins' numbers macro |
<> | 144:ef7eb2e8f9f7 | 375 | */ |
<> | 144:ef7eb2e8f9f7 | 376 | void FGPIO_ClearPinsInterruptFlags(FGPIO_Type *base, uint32_t mask); |
<> | 144:ef7eb2e8f9f7 | 377 | |
<> | 144:ef7eb2e8f9f7 | 378 | /*@}*/ |
<> | 144:ef7eb2e8f9f7 | 379 | |
<> | 144:ef7eb2e8f9f7 | 380 | #endif /* FSL_FEATURE_SOC_FGPIO_COUNT */ |
<> | 144:ef7eb2e8f9f7 | 381 | |
<> | 144:ef7eb2e8f9f7 | 382 | #if defined(__cplusplus) |
<> | 144:ef7eb2e8f9f7 | 383 | } |
<> | 144:ef7eb2e8f9f7 | 384 | #endif |
<> | 144:ef7eb2e8f9f7 | 385 | |
<> | 144:ef7eb2e8f9f7 | 386 | /*! |
<> | 144:ef7eb2e8f9f7 | 387 | * @} |
<> | 144:ef7eb2e8f9f7 | 388 | */ |
<> | 144:ef7eb2e8f9f7 | 389 | |
<> | 144:ef7eb2e8f9f7 | 390 | #endif /* _FSL_GPIO_H_*/ |