added prescaler for 16 bit pwm in LPC1347 target
Fork of mbed-dev by
targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_KL43Z/drivers/fsl_gpio.c@147:ba84b7dc41a7, 2016-09-10 (annotated)
- Committer:
- JojoS
- Date:
- Sat Sep 10 15:32:04 2016 +0000
- Revision:
- 147:ba84b7dc41a7
- Parent:
- 144:ef7eb2e8f9f7
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /* |
<> | 144:ef7eb2e8f9f7 | 2 | * Copyright (c) 2015, Freescale Semiconductor, Inc. |
<> | 144:ef7eb2e8f9f7 | 3 | * All rights reserved. |
<> | 144:ef7eb2e8f9f7 | 4 | * |
<> | 144:ef7eb2e8f9f7 | 5 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 144:ef7eb2e8f9f7 | 6 | * are permitted provided that the following conditions are met: |
<> | 144:ef7eb2e8f9f7 | 7 | * |
<> | 144:ef7eb2e8f9f7 | 8 | * o Redistributions of source code must retain the above copyright notice, this list |
<> | 144:ef7eb2e8f9f7 | 9 | * of conditions and the following disclaimer. |
<> | 144:ef7eb2e8f9f7 | 10 | * |
<> | 144:ef7eb2e8f9f7 | 11 | * o Redistributions in binary form must reproduce the above copyright notice, this |
<> | 144:ef7eb2e8f9f7 | 12 | * list of conditions and the following disclaimer in the documentation and/or |
<> | 144:ef7eb2e8f9f7 | 13 | * other materials provided with the distribution. |
<> | 144:ef7eb2e8f9f7 | 14 | * |
<> | 144:ef7eb2e8f9f7 | 15 | * o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
<> | 144:ef7eb2e8f9f7 | 16 | * contributors may be used to endorse or promote products derived from this |
<> | 144:ef7eb2e8f9f7 | 17 | * software without specific prior written permission. |
<> | 144:ef7eb2e8f9f7 | 18 | * |
<> | 144:ef7eb2e8f9f7 | 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
<> | 144:ef7eb2e8f9f7 | 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
<> | 144:ef7eb2e8f9f7 | 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 144:ef7eb2e8f9f7 | 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
<> | 144:ef7eb2e8f9f7 | 23 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
<> | 144:ef7eb2e8f9f7 | 24 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
<> | 144:ef7eb2e8f9f7 | 25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
<> | 144:ef7eb2e8f9f7 | 26 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
<> | 144:ef7eb2e8f9f7 | 27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
<> | 144:ef7eb2e8f9f7 | 28 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 144:ef7eb2e8f9f7 | 29 | */ |
<> | 144:ef7eb2e8f9f7 | 30 | |
<> | 144:ef7eb2e8f9f7 | 31 | #include "fsl_gpio.h" |
<> | 144:ef7eb2e8f9f7 | 32 | |
<> | 144:ef7eb2e8f9f7 | 33 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 34 | * Variables |
<> | 144:ef7eb2e8f9f7 | 35 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 36 | static PORT_Type *const s_portBases[] = PORT_BASE_PTRS; |
<> | 144:ef7eb2e8f9f7 | 37 | static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS; |
<> | 144:ef7eb2e8f9f7 | 38 | |
<> | 144:ef7eb2e8f9f7 | 39 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 40 | * Prototypes |
<> | 144:ef7eb2e8f9f7 | 41 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 42 | |
<> | 144:ef7eb2e8f9f7 | 43 | /*! |
<> | 144:ef7eb2e8f9f7 | 44 | * @brief Gets the GPIO instance according to the GPIO base |
<> | 144:ef7eb2e8f9f7 | 45 | * |
<> | 144:ef7eb2e8f9f7 | 46 | * @param base GPIO peripheral base pointer(PTA, PTB, PTC, etc.) |
<> | 144:ef7eb2e8f9f7 | 47 | * @retval GPIO instance |
<> | 144:ef7eb2e8f9f7 | 48 | */ |
<> | 144:ef7eb2e8f9f7 | 49 | static uint32_t GPIO_GetInstance(GPIO_Type *base); |
<> | 144:ef7eb2e8f9f7 | 50 | |
<> | 144:ef7eb2e8f9f7 | 51 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 52 | * Code |
<> | 144:ef7eb2e8f9f7 | 53 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 54 | |
<> | 144:ef7eb2e8f9f7 | 55 | static uint32_t GPIO_GetInstance(GPIO_Type *base) |
<> | 144:ef7eb2e8f9f7 | 56 | { |
<> | 144:ef7eb2e8f9f7 | 57 | uint32_t instance; |
<> | 144:ef7eb2e8f9f7 | 58 | |
<> | 144:ef7eb2e8f9f7 | 59 | /* Find the instance index from base address mappings. */ |
<> | 144:ef7eb2e8f9f7 | 60 | for (instance = 0; instance < FSL_FEATURE_SOC_GPIO_COUNT; instance++) |
<> | 144:ef7eb2e8f9f7 | 61 | { |
<> | 144:ef7eb2e8f9f7 | 62 | if (s_gpioBases[instance] == base) |
<> | 144:ef7eb2e8f9f7 | 63 | { |
<> | 144:ef7eb2e8f9f7 | 64 | break; |
<> | 144:ef7eb2e8f9f7 | 65 | } |
<> | 144:ef7eb2e8f9f7 | 66 | } |
<> | 144:ef7eb2e8f9f7 | 67 | |
<> | 144:ef7eb2e8f9f7 | 68 | assert(instance < FSL_FEATURE_SOC_GPIO_COUNT); |
<> | 144:ef7eb2e8f9f7 | 69 | |
<> | 144:ef7eb2e8f9f7 | 70 | return instance; |
<> | 144:ef7eb2e8f9f7 | 71 | } |
<> | 144:ef7eb2e8f9f7 | 72 | |
<> | 144:ef7eb2e8f9f7 | 73 | void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config) |
<> | 144:ef7eb2e8f9f7 | 74 | { |
<> | 144:ef7eb2e8f9f7 | 75 | assert(config); |
<> | 144:ef7eb2e8f9f7 | 76 | |
<> | 144:ef7eb2e8f9f7 | 77 | if (config->pinDirection == kGPIO_DigitalInput) |
<> | 144:ef7eb2e8f9f7 | 78 | { |
<> | 144:ef7eb2e8f9f7 | 79 | base->PDDR &= ~(1U << pin); |
<> | 144:ef7eb2e8f9f7 | 80 | } |
<> | 144:ef7eb2e8f9f7 | 81 | else |
<> | 144:ef7eb2e8f9f7 | 82 | { |
<> | 144:ef7eb2e8f9f7 | 83 | GPIO_WritePinOutput(base, pin, config->outputLogic); |
<> | 144:ef7eb2e8f9f7 | 84 | base->PDDR |= (1U << pin); |
<> | 144:ef7eb2e8f9f7 | 85 | } |
<> | 144:ef7eb2e8f9f7 | 86 | } |
<> | 144:ef7eb2e8f9f7 | 87 | |
<> | 144:ef7eb2e8f9f7 | 88 | uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base) |
<> | 144:ef7eb2e8f9f7 | 89 | { |
<> | 144:ef7eb2e8f9f7 | 90 | uint8_t instance; |
<> | 144:ef7eb2e8f9f7 | 91 | PORT_Type *portBase; |
<> | 144:ef7eb2e8f9f7 | 92 | instance = GPIO_GetInstance(base); |
<> | 144:ef7eb2e8f9f7 | 93 | portBase = s_portBases[instance]; |
<> | 144:ef7eb2e8f9f7 | 94 | return portBase->ISFR; |
<> | 144:ef7eb2e8f9f7 | 95 | } |
<> | 144:ef7eb2e8f9f7 | 96 | |
<> | 144:ef7eb2e8f9f7 | 97 | void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask) |
<> | 144:ef7eb2e8f9f7 | 98 | { |
<> | 144:ef7eb2e8f9f7 | 99 | uint8_t instance; |
<> | 144:ef7eb2e8f9f7 | 100 | PORT_Type *portBase; |
<> | 144:ef7eb2e8f9f7 | 101 | instance = GPIO_GetInstance(base); |
<> | 144:ef7eb2e8f9f7 | 102 | portBase = s_portBases[instance]; |
<> | 144:ef7eb2e8f9f7 | 103 | portBase->ISFR = mask; |
<> | 144:ef7eb2e8f9f7 | 104 | } |
<> | 144:ef7eb2e8f9f7 | 105 | |
<> | 144:ef7eb2e8f9f7 | 106 | #if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT |
<> | 144:ef7eb2e8f9f7 | 107 | |
<> | 144:ef7eb2e8f9f7 | 108 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 109 | * Variables |
<> | 144:ef7eb2e8f9f7 | 110 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 111 | static FGPIO_Type *const s_fgpioBases[] = FGPIO_BASE_PTRS; |
<> | 144:ef7eb2e8f9f7 | 112 | |
<> | 144:ef7eb2e8f9f7 | 113 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 114 | * Prototypes |
<> | 144:ef7eb2e8f9f7 | 115 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 116 | /*! |
<> | 144:ef7eb2e8f9f7 | 117 | * @brief Gets the FGPIO instance according to the GPIO base |
<> | 144:ef7eb2e8f9f7 | 118 | * |
<> | 144:ef7eb2e8f9f7 | 119 | * @param base FGPIO peripheral base pointer(PTA, PTB, PTC, etc.) |
<> | 144:ef7eb2e8f9f7 | 120 | * @retval FGPIO instance |
<> | 144:ef7eb2e8f9f7 | 121 | */ |
<> | 144:ef7eb2e8f9f7 | 122 | static uint32_t FGPIO_GetInstance(FGPIO_Type *base); |
<> | 144:ef7eb2e8f9f7 | 123 | |
<> | 144:ef7eb2e8f9f7 | 124 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 125 | * Code |
<> | 144:ef7eb2e8f9f7 | 126 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 127 | |
<> | 144:ef7eb2e8f9f7 | 128 | static uint32_t FGPIO_GetInstance(FGPIO_Type *base) |
<> | 144:ef7eb2e8f9f7 | 129 | { |
<> | 144:ef7eb2e8f9f7 | 130 | uint32_t instance; |
<> | 144:ef7eb2e8f9f7 | 131 | |
<> | 144:ef7eb2e8f9f7 | 132 | /* Find the instance index from base address mappings. */ |
<> | 144:ef7eb2e8f9f7 | 133 | for (instance = 0; instance < FSL_FEATURE_SOC_FGPIO_COUNT; instance++) |
<> | 144:ef7eb2e8f9f7 | 134 | { |
<> | 144:ef7eb2e8f9f7 | 135 | if (s_fgpioBases[instance] == base) |
<> | 144:ef7eb2e8f9f7 | 136 | { |
<> | 144:ef7eb2e8f9f7 | 137 | break; |
<> | 144:ef7eb2e8f9f7 | 138 | } |
<> | 144:ef7eb2e8f9f7 | 139 | } |
<> | 144:ef7eb2e8f9f7 | 140 | |
<> | 144:ef7eb2e8f9f7 | 141 | assert(instance < FSL_FEATURE_SOC_FGPIO_COUNT); |
<> | 144:ef7eb2e8f9f7 | 142 | |
<> | 144:ef7eb2e8f9f7 | 143 | return instance; |
<> | 144:ef7eb2e8f9f7 | 144 | } |
<> | 144:ef7eb2e8f9f7 | 145 | |
<> | 144:ef7eb2e8f9f7 | 146 | void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config) |
<> | 144:ef7eb2e8f9f7 | 147 | { |
<> | 144:ef7eb2e8f9f7 | 148 | assert(config); |
<> | 144:ef7eb2e8f9f7 | 149 | |
<> | 144:ef7eb2e8f9f7 | 150 | if (config->pinDirection == kGPIO_DigitalInput) |
<> | 144:ef7eb2e8f9f7 | 151 | { |
<> | 144:ef7eb2e8f9f7 | 152 | base->PDDR &= ~(1U << pin); |
<> | 144:ef7eb2e8f9f7 | 153 | } |
<> | 144:ef7eb2e8f9f7 | 154 | else |
<> | 144:ef7eb2e8f9f7 | 155 | { |
<> | 144:ef7eb2e8f9f7 | 156 | FGPIO_WritePinOutput(base, pin, config->outputLogic); |
<> | 144:ef7eb2e8f9f7 | 157 | base->PDDR |= (1U << pin); |
<> | 144:ef7eb2e8f9f7 | 158 | } |
<> | 144:ef7eb2e8f9f7 | 159 | } |
<> | 144:ef7eb2e8f9f7 | 160 | |
<> | 144:ef7eb2e8f9f7 | 161 | uint32_t FGPIO_GetPinsInterruptFlags(FGPIO_Type *base) |
<> | 144:ef7eb2e8f9f7 | 162 | { |
<> | 144:ef7eb2e8f9f7 | 163 | uint8_t instance; |
<> | 144:ef7eb2e8f9f7 | 164 | instance = FGPIO_GetInstance(base); |
<> | 144:ef7eb2e8f9f7 | 165 | PORT_Type *portBase; |
<> | 144:ef7eb2e8f9f7 | 166 | portBase = s_portBases[instance]; |
<> | 144:ef7eb2e8f9f7 | 167 | return portBase->ISFR; |
<> | 144:ef7eb2e8f9f7 | 168 | } |
<> | 144:ef7eb2e8f9f7 | 169 | |
<> | 144:ef7eb2e8f9f7 | 170 | void FGPIO_ClearPinsInterruptFlags(FGPIO_Type *base, uint32_t mask) |
<> | 144:ef7eb2e8f9f7 | 171 | { |
<> | 144:ef7eb2e8f9f7 | 172 | uint8_t instance; |
<> | 144:ef7eb2e8f9f7 | 173 | instance = FGPIO_GetInstance(base); |
<> | 144:ef7eb2e8f9f7 | 174 | PORT_Type *portBase; |
<> | 144:ef7eb2e8f9f7 | 175 | portBase = s_portBases[instance]; |
<> | 144:ef7eb2e8f9f7 | 176 | portBase->ISFR = mask; |
<> | 144:ef7eb2e8f9f7 | 177 | } |
<> | 144:ef7eb2e8f9f7 | 178 | |
<> | 144:ef7eb2e8f9f7 | 179 | #endif /* FSL_FEATURE_SOC_FGPIO_COUNT */ |