added prescaler for 16 bit pwm in LPC1347 target
Fork of mbed-dev by
targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_vref.c@147:ba84b7dc41a7, 2016-09-10 (annotated)
- Committer:
- JojoS
- Date:
- Sat Sep 10 15:32:04 2016 +0000
- Revision:
- 147:ba84b7dc41a7
- Parent:
- 144:ef7eb2e8f9f7
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /* |
<> | 144:ef7eb2e8f9f7 | 2 | * Copyright (c) 2015, Freescale Semiconductor, Inc. |
<> | 144:ef7eb2e8f9f7 | 3 | * All rights reserved. |
<> | 144:ef7eb2e8f9f7 | 4 | * |
<> | 144:ef7eb2e8f9f7 | 5 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 144:ef7eb2e8f9f7 | 6 | * are permitted provided that the following conditions are met: |
<> | 144:ef7eb2e8f9f7 | 7 | * |
<> | 144:ef7eb2e8f9f7 | 8 | * o Redistributions of source code must retain the above copyright notice, this list |
<> | 144:ef7eb2e8f9f7 | 9 | * of conditions and the following disclaimer. |
<> | 144:ef7eb2e8f9f7 | 10 | * |
<> | 144:ef7eb2e8f9f7 | 11 | * o Redistributions in binary form must reproduce the above copyright notice, this |
<> | 144:ef7eb2e8f9f7 | 12 | * list of conditions and the following disclaimer in the documentation and/or |
<> | 144:ef7eb2e8f9f7 | 13 | * other materials provided with the distribution. |
<> | 144:ef7eb2e8f9f7 | 14 | * |
<> | 144:ef7eb2e8f9f7 | 15 | * o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
<> | 144:ef7eb2e8f9f7 | 16 | * contributors may be used to endorse or promote products derived from this |
<> | 144:ef7eb2e8f9f7 | 17 | * software without specific prior written permission. |
<> | 144:ef7eb2e8f9f7 | 18 | * |
<> | 144:ef7eb2e8f9f7 | 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
<> | 144:ef7eb2e8f9f7 | 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
<> | 144:ef7eb2e8f9f7 | 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 144:ef7eb2e8f9f7 | 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
<> | 144:ef7eb2e8f9f7 | 23 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
<> | 144:ef7eb2e8f9f7 | 24 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
<> | 144:ef7eb2e8f9f7 | 25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
<> | 144:ef7eb2e8f9f7 | 26 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
<> | 144:ef7eb2e8f9f7 | 27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
<> | 144:ef7eb2e8f9f7 | 28 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 144:ef7eb2e8f9f7 | 29 | */ |
<> | 144:ef7eb2e8f9f7 | 30 | |
<> | 144:ef7eb2e8f9f7 | 31 | #include "fsl_vref.h" |
<> | 144:ef7eb2e8f9f7 | 32 | |
<> | 144:ef7eb2e8f9f7 | 33 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 34 | * Prototypes |
<> | 144:ef7eb2e8f9f7 | 35 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 36 | |
<> | 144:ef7eb2e8f9f7 | 37 | /*! |
<> | 144:ef7eb2e8f9f7 | 38 | * @brief Gets the instance from the base address |
<> | 144:ef7eb2e8f9f7 | 39 | * |
<> | 144:ef7eb2e8f9f7 | 40 | * @param base VREF peripheral base address |
<> | 144:ef7eb2e8f9f7 | 41 | * |
<> | 144:ef7eb2e8f9f7 | 42 | * @return The VREF instance |
<> | 144:ef7eb2e8f9f7 | 43 | */ |
<> | 144:ef7eb2e8f9f7 | 44 | static uint32_t VREF_GetInstance(VREF_Type *base); |
<> | 144:ef7eb2e8f9f7 | 45 | |
<> | 144:ef7eb2e8f9f7 | 46 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 47 | * Variables |
<> | 144:ef7eb2e8f9f7 | 48 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 49 | |
<> | 144:ef7eb2e8f9f7 | 50 | /*! @brief Pointers to VREF bases for each instance. */ |
<> | 144:ef7eb2e8f9f7 | 51 | static VREF_Type *const s_vrefBases[] = VREF_BASE_PTRS; |
<> | 144:ef7eb2e8f9f7 | 52 | |
<> | 144:ef7eb2e8f9f7 | 53 | /*! @brief Pointers to VREF clocks for each instance. */ |
<> | 144:ef7eb2e8f9f7 | 54 | static const clock_ip_name_t s_vrefClocks[] = VREF_CLOCKS; |
<> | 144:ef7eb2e8f9f7 | 55 | |
<> | 144:ef7eb2e8f9f7 | 56 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 57 | * Code |
<> | 144:ef7eb2e8f9f7 | 58 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 59 | |
<> | 144:ef7eb2e8f9f7 | 60 | static uint32_t VREF_GetInstance(VREF_Type *base) |
<> | 144:ef7eb2e8f9f7 | 61 | { |
<> | 144:ef7eb2e8f9f7 | 62 | uint32_t instance; |
<> | 144:ef7eb2e8f9f7 | 63 | |
<> | 144:ef7eb2e8f9f7 | 64 | /* Find the instance index from base address mappings. */ |
<> | 144:ef7eb2e8f9f7 | 65 | for (instance = 0; instance < FSL_FEATURE_SOC_VREF_COUNT; instance++) |
<> | 144:ef7eb2e8f9f7 | 66 | { |
<> | 144:ef7eb2e8f9f7 | 67 | if (s_vrefBases[instance] == base) |
<> | 144:ef7eb2e8f9f7 | 68 | { |
<> | 144:ef7eb2e8f9f7 | 69 | break; |
<> | 144:ef7eb2e8f9f7 | 70 | } |
<> | 144:ef7eb2e8f9f7 | 71 | } |
<> | 144:ef7eb2e8f9f7 | 72 | |
<> | 144:ef7eb2e8f9f7 | 73 | assert(instance < FSL_FEATURE_SOC_VREF_COUNT); |
<> | 144:ef7eb2e8f9f7 | 74 | |
<> | 144:ef7eb2e8f9f7 | 75 | return instance; |
<> | 144:ef7eb2e8f9f7 | 76 | } |
<> | 144:ef7eb2e8f9f7 | 77 | |
<> | 144:ef7eb2e8f9f7 | 78 | void VREF_Init(VREF_Type *base, const vref_config_t *config) |
<> | 144:ef7eb2e8f9f7 | 79 | { |
<> | 144:ef7eb2e8f9f7 | 80 | assert(config != NULL); |
<> | 144:ef7eb2e8f9f7 | 81 | |
<> | 144:ef7eb2e8f9f7 | 82 | uint8_t reg = 0U; |
<> | 144:ef7eb2e8f9f7 | 83 | |
<> | 144:ef7eb2e8f9f7 | 84 | /* Ungate clock for VREF */ |
<> | 144:ef7eb2e8f9f7 | 85 | CLOCK_EnableClock(s_vrefClocks[VREF_GetInstance(base)]); |
<> | 144:ef7eb2e8f9f7 | 86 | |
<> | 144:ef7eb2e8f9f7 | 87 | /* Configure VREF to a known state */ |
<> | 144:ef7eb2e8f9f7 | 88 | #if defined(FSL_FEATURE_VREF_HAS_CHOP_OSC) && FSL_FEATURE_VREF_HAS_CHOP_OSC |
<> | 144:ef7eb2e8f9f7 | 89 | /* Set chop oscillator bit */ |
<> | 144:ef7eb2e8f9f7 | 90 | base->TRM |= VREF_TRM_CHOPEN_MASK; |
<> | 144:ef7eb2e8f9f7 | 91 | #endif /* FSL_FEATURE_VREF_HAS_CHOP_OSC */ |
<> | 144:ef7eb2e8f9f7 | 92 | reg = base->SC; |
<> | 144:ef7eb2e8f9f7 | 93 | /* Set buffer Mode selection and Regulator enable bit */ |
<> | 144:ef7eb2e8f9f7 | 94 | reg |= VREF_SC_MODE_LV(config->bufferMode) | VREF_SC_REGEN(1U); |
<> | 144:ef7eb2e8f9f7 | 95 | #if defined(FSL_FEATURE_VREF_HAS_COMPENSATION) && FSL_FEATURE_VREF_HAS_COMPENSATION |
<> | 144:ef7eb2e8f9f7 | 96 | /* Set second order curvature compensation enable bit */ |
<> | 144:ef7eb2e8f9f7 | 97 | reg |= VREF_SC_ICOMPEN(1U); |
<> | 144:ef7eb2e8f9f7 | 98 | #endif /* FSL_FEATURE_VREF_HAS_COMPENSATION */ |
<> | 144:ef7eb2e8f9f7 | 99 | /* Enable VREF module */ |
<> | 144:ef7eb2e8f9f7 | 100 | reg |= VREF_SC_VREFEN(1U); |
<> | 144:ef7eb2e8f9f7 | 101 | /* Update bit-field from value to Status and Control register */ |
<> | 144:ef7eb2e8f9f7 | 102 | base->SC = reg; |
<> | 144:ef7eb2e8f9f7 | 103 | #if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE |
<> | 144:ef7eb2e8f9f7 | 104 | reg = base->VREFL_TRM; |
<> | 144:ef7eb2e8f9f7 | 105 | /* Clear old select external voltage reference and VREFL (0.4 V) reference buffer enable bits*/ |
<> | 144:ef7eb2e8f9f7 | 106 | reg &= ~(VREF_VREFL_TRM_VREFL_EN_MASK | VREF_VREFL_TRM_VREFL_SEL_MASK); |
<> | 144:ef7eb2e8f9f7 | 107 | /* Select external voltage reference and set VREFL (0.4 V) reference buffer enable */ |
<> | 144:ef7eb2e8f9f7 | 108 | reg |= VREF_VREFL_TRM_VREFL_SEL(config->enableExternalVoltRef) | VREF_VREFL_TRM_VREFL_EN(config->enableLowRef); |
<> | 144:ef7eb2e8f9f7 | 109 | base->VREFL_TRM = reg; |
<> | 144:ef7eb2e8f9f7 | 110 | #endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */ |
<> | 144:ef7eb2e8f9f7 | 111 | |
<> | 144:ef7eb2e8f9f7 | 112 | /* Wait until internal voltage stable */ |
<> | 144:ef7eb2e8f9f7 | 113 | while ((base->SC & VREF_SC_VREFST_MASK) == 0) |
<> | 144:ef7eb2e8f9f7 | 114 | { |
<> | 144:ef7eb2e8f9f7 | 115 | } |
<> | 144:ef7eb2e8f9f7 | 116 | } |
<> | 144:ef7eb2e8f9f7 | 117 | |
<> | 144:ef7eb2e8f9f7 | 118 | void VREF_Deinit(VREF_Type *base) |
<> | 144:ef7eb2e8f9f7 | 119 | { |
<> | 144:ef7eb2e8f9f7 | 120 | /* Gate clock for VREF */ |
<> | 144:ef7eb2e8f9f7 | 121 | CLOCK_DisableClock(s_vrefClocks[VREF_GetInstance(base)]); |
<> | 144:ef7eb2e8f9f7 | 122 | } |
<> | 144:ef7eb2e8f9f7 | 123 | |
<> | 144:ef7eb2e8f9f7 | 124 | void VREF_GetDefaultConfig(vref_config_t *config) |
<> | 144:ef7eb2e8f9f7 | 125 | { |
<> | 144:ef7eb2e8f9f7 | 126 | /* Set High power buffer mode in */ |
<> | 144:ef7eb2e8f9f7 | 127 | #if defined(FSL_FEATURE_VREF_MODE_LV_TYPE) && FSL_FEATURE_VREF_MODE_LV_TYPE |
<> | 144:ef7eb2e8f9f7 | 128 | config->bufferMode = kVREF_ModeHighPowerBuffer; |
<> | 144:ef7eb2e8f9f7 | 129 | #else |
<> | 144:ef7eb2e8f9f7 | 130 | config->bufferMode = kVREF_ModeTightRegulationBuffer; |
<> | 144:ef7eb2e8f9f7 | 131 | #endif /* FSL_FEATURE_VREF_MODE_LV_TYPE */ |
<> | 144:ef7eb2e8f9f7 | 132 | |
<> | 144:ef7eb2e8f9f7 | 133 | #if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE |
<> | 144:ef7eb2e8f9f7 | 134 | /* Select internal voltage reference */ |
<> | 144:ef7eb2e8f9f7 | 135 | config->enableExternalVoltRef = false; |
<> | 144:ef7eb2e8f9f7 | 136 | /* Set VREFL (0.4 V) reference buffer disable */ |
<> | 144:ef7eb2e8f9f7 | 137 | config->enableLowRef = false; |
<> | 144:ef7eb2e8f9f7 | 138 | #endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */ |
<> | 144:ef7eb2e8f9f7 | 139 | } |
<> | 144:ef7eb2e8f9f7 | 140 | |
<> | 144:ef7eb2e8f9f7 | 141 | void VREF_SetTrimVal(VREF_Type *base, uint8_t trimValue) |
<> | 144:ef7eb2e8f9f7 | 142 | { |
<> | 144:ef7eb2e8f9f7 | 143 | uint8_t reg = 0U; |
<> | 144:ef7eb2e8f9f7 | 144 | |
<> | 144:ef7eb2e8f9f7 | 145 | /* Set TRIM bits value in voltage reference */ |
<> | 144:ef7eb2e8f9f7 | 146 | reg = base->TRM; |
<> | 144:ef7eb2e8f9f7 | 147 | reg = ((reg & ~VREF_TRM_TRIM_MASK) | VREF_TRM_TRIM(trimValue)); |
<> | 144:ef7eb2e8f9f7 | 148 | base->TRM = reg; |
<> | 144:ef7eb2e8f9f7 | 149 | /* Wait until internal voltage stable */ |
<> | 144:ef7eb2e8f9f7 | 150 | while ((base->SC & VREF_SC_VREFST_MASK) == 0) |
<> | 144:ef7eb2e8f9f7 | 151 | { |
<> | 144:ef7eb2e8f9f7 | 152 | } |
<> | 144:ef7eb2e8f9f7 | 153 | } |
<> | 144:ef7eb2e8f9f7 | 154 | |
<> | 144:ef7eb2e8f9f7 | 155 | #if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE |
<> | 144:ef7eb2e8f9f7 | 156 | void VREF_SetLowReferenceTrimVal(VREF_Type *base, uint8_t trimValue) |
<> | 144:ef7eb2e8f9f7 | 157 | { |
<> | 144:ef7eb2e8f9f7 | 158 | /* The values 111b and 110b are NOT valid/allowed */ |
<> | 144:ef7eb2e8f9f7 | 159 | assert((trimValue != 0x7U) && (trimValue != 0x6U)); |
<> | 144:ef7eb2e8f9f7 | 160 | |
<> | 144:ef7eb2e8f9f7 | 161 | uint8_t reg = 0U; |
<> | 144:ef7eb2e8f9f7 | 162 | |
<> | 144:ef7eb2e8f9f7 | 163 | /* Set TRIM bits value in low voltage reference */ |
<> | 144:ef7eb2e8f9f7 | 164 | reg = base->VREFL_TRM; |
<> | 144:ef7eb2e8f9f7 | 165 | reg = ((reg & ~VREF_VREFL_TRM_VREFL_TRIM_MASK) | VREF_VREFL_TRM_VREFL_TRIM(trimValue)); |
<> | 144:ef7eb2e8f9f7 | 166 | base->VREFL_TRM = reg; |
<> | 144:ef7eb2e8f9f7 | 167 | /* Wait until internal voltage stable */ |
<> | 144:ef7eb2e8f9f7 | 168 | while ((base->SC & VREF_SC_VREFST_MASK) == 0) |
<> | 144:ef7eb2e8f9f7 | 169 | { |
<> | 144:ef7eb2e8f9f7 | 170 | } |
<> | 144:ef7eb2e8f9f7 | 171 | } |
<> | 144:ef7eb2e8f9f7 | 172 | #endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */ |