Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_sdramc.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 144:ef7eb2e8f9f7 3 * All rights reserved.
<> 144:ef7eb2e8f9f7 4 *
<> 144:ef7eb2e8f9f7 5 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 6 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 144:ef7eb2e8f9f7 9 * of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 144:ef7eb2e8f9f7 12 * list of conditions and the following disclaimer in the documentation and/or
<> 144:ef7eb2e8f9f7 13 * other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 144:ef7eb2e8f9f7 16 * contributors may be used to endorse or promote products derived from this
<> 144:ef7eb2e8f9f7 17 * software without specific prior written permission.
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 29 */
<> 144:ef7eb2e8f9f7 30 #ifndef _FSL_SDRAMC_H_
<> 144:ef7eb2e8f9f7 31 #define _FSL_SDRAMC_H_
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 #include "fsl_common.h"
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 /*!
<> 144:ef7eb2e8f9f7 36 * @addtogroup sdramc
<> 144:ef7eb2e8f9f7 37 * @{
<> 144:ef7eb2e8f9f7 38 */
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 /*! @file */
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 /*******************************************************************************
<> 144:ef7eb2e8f9f7 43 * Definitions
<> 144:ef7eb2e8f9f7 44 ******************************************************************************/
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /*! @name Driver version */
<> 144:ef7eb2e8f9f7 47 /*@{*/
<> 144:ef7eb2e8f9f7 48 /*! @brief SDRAMC driver version 2.0.0. */
<> 144:ef7eb2e8f9f7 49 #define FSL_SDRAMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
<> 144:ef7eb2e8f9f7 50 /*@}*/
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 /*! @brief SDRAM controller auto-refresh timing. */
<> 144:ef7eb2e8f9f7 53 typedef enum _sdramc_refresh_time
<> 144:ef7eb2e8f9f7 54 {
<> 144:ef7eb2e8f9f7 55 kSDRAMC_RefreshThreeClocks = 0x0U, /*!< The refresh timing with three bus clocks. */
<> 144:ef7eb2e8f9f7 56 kSDRAMC_RefreshSixClocks, /*!< The refresh timing with six bus clocks. */
<> 144:ef7eb2e8f9f7 57 kSDRAMC_RefreshNineClocks /*!< The refresh timing with nine bus clocks. */
<> 144:ef7eb2e8f9f7 58 } sdramc_refresh_time_t;
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 /*!
<> 144:ef7eb2e8f9f7 61 * @brief Setting latency for SDRAM controller timing specifications.
<> 144:ef7eb2e8f9f7 62 *
<> 144:ef7eb2e8f9f7 63 * The latency setting will affects the following SDRAM timing specifications:
<> 144:ef7eb2e8f9f7 64 * - trcd: SRAS assertion to SCAS assertion \n
<> 144:ef7eb2e8f9f7 65 * - tcasl: SCAS assertion to data out \n
<> 144:ef7eb2e8f9f7 66 * - tras: ACTV command to Precharge command \n
<> 144:ef7eb2e8f9f7 67 * - trp: Precharge command to ACTV command \n
<> 144:ef7eb2e8f9f7 68 * - trwl, trdl: Last data input to Precharge command \n
<> 144:ef7eb2e8f9f7 69 * - tep: Last data out to Precharge command \n
<> 144:ef7eb2e8f9f7 70 * the details of the latency setting and timing specifications are shown on the following table list: \n
<> 144:ef7eb2e8f9f7 71 * latency trcd: tcasl tras trp trwl,trdl tep \n
<> 144:ef7eb2e8f9f7 72 * 0 1 bus clock 1 bus clock 2 bus clocks 1 bus clock 1 bus clock 1 bus clock \n
<> 144:ef7eb2e8f9f7 73 * 1 2 bus clock 2 bus clock 4 bus clocks 2 bus clock 1 bus clock 1 bus clock \n
<> 144:ef7eb2e8f9f7 74 * 2 3 bus clock 3 bus clock 6 bus clocks 3 bus clock 1 bus clock 1 bus clock \n
<> 144:ef7eb2e8f9f7 75 * 3 3 bus clock 3 bus clock 6 bus clocks 3 bus clock 1 bus clock 1 bus clock \n
<> 144:ef7eb2e8f9f7 76 */
<> 144:ef7eb2e8f9f7 77 typedef enum _sdramc_latency
<> 144:ef7eb2e8f9f7 78 {
<> 144:ef7eb2e8f9f7 79 kSDRAMC_LatencyZero = 0x0U, /*!< Latency 0. */
<> 144:ef7eb2e8f9f7 80 kSDRAMC_LatencyOne, /*!< Latency 1. */
<> 144:ef7eb2e8f9f7 81 kSDRAMC_LatencyTwo, /*!< Latency 2. */
<> 144:ef7eb2e8f9f7 82 kSDRAMC_LatencyThree, /*!< Latency 3. */
<> 144:ef7eb2e8f9f7 83 } sdramc_latency_t;
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 /*! @brief SDRAM controller command bit location. */
<> 144:ef7eb2e8f9f7 86 typedef enum _sdramc_command_bit_location
<> 144:ef7eb2e8f9f7 87 {
<> 144:ef7eb2e8f9f7 88 kSDRAMC_Commandbit17 = 0x0U, /*!< Command bit location is bit 17. */
<> 144:ef7eb2e8f9f7 89 kSDRAMC_Commandbit18, /*!< Command bit location is bit 18. */
<> 144:ef7eb2e8f9f7 90 kSDRAMC_Commandbit19, /*!< Command bit location is bit 19. */
<> 144:ef7eb2e8f9f7 91 kSDRAMC_Commandbit20, /*!< Command bit location is bit 20. */
<> 144:ef7eb2e8f9f7 92 kSDRAMC_Commandbit21, /*!< Command bit location is bit 21. */
<> 144:ef7eb2e8f9f7 93 kSDRAMC_Commandbit22, /*!< Command bit location is bit 22. */
<> 144:ef7eb2e8f9f7 94 kSDRAMC_Commandbit23, /*!< Command bit location is bit 23. */
<> 144:ef7eb2e8f9f7 95 kSDRAMC_Commandbit24 /*!< Command bit location is bit 24. */
<> 144:ef7eb2e8f9f7 96 } sdramc_command_bit_location_t;
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 /*! @brief SDRAM controller command. */
<> 144:ef7eb2e8f9f7 99 typedef enum _sdramc_command
<> 144:ef7eb2e8f9f7 100 {
<> 144:ef7eb2e8f9f7 101 kSDRAMC_ImrsCommand = 0x0U, /*!< Initiate MRS command. */
<> 144:ef7eb2e8f9f7 102 kSDRAMC_PrechargeCommand, /*!< Initiate precharge command. */
<> 144:ef7eb2e8f9f7 103 kSDRAMC_SelfrefreshEnterCommand, /*!< Enter self-refresh command. */
<> 144:ef7eb2e8f9f7 104 kSDRAMC_SelfrefreshExitCommand, /*!< Exit self-refresh command. */
<> 144:ef7eb2e8f9f7 105 kSDRAMC_AutoRefreshEnableCommand, /*!< Enable Auto refresh command. */
<> 144:ef7eb2e8f9f7 106 kSDRAMC_AutoRefreshDisableCommand, /*!< Disable Auto refresh command. */
<> 144:ef7eb2e8f9f7 107 } sdramc_command_t;
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 /*! @brief SDRAM port size. */
<> 144:ef7eb2e8f9f7 110 typedef enum _sdramc_port_size
<> 144:ef7eb2e8f9f7 111 {
<> 144:ef7eb2e8f9f7 112 kSDRAMC_PortSize32Bit = 0x0U, /*!< 32-Bit port size. */
<> 144:ef7eb2e8f9f7 113 kSDRAMC_PortSize8Bit, /*!< 8-Bit port size. */
<> 144:ef7eb2e8f9f7 114 kSDRAMC_PortSize16Bit /*!< 16-Bit port size. */
<> 144:ef7eb2e8f9f7 115 } sdramc_port_size_t;
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 /*! @brief SDRAM controller block selection. */
<> 144:ef7eb2e8f9f7 118 typedef enum _sdramc_block_selection
<> 144:ef7eb2e8f9f7 119 {
<> 144:ef7eb2e8f9f7 120 kSDRAMC_Block0 = 0x0U, /*!< Select SDRAM block 0. */
<> 144:ef7eb2e8f9f7 121 kSDRAMC_Block1, /*!< Select SDRAM block 1. */
<> 144:ef7eb2e8f9f7 122 } sdramc_block_selection_t;
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 /*! @brief SDRAM controller block control configuration structure. */
<> 144:ef7eb2e8f9f7 125 typedef struct _sdramc_blockctl_config
<> 144:ef7eb2e8f9f7 126 {
<> 144:ef7eb2e8f9f7 127 sdramc_block_selection_t block; /*!< The block number. */
<> 144:ef7eb2e8f9f7 128 sdramc_port_size_t portSize; /*!< The port size of the associated SDRAM block. */
<> 144:ef7eb2e8f9f7 129 sdramc_command_bit_location_t location; /*!< The command bit location. */
<> 144:ef7eb2e8f9f7 130 sdramc_latency_t latency; /*!< The latency for some timing specifications. */
<> 144:ef7eb2e8f9f7 131 uint32_t address; /*!< The base address of the SDRAM block. */
<> 144:ef7eb2e8f9f7 132 uint32_t addressMask; /*!< The base address mask of the SDRAM block. */
<> 144:ef7eb2e8f9f7 133 } sdramc_blockctl_config_t;
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 /*! @brief SDRAM controller refresh timing configuration structure. */
<> 144:ef7eb2e8f9f7 136 typedef struct _sdramc_refresh_config
<> 144:ef7eb2e8f9f7 137 {
<> 144:ef7eb2e8f9f7 138 sdramc_refresh_time_t refreshTime; /*!< Trc:The number of bus clocks inserted
<> 144:ef7eb2e8f9f7 139 between a REF and next ACTIVE command. */
<> 144:ef7eb2e8f9f7 140 uint32_t sdramRefreshRow; /*!< The SDRAM refresh time each row: ns/row. */
<> 144:ef7eb2e8f9f7 141 uint32_t busClock_Hz; /*!< The bus clock for SDRAMC. */
<> 144:ef7eb2e8f9f7 142 } sdramc_refresh_config_t;
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 /*!
<> 144:ef7eb2e8f9f7 145 * @brief SDRAM controller configuration structure.
<> 144:ef7eb2e8f9f7 146 *
<> 144:ef7eb2e8f9f7 147 * Defines a configure structure and uses the SDRAMC_Configure() function to make necessary
<> 144:ef7eb2e8f9f7 148 * initializations.
<> 144:ef7eb2e8f9f7 149 */
<> 144:ef7eb2e8f9f7 150 typedef struct _sdramc_config_t
<> 144:ef7eb2e8f9f7 151 {
<> 144:ef7eb2e8f9f7 152 sdramc_refresh_config_t *refreshConfig; /*!< Refresh timing configure structure pointer. */
<> 144:ef7eb2e8f9f7 153 sdramc_blockctl_config_t *blockConfig; /*!< Block configure structure pointer. If both SDRAM
<> 144:ef7eb2e8f9f7 154 blocks are used, use the two continuous blockConfig. */
<> 144:ef7eb2e8f9f7 155 uint8_t numBlockConfig; /*!< SDRAM block numbers for configuration. */
<> 144:ef7eb2e8f9f7 156 } sdramc_config_t;
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 /*******************************************************************************
<> 144:ef7eb2e8f9f7 159 * API
<> 144:ef7eb2e8f9f7 160 ******************************************************************************/
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 #if defined(__cplusplus)
<> 144:ef7eb2e8f9f7 163 extern "C" {
<> 144:ef7eb2e8f9f7 164 #endif
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 /*!
<> 144:ef7eb2e8f9f7 167 * @name SDRAM Controller Initialization and De-initialization
<> 144:ef7eb2e8f9f7 168 * @{
<> 144:ef7eb2e8f9f7 169 */
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 /*!
<> 144:ef7eb2e8f9f7 172 * @brief Initializes the SDRAM controller.
<> 144:ef7eb2e8f9f7 173 * This function ungates the SDRAM controller clock and initializes the SDRAM controller.
<> 144:ef7eb2e8f9f7 174 * This function must be called before calling any other SDRAM controller driver functions.
<> 144:ef7eb2e8f9f7 175 * Example
<> 144:ef7eb2e8f9f7 176 @code
<> 144:ef7eb2e8f9f7 177 sdramc_refresh_config_t refreshConfig;
<> 144:ef7eb2e8f9f7 178 sdramc_blockctl_config_t blockConfig;
<> 144:ef7eb2e8f9f7 179 sdramc_config_t config;
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 refreshConfig.refreshTime = kSDRAM_RefreshThreeClocks;
<> 144:ef7eb2e8f9f7 182 refreshConfig.sdramRefreshRow = 15625;
<> 144:ef7eb2e8f9f7 183 refreshConfig.busClock = 60000000;
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 blockConfig.block = kSDRAMC_Block0;
<> 144:ef7eb2e8f9f7 186 blockConfig.portSize = kSDRAMC_PortSize16Bit;
<> 144:ef7eb2e8f9f7 187 blockConfig.location = kSDRAMC_Commandbit19;
<> 144:ef7eb2e8f9f7 188 blockConfig.latency = kSDRAMC_RefreshThreeClocks;
<> 144:ef7eb2e8f9f7 189 blockConfig.address = SDRAM_START_ADDRESS;
<> 144:ef7eb2e8f9f7 190 blockConfig.addressMask = 0x7c0000;
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 config.refreshConfig = &refreshConfig,
<> 144:ef7eb2e8f9f7 193 config.blockConfig = &blockConfig,
<> 144:ef7eb2e8f9f7 194 config.totalBlocks = 1;
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 SDRAMC_Init(SDRAM, &config);
<> 144:ef7eb2e8f9f7 197 @endcode
<> 144:ef7eb2e8f9f7 198 *
<> 144:ef7eb2e8f9f7 199 * @param base SDRAM controller peripheral base address.
<> 144:ef7eb2e8f9f7 200 * @param configure The SDRAM configuration structure pointer.
<> 144:ef7eb2e8f9f7 201 */
<> 144:ef7eb2e8f9f7 202 void SDRAMC_Init(SDRAM_Type *base, sdramc_config_t *configure);
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 /*!
<> 144:ef7eb2e8f9f7 205 * @brief Deinitializes the SDRAM controller module and gates the clock.
<> 144:ef7eb2e8f9f7 206 * This function gates the SDRAM controller clock. As a result, the SDRAM
<> 144:ef7eb2e8f9f7 207 * controller module doesn't work after calling this function.
<> 144:ef7eb2e8f9f7 208 *
<> 144:ef7eb2e8f9f7 209 * @param base SDRAM controller peripheral base address.
<> 144:ef7eb2e8f9f7 210 */
<> 144:ef7eb2e8f9f7 211 void SDRAMC_Deinit(SDRAM_Type *base);
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 /* @} */
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 /*!
<> 144:ef7eb2e8f9f7 216 * @name SDRAM Controller Basic Operation
<> 144:ef7eb2e8f9f7 217 * @{
<> 144:ef7eb2e8f9f7 218 */
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 /*!
<> 144:ef7eb2e8f9f7 221 * @brief Sends the SDRAM command.
<> 144:ef7eb2e8f9f7 222 * This function sends the command to SDRAM. There are precharge command, initialize MRS command,
<> 144:ef7eb2e8f9f7 223 * auto-refresh enable/disable command, and self-refresh enter/exit commands.
<> 144:ef7eb2e8f9f7 224 * Note the self-refresh enter/exit commands are all blocks setting and "block"
<> 144:ef7eb2e8f9f7 225 * are ignored. Ensure to set the right "block" when send other commands.
<> 144:ef7eb2e8f9f7 226 *
<> 144:ef7eb2e8f9f7 227 * @param base SDRAM controller peripheral base address.
<> 144:ef7eb2e8f9f7 228 * @param block The block selection.
<> 144:ef7eb2e8f9f7 229 * @param command The SDRAM command, see "sdramc_command_t".
<> 144:ef7eb2e8f9f7 230 * kSDRAMC_ImrsCommand - Initialize MRS command \n
<> 144:ef7eb2e8f9f7 231 * kSDRAMC_PrechargeCommand - Initialize precharge command \n
<> 144:ef7eb2e8f9f7 232 * kSDRAMC_SelfrefreshEnterCommand - Enter self-refresh command \n
<> 144:ef7eb2e8f9f7 233 * kSDRAMC_SelfrefreshExitCommand - Exit self-refresh command \n
<> 144:ef7eb2e8f9f7 234 * kSDRAMC_AutoRefreshEnableCommand - Enable auto refresh command \n
<> 144:ef7eb2e8f9f7 235 * kSDRAMC_AutoRefreshDisableCommand - Disable auto refresh command
<> 144:ef7eb2e8f9f7 236 * @return Command execution status.
<> 144:ef7eb2e8f9f7 237 * All commands except the "initialize MRS command" and "precharge command"
<> 144:ef7eb2e8f9f7 238 * return kStatus_Success directly.
<> 144:ef7eb2e8f9f7 239 * For "initialize MRS command" and "precharge command"
<> 144:ef7eb2e8f9f7 240 * return kStatus_Success when the command success else return kStatus_Fail.
<> 144:ef7eb2e8f9f7 241 */
<> 144:ef7eb2e8f9f7 242 status_t SDRAMC_SendCommand(SDRAM_Type *base, sdramc_block_selection_t block, sdramc_command_t command);
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 /*!
<> 144:ef7eb2e8f9f7 245 * @brief Enables/disables the write protection.
<> 144:ef7eb2e8f9f7 246 *
<> 144:ef7eb2e8f9f7 247 * @param base SDRAM peripheral base address.
<> 144:ef7eb2e8f9f7 248 * @param block The block which is selected.
<> 144:ef7eb2e8f9f7 249 * @param enable True enable write protection, false disable write protection.
<> 144:ef7eb2e8f9f7 250 */
<> 144:ef7eb2e8f9f7 251 static inline void SDRAMC_EnableWriteProtect(SDRAM_Type *base, sdramc_block_selection_t block, bool enable)
<> 144:ef7eb2e8f9f7 252 {
<> 144:ef7eb2e8f9f7 253 if (enable)
<> 144:ef7eb2e8f9f7 254 {
<> 144:ef7eb2e8f9f7 255 base->BLOCK[block].CM |= SDRAM_CM_WP_MASK;
<> 144:ef7eb2e8f9f7 256 }
<> 144:ef7eb2e8f9f7 257 else
<> 144:ef7eb2e8f9f7 258 {
<> 144:ef7eb2e8f9f7 259 base->BLOCK[block].CM &= ~SDRAM_CM_WP_MASK;
<> 144:ef7eb2e8f9f7 260 }
<> 144:ef7eb2e8f9f7 261 }
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 /*!
<> 144:ef7eb2e8f9f7 264 * @brief Enables/disables the operation valid.
<> 144:ef7eb2e8f9f7 265 *
<> 144:ef7eb2e8f9f7 266 * @param base SDRAM peripheral base address.
<> 144:ef7eb2e8f9f7 267 * @param block The block which is selected.
<> 144:ef7eb2e8f9f7 268 * @param enable True enable the operation valid, false disable the operation valid.
<> 144:ef7eb2e8f9f7 269 */
<> 144:ef7eb2e8f9f7 270 static inline void SDRAMC_EnableOperateValid(SDRAM_Type *base, sdramc_block_selection_t block, bool enable)
<> 144:ef7eb2e8f9f7 271 {
<> 144:ef7eb2e8f9f7 272 if (enable)
<> 144:ef7eb2e8f9f7 273 {
<> 144:ef7eb2e8f9f7 274 base->BLOCK[block].CM |= SDRAM_CM_V_MASK;
<> 144:ef7eb2e8f9f7 275 }
<> 144:ef7eb2e8f9f7 276 else
<> 144:ef7eb2e8f9f7 277 {
<> 144:ef7eb2e8f9f7 278 base->BLOCK[block].CM &= ~SDRAM_CM_V_MASK;
<> 144:ef7eb2e8f9f7 279 }
<> 144:ef7eb2e8f9f7 280 }
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 /* @} */
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 #if defined(__cplusplus)
<> 144:ef7eb2e8f9f7 285 }
<> 144:ef7eb2e8f9f7 286 #endif
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 /*! @}*/
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 #endif /* _FSL_SDRAMC_H_*/