Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K66F/drivers/fsl_flexbus.c@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 144:ef7eb2e8f9f7 3 * All rights reserved.
<> 144:ef7eb2e8f9f7 4 *
<> 144:ef7eb2e8f9f7 5 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 6 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 144:ef7eb2e8f9f7 9 * of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 144:ef7eb2e8f9f7 12 * list of conditions and the following disclaimer in the documentation and/or
<> 144:ef7eb2e8f9f7 13 * other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 144:ef7eb2e8f9f7 16 * contributors may be used to endorse or promote products derived from this
<> 144:ef7eb2e8f9f7 17 * software without specific prior written permission.
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 29 */
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 #include "fsl_flexbus.h"
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 /*******************************************************************************
<> 144:ef7eb2e8f9f7 34 * Prototypes
<> 144:ef7eb2e8f9f7 35 ******************************************************************************/
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 /*!
<> 144:ef7eb2e8f9f7 38 * @brief Gets the instance from the base address
<> 144:ef7eb2e8f9f7 39 *
<> 144:ef7eb2e8f9f7 40 * @param base FLEXBUS peripheral base address
<> 144:ef7eb2e8f9f7 41 *
<> 144:ef7eb2e8f9f7 42 * @return The FLEXBUS instance
<> 144:ef7eb2e8f9f7 43 */
<> 144:ef7eb2e8f9f7 44 static uint32_t FLEXBUS_GetInstance(FB_Type *base);
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /*******************************************************************************
<> 144:ef7eb2e8f9f7 47 * Variables
<> 144:ef7eb2e8f9f7 48 ******************************************************************************/
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 /*! @brief Pointers to FLEXBUS bases for each instance. */
<> 144:ef7eb2e8f9f7 51 static FB_Type *const s_flexbusBases[] = FB_BASE_PTRS;
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /*! @brief Pointers to FLEXBUS clocks for each instance. */
<> 144:ef7eb2e8f9f7 54 static const clock_ip_name_t s_flexbusClocks[] = FLEXBUS_CLOCKS;
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 /*******************************************************************************
<> 144:ef7eb2e8f9f7 57 * Code
<> 144:ef7eb2e8f9f7 58 ******************************************************************************/
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 static uint32_t FLEXBUS_GetInstance(FB_Type *base)
<> 144:ef7eb2e8f9f7 61 {
<> 144:ef7eb2e8f9f7 62 uint32_t instance;
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 /* Find the instance index from base address mappings. */
<> 144:ef7eb2e8f9f7 65 for (instance = 0; instance < FSL_FEATURE_SOC_FB_COUNT; instance++)
<> 144:ef7eb2e8f9f7 66 {
<> 144:ef7eb2e8f9f7 67 if (s_flexbusBases[instance] == base)
<> 144:ef7eb2e8f9f7 68 {
<> 144:ef7eb2e8f9f7 69 break;
<> 144:ef7eb2e8f9f7 70 }
<> 144:ef7eb2e8f9f7 71 }
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 assert(instance < FSL_FEATURE_SOC_FB_COUNT);
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 return instance;
<> 144:ef7eb2e8f9f7 76 }
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 void FLEXBUS_Init(FB_Type *base, const flexbus_config_t *config)
<> 144:ef7eb2e8f9f7 79 {
<> 144:ef7eb2e8f9f7 80 assert(config != NULL);
<> 144:ef7eb2e8f9f7 81 assert(config->chip < FB_CSAR_COUNT);
<> 144:ef7eb2e8f9f7 82 assert(config->waitStates <= 0x3FU);
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 uint32_t chip = 0;
<> 144:ef7eb2e8f9f7 85 uint32_t reg_value = 0;
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 /* Ungate clock for FLEXBUS */
<> 144:ef7eb2e8f9f7 88 CLOCK_EnableClock(s_flexbusClocks[FLEXBUS_GetInstance(base)]);
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 /* Reset all the register to default state */
<> 144:ef7eb2e8f9f7 91 for (chip = 0; chip < FB_CSAR_COUNT; chip++)
<> 144:ef7eb2e8f9f7 92 {
<> 144:ef7eb2e8f9f7 93 /* Reset CSMR register, all chips not valid (disabled) */
<> 144:ef7eb2e8f9f7 94 base->CS[chip].CSMR = 0x0000U;
<> 144:ef7eb2e8f9f7 95 /* Set default base address */
<> 144:ef7eb2e8f9f7 96 base->CS[chip].CSAR &= (~FB_CSAR_BA_MASK);
<> 144:ef7eb2e8f9f7 97 /* Reset FB_CSCRx register */
<> 144:ef7eb2e8f9f7 98 base->CS[chip].CSCR = 0x0000U;
<> 144:ef7eb2e8f9f7 99 }
<> 144:ef7eb2e8f9f7 100 /* Set FB_CSPMCR register */
<> 144:ef7eb2e8f9f7 101 /* FlexBus signal group 1 multiplex control */
<> 144:ef7eb2e8f9f7 102 reg_value |= kFLEXBUS_MultiplexGroup1_FB_ALE << FB_CSPMCR_GROUP1_SHIFT;
<> 144:ef7eb2e8f9f7 103 /* FlexBus signal group 2 multiplex control */
<> 144:ef7eb2e8f9f7 104 reg_value |= kFLEXBUS_MultiplexGroup2_FB_CS4 << FB_CSPMCR_GROUP2_SHIFT;
<> 144:ef7eb2e8f9f7 105 /* FlexBus signal group 3 multiplex control */
<> 144:ef7eb2e8f9f7 106 reg_value |= kFLEXBUS_MultiplexGroup3_FB_CS5 << FB_CSPMCR_GROUP3_SHIFT;
<> 144:ef7eb2e8f9f7 107 /* FlexBus signal group 4 multiplex control */
<> 144:ef7eb2e8f9f7 108 reg_value |= kFLEXBUS_MultiplexGroup4_FB_TBST << FB_CSPMCR_GROUP4_SHIFT;
<> 144:ef7eb2e8f9f7 109 /* FlexBus signal group 5 multiplex control */
<> 144:ef7eb2e8f9f7 110 reg_value |= kFLEXBUS_MultiplexGroup5_FB_TA << FB_CSPMCR_GROUP5_SHIFT;
<> 144:ef7eb2e8f9f7 111 /* Write to CSPMCR register */
<> 144:ef7eb2e8f9f7 112 base->CSPMCR = reg_value;
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 /* Update chip value */
<> 144:ef7eb2e8f9f7 115 chip = config->chip;
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 /* Base address */
<> 144:ef7eb2e8f9f7 118 reg_value = config->chipBaseAddress;
<> 144:ef7eb2e8f9f7 119 /* Write to CSAR register */
<> 144:ef7eb2e8f9f7 120 base->CS[chip].CSAR = reg_value;
<> 144:ef7eb2e8f9f7 121 /* Chip-select validation */
<> 144:ef7eb2e8f9f7 122 reg_value = 0x1U << FB_CSMR_V_SHIFT;
<> 144:ef7eb2e8f9f7 123 /* Write protect */
<> 144:ef7eb2e8f9f7 124 reg_value |= (uint32_t)(config->writeProtect) << FB_CSMR_WP_SHIFT;
<> 144:ef7eb2e8f9f7 125 /* Base address mask */
<> 144:ef7eb2e8f9f7 126 reg_value |= config->chipBaseAddressMask << FB_CSMR_BAM_SHIFT;
<> 144:ef7eb2e8f9f7 127 /* Write to CSMR register */
<> 144:ef7eb2e8f9f7 128 base->CS[chip].CSMR = reg_value;
<> 144:ef7eb2e8f9f7 129 /* Burst write */
<> 144:ef7eb2e8f9f7 130 reg_value = (uint32_t)(config->burstWrite) << FB_CSCR_BSTW_SHIFT;
<> 144:ef7eb2e8f9f7 131 /* Burst read */
<> 144:ef7eb2e8f9f7 132 reg_value |= (uint32_t)(config->burstRead) << FB_CSCR_BSTR_SHIFT;
<> 144:ef7eb2e8f9f7 133 /* Byte-enable mode */
<> 144:ef7eb2e8f9f7 134 reg_value |= (uint32_t)(config->byteEnableMode) << FB_CSCR_BEM_SHIFT;
<> 144:ef7eb2e8f9f7 135 /* Port size */
<> 144:ef7eb2e8f9f7 136 reg_value |= (uint32_t)config->portSize << FB_CSCR_PS_SHIFT;
<> 144:ef7eb2e8f9f7 137 /* The internal transfer acknowledge for accesses */
<> 144:ef7eb2e8f9f7 138 reg_value |= (uint32_t)(config->autoAcknowledge) << FB_CSCR_AA_SHIFT;
<> 144:ef7eb2e8f9f7 139 /* Byte-Lane shift */
<> 144:ef7eb2e8f9f7 140 reg_value |= (uint32_t)config->byteLaneShift << FB_CSCR_BLS_SHIFT;
<> 144:ef7eb2e8f9f7 141 /* The number of wait states */
<> 144:ef7eb2e8f9f7 142 reg_value |= (uint32_t)config->waitStates << FB_CSCR_WS_SHIFT;
<> 144:ef7eb2e8f9f7 143 /* Write address hold or deselect */
<> 144:ef7eb2e8f9f7 144 reg_value |= (uint32_t)config->writeAddressHold << FB_CSCR_WRAH_SHIFT;
<> 144:ef7eb2e8f9f7 145 /* Read address hold or deselect */
<> 144:ef7eb2e8f9f7 146 reg_value |= (uint32_t)config->readAddressHold << FB_CSCR_RDAH_SHIFT;
<> 144:ef7eb2e8f9f7 147 /* Address setup */
<> 144:ef7eb2e8f9f7 148 reg_value |= (uint32_t)config->addressSetup << FB_CSCR_ASET_SHIFT;
<> 144:ef7eb2e8f9f7 149 /* Extended transfer start/extended address latch */
<> 144:ef7eb2e8f9f7 150 reg_value |= (uint32_t)(config->extendTransferAddress) << FB_CSCR_EXTS_SHIFT;
<> 144:ef7eb2e8f9f7 151 /* Secondary wait state */
<> 144:ef7eb2e8f9f7 152 reg_value |= (uint32_t)(config->secondaryWaitStates) << FB_CSCR_SWSEN_SHIFT;
<> 144:ef7eb2e8f9f7 153 /* Write to CSCR register */
<> 144:ef7eb2e8f9f7 154 base->CS[chip].CSCR = reg_value;
<> 144:ef7eb2e8f9f7 155 /* FlexBus signal group 1 multiplex control */
<> 144:ef7eb2e8f9f7 156 reg_value = (uint32_t)config->group1MultiplexControl << FB_CSPMCR_GROUP1_SHIFT;
<> 144:ef7eb2e8f9f7 157 /* FlexBus signal group 2 multiplex control */
<> 144:ef7eb2e8f9f7 158 reg_value |= (uint32_t)config->group2MultiplexControl << FB_CSPMCR_GROUP2_SHIFT;
<> 144:ef7eb2e8f9f7 159 /* FlexBus signal group 3 multiplex control */
<> 144:ef7eb2e8f9f7 160 reg_value |= (uint32_t)config->group3MultiplexControl << FB_CSPMCR_GROUP3_SHIFT;
<> 144:ef7eb2e8f9f7 161 /* FlexBus signal group 4 multiplex control */
<> 144:ef7eb2e8f9f7 162 reg_value |= (uint32_t)config->group4MultiplexControl << FB_CSPMCR_GROUP4_SHIFT;
<> 144:ef7eb2e8f9f7 163 /* FlexBus signal group 5 multiplex control */
<> 144:ef7eb2e8f9f7 164 reg_value |= (uint32_t)config->group5MultiplexControl << FB_CSPMCR_GROUP5_SHIFT;
<> 144:ef7eb2e8f9f7 165 /* Write to CSPMCR register */
<> 144:ef7eb2e8f9f7 166 base->CSPMCR = reg_value;
<> 144:ef7eb2e8f9f7 167 }
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 void FLEXBUS_Deinit(FB_Type *base)
<> 144:ef7eb2e8f9f7 170 {
<> 144:ef7eb2e8f9f7 171 /* Gate clock for FLEXBUS */
<> 144:ef7eb2e8f9f7 172 CLOCK_EnableClock(s_flexbusClocks[FLEXBUS_GetInstance(base)]);
<> 144:ef7eb2e8f9f7 173 }
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 void FLEXBUS_GetDefaultConfig(flexbus_config_t *config)
<> 144:ef7eb2e8f9f7 176 {
<> 144:ef7eb2e8f9f7 177 config->chip = 0; /* Chip 0 FlexBus for validation */
<> 144:ef7eb2e8f9f7 178 config->writeProtect = 0; /* Write accesses are allowed */
<> 144:ef7eb2e8f9f7 179 config->burstWrite = 0; /* Burst-Write disable */
<> 144:ef7eb2e8f9f7 180 config->burstRead = 0; /* Burst-Read disable */
<> 144:ef7eb2e8f9f7 181 config->byteEnableMode = 0; /* Byte-Enable mode is asserted for data write only */
<> 144:ef7eb2e8f9f7 182 config->autoAcknowledge = true; /* Auto-Acknowledge enable */
<> 144:ef7eb2e8f9f7 183 config->extendTransferAddress = 0; /* Extend transfer start/extend address latch disable */
<> 144:ef7eb2e8f9f7 184 config->secondaryWaitStates = 0; /* Secondary wait state disable */
<> 144:ef7eb2e8f9f7 185 config->byteLaneShift = kFLEXBUS_NotShifted; /* Byte-Lane shift disable */
<> 144:ef7eb2e8f9f7 186 config->writeAddressHold = kFLEXBUS_Hold1Cycle; /* Write address hold 1 cycles */
<> 144:ef7eb2e8f9f7 187 config->readAddressHold = kFLEXBUS_Hold1Or0Cycles; /* Read address hold 0 cycles */
<> 144:ef7eb2e8f9f7 188 config->addressSetup =
<> 144:ef7eb2e8f9f7 189 kFLEXBUS_FirstRisingEdge; /* Assert ~FB_CSn on the first rising clock edge after the address is asserted */
<> 144:ef7eb2e8f9f7 190 config->portSize = kFLEXBUS_1Byte; /* 1 byte port size of transfer */
<> 144:ef7eb2e8f9f7 191 config->group1MultiplexControl = kFLEXBUS_MultiplexGroup1_FB_ALE; /* FB_ALE */
<> 144:ef7eb2e8f9f7 192 config->group2MultiplexControl = kFLEXBUS_MultiplexGroup2_FB_CS4; /* FB_CS4 */
<> 144:ef7eb2e8f9f7 193 config->group3MultiplexControl = kFLEXBUS_MultiplexGroup3_FB_CS5; /* FB_CS5 */
<> 144:ef7eb2e8f9f7 194 config->group4MultiplexControl = kFLEXBUS_MultiplexGroup4_FB_TBST; /* FB_TBST */
<> 144:ef7eb2e8f9f7 195 config->group5MultiplexControl = kFLEXBUS_MultiplexGroup5_FB_TA; /* FB_TA */
<> 144:ef7eb2e8f9f7 196 }