Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/gic.c@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 2 * @file gic.c
<> 144:ef7eb2e8f9f7 3 * @brief Implementation of GIC functions declared in CMSIS Cortex-A9 Core Peripheral Access Layer Header File
<> 144:ef7eb2e8f9f7 4 * @version
<> 144:ef7eb2e8f9f7 5 * @date 19 Sept 2013
<> 144:ef7eb2e8f9f7 6 *
<> 144:ef7eb2e8f9f7 7 * @note
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 ******************************************************************************/
<> 144:ef7eb2e8f9f7 10 /* Copyright (c) 2011 - 2013 ARM LIMITED
<> 144:ef7eb2e8f9f7 11
<> 144:ef7eb2e8f9f7 12 All rights reserved.
<> 144:ef7eb2e8f9f7 13 Redistribution and use in source and binary forms, with or without
<> 144:ef7eb2e8f9f7 14 modification, are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 - Redistributions of source code must retain the above copyright
<> 144:ef7eb2e8f9f7 16 notice, this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 - Redistributions in binary form must reproduce the above copyright
<> 144:ef7eb2e8f9f7 18 notice, this list of conditions and the following disclaimer in the
<> 144:ef7eb2e8f9f7 19 documentation and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 - Neither the name of ARM nor the names of its contributors may be used
<> 144:ef7eb2e8f9f7 21 to endorse or promote products derived from this software without
<> 144:ef7eb2e8f9f7 22 specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 144:ef7eb2e8f9f7 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 144:ef7eb2e8f9f7 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 144:ef7eb2e8f9f7 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 144:ef7eb2e8f9f7 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 144:ef7eb2e8f9f7 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 144:ef7eb2e8f9f7 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 144:ef7eb2e8f9f7 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 144:ef7eb2e8f9f7 34 POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 35 ---------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 #include "MBRZA1H.h"
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 #define GICDistributor ((GICDistributor_Type *) Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE ) /*!< GIC Distributor configuration struct */
<> 144:ef7eb2e8f9f7 40 #define GICInterface ((GICInterface_Type *) Renesas_RZ_A1_GIC_INTERFACE_BASE ) /*!< GIC Interface configuration struct */
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 /* Globals for use of post-scatterloading code that must access GIC */
<> 144:ef7eb2e8f9f7 43 const uint32_t GICDistributor_BASE = Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE;
<> 144:ef7eb2e8f9f7 44 const uint32_t GICInterface_BASE = Renesas_RZ_A1_GIC_INTERFACE_BASE;
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 void GIC_EnableDistributor(void)
<> 144:ef7eb2e8f9f7 47 {
<> 144:ef7eb2e8f9f7 48 GICDistributor->ICDDCR |= 1; //enable distributor
<> 144:ef7eb2e8f9f7 49 }
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 void GIC_DisableDistributor(void)
<> 144:ef7eb2e8f9f7 52 {
<> 144:ef7eb2e8f9f7 53 GICDistributor->ICDDCR &=~1; //disable distributor
<> 144:ef7eb2e8f9f7 54 }
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 uint32_t GIC_DistributorInfo(void)
<> 144:ef7eb2e8f9f7 57 {
<> 144:ef7eb2e8f9f7 58 return (uint32_t)(GICDistributor->ICDICTR);
<> 144:ef7eb2e8f9f7 59 }
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 uint32_t GIC_DistributorImplementer(void)
<> 144:ef7eb2e8f9f7 62 {
<> 144:ef7eb2e8f9f7 63 return (uint32_t)(GICDistributor->ICDIIDR);
<> 144:ef7eb2e8f9f7 64 }
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target)
<> 144:ef7eb2e8f9f7 67 {
<> 144:ef7eb2e8f9f7 68 volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPTR[IRQn / 4]);
<> 144:ef7eb2e8f9f7 69 field += IRQn % 4;
<> 144:ef7eb2e8f9f7 70 *field = (uint8_t)cpu_target & 0xf;
<> 144:ef7eb2e8f9f7 71 }
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 void GIC_SetICDICFR (const uint32_t *ICDICFRn)
<> 144:ef7eb2e8f9f7 74 {
<> 144:ef7eb2e8f9f7 75 uint32_t i, num_irq;
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 //Get the maximum number of interrupts that the GIC supports
<> 144:ef7eb2e8f9f7 78 num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1);
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 for (i = 0; i < (num_irq/16); i++)
<> 144:ef7eb2e8f9f7 81 {
<> 144:ef7eb2e8f9f7 82 GICDistributor->ICDISPR[i] = *ICDICFRn++;
<> 144:ef7eb2e8f9f7 83 }
<> 144:ef7eb2e8f9f7 84 }
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 uint32_t GIC_GetTarget(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 87 {
<> 144:ef7eb2e8f9f7 88 volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPTR[IRQn / 4]);
<> 144:ef7eb2e8f9f7 89 field += IRQn % 4;
<> 144:ef7eb2e8f9f7 90 return ((uint32_t)*field & 0xf);
<> 144:ef7eb2e8f9f7 91 }
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 void GIC_EnableInterface(void)
<> 144:ef7eb2e8f9f7 94 {
<> 144:ef7eb2e8f9f7 95 GICInterface->ICCICR |= 1; //enable interface
<> 144:ef7eb2e8f9f7 96 }
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 void GIC_DisableInterface(void)
<> 144:ef7eb2e8f9f7 99 {
<> 144:ef7eb2e8f9f7 100 GICInterface->ICCICR &=~1; //disable distributor
<> 144:ef7eb2e8f9f7 101 }
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 IRQn_Type GIC_AcknowledgePending(void)
<> 144:ef7eb2e8f9f7 104 {
<> 144:ef7eb2e8f9f7 105 return (IRQn_Type)(GICInterface->ICCIAR);
<> 144:ef7eb2e8f9f7 106 }
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 void GIC_EndInterrupt(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 109 {
<> 144:ef7eb2e8f9f7 110 GICInterface->ICCEOIR = IRQn;
<> 144:ef7eb2e8f9f7 111 }
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 void GIC_EnableIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 114 {
<> 144:ef7eb2e8f9f7 115 GICDistributor->ICDISER[IRQn / 32] = 1 << (IRQn % 32);
<> 144:ef7eb2e8f9f7 116 }
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 void GIC_DisableIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 119 {
<> 144:ef7eb2e8f9f7 120 GICDistributor->ICDICER[IRQn / 32] = 1 << (IRQn % 32);
<> 144:ef7eb2e8f9f7 121 }
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 void GIC_SetPendingIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 124 {
<> 144:ef7eb2e8f9f7 125 GICDistributor->ICDISPR[IRQn / 32] = 1 << (IRQn % 32);
<> 144:ef7eb2e8f9f7 126 }
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 void GIC_ClearPendingIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 129 {
<> 144:ef7eb2e8f9f7 130 GICDistributor->ICDICPR[IRQn / 32] = 1 << (IRQn % 32);
<> 144:ef7eb2e8f9f7 131 }
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model)
<> 144:ef7eb2e8f9f7 134 {
<> 144:ef7eb2e8f9f7 135 volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDICFR[IRQn / 16]);
<> 144:ef7eb2e8f9f7 136 int bit_shift = (IRQn % 16)<<1;
<> 144:ef7eb2e8f9f7 137 uint8_t save_byte;
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 field += (bit_shift / 8);
<> 144:ef7eb2e8f9f7 140 bit_shift %= 8;
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 save_byte = *field;
<> 144:ef7eb2e8f9f7 143 save_byte &= ((uint8_t)~(3u << bit_shift));
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 *field = save_byte | ((uint8_t)((edge_level<<1) | model)<< bit_shift);
<> 144:ef7eb2e8f9f7 146 }
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
<> 144:ef7eb2e8f9f7 149 {
<> 144:ef7eb2e8f9f7 150 volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPR[IRQn / 4]);
<> 144:ef7eb2e8f9f7 151 field += (IRQn % 4);
<> 144:ef7eb2e8f9f7 152 *field = (uint8_t)priority;
<> 144:ef7eb2e8f9f7 153 }
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 uint32_t GIC_GetPriority(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 156 {
<> 144:ef7eb2e8f9f7 157 volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPR[IRQn / 4]);
<> 144:ef7eb2e8f9f7 158 field += (IRQn % 4);
<> 144:ef7eb2e8f9f7 159 return (uint32_t)*field;
<> 144:ef7eb2e8f9f7 160 }
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 void GIC_InterfacePriorityMask(uint32_t priority)
<> 144:ef7eb2e8f9f7 163 {
<> 144:ef7eb2e8f9f7 164 GICInterface->ICCPMR = priority & 0xff; //set priority mask
<> 144:ef7eb2e8f9f7 165 }
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 void GIC_SetBinaryPoint(uint32_t binary_point)
<> 144:ef7eb2e8f9f7 168 {
<> 144:ef7eb2e8f9f7 169 GICInterface->ICCBPR = binary_point & 0x07; //set binary point
<> 144:ef7eb2e8f9f7 170 }
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 uint32_t GIC_GetBinaryPoint(uint32_t binary_point)
<> 144:ef7eb2e8f9f7 173 {
<> 144:ef7eb2e8f9f7 174 return (uint32_t)GICInterface->ICCBPR;
<> 144:ef7eb2e8f9f7 175 }
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 uint32_t GIC_GetIRQStatus(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 178 {
<> 144:ef7eb2e8f9f7 179 uint32_t pending, active;
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 active = ((GICDistributor->ICDABR[IRQn / 32]) >> (IRQn % 32)) & 0x1;
<> 144:ef7eb2e8f9f7 182 pending =((GICDistributor->ICDISPR[IRQn / 32]) >> (IRQn % 32)) & 0x1;
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 return ((active<<1) | pending);
<> 144:ef7eb2e8f9f7 185 }
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list)
<> 144:ef7eb2e8f9f7 188 {
<> 144:ef7eb2e8f9f7 189 GICDistributor->ICDSGIR = ((filter_list & 0x3) << 24) | ((target_list & 0xff) << 16) | (IRQn & 0xf);
<> 144:ef7eb2e8f9f7 190 }
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 void GIC_DistInit(void)
<> 144:ef7eb2e8f9f7 193 {
<> 144:ef7eb2e8f9f7 194 //IRQn_Type i;
<> 144:ef7eb2e8f9f7 195 uint32_t i;
<> 144:ef7eb2e8f9f7 196 uint32_t num_irq = 0;
<> 144:ef7eb2e8f9f7 197 uint32_t priority_field;
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0,
<> 144:ef7eb2e8f9f7 200 //configuring all of the interrupts as Secure.
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 //Disable interrupt forwarding
<> 144:ef7eb2e8f9f7 203 GIC_DisableDistributor();
<> 144:ef7eb2e8f9f7 204 //Get the maximum number of interrupts that the GIC supports
<> 144:ef7eb2e8f9f7 205 num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1);
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 /* Priority level is implementation defined.
<> 144:ef7eb2e8f9f7 208 To determine the number of priority bits implemented write 0xFF to an ICDIPR
<> 144:ef7eb2e8f9f7 209 priority field and read back the value stored.*/
<> 144:ef7eb2e8f9f7 210 GIC_SetPriority((IRQn_Type)0, 0xff);
<> 144:ef7eb2e8f9f7 211 priority_field = GIC_GetPriority((IRQn_Type)0);
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 for (i = 32; i < num_irq; i++)
<> 144:ef7eb2e8f9f7 214 {
<> 144:ef7eb2e8f9f7 215 //Disable all SPI the interrupts
<> 144:ef7eb2e8f9f7 216 GIC_DisableIRQ((IRQn_Type)i);
<> 144:ef7eb2e8f9f7 217 //Set level-sensitive and N-N model
<> 144:ef7eb2e8f9f7 218 //GIC_SetLevelModel(i, 0, 0);
<> 144:ef7eb2e8f9f7 219 //Set priority
<> 144:ef7eb2e8f9f7 220 GIC_SetPriority((IRQn_Type)i, priority_field/2);
<> 144:ef7eb2e8f9f7 221 //Set target list to "all cpus"
<> 144:ef7eb2e8f9f7 222 GIC_SetTarget((IRQn_Type)i, 0xff);
<> 144:ef7eb2e8f9f7 223 }
<> 144:ef7eb2e8f9f7 224 /* Set level-edge and 1-N model */
<> 144:ef7eb2e8f9f7 225 /* GICDistributor->ICDICFR[ 0] is read only */
<> 144:ef7eb2e8f9f7 226 GICDistributor->ICDICFR[ 1] = 0x00000055;
<> 144:ef7eb2e8f9f7 227 GICDistributor->ICDICFR[ 2] = 0xFFFD5555;
<> 144:ef7eb2e8f9f7 228 GICDistributor->ICDICFR[ 3] = 0x555FFFFF;
<> 144:ef7eb2e8f9f7 229 GICDistributor->ICDICFR[ 4] = 0x55555555;
<> 144:ef7eb2e8f9f7 230 GICDistributor->ICDICFR[ 5] = 0x55555555;
<> 144:ef7eb2e8f9f7 231 GICDistributor->ICDICFR[ 6] = 0x55555555;
<> 144:ef7eb2e8f9f7 232 GICDistributor->ICDICFR[ 7] = 0x55555555;
<> 144:ef7eb2e8f9f7 233 GICDistributor->ICDICFR[ 8] = 0x5555F555;
<> 144:ef7eb2e8f9f7 234 GICDistributor->ICDICFR[ 9] = 0x55555555;
<> 144:ef7eb2e8f9f7 235 GICDistributor->ICDICFR[10] = 0x55555555;
<> 144:ef7eb2e8f9f7 236 GICDistributor->ICDICFR[11] = 0xF5555555;
<> 144:ef7eb2e8f9f7 237 GICDistributor->ICDICFR[12] = 0xF555F555;
<> 144:ef7eb2e8f9f7 238 GICDistributor->ICDICFR[13] = 0x5555F555;
<> 144:ef7eb2e8f9f7 239 GICDistributor->ICDICFR[14] = 0x55555555;
<> 144:ef7eb2e8f9f7 240 GICDistributor->ICDICFR[15] = 0x55555555;
<> 144:ef7eb2e8f9f7 241 GICDistributor->ICDICFR[16] = 0x55555555;
<> 144:ef7eb2e8f9f7 242 GICDistributor->ICDICFR[17] = 0xFD555555;
<> 144:ef7eb2e8f9f7 243 GICDistributor->ICDICFR[18] = 0x55555557;
<> 144:ef7eb2e8f9f7 244 GICDistributor->ICDICFR[19] = 0x55555555;
<> 144:ef7eb2e8f9f7 245 GICDistributor->ICDICFR[20] = 0xFFD55555;
<> 144:ef7eb2e8f9f7 246 GICDistributor->ICDICFR[21] = 0x5F55557F;
<> 144:ef7eb2e8f9f7 247 GICDistributor->ICDICFR[22] = 0xFD55555F;
<> 144:ef7eb2e8f9f7 248 GICDistributor->ICDICFR[23] = 0x55555557;
<> 144:ef7eb2e8f9f7 249 GICDistributor->ICDICFR[24] = 0x55555555;
<> 144:ef7eb2e8f9f7 250 GICDistributor->ICDICFR[25] = 0x55555555;
<> 144:ef7eb2e8f9f7 251 GICDistributor->ICDICFR[26] = 0x55555555;
<> 144:ef7eb2e8f9f7 252 GICDistributor->ICDICFR[27] = 0x55555555;
<> 144:ef7eb2e8f9f7 253 GICDistributor->ICDICFR[28] = 0x55555555;
<> 144:ef7eb2e8f9f7 254 GICDistributor->ICDICFR[29] = 0x55555555;
<> 144:ef7eb2e8f9f7 255 GICDistributor->ICDICFR[30] = 0x55555555;
<> 144:ef7eb2e8f9f7 256 GICDistributor->ICDICFR[31] = 0x55555555;
<> 144:ef7eb2e8f9f7 257 GICDistributor->ICDICFR[32] = 0x55555555;
<> 144:ef7eb2e8f9f7 258 GICDistributor->ICDICFR[33] = 0x55555555;
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 //Enable distributor
<> 144:ef7eb2e8f9f7 261 GIC_EnableDistributor();
<> 144:ef7eb2e8f9f7 262 }
<> 144:ef7eb2e8f9f7 263
<> 144:ef7eb2e8f9f7 264 void GIC_CPUInterfaceInit(void)
<> 144:ef7eb2e8f9f7 265 {
<> 144:ef7eb2e8f9f7 266 IRQn_Type i;
<> 144:ef7eb2e8f9f7 267 uint32_t priority_field;
<> 144:ef7eb2e8f9f7 268
<> 144:ef7eb2e8f9f7 269 //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0,
<> 144:ef7eb2e8f9f7 270 //configuring all of the interrupts as Secure.
<> 144:ef7eb2e8f9f7 271
<> 144:ef7eb2e8f9f7 272 //Disable interrupt forwarding
<> 144:ef7eb2e8f9f7 273 GIC_DisableInterface();
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275 /* Priority level is implementation defined.
<> 144:ef7eb2e8f9f7 276 To determine the number of priority bits implemented write 0xFF to an ICDIPR
<> 144:ef7eb2e8f9f7 277 priority field and read back the value stored.*/
<> 144:ef7eb2e8f9f7 278 GIC_SetPriority((IRQn_Type)0, 0xff);
<> 144:ef7eb2e8f9f7 279 priority_field = GIC_GetPriority((IRQn_Type)0);
<> 144:ef7eb2e8f9f7 280
<> 144:ef7eb2e8f9f7 281 //SGI and PPI
<> 144:ef7eb2e8f9f7 282 for (i = (IRQn_Type)0; i < 32; i++)
<> 144:ef7eb2e8f9f7 283 {
<> 144:ef7eb2e8f9f7 284 //Set level-sensitive and N-N model for PPI
<> 144:ef7eb2e8f9f7 285 //if(i > 15)
<> 144:ef7eb2e8f9f7 286 //GIC_SetLevelModel(i, 0, 0);
<> 144:ef7eb2e8f9f7 287 //Disable SGI and PPI interrupts
<> 144:ef7eb2e8f9f7 288 GIC_DisableIRQ(i);
<> 144:ef7eb2e8f9f7 289 //Set priority
<> 144:ef7eb2e8f9f7 290 GIC_SetPriority(i, priority_field/2);
<> 144:ef7eb2e8f9f7 291 }
<> 144:ef7eb2e8f9f7 292 //Enable interface
<> 144:ef7eb2e8f9f7 293 GIC_EnableInterface();
<> 144:ef7eb2e8f9f7 294 //Set binary point to 0
<> 144:ef7eb2e8f9f7 295 GIC_SetBinaryPoint(0);
<> 144:ef7eb2e8f9f7 296 //Set priority mask
<> 144:ef7eb2e8f9f7 297 GIC_InterfacePriorityMask(0xff);
<> 144:ef7eb2e8f9f7 298 }
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 void GIC_Enable(void)
<> 144:ef7eb2e8f9f7 301 {
<> 144:ef7eb2e8f9f7 302 GIC_DistInit();
<> 144:ef7eb2e8f9f7 303 GIC_CPUInterfaceInit(); //per CPU
<> 144:ef7eb2e8f9f7 304 }
<> 144:ef7eb2e8f9f7 305