Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_NXP/TARGET_LPC23XX/core_arm7.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (C) 2008-2009 ARM Limited. All rights reserved.
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * ARM7 version of CMSIS-like functionality - not advised for use outside mbed!
<> 144:ef7eb2e8f9f7 5 * based on core_cm3.h, V1.20
<> 144:ef7eb2e8f9f7 6 */
<> 144:ef7eb2e8f9f7 7
<> 144:ef7eb2e8f9f7 8 #ifndef __ARM7_CORE_H__
<> 144:ef7eb2e8f9f7 9 #define __ARM7_CORE_H__
<> 144:ef7eb2e8f9f7 10
<> 144:ef7eb2e8f9f7 11 #include "vector_defns.h"
<> 144:ef7eb2e8f9f7 12
<> 144:ef7eb2e8f9f7 13 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 14 extern "C" {
<> 144:ef7eb2e8f9f7 15 #endif
<> 144:ef7eb2e8f9f7 16
<> 144:ef7eb2e8f9f7 17 #define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */
<> 144:ef7eb2e8f9f7 18 #define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
<> 144:ef7eb2e8f9f7 19 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
<> 144:ef7eb2e8f9f7 20
<> 144:ef7eb2e8f9f7 21 #define __CORTEX_M (0x03) /*!< Cortex core */
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 /**
<> 144:ef7eb2e8f9f7 24 * Lint configuration \n
<> 144:ef7eb2e8f9f7 25 * ----------------------- \n
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * The following Lint messages will be suppressed and not shown: \n
<> 144:ef7eb2e8f9f7 28 * \n
<> 144:ef7eb2e8f9f7 29 * --- Error 10: --- \n
<> 144:ef7eb2e8f9f7 30 * register uint32_t __regBasePri __asm("basepri"); \n
<> 144:ef7eb2e8f9f7 31 * Error 10: Expecting ';' \n
<> 144:ef7eb2e8f9f7 32 * \n
<> 144:ef7eb2e8f9f7 33 * --- Error 530: --- \n
<> 144:ef7eb2e8f9f7 34 * return(__regBasePri); \n
<> 144:ef7eb2e8f9f7 35 * Warning 530: Symbol '__regBasePri' (line 264) not initialized \n
<> 144:ef7eb2e8f9f7 36 * \n
<> 144:ef7eb2e8f9f7 37 * --- Error 550: --- \n
<> 144:ef7eb2e8f9f7 38 * __regBasePri = (basePri & 0x1ff); \n
<> 144:ef7eb2e8f9f7 39 * } \n
<> 144:ef7eb2e8f9f7 40 * Warning 550: Symbol '__regBasePri' (line 271) not accessed \n
<> 144:ef7eb2e8f9f7 41 * \n
<> 144:ef7eb2e8f9f7 42 * --- Error 754: --- \n
<> 144:ef7eb2e8f9f7 43 * uint32_t RESERVED0[24]; \n
<> 144:ef7eb2e8f9f7 44 * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced \n
<> 144:ef7eb2e8f9f7 45 * \n
<> 144:ef7eb2e8f9f7 46 * --- Error 750: --- \n
<> 144:ef7eb2e8f9f7 47 * #define __CM3_CORE_H__ \n
<> 144:ef7eb2e8f9f7 48 * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n
<> 144:ef7eb2e8f9f7 49 * \n
<> 144:ef7eb2e8f9f7 50 * --- Error 528: --- \n
<> 144:ef7eb2e8f9f7 51 * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
<> 144:ef7eb2e8f9f7 52 * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n
<> 144:ef7eb2e8f9f7 53 * \n
<> 144:ef7eb2e8f9f7 54 * --- Error 751: --- \n
<> 144:ef7eb2e8f9f7 55 * } InterruptType_Type; \n
<> 144:ef7eb2e8f9f7 56 * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n
<> 144:ef7eb2e8f9f7 57 * \n
<> 144:ef7eb2e8f9f7 58 * \n
<> 144:ef7eb2e8f9f7 59 * Note: To re-enable a Message, insert a space before 'lint' * \n
<> 144:ef7eb2e8f9f7 60 *
<> 144:ef7eb2e8f9f7 61 */
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /*lint -save */
<> 144:ef7eb2e8f9f7 64 /*lint -e10 */
<> 144:ef7eb2e8f9f7 65 /*lint -e530 */
<> 144:ef7eb2e8f9f7 66 /*lint -e550 */
<> 144:ef7eb2e8f9f7 67 /*lint -e754 */
<> 144:ef7eb2e8f9f7 68 /*lint -e750 */
<> 144:ef7eb2e8f9f7 69 /*lint -e528 */
<> 144:ef7eb2e8f9f7 70 /*lint -e751 */
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 #include <stdint.h> /* Include standard types */
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 #if defined ( __CC_ARM )
<> 144:ef7eb2e8f9f7 75 /**
<> 144:ef7eb2e8f9f7 76 * @brief Return the Main Stack Pointer (current ARM7 stack)
<> 144:ef7eb2e8f9f7 77 *
<> 144:ef7eb2e8f9f7 78 * @param none
<> 144:ef7eb2e8f9f7 79 * @return uint32_t Main Stack Pointer
<> 144:ef7eb2e8f9f7 80 *
<> 144:ef7eb2e8f9f7 81 * Return the current value of the MSP (main stack pointer)
<> 144:ef7eb2e8f9f7 82 * Cortex processor register
<> 144:ef7eb2e8f9f7 83 */
<> 144:ef7eb2e8f9f7 84 extern uint32_t __get_MSP(void);
<> 144:ef7eb2e8f9f7 85 #endif
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 #if defined (__ICCARM__)
<> 144:ef7eb2e8f9f7 89 #include <intrinsics.h> /* IAR Intrinsics */
<> 144:ef7eb2e8f9f7 90 #endif
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 #ifndef __NVIC_PRIO_BITS
<> 144:ef7eb2e8f9f7 94 #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */
<> 144:ef7eb2e8f9f7 95 #endif
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 typedef struct
<> 144:ef7eb2e8f9f7 98 {
<> 144:ef7eb2e8f9f7 99 uint32_t IRQStatus;
<> 144:ef7eb2e8f9f7 100 uint32_t FIQStatus;
<> 144:ef7eb2e8f9f7 101 uint32_t RawIntr;
<> 144:ef7eb2e8f9f7 102 uint32_t IntSelect;
<> 144:ef7eb2e8f9f7 103 uint32_t IntEnable;
<> 144:ef7eb2e8f9f7 104 uint32_t IntEnClr;
<> 144:ef7eb2e8f9f7 105 uint32_t SoftInt;
<> 144:ef7eb2e8f9f7 106 uint32_t SoftIntClr;
<> 144:ef7eb2e8f9f7 107 uint32_t Protection;
<> 144:ef7eb2e8f9f7 108 uint32_t SWPriorityMask;
<> 144:ef7eb2e8f9f7 109 uint32_t RESERVED0[54];
<> 144:ef7eb2e8f9f7 110 uint32_t VectAddr[32];
<> 144:ef7eb2e8f9f7 111 uint32_t RESERVED1[32];
<> 144:ef7eb2e8f9f7 112 uint32_t VectPriority[32];
<> 144:ef7eb2e8f9f7 113 uint32_t RESERVED2[800];
<> 144:ef7eb2e8f9f7 114 uint32_t Address;
<> 144:ef7eb2e8f9f7 115 } NVIC_TypeDef;
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 #define NVIC_BASE (0xFFFFF000)
<> 144:ef7eb2e8f9f7 118 #define NVIC (( NVIC_TypeDef *) NVIC_BASE)
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 /**
<> 144:ef7eb2e8f9f7 123 * IO definitions
<> 144:ef7eb2e8f9f7 124 *
<> 144:ef7eb2e8f9f7 125 * define access restrictions to peripheral registers
<> 144:ef7eb2e8f9f7 126 */
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 129 #define __I volatile /*!< defines 'read only' permissions */
<> 144:ef7eb2e8f9f7 130 #else
<> 144:ef7eb2e8f9f7 131 #define __I volatile const /*!< defines 'read only' permissions */
<> 144:ef7eb2e8f9f7 132 #endif
<> 144:ef7eb2e8f9f7 133 #define __O volatile /*!< defines 'write only' permissions */
<> 144:ef7eb2e8f9f7 134 #define __IO volatile /*!< defines 'read / write' permissions */
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 #if defined ( __CC_ARM )
<> 144:ef7eb2e8f9f7 141 #define __ASM __asm /*!< asm keyword for ARM Compiler */
<> 144:ef7eb2e8f9f7 142 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 #elif defined ( __ICCARM__ )
<> 144:ef7eb2e8f9f7 145 #define __ASM __asm /*!< asm keyword for IAR Compiler */
<> 144:ef7eb2e8f9f7 146 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 #elif defined ( __GNUC__ )
<> 144:ef7eb2e8f9f7 149 #define __ASM __asm /*!< asm keyword for GNU Compiler */
<> 144:ef7eb2e8f9f7 150 #define __INLINE inline /*!< inline keyword for GNU Compiler */
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 #elif defined ( __TASKING__ )
<> 144:ef7eb2e8f9f7 153 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
<> 144:ef7eb2e8f9f7 154 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 #endif
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 /* ################### Compiler specific Intrinsics ########################### */
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
<> 144:ef7eb2e8f9f7 162 /* ARM armcc specific functions */
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 #define __enable_fault_irq __enable_fiq
<> 144:ef7eb2e8f9f7 165 #define __disable_fault_irq __disable_fiq
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 #define __NOP __nop
<> 144:ef7eb2e8f9f7 168 //#define __WFI __wfi
<> 144:ef7eb2e8f9f7 169 //#define __WFE __wfe
<> 144:ef7eb2e8f9f7 170 //#define __SEV __sev
<> 144:ef7eb2e8f9f7 171 //#define __ISB() __isb(0)
<> 144:ef7eb2e8f9f7 172 //#define __DSB() __dsb(0)
<> 144:ef7eb2e8f9f7 173 //#define __DMB() __dmb(0)
<> 144:ef7eb2e8f9f7 174 //#define __REV __rev
<> 144:ef7eb2e8f9f7 175 //#define __RBIT __rbit
<> 144:ef7eb2e8f9f7 176 #define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
<> 144:ef7eb2e8f9f7 177 #define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
<> 144:ef7eb2e8f9f7 178 #define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
<> 144:ef7eb2e8f9f7 179 #define __STREXB(value, ptr) __strex(value, ptr)
<> 144:ef7eb2e8f9f7 180 #define __STREXH(value, ptr) __strex(value, ptr)
<> 144:ef7eb2e8f9f7 181 #define __STREXW(value, ptr) __strex(value, ptr)
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 #define __disable_irq() unsigned tmp_IntEnable = LPC_VIC->IntEnable; \
<> 144:ef7eb2e8f9f7 184 LPC_VIC->IntEnClr = 0xffffffff
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 #define __enable_irq() LPC_VIC->IntEnable = tmp_IntEnable
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 #elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 #define __enable_irq __enable_interrupt /*!< global Interrupt enable */
<> 144:ef7eb2e8f9f7 191 #define __disable_irq __disable_interrupt /*!< global Interrupt disable */
<> 144:ef7eb2e8f9f7 192 #define __NOP __no_operation() /*!< no operation intrinsic in IAR Compiler */
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 static __INLINE void __enable_irq() {
<> 144:ef7eb2e8f9f7 197 unsigned long temp;
<> 144:ef7eb2e8f9f7 198 __asm__ __volatile__("mrs %0, cpsr\n"
<> 144:ef7eb2e8f9f7 199 "bic %0, %0, #0x80\n"
<> 144:ef7eb2e8f9f7 200 "msr cpsr_c, %0"
<> 144:ef7eb2e8f9f7 201 : "=r" (temp)
<> 144:ef7eb2e8f9f7 202 :
<> 144:ef7eb2e8f9f7 203 : "memory");
<> 144:ef7eb2e8f9f7 204 }
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 static __INLINE void __disable_irq() {
<> 144:ef7eb2e8f9f7 207 unsigned long old,temp;
<> 144:ef7eb2e8f9f7 208 __asm__ __volatile__("mrs %0, cpsr\n"
<> 144:ef7eb2e8f9f7 209 "orr %1, %0, #0xc0\n"
<> 144:ef7eb2e8f9f7 210 "msr cpsr_c, %1"
<> 144:ef7eb2e8f9f7 211 : "=r" (old), "=r" (temp)
<> 144:ef7eb2e8f9f7 212 :
<> 144:ef7eb2e8f9f7 213 : "memory");
<> 144:ef7eb2e8f9f7 214 // return (old & 0x80) == 0;
<> 144:ef7eb2e8f9f7 215 }
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 static __INLINE void __NOP() { __ASM volatile ("nop"); }
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 #elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
<> 144:ef7eb2e8f9f7 220 /* TASKING carm specific functions */
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 /*
<> 144:ef7eb2e8f9f7 223 * The CMSIS functions have been implemented as intrinsics in the compiler.
<> 144:ef7eb2e8f9f7 224 * Please use "carm -?i" to get an up to date list of all instrinsics,
<> 144:ef7eb2e8f9f7 225 * Including the CMSIS ones.
<> 144:ef7eb2e8f9f7 226 */
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 #endif
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 /**
<> 144:ef7eb2e8f9f7 232 * @brief Enable Interrupt in NVIC Interrupt Controller
<> 144:ef7eb2e8f9f7 233 *
<> 144:ef7eb2e8f9f7 234 * @param IRQn_Type IRQn specifies the interrupt number
<> 144:ef7eb2e8f9f7 235 * @return none
<> 144:ef7eb2e8f9f7 236 *
<> 144:ef7eb2e8f9f7 237 * Enable a device specific interupt in the NVIC interrupt controller.
<> 144:ef7eb2e8f9f7 238 * The interrupt number cannot be a negative value.
<> 144:ef7eb2e8f9f7 239 */
<> 144:ef7eb2e8f9f7 240 static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 241 {
<> 144:ef7eb2e8f9f7 242 NVIC->IntEnable = 1 << (uint32_t)IRQn;
<> 144:ef7eb2e8f9f7 243 }
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 /**
<> 144:ef7eb2e8f9f7 247 * @brief Disable the interrupt line for external interrupt specified
<> 144:ef7eb2e8f9f7 248 *
<> 144:ef7eb2e8f9f7 249 * @param IRQn_Type IRQn is the positive number of the external interrupt
<> 144:ef7eb2e8f9f7 250 * @return none
<> 144:ef7eb2e8f9f7 251 *
<> 144:ef7eb2e8f9f7 252 * Disable a device specific interupt in the NVIC interrupt controller.
<> 144:ef7eb2e8f9f7 253 * The interrupt number cannot be a negative value.
<> 144:ef7eb2e8f9f7 254 */
<> 144:ef7eb2e8f9f7 255 static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 256 {
<> 144:ef7eb2e8f9f7 257 NVIC->IntEnClr = 1 << (uint32_t)IRQn;
<> 144:ef7eb2e8f9f7 258 }
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 static __INLINE uint32_t __get_IPSR(void)
<> 144:ef7eb2e8f9f7 261 {
<> 144:ef7eb2e8f9f7 262 unsigned i;
<> 144:ef7eb2e8f9f7 263
<> 144:ef7eb2e8f9f7 264 for(i = 0; i < 32; i ++)
<> 144:ef7eb2e8f9f7 265 if(NVIC->Address == NVIC->VectAddr[i])
<> 144:ef7eb2e8f9f7 266 return i;
<> 144:ef7eb2e8f9f7 267 return 1; // 1 is an invalid entry in the interrupt table on LPC2368
<> 144:ef7eb2e8f9f7 268 }
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 271 }
<> 144:ef7eb2e8f9f7 272 #endif
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 #endif /* __ARM7_CORE_H__ */
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 /*lint -restore */