added prescaler for 16 bit pwm in LPC1347 target
Fork of mbed-dev by
targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TOOLCHAIN_IAR/TARGET_LPC11XX/startup_LPC11xx.S@147:ba84b7dc41a7, 2016-09-10 (annotated)
- Committer:
- JojoS
- Date:
- Sat Sep 10 15:32:04 2016 +0000
- Revision:
- 147:ba84b7dc41a7
- Parent:
- 144:ef7eb2e8f9f7
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /************************************************** |
<> | 144:ef7eb2e8f9f7 | 2 | * |
<> | 144:ef7eb2e8f9f7 | 3 | * Part one of the system initialization code, contains low-level |
<> | 144:ef7eb2e8f9f7 | 4 | * initialization, plain thumb variant. |
<> | 144:ef7eb2e8f9f7 | 5 | * |
<> | 144:ef7eb2e8f9f7 | 6 | * Copyright 2012 IAR Systems. All rights reserved. |
<> | 144:ef7eb2e8f9f7 | 7 | * |
<> | 144:ef7eb2e8f9f7 | 8 | * $Revision: 28 $ |
<> | 144:ef7eb2e8f9f7 | 9 | * |
<> | 144:ef7eb2e8f9f7 | 10 | **************************************************/ |
<> | 144:ef7eb2e8f9f7 | 11 | |
<> | 144:ef7eb2e8f9f7 | 12 | ; |
<> | 144:ef7eb2e8f9f7 | 13 | ; The modules in this file are included in the libraries, and may be replaced |
<> | 144:ef7eb2e8f9f7 | 14 | ; by any user-defined modules that define the PUBLIC symbol _program_start or |
<> | 144:ef7eb2e8f9f7 | 15 | ; a user defined start symbol. |
<> | 144:ef7eb2e8f9f7 | 16 | ; To override the cstartup defined in the library, simply add your modified |
<> | 144:ef7eb2e8f9f7 | 17 | ; version to the workbench project. |
<> | 144:ef7eb2e8f9f7 | 18 | ; |
<> | 144:ef7eb2e8f9f7 | 19 | ; The vector table is normally located at address 0. |
<> | 144:ef7eb2e8f9f7 | 20 | ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. |
<> | 144:ef7eb2e8f9f7 | 21 | ; The name "__vector_table" has special meaning for C-SPY: |
<> | 144:ef7eb2e8f9f7 | 22 | ; it is where the SP start value is found, and the NVIC vector |
<> | 144:ef7eb2e8f9f7 | 23 | ; table register (VTOR) is initialized to this address if != 0. |
<> | 144:ef7eb2e8f9f7 | 24 | ; |
<> | 144:ef7eb2e8f9f7 | 25 | ; Cortex-M version |
<> | 144:ef7eb2e8f9f7 | 26 | ; |
<> | 144:ef7eb2e8f9f7 | 27 | |
<> | 144:ef7eb2e8f9f7 | 28 | MODULE ?cstartup |
<> | 144:ef7eb2e8f9f7 | 29 | |
<> | 144:ef7eb2e8f9f7 | 30 | ;; Forward declaration of sections. |
<> | 144:ef7eb2e8f9f7 | 31 | SECTION CSTACK:DATA:NOROOT(3) |
<> | 144:ef7eb2e8f9f7 | 32 | |
<> | 144:ef7eb2e8f9f7 | 33 | SECTION .intvec:CODE:NOROOT(2) |
<> | 144:ef7eb2e8f9f7 | 34 | |
<> | 144:ef7eb2e8f9f7 | 35 | EXTERN __iar_program_start |
<> | 144:ef7eb2e8f9f7 | 36 | EXTERN SystemInit |
<> | 144:ef7eb2e8f9f7 | 37 | |
<> | 144:ef7eb2e8f9f7 | 38 | PUBLIC __vector_table |
<> | 144:ef7eb2e8f9f7 | 39 | PUBLIC __vector_table_0x1c |
<> | 144:ef7eb2e8f9f7 | 40 | DATA |
<> | 144:ef7eb2e8f9f7 | 41 | |
<> | 144:ef7eb2e8f9f7 | 42 | |
<> | 144:ef7eb2e8f9f7 | 43 | __vector_table |
<> | 144:ef7eb2e8f9f7 | 44 | DCD sfe(CSTACK) ; Top of Stack |
<> | 144:ef7eb2e8f9f7 | 45 | DCD Reset_Handler ; Reset Handler |
<> | 144:ef7eb2e8f9f7 | 46 | DCD NMI_Handler ; NMI Handler |
<> | 144:ef7eb2e8f9f7 | 47 | DCD HardFault_Handler ; Hard Fault Handler |
<> | 144:ef7eb2e8f9f7 | 48 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 49 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 50 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 51 | __vector_table_0x1c |
<> | 144:ef7eb2e8f9f7 | 52 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 53 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 54 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 55 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 56 | DCD SVC_Handler ; SVCall Handler |
<> | 144:ef7eb2e8f9f7 | 57 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 58 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 59 | DCD PendSV_Handler ; PendSV Handler |
<> | 144:ef7eb2e8f9f7 | 60 | DCD SysTick_Handler ; SysTick Handler |
<> | 144:ef7eb2e8f9f7 | 61 | |
<> | 144:ef7eb2e8f9f7 | 62 | ; External Interrupts |
<> | 144:ef7eb2e8f9f7 | 63 | DCD SLWU_INT0_IRQHandler ; Start logic wake-up interrupt 0 |
<> | 144:ef7eb2e8f9f7 | 64 | DCD SLWU_INT1_IRQHandler ; Start logic wake-up interrupt 1 |
<> | 144:ef7eb2e8f9f7 | 65 | DCD SLWU_INT2_IRQHandler ; Start logic wake-up interrupt 2 |
<> | 144:ef7eb2e8f9f7 | 66 | DCD SLWU_INT3_IRQHandler ; Start logic wake-up interrupt 3 |
<> | 144:ef7eb2e8f9f7 | 67 | DCD SLWU_INT4_IRQHandler ; Start logic wake-up interrupt 4 |
<> | 144:ef7eb2e8f9f7 | 68 | DCD SLWU_INT5_IRQHandler ; Start logic wake-up interrupt 5 |
<> | 144:ef7eb2e8f9f7 | 69 | DCD SLWU_INT6_IRQHandler ; Start logic wake-up interrupt 6 |
<> | 144:ef7eb2e8f9f7 | 70 | DCD SLWU_INT7_IRQHandler ; Start logic wake-up interrupt 7 |
<> | 144:ef7eb2e8f9f7 | 71 | DCD SLWU_INT8_IRQHandler ; Start logic wake-up interrupt 8 |
<> | 144:ef7eb2e8f9f7 | 72 | DCD SLWU_INT9_IRQHandler ; Start logic wake-up interrupt 9 |
<> | 144:ef7eb2e8f9f7 | 73 | DCD SLWU_INT10_IRQHandler ; Start logic wake-up interrupt 10 |
<> | 144:ef7eb2e8f9f7 | 74 | DCD SLWU_INT11_IRQHandler ; Start logic wake-up interrupt 11 |
<> | 144:ef7eb2e8f9f7 | 75 | DCD SLWU_INT12_IRQHandler ; Start logic wake-up interrupt 12 |
<> | 144:ef7eb2e8f9f7 | 76 | DCD C_CAN_IRQHandler ; C_CAN |
<> | 144:ef7eb2e8f9f7 | 77 | DCD SSP1_IRQHandler ; SSP1 |
<> | 144:ef7eb2e8f9f7 | 78 | DCD I2C_IRQHandler ; I2C |
<> | 144:ef7eb2e8f9f7 | 79 | DCD TIMER16_0_IRQHandler ; 16-bit Timer0 |
<> | 144:ef7eb2e8f9f7 | 80 | DCD TIMER16_1_IRQHandler ; 16-bit Timer1 |
<> | 144:ef7eb2e8f9f7 | 81 | DCD TIMER32_0_IRQHandler ; 32-bit Timer0 |
<> | 144:ef7eb2e8f9f7 | 82 | DCD TIMER32_1_IRQHandler ; 32-bit Timer1 |
<> | 144:ef7eb2e8f9f7 | 83 | DCD SSP0_IRQHandler ; SSP0 |
<> | 144:ef7eb2e8f9f7 | 84 | DCD UART_IRQHandler ; UART |
<> | 144:ef7eb2e8f9f7 | 85 | DCD Reserved_IRQHandler ; Reserved |
<> | 144:ef7eb2e8f9f7 | 86 | DCD Reserved_IRQHandler ; Reserved |
<> | 144:ef7eb2e8f9f7 | 87 | DCD ADC_IRQHandler ; A/D Converter |
<> | 144:ef7eb2e8f9f7 | 88 | DCD WDT_IRQHandler ; Watchdog timer |
<> | 144:ef7eb2e8f9f7 | 89 | DCD BOD_IRQHandler ; Brown Out Detect |
<> | 144:ef7eb2e8f9f7 | 90 | DCD Reserved_IRQHandler ; Reserved |
<> | 144:ef7eb2e8f9f7 | 91 | DCD PIO_3_IRQHandler ; GPIO interrupt status of port 3 |
<> | 144:ef7eb2e8f9f7 | 92 | DCD PIO_2_IRQHandler ; GPIO interrupt status of port 2 |
<> | 144:ef7eb2e8f9f7 | 93 | DCD PIO_1_IRQHandler ; GPIO interrupt status of port 1 |
<> | 144:ef7eb2e8f9f7 | 94 | DCD PIO_0_IRQHandler ; GPIO interrupt status of port 0 |
<> | 144:ef7eb2e8f9f7 | 95 | |
<> | 144:ef7eb2e8f9f7 | 96 | ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space |
<> | 144:ef7eb2e8f9f7 | 97 | |
<> | 144:ef7eb2e8f9f7 | 98 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 99 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 100 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 101 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 102 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 103 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 104 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 105 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 106 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 107 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 108 | |
<> | 144:ef7eb2e8f9f7 | 109 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 110 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 111 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 112 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 113 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 114 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 115 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 116 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 117 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 118 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 119 | |
<> | 144:ef7eb2e8f9f7 | 120 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 121 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 122 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 123 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 124 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 125 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 126 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 127 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 128 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 129 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 130 | |
<> | 144:ef7eb2e8f9f7 | 131 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 132 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 133 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 134 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 135 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 136 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 137 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 138 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 139 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 140 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 141 | |
<> | 144:ef7eb2e8f9f7 | 142 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 143 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 144 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 145 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 146 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 147 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 148 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 149 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 150 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 151 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 152 | |
<> | 144:ef7eb2e8f9f7 | 153 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 154 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 155 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 156 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 157 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 158 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 159 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 160 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 161 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 162 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 163 | |
<> | 144:ef7eb2e8f9f7 | 164 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 165 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 166 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 167 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 168 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 169 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 170 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 171 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 172 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 173 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 174 | |
<> | 144:ef7eb2e8f9f7 | 175 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 176 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 177 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 178 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 179 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 180 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 181 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 182 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 183 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 184 | DCD 0xFFFFFFFF ; Datafill |
<> | 144:ef7eb2e8f9f7 | 185 | |
<> | 144:ef7eb2e8f9f7 | 186 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
<> | 144:ef7eb2e8f9f7 | 187 | ;; |
<> | 144:ef7eb2e8f9f7 | 188 | ;; Default interrupt handlers. |
<> | 144:ef7eb2e8f9f7 | 189 | ;; |
<> | 144:ef7eb2e8f9f7 | 190 | THUMB |
<> | 144:ef7eb2e8f9f7 | 191 | PUBWEAK Reset_Handler |
<> | 144:ef7eb2e8f9f7 | 192 | SECTION .text:CODE:NOROOT:REORDER(2) |
<> | 144:ef7eb2e8f9f7 | 193 | Reset_Handler |
<> | 144:ef7eb2e8f9f7 | 194 | LDR R0, =SystemInit |
<> | 144:ef7eb2e8f9f7 | 195 | BLX R0 |
<> | 144:ef7eb2e8f9f7 | 196 | LDR R0, =__iar_program_start |
<> | 144:ef7eb2e8f9f7 | 197 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 198 | |
<> | 144:ef7eb2e8f9f7 | 199 | PUBWEAK NMI_Handler |
<> | 144:ef7eb2e8f9f7 | 200 | PUBWEAK HardFault_Handler |
<> | 144:ef7eb2e8f9f7 | 201 | PUBWEAK SVC_Handler |
<> | 144:ef7eb2e8f9f7 | 202 | PUBWEAK PendSV_Handler |
<> | 144:ef7eb2e8f9f7 | 203 | PUBWEAK SysTick_Handler |
<> | 144:ef7eb2e8f9f7 | 204 | PUBWEAK Reserved_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 205 | PUBWEAK SLWU_INT0_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 206 | PUBWEAK SLWU_INT1_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 207 | PUBWEAK SLWU_INT2_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 208 | PUBWEAK SLWU_INT3_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 209 | PUBWEAK SLWU_INT4_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 210 | PUBWEAK SLWU_INT5_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 211 | PUBWEAK SLWU_INT6_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 212 | PUBWEAK SLWU_INT7_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 213 | PUBWEAK SLWU_INT8_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 214 | PUBWEAK SLWU_INT9_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 215 | PUBWEAK SLWU_INT10_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 216 | PUBWEAK SLWU_INT11_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 217 | PUBWEAK SLWU_INT12_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 218 | PUBWEAK C_CAN_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 219 | PUBWEAK SSP1_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 220 | PUBWEAK I2C_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 221 | PUBWEAK TIMER16_0_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 222 | PUBWEAK TIMER16_1_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 223 | PUBWEAK TIMER32_0_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 224 | PUBWEAK TIMER32_1_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 225 | PUBWEAK SSP0_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 226 | PUBWEAK UART_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 227 | PUBWEAK ADC_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 228 | PUBWEAK WDT_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 229 | PUBWEAK BOD_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 230 | PUBWEAK PIO_3_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 231 | PUBWEAK PIO_2_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 232 | PUBWEAK PIO_1_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 233 | PUBWEAK PIO_0_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 234 | |
<> | 144:ef7eb2e8f9f7 | 235 | SECTION .text:CODE:REORDER:NOROOT(1) |
<> | 144:ef7eb2e8f9f7 | 236 | THUMB |
<> | 144:ef7eb2e8f9f7 | 237 | |
<> | 144:ef7eb2e8f9f7 | 238 | NMI_Handler |
<> | 144:ef7eb2e8f9f7 | 239 | HardFault_Handler |
<> | 144:ef7eb2e8f9f7 | 240 | SVC_Handler |
<> | 144:ef7eb2e8f9f7 | 241 | PendSV_Handler |
<> | 144:ef7eb2e8f9f7 | 242 | SysTick_Handler |
<> | 144:ef7eb2e8f9f7 | 243 | Reserved_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 244 | SLWU_INT0_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 245 | SLWU_INT1_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 246 | SLWU_INT2_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 247 | SLWU_INT3_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 248 | SLWU_INT4_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 249 | SLWU_INT5_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 250 | SLWU_INT6_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 251 | SLWU_INT7_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 252 | SLWU_INT8_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 253 | SLWU_INT9_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 254 | SLWU_INT10_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 255 | SLWU_INT11_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 256 | SLWU_INT12_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 257 | C_CAN_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 258 | SSP1_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 259 | I2C_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 260 | TIMER16_0_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 261 | TIMER16_1_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 262 | TIMER32_0_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 263 | TIMER32_1_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 264 | SSP0_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 265 | UART_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 266 | ADC_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 267 | WDT_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 268 | BOD_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 269 | PIO_3_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 270 | PIO_2_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 271 | PIO_1_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 272 | PIO_0_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 273 | Default_Handler |
<> | 144:ef7eb2e8f9f7 | 274 | B Default_Handler |
<> | 144:ef7eb2e8f9f7 | 275 | |
<> | 144:ef7eb2e8f9f7 | 276 | SECTION .crp:CODE:ROOT(2) |
<> | 144:ef7eb2e8f9f7 | 277 | DATA |
<> | 144:ef7eb2e8f9f7 | 278 | /* Code Read Protection |
<> | 144:ef7eb2e8f9f7 | 279 | NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode |
<> | 144:ef7eb2e8f9f7 | 280 | CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300. |
<> | 144:ef7eb2e8f9f7 | 281 | - Copy RAM to flash command can not write to Sector 0. |
<> | 144:ef7eb2e8f9f7 | 282 | - Erase command can erase Sector 0 only when all sectors |
<> | 144:ef7eb2e8f9f7 | 283 | are selected for erase. |
<> | 144:ef7eb2e8f9f7 | 284 | - Compare command is disabled. |
<> | 144:ef7eb2e8f9f7 | 285 | - Read Memory command is disabled. |
<> | 144:ef7eb2e8f9f7 | 286 | CRP2 0x87654321 - Read Memory is disabled. |
<> | 144:ef7eb2e8f9f7 | 287 | - Write to RAM is disabled. |
<> | 144:ef7eb2e8f9f7 | 288 | - "Go" command is disabled. |
<> | 144:ef7eb2e8f9f7 | 289 | - Copy RAM to flash is disabled. |
<> | 144:ef7eb2e8f9f7 | 290 | - Compare is disabled. |
<> | 144:ef7eb2e8f9f7 | 291 | CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry |
<> | 144:ef7eb2e8f9f7 | 292 | by pulling PIO0_1 LOW is disabled if a valid user code is |
<> | 144:ef7eb2e8f9f7 | 293 | present in flash sector 0. |
<> | 144:ef7eb2e8f9f7 | 294 | Caution: If CRP3 is selected, no future factory testing can be |
<> | 144:ef7eb2e8f9f7 | 295 | performed on the device. |
<> | 144:ef7eb2e8f9f7 | 296 | */ |
<> | 144:ef7eb2e8f9f7 | 297 | DCD 0xFFFFFFFF |
<> | 144:ef7eb2e8f9f7 | 298 | |
<> | 144:ef7eb2e8f9f7 | 299 | END |