Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/system_MK64F12.c@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 ** ###################################################################
<> 144:ef7eb2e8f9f7 3 ** Processors: MK64FN1M0VDC12
<> 144:ef7eb2e8f9f7 4 ** MK64FN1M0VLL12
<> 144:ef7eb2e8f9f7 5 ** MK64FN1M0VLQ12
<> 144:ef7eb2e8f9f7 6 ** MK64FN1M0VMD12
<> 144:ef7eb2e8f9f7 7 ** MK64FX512VDC12
<> 144:ef7eb2e8f9f7 8 ** MK64FX512VLL12
<> 144:ef7eb2e8f9f7 9 ** MK64FX512VLQ12
<> 144:ef7eb2e8f9f7 10 ** MK64FX512VMD12
<> 144:ef7eb2e8f9f7 11 **
<> 144:ef7eb2e8f9f7 12 ** Compilers: Keil ARM C/C++ Compiler
<> 144:ef7eb2e8f9f7 13 ** Freescale C/C++ for Embedded ARM
<> 144:ef7eb2e8f9f7 14 ** GNU C Compiler
<> 144:ef7eb2e8f9f7 15 ** IAR ANSI C/C++ Compiler for ARM
<> 144:ef7eb2e8f9f7 16 **
<> 144:ef7eb2e8f9f7 17 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
<> 144:ef7eb2e8f9f7 18 ** Version: rev. 2.8, 2015-02-19
<> 144:ef7eb2e8f9f7 19 ** Build: b151216
<> 144:ef7eb2e8f9f7 20 **
<> 144:ef7eb2e8f9f7 21 ** Abstract:
<> 144:ef7eb2e8f9f7 22 ** Provides a system configuration function and a global variable that
<> 144:ef7eb2e8f9f7 23 ** contains the system frequency. It configures the device and initializes
<> 144:ef7eb2e8f9f7 24 ** the oscillator (PLL) that is part of the microcontroller device.
<> 144:ef7eb2e8f9f7 25 **
<> 144:ef7eb2e8f9f7 26 ** Copyright (c) 2015 Freescale Semiconductor, Inc.
<> 144:ef7eb2e8f9f7 27 ** All rights reserved.
<> 144:ef7eb2e8f9f7 28 **
<> 144:ef7eb2e8f9f7 29 ** Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 30 ** are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 31 **
<> 144:ef7eb2e8f9f7 32 ** o Redistributions of source code must retain the above copyright notice, this list
<> 144:ef7eb2e8f9f7 33 ** of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 34 **
<> 144:ef7eb2e8f9f7 35 ** o Redistributions in binary form must reproduce the above copyright notice, this
<> 144:ef7eb2e8f9f7 36 ** list of conditions and the following disclaimer in the documentation and/or
<> 144:ef7eb2e8f9f7 37 ** other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 38 **
<> 144:ef7eb2e8f9f7 39 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 144:ef7eb2e8f9f7 40 ** contributors may be used to endorse or promote products derived from this
<> 144:ef7eb2e8f9f7 41 ** software without specific prior written permission.
<> 144:ef7eb2e8f9f7 42 **
<> 144:ef7eb2e8f9f7 43 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 44 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 45 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 46 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 47 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 48 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 49 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 50 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 51 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 52 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 53 **
<> 144:ef7eb2e8f9f7 54 ** http: www.freescale.com
<> 144:ef7eb2e8f9f7 55 ** mail: support@freescale.com
<> 144:ef7eb2e8f9f7 56 **
<> 144:ef7eb2e8f9f7 57 ** Revisions:
<> 144:ef7eb2e8f9f7 58 ** - rev. 1.0 (2013-08-12)
<> 144:ef7eb2e8f9f7 59 ** Initial version.
<> 144:ef7eb2e8f9f7 60 ** - rev. 2.0 (2013-10-29)
<> 144:ef7eb2e8f9f7 61 ** Register accessor macros added to the memory map.
<> 144:ef7eb2e8f9f7 62 ** Symbols for Processor Expert memory map compatibility added to the memory map.
<> 144:ef7eb2e8f9f7 63 ** Startup file for gcc has been updated according to CMSIS 3.2.
<> 144:ef7eb2e8f9f7 64 ** System initialization updated.
<> 144:ef7eb2e8f9f7 65 ** MCG - registers updated.
<> 144:ef7eb2e8f9f7 66 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
<> 144:ef7eb2e8f9f7 67 ** - rev. 2.1 (2013-10-30)
<> 144:ef7eb2e8f9f7 68 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
<> 144:ef7eb2e8f9f7 69 ** - rev. 2.2 (2013-12-09)
<> 144:ef7eb2e8f9f7 70 ** DMA - EARS register removed.
<> 144:ef7eb2e8f9f7 71 ** AIPS0, AIPS1 - MPRA register updated.
<> 144:ef7eb2e8f9f7 72 ** - rev. 2.3 (2014-01-24)
<> 144:ef7eb2e8f9f7 73 ** Update according to reference manual rev. 2
<> 144:ef7eb2e8f9f7 74 ** ENET, MCG, MCM, SIM, USB - registers updated
<> 144:ef7eb2e8f9f7 75 ** - rev. 2.4 (2014-02-10)
<> 144:ef7eb2e8f9f7 76 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
<> 144:ef7eb2e8f9f7 77 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
<> 144:ef7eb2e8f9f7 78 ** - rev. 2.5 (2014-02-10)
<> 144:ef7eb2e8f9f7 79 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
<> 144:ef7eb2e8f9f7 80 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
<> 144:ef7eb2e8f9f7 81 ** Module access macro module_BASES replaced by module_BASE_PTRS.
<> 144:ef7eb2e8f9f7 82 ** - rev. 2.6 (2014-08-28)
<> 144:ef7eb2e8f9f7 83 ** Update of system files - default clock configuration changed.
<> 144:ef7eb2e8f9f7 84 ** Update of startup files - possibility to override DefaultISR added.
<> 144:ef7eb2e8f9f7 85 ** - rev. 2.7 (2014-10-14)
<> 144:ef7eb2e8f9f7 86 ** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
<> 144:ef7eb2e8f9f7 87 ** - rev. 2.8 (2015-02-19)
<> 144:ef7eb2e8f9f7 88 ** Renamed interrupt vector LLW to LLWU.
<> 144:ef7eb2e8f9f7 89 **
<> 144:ef7eb2e8f9f7 90 ** ###################################################################
<> 144:ef7eb2e8f9f7 91 */
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 /*!
<> 144:ef7eb2e8f9f7 94 * @file MK64F12
<> 144:ef7eb2e8f9f7 95 * @version 2.8
<> 144:ef7eb2e8f9f7 96 * @date 2015-02-19
<> 144:ef7eb2e8f9f7 97 * @brief Device specific configuration file for MK64F12 (implementation file)
<> 144:ef7eb2e8f9f7 98 *
<> 144:ef7eb2e8f9f7 99 * Provides a system configuration function and a global variable that contains
<> 144:ef7eb2e8f9f7 100 * the system frequency. It configures the device and initializes the oscillator
<> 144:ef7eb2e8f9f7 101 * (PLL) that is part of the microcontroller device.
<> 144:ef7eb2e8f9f7 102 */
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 #include <stdint.h>
<> 144:ef7eb2e8f9f7 105 #include "fsl_device_registers.h"
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 110 -- Core clock
<> 144:ef7eb2e8f9f7 111 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 116 -- SystemInit()
<> 144:ef7eb2e8f9f7 117 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 void SystemInit (void) {
<> 144:ef7eb2e8f9f7 120 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
<> 144:ef7eb2e8f9f7 121 SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
<> 144:ef7eb2e8f9f7 122 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
<> 144:ef7eb2e8f9f7 123 #if (DISABLE_WDOG)
<> 144:ef7eb2e8f9f7 124 /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
<> 144:ef7eb2e8f9f7 125 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
<> 144:ef7eb2e8f9f7 126 /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
<> 144:ef7eb2e8f9f7 127 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
<> 144:ef7eb2e8f9f7 128 /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
<> 144:ef7eb2e8f9f7 129 WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
<> 144:ef7eb2e8f9f7 130 WDOG_STCTRLH_WAITEN_MASK |
<> 144:ef7eb2e8f9f7 131 WDOG_STCTRLH_STOPEN_MASK |
<> 144:ef7eb2e8f9f7 132 WDOG_STCTRLH_ALLOWUPDATE_MASK |
<> 144:ef7eb2e8f9f7 133 WDOG_STCTRLH_CLKSRC_MASK |
<> 144:ef7eb2e8f9f7 134 0x0100U;
<> 144:ef7eb2e8f9f7 135 #endif /* (DISABLE_WDOG) */
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 }
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 140 -- SystemCoreClockUpdate()
<> 144:ef7eb2e8f9f7 141 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 void SystemCoreClockUpdate (void) {
<> 144:ef7eb2e8f9f7 144 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
<> 144:ef7eb2e8f9f7 145 uint16_t Divider;
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
<> 144:ef7eb2e8f9f7 148 /* Output of FLL or PLL is selected */
<> 144:ef7eb2e8f9f7 149 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
<> 144:ef7eb2e8f9f7 150 /* FLL is selected */
<> 144:ef7eb2e8f9f7 151 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
<> 144:ef7eb2e8f9f7 152 /* External reference clock is selected */
<> 144:ef7eb2e8f9f7 153 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
<> 144:ef7eb2e8f9f7 154 case 0x00U:
<> 144:ef7eb2e8f9f7 155 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
<> 144:ef7eb2e8f9f7 156 break;
<> 144:ef7eb2e8f9f7 157 case 0x01U:
<> 144:ef7eb2e8f9f7 158 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
<> 144:ef7eb2e8f9f7 159 break;
<> 144:ef7eb2e8f9f7 160 case 0x02U:
<> 144:ef7eb2e8f9f7 161 default:
<> 144:ef7eb2e8f9f7 162 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
<> 144:ef7eb2e8f9f7 163 break;
<> 144:ef7eb2e8f9f7 164 }
<> 144:ef7eb2e8f9f7 165 if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
<> 144:ef7eb2e8f9f7 166 switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
<> 144:ef7eb2e8f9f7 167 case 0x38U:
<> 144:ef7eb2e8f9f7 168 Divider = 1536U;
<> 144:ef7eb2e8f9f7 169 break;
<> 144:ef7eb2e8f9f7 170 case 0x30U:
<> 144:ef7eb2e8f9f7 171 Divider = 1280U;
<> 144:ef7eb2e8f9f7 172 break;
<> 144:ef7eb2e8f9f7 173 default:
<> 144:ef7eb2e8f9f7 174 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
<> 144:ef7eb2e8f9f7 175 break;
<> 144:ef7eb2e8f9f7 176 }
<> 144:ef7eb2e8f9f7 177 } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
<> 144:ef7eb2e8f9f7 178 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
<> 144:ef7eb2e8f9f7 179 }
<> 144:ef7eb2e8f9f7 180 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
<> 144:ef7eb2e8f9f7 181 } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
<> 144:ef7eb2e8f9f7 182 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
<> 144:ef7eb2e8f9f7 183 } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
<> 144:ef7eb2e8f9f7 184 /* Select correct multiplier to calculate the MCG output clock */
<> 144:ef7eb2e8f9f7 185 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
<> 144:ef7eb2e8f9f7 186 case 0x00U:
<> 144:ef7eb2e8f9f7 187 MCGOUTClock *= 640U;
<> 144:ef7eb2e8f9f7 188 break;
<> 144:ef7eb2e8f9f7 189 case 0x20U:
<> 144:ef7eb2e8f9f7 190 MCGOUTClock *= 1280U;
<> 144:ef7eb2e8f9f7 191 break;
<> 144:ef7eb2e8f9f7 192 case 0x40U:
<> 144:ef7eb2e8f9f7 193 MCGOUTClock *= 1920U;
<> 144:ef7eb2e8f9f7 194 break;
<> 144:ef7eb2e8f9f7 195 case 0x60U:
<> 144:ef7eb2e8f9f7 196 MCGOUTClock *= 2560U;
<> 144:ef7eb2e8f9f7 197 break;
<> 144:ef7eb2e8f9f7 198 case 0x80U:
<> 144:ef7eb2e8f9f7 199 MCGOUTClock *= 732U;
<> 144:ef7eb2e8f9f7 200 break;
<> 144:ef7eb2e8f9f7 201 case 0xA0U:
<> 144:ef7eb2e8f9f7 202 MCGOUTClock *= 1464U;
<> 144:ef7eb2e8f9f7 203 break;
<> 144:ef7eb2e8f9f7 204 case 0xC0U:
<> 144:ef7eb2e8f9f7 205 MCGOUTClock *= 2197U;
<> 144:ef7eb2e8f9f7 206 break;
<> 144:ef7eb2e8f9f7 207 case 0xE0U:
<> 144:ef7eb2e8f9f7 208 MCGOUTClock *= 2929U;
<> 144:ef7eb2e8f9f7 209 break;
<> 144:ef7eb2e8f9f7 210 default:
<> 144:ef7eb2e8f9f7 211 break;
<> 144:ef7eb2e8f9f7 212 }
<> 144:ef7eb2e8f9f7 213 } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
<> 144:ef7eb2e8f9f7 214 /* PLL is selected */
<> 144:ef7eb2e8f9f7 215 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U);
<> 144:ef7eb2e8f9f7 216 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
<> 144:ef7eb2e8f9f7 217 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U);
<> 144:ef7eb2e8f9f7 218 MCGOUTClock *= Divider; /* Calculate the MCG output clock */
<> 144:ef7eb2e8f9f7 219 } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
<> 144:ef7eb2e8f9f7 220 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
<> 144:ef7eb2e8f9f7 221 /* Internal reference clock is selected */
<> 144:ef7eb2e8f9f7 222 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
<> 144:ef7eb2e8f9f7 223 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
<> 144:ef7eb2e8f9f7 224 } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
<> 144:ef7eb2e8f9f7 225 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
<> 144:ef7eb2e8f9f7 226 MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
<> 144:ef7eb2e8f9f7 227 } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
<> 144:ef7eb2e8f9f7 228 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
<> 144:ef7eb2e8f9f7 229 /* External reference clock is selected */
<> 144:ef7eb2e8f9f7 230 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
<> 144:ef7eb2e8f9f7 231 case 0x00U:
<> 144:ef7eb2e8f9f7 232 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
<> 144:ef7eb2e8f9f7 233 break;
<> 144:ef7eb2e8f9f7 234 case 0x01U:
<> 144:ef7eb2e8f9f7 235 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
<> 144:ef7eb2e8f9f7 236 break;
<> 144:ef7eb2e8f9f7 237 case 0x02U:
<> 144:ef7eb2e8f9f7 238 default:
<> 144:ef7eb2e8f9f7 239 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
<> 144:ef7eb2e8f9f7 240 break;
<> 144:ef7eb2e8f9f7 241 }
<> 144:ef7eb2e8f9f7 242 } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
<> 144:ef7eb2e8f9f7 243 /* Reserved value */
<> 144:ef7eb2e8f9f7 244 return;
<> 144:ef7eb2e8f9f7 245 } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
<> 144:ef7eb2e8f9f7 246 SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
<> 144:ef7eb2e8f9f7 247 }