Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/system_MKL26Z4.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 ** ###################################################################
<> 144:ef7eb2e8f9f7 3 ** Processors: MKL26Z128CAL4
<> 144:ef7eb2e8f9f7 4 ** MKL26Z128VFM4
<> 144:ef7eb2e8f9f7 5 ** MKL26Z64VFM4
<> 144:ef7eb2e8f9f7 6 ** MKL26Z32VM4
<> 144:ef7eb2e8f9f7 7 ** MKL26Z128VFT4
<> 144:ef7eb2e8f9f7 8 ** MKL26Z64VFT4
<> 144:ef7eb2e8f9f7 9 ** MKL26Z32VFT4
<> 144:ef7eb2e8f9f7 10 ** MKL26Z128VLH4
<> 144:ef7eb2e8f9f7 11 ** MKL26Z64VLH4
<> 144:ef7eb2e8f9f7 12 ** MKL26Z32VLH4
<> 144:ef7eb2e8f9f7 13 ** MKL26Z256VLH4
<> 144:ef7eb2e8f9f7 14 ** MKL26Z256VLL4
<> 144:ef7eb2e8f9f7 15 ** MKL26Z128VLL4
<> 144:ef7eb2e8f9f7 16 ** MKL26Z256VMC4
<> 144:ef7eb2e8f9f7 17 ** MKL26Z128VMC4
<> 144:ef7eb2e8f9f7 18 ** MKL26Z256VMP4
<> 144:ef7eb2e8f9f7 19 **
<> 144:ef7eb2e8f9f7 20 ** Compilers: Keil ARM C/C++ Compiler
<> 144:ef7eb2e8f9f7 21 ** Freescale C/C++ for Embedded ARM
<> 144:ef7eb2e8f9f7 22 ** GNU C Compiler
<> 144:ef7eb2e8f9f7 23 ** GNU C Compiler - CodeSourcery Sourcery G++
<> 144:ef7eb2e8f9f7 24 ** IAR ANSI C/C++ Compiler for ARM
<> 144:ef7eb2e8f9f7 25 **
<> 144:ef7eb2e8f9f7 26 ** Reference manuals: KL26P121M48SF4RM Rev. 3.2, October 2013
<> 144:ef7eb2e8f9f7 27 ** KL26P121M48SF4RM, Rev.2, Dec 2012
<> 144:ef7eb2e8f9f7 28 **
<> 144:ef7eb2e8f9f7 29 ** Version: rev. 1.7, 2015-01-13
<> 144:ef7eb2e8f9f7 30 ** Build: b150129
<> 144:ef7eb2e8f9f7 31 **
<> 144:ef7eb2e8f9f7 32 ** Abstract:
<> 144:ef7eb2e8f9f7 33 ** Provides a system configuration function and a global variable that
<> 144:ef7eb2e8f9f7 34 ** contains the system frequency. It configures the device and initializes
<> 144:ef7eb2e8f9f7 35 ** the oscillator (PLL) that is part of the microcontroller device.
<> 144:ef7eb2e8f9f7 36 **
<> 144:ef7eb2e8f9f7 37 ** Copyright (c) 2015 Freescale Semiconductor, Inc.
<> 144:ef7eb2e8f9f7 38 ** All rights reserved.
<> 144:ef7eb2e8f9f7 39 **
<> 144:ef7eb2e8f9f7 40 ** Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 41 ** are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 42 **
<> 144:ef7eb2e8f9f7 43 ** o Redistributions of source code must retain the above copyright notice, this list
<> 144:ef7eb2e8f9f7 44 ** of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 45 **
<> 144:ef7eb2e8f9f7 46 ** o Redistributions in binary form must reproduce the above copyright notice, this
<> 144:ef7eb2e8f9f7 47 ** list of conditions and the following disclaimer in the documentation and/or
<> 144:ef7eb2e8f9f7 48 ** other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 49 **
<> 144:ef7eb2e8f9f7 50 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 144:ef7eb2e8f9f7 51 ** contributors may be used to endorse or promote products derived from this
<> 144:ef7eb2e8f9f7 52 ** software without specific prior written permission.
<> 144:ef7eb2e8f9f7 53 **
<> 144:ef7eb2e8f9f7 54 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 55 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 56 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 57 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 58 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 59 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 60 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 61 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 62 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 63 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 64 **
<> 144:ef7eb2e8f9f7 65 ** http: www.freescale.com
<> 144:ef7eb2e8f9f7 66 ** mail: support@freescale.com
<> 144:ef7eb2e8f9f7 67 **
<> 144:ef7eb2e8f9f7 68 ** Revisions:
<> 144:ef7eb2e8f9f7 69 ** - rev. 1.0 (2012-12-12)
<> 144:ef7eb2e8f9f7 70 ** Initial version.
<> 144:ef7eb2e8f9f7 71 ** - rev. 1.1 (2013-04-05)
<> 144:ef7eb2e8f9f7 72 ** Changed start of doxygen comment.
<> 144:ef7eb2e8f9f7 73 ** - rev. 1.2 (2013-04-12)
<> 144:ef7eb2e8f9f7 74 ** SystemInit function fixed for clock configuration 1.
<> 144:ef7eb2e8f9f7 75 ** Name of the interrupt num. 31 updated to reflect proper function.
<> 144:ef7eb2e8f9f7 76 ** - rev. 1.3 (2014-05-27)
<> 144:ef7eb2e8f9f7 77 ** Updated to Kinetis SDK support standard.
<> 144:ef7eb2e8f9f7 78 ** MCG OSC clock select supported (MCG_C7[OSCSEL]).
<> 144:ef7eb2e8f9f7 79 ** - rev. 1.4 (2014-07-25)
<> 144:ef7eb2e8f9f7 80 ** System initialization updated:
<> 144:ef7eb2e8f9f7 81 ** - Prefix added to the system initialization parameterization constants to avoid name conflicts..
<> 144:ef7eb2e8f9f7 82 ** - VLLSx wake-up recovery added.
<> 144:ef7eb2e8f9f7 83 ** - Delay of 1 ms added to SystemInit() to ensure stable FLL output in FEI and FEE MCG modes.
<> 144:ef7eb2e8f9f7 84 ** - rev. 1.5 (2014-08-28)
<> 144:ef7eb2e8f9f7 85 ** Update of system files - default clock configuration changed, fix of OSC initialization.
<> 144:ef7eb2e8f9f7 86 ** Update of startup files - possibility to override DefaultISR added.
<> 144:ef7eb2e8f9f7 87 ** - rev. 1.6 (2014-10-14)
<> 144:ef7eb2e8f9f7 88 ** Renamed interrupt vector LPTimer to LPTMR0
<> 144:ef7eb2e8f9f7 89 ** - rev. 1.7 (2015-01-13)
<> 144:ef7eb2e8f9f7 90 ** Update of the copyright.
<> 144:ef7eb2e8f9f7 91 **
<> 144:ef7eb2e8f9f7 92 ** ###################################################################
<> 144:ef7eb2e8f9f7 93 */
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 /*!
<> 144:ef7eb2e8f9f7 96 * @file MKL26Z4
<> 144:ef7eb2e8f9f7 97 * @version 1.7
<> 144:ef7eb2e8f9f7 98 * @date 2015-01-13
<> 144:ef7eb2e8f9f7 99 * @brief Device specific configuration file for MKL26Z4 (header file)
<> 144:ef7eb2e8f9f7 100 *
<> 144:ef7eb2e8f9f7 101 * Provides a system configuration function and a global variable that contains
<> 144:ef7eb2e8f9f7 102 * the system frequency. It configures the device and initializes the oscillator
<> 144:ef7eb2e8f9f7 103 * (PLL) that is part of the microcontroller device.
<> 144:ef7eb2e8f9f7 104 */
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 #ifndef SYSTEM_MKL26Z4_H_
<> 144:ef7eb2e8f9f7 107 #define SYSTEM_MKL26Z4_H_ /**< Symbol preventing repeated inclusion */
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 110 extern "C" {
<> 144:ef7eb2e8f9f7 111 #endif
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 #include <stdint.h>
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 #ifndef DISABLE_WDOG
<> 144:ef7eb2e8f9f7 117 #define DISABLE_WDOG 1
<> 144:ef7eb2e8f9f7 118 #endif
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120 #define ACK_ISOLATION 1
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 #ifndef RTC_CLKIN_USED
<> 144:ef7eb2e8f9f7 123 #define RTC_CLKIN_USED 1
<> 144:ef7eb2e8f9f7 124 #endif
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 /* MCG mode constants */
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 #define MCG_MODE_FEI 0U
<> 144:ef7eb2e8f9f7 130 #define MCG_MODE_FBI 1U
<> 144:ef7eb2e8f9f7 131 #define MCG_MODE_BLPI 2U
<> 144:ef7eb2e8f9f7 132 #define MCG_MODE_FEE 3U
<> 144:ef7eb2e8f9f7 133 #define MCG_MODE_FBE 4U
<> 144:ef7eb2e8f9f7 134 #define MCG_MODE_BLPE 5U
<> 144:ef7eb2e8f9f7 135 #define MCG_MODE_PBE 6U
<> 144:ef7eb2e8f9f7 136 #define MCG_MODE_PEE 7U
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 /* Predefined clock setups
<> 144:ef7eb2e8f9f7 139 0 ... Default part configuration
<> 144:ef7eb2e8f9f7 140 Multipurpose Clock Generator (MCG) in FEI mode.
<> 144:ef7eb2e8f9f7 141 Reference clock source for MCG module: Slow internal reference clock
<> 144:ef7eb2e8f9f7 142 Core clock = 20.97152MHz
<> 144:ef7eb2e8f9f7 143 Bus clock = 20.97152MHz
<> 144:ef7eb2e8f9f7 144 1 ... Maximum achievable clock frequency configuration
<> 144:ef7eb2e8f9f7 145 Multipurpose Clock Generator (MCG) in PEE mode.
<> 144:ef7eb2e8f9f7 146 Reference clock source for MCG module: System oscillator reference clock
<> 144:ef7eb2e8f9f7 147 Core clock = 48MHz
<> 144:ef7eb2e8f9f7 148 Bus clock = 24MHz
<> 144:ef7eb2e8f9f7 149 2 ... Chip internally clocked, ready for Very Low Power Run mode
<> 144:ef7eb2e8f9f7 150 Multipurpose Clock Generator (MCG) in BLPI mode.
<> 144:ef7eb2e8f9f7 151 Reference clock source for MCG module: Fast internal reference clock
<> 144:ef7eb2e8f9f7 152 Core clock = 4MHz
<> 144:ef7eb2e8f9f7 153 Bus clock = 0.8MHz
<> 144:ef7eb2e8f9f7 154 3 ... Chip externally clocked, ready for Very Low Power Run mode
<> 144:ef7eb2e8f9f7 155 Multipurpose Clock Generator (MCG) in BLPE mode.
<> 144:ef7eb2e8f9f7 156 Reference clock source for MCG module: System oscillator reference clock
<> 144:ef7eb2e8f9f7 157 Core clock = 4MHz
<> 144:ef7eb2e8f9f7 158 Bus clock = 1MHz
<> 144:ef7eb2e8f9f7 159 4 ... USB clock setup
<> 144:ef7eb2e8f9f7 160 Multipurpose Clock Generator (MCG) in PEE mode.
<> 144:ef7eb2e8f9f7 161 Reference clock source for MCG module: System oscillator reference clock
<> 144:ef7eb2e8f9f7 162 Core clock = 48MHz
<> 144:ef7eb2e8f9f7 163 Bus clock = 24MHz
<> 144:ef7eb2e8f9f7 164 */
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 /* Define clock source values */
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 #define CPU_XTAL_CLK_HZ 8000000U /* Value of the external crystal or oscillator clock frequency of the system oscillator (OSC) in Hz */
<> 144:ef7eb2e8f9f7 169 #define CPU_INT_SLOW_CLK_HZ 32768U /* Value of the slow internal oscillator clock frequency in Hz */
<> 144:ef7eb2e8f9f7 170 #define CPU_INT_FAST_CLK_HZ 4000000U /* Value of the fast internal oscillator clock frequency in Hz */
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 /* RTC oscillator setting */
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 /* Low power mode enable */
<> 144:ef7eb2e8f9f7 175 /* SMC_PMPROT: AVLP=1,ALLS=1,AVLLS=1 */
<> 144:ef7eb2e8f9f7 176 #define SYSTEM_SMC_PMPROT_VALUE 0x2AU /* SMC_PMPROT */
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 /* Internal reference clock trim */
<> 144:ef7eb2e8f9f7 179 /* #undef SLOW_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
<> 144:ef7eb2e8f9f7 180 /* #undef SLOW_FINE_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
<> 144:ef7eb2e8f9f7 181 /* #undef FAST_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
<> 144:ef7eb2e8f9f7 182 /* #undef FAST_FINE_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 #ifdef CLOCK_SETUP
<> 144:ef7eb2e8f9f7 185 #if (CLOCK_SETUP == 0)
<> 144:ef7eb2e8f9f7 186 #define DEFAULT_SYSTEM_CLOCK 20971520U /* Default System clock value */
<> 144:ef7eb2e8f9f7 187 #define MCG_MODE MCG_MODE_FEI /* Clock generator mode */
<> 144:ef7eb2e8f9f7 188 /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
<> 144:ef7eb2e8f9f7 189 #define SYSTEM_MCG_C1_VALUE 0x06U /* MCG_C1 */
<> 144:ef7eb2e8f9f7 190 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
<> 144:ef7eb2e8f9f7 191 #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
<> 144:ef7eb2e8f9f7 192 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
<> 144:ef7eb2e8f9f7 193 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
<> 144:ef7eb2e8f9f7 194 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
<> 144:ef7eb2e8f9f7 195 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
<> 144:ef7eb2e8f9f7 196 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
<> 144:ef7eb2e8f9f7 197 #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
<> 144:ef7eb2e8f9f7 198 /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
<> 144:ef7eb2e8f9f7 199 #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
<> 144:ef7eb2e8f9f7 200 /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
<> 144:ef7eb2e8f9f7 201 #define SYSTEM_OSC0_CR_VALUE 0x80U /* OSC0_CR */
<> 144:ef7eb2e8f9f7 202 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
<> 144:ef7eb2e8f9f7 203 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
<> 144:ef7eb2e8f9f7 204 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=0 */
<> 144:ef7eb2e8f9f7 205 #define SYSTEM_SIM_CLKDIV1_VALUE 0x00U /* SIM_CLKDIV1 */
<> 144:ef7eb2e8f9f7 206 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=3 */
<> 144:ef7eb2e8f9f7 207 #define SYSTEM_SIM_SOPT1_VALUE 0x000C0000U /* SIM_SOPT1 */
<> 144:ef7eb2e8f9f7 208 /* SIM_SOPT2: UART0SRC=0,TPMSRC=1,USBSRC=0,PLLFLLSEL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
<> 144:ef7eb2e8f9f7 209 #define SYSTEM_SIM_SOPT2_VALUE 0x01000000U /* SIM_SOPT2 */
<> 144:ef7eb2e8f9f7 210 #elif (CLOCK_SETUP == 1)
<> 144:ef7eb2e8f9f7 211 #define DEFAULT_SYSTEM_CLOCK 48000000U /* Default System clock value */
<> 144:ef7eb2e8f9f7 212 #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
<> 144:ef7eb2e8f9f7 213 /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
<> 144:ef7eb2e8f9f7 214 #define SYSTEM_MCG_C1_VALUE 0x1AU /* MCG_C1 */
<> 144:ef7eb2e8f9f7 215 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
<> 144:ef7eb2e8f9f7 216 #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
<> 144:ef7eb2e8f9f7 217 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
<> 144:ef7eb2e8f9f7 218 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
<> 144:ef7eb2e8f9f7 219 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
<> 144:ef7eb2e8f9f7 220 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
<> 144:ef7eb2e8f9f7 221 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=3 */
<> 144:ef7eb2e8f9f7 222 #define SYSTEM_MCG_C5_VALUE 0x03U /* MCG_C5 */
<> 144:ef7eb2e8f9f7 223 /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */
<> 144:ef7eb2e8f9f7 224 #define SYSTEM_MCG_C6_VALUE 0x40U /* MCG_C6 */
<> 144:ef7eb2e8f9f7 225 /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
<> 144:ef7eb2e8f9f7 226 #define SYSTEM_OSC0_CR_VALUE 0x80U /* OSC0_CR */
<> 144:ef7eb2e8f9f7 227 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
<> 144:ef7eb2e8f9f7 228 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
<> 144:ef7eb2e8f9f7 229 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */
<> 144:ef7eb2e8f9f7 230 #define SYSTEM_SIM_CLKDIV1_VALUE 0x00010000U /* SIM_CLKDIV1 */
<> 144:ef7eb2e8f9f7 231 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=3 */
<> 144:ef7eb2e8f9f7 232 #define SYSTEM_SIM_SOPT1_VALUE 0x000C0000U /* SIM_SOPT1 */
<> 144:ef7eb2e8f9f7 233 /* SIM_SOPT2: UART0SRC=0,TPMSRC=1,USBSRC=0,PLLFLLSEL=1,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
<> 144:ef7eb2e8f9f7 234 #define SYSTEM_SIM_SOPT2_VALUE 0x01010000U /* SIM_SOPT2 */
<> 144:ef7eb2e8f9f7 235 #elif (CLOCK_SETUP == 2)
<> 144:ef7eb2e8f9f7 236 #define DEFAULT_SYSTEM_CLOCK 4000000U /* Default System clock value */
<> 144:ef7eb2e8f9f7 237 #define MCG_MODE MCG_MODE_BLPI /* Clock generator mode */
<> 144:ef7eb2e8f9f7 238 /* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
<> 144:ef7eb2e8f9f7 239 #define SYSTEM_MCG_C1_VALUE 0x46U /* MCG_C1 */
<> 144:ef7eb2e8f9f7 240 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE0=2,HGO0=0,EREFS0=1,LP=1,IRCS=1 */
<> 144:ef7eb2e8f9f7 241 #define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */
<> 144:ef7eb2e8f9f7 242 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
<> 144:ef7eb2e8f9f7 243 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
<> 144:ef7eb2e8f9f7 244 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
<> 144:ef7eb2e8f9f7 245 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
<> 144:ef7eb2e8f9f7 246 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
<> 144:ef7eb2e8f9f7 247 #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
<> 144:ef7eb2e8f9f7 248 /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
<> 144:ef7eb2e8f9f7 249 #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
<> 144:ef7eb2e8f9f7 250 /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
<> 144:ef7eb2e8f9f7 251 #define SYSTEM_OSC0_CR_VALUE 0x80U /* OSC0_CR */
<> 144:ef7eb2e8f9f7 252 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
<> 144:ef7eb2e8f9f7 253 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
<> 144:ef7eb2e8f9f7 254 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=4 */
<> 144:ef7eb2e8f9f7 255 #define SYSTEM_SIM_CLKDIV1_VALUE 0x00040000U /* SIM_CLKDIV1 */
<> 144:ef7eb2e8f9f7 256 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=3 */
<> 144:ef7eb2e8f9f7 257 #define SYSTEM_SIM_SOPT1_VALUE 0x000C0000U /* SIM_SOPT1 */
<> 144:ef7eb2e8f9f7 258 /* SIM_SOPT2: UART0SRC=0,TPMSRC=2,USBSRC=0,PLLFLLSEL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
<> 144:ef7eb2e8f9f7 259 #define SYSTEM_SIM_SOPT2_VALUE 0x02000000U /* SIM_SOPT2 */
<> 144:ef7eb2e8f9f7 260 #elif (CLOCK_SETUP == 3)
<> 144:ef7eb2e8f9f7 261 #define DEFAULT_SYSTEM_CLOCK 4000000U /* Default System clock value */
<> 144:ef7eb2e8f9f7 262 #define MCG_MODE MCG_MODE_BLPE /* Clock generator mode */
<> 144:ef7eb2e8f9f7 263 /* MCG_C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
<> 144:ef7eb2e8f9f7 264 #define SYSTEM_MCG_C1_VALUE 0x9AU /* MCG_C1 */
<> 144:ef7eb2e8f9f7 265 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE0=2,HGO0=0,EREFS0=1,LP=1,IRCS=1 */
<> 144:ef7eb2e8f9f7 266 #define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */
<> 144:ef7eb2e8f9f7 267 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
<> 144:ef7eb2e8f9f7 268 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
<> 144:ef7eb2e8f9f7 269 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
<> 144:ef7eb2e8f9f7 270 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
<> 144:ef7eb2e8f9f7 271 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
<> 144:ef7eb2e8f9f7 272 #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
<> 144:ef7eb2e8f9f7 273 /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
<> 144:ef7eb2e8f9f7 274 #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
<> 144:ef7eb2e8f9f7 275 /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
<> 144:ef7eb2e8f9f7 276 #define SYSTEM_OSC0_CR_VALUE 0x80U /* OSC0_CR */
<> 144:ef7eb2e8f9f7 277 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
<> 144:ef7eb2e8f9f7 278 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
<> 144:ef7eb2e8f9f7 279 /* SIM_CLKDIV1: OUTDIV1=1,OUTDIV4=3 */
<> 144:ef7eb2e8f9f7 280 #define SYSTEM_SIM_CLKDIV1_VALUE 0x10030000U /* SIM_CLKDIV1 */
<> 144:ef7eb2e8f9f7 281 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=3 */
<> 144:ef7eb2e8f9f7 282 #define SYSTEM_SIM_SOPT1_VALUE 0x000C0000U /* SIM_SOPT1 */
<> 144:ef7eb2e8f9f7 283 /* SIM_SOPT2: UART0SRC=0,TPMSRC=2,USBSRC=0,PLLFLLSEL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
<> 144:ef7eb2e8f9f7 284 #define SYSTEM_SIM_SOPT2_VALUE 0x02000000U /* SIM_SOPT2 */
<> 144:ef7eb2e8f9f7 285 #elif (CLOCK_SETUP == 4)
<> 144:ef7eb2e8f9f7 286 #define DEFAULT_SYSTEM_CLOCK 48000000U /* Default System clock value */
<> 144:ef7eb2e8f9f7 287 #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
<> 144:ef7eb2e8f9f7 288 /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
<> 144:ef7eb2e8f9f7 289 #define SYSTEM_MCG_C1_VALUE 0x1AU /* MCG_C1 */
<> 144:ef7eb2e8f9f7 290 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
<> 144:ef7eb2e8f9f7 291 #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
<> 144:ef7eb2e8f9f7 292 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
<> 144:ef7eb2e8f9f7 293 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
<> 144:ef7eb2e8f9f7 294 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
<> 144:ef7eb2e8f9f7 295 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
<> 144:ef7eb2e8f9f7 296 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=3 */
<> 144:ef7eb2e8f9f7 297 #define SYSTEM_MCG_C5_VALUE 0x03U /* MCG_C5 */
<> 144:ef7eb2e8f9f7 298 /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=24 */
<> 144:ef7eb2e8f9f7 299 #define SYSTEM_MCG_C6_VALUE 0x58U /* MCG_C6 */
<> 144:ef7eb2e8f9f7 300 /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
<> 144:ef7eb2e8f9f7 301 #define SYSTEM_OSC0_CR_VALUE 0x80U /* OSC0_CR */
<> 144:ef7eb2e8f9f7 302 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
<> 144:ef7eb2e8f9f7 303 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
<> 144:ef7eb2e8f9f7 304 /* SIM_CLKDIV1: OUTDIV1=1,OUTDIV4=1 */
<> 144:ef7eb2e8f9f7 305 #define SYSTEM_SIM_CLKDIV1_VALUE 0x10010000U /* SIM_CLKDIV1 */
<> 144:ef7eb2e8f9f7 306 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=3 */
<> 144:ef7eb2e8f9f7 307 #define SYSTEM_SIM_SOPT1_VALUE 0x000C0000U /* SIM_SOPT1 */
<> 144:ef7eb2e8f9f7 308 /* SIM_SOPT2: UART0SRC=0,TPMSRC=1,USBSRC=0,PLLFLLSEL=1,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
<> 144:ef7eb2e8f9f7 309 #define SYSTEM_SIM_SOPT2_VALUE 0x01010000U /* SIM_SOPT2 */
<> 144:ef7eb2e8f9f7 310 #else
<> 144:ef7eb2e8f9f7 311 #error The selected clock setup is not supported.
<> 144:ef7eb2e8f9f7 312 #endif
<> 144:ef7eb2e8f9f7 313 #else //#ifdef CLOCK_SETUP
<> 144:ef7eb2e8f9f7 314 #define DEFAULT_SYSTEM_CLOCK 20971520U /* Default System clock value */
<> 144:ef7eb2e8f9f7 315 #endif //#ifdef CLOCK_SETUP
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318 /**
<> 144:ef7eb2e8f9f7 319 * @brief System clock frequency (core clock)
<> 144:ef7eb2e8f9f7 320 *
<> 144:ef7eb2e8f9f7 321 * The system clock frequency supplied to the SysTick timer and the processor
<> 144:ef7eb2e8f9f7 322 * core clock. This variable can be used by the user application to setup the
<> 144:ef7eb2e8f9f7 323 * SysTick timer or configure other parameters. It may also be used by debugger to
<> 144:ef7eb2e8f9f7 324 * query the frequency of the debug timer or configure the trace clock speed
<> 144:ef7eb2e8f9f7 325 * SystemCoreClock is initialized with a correct predefined value.
<> 144:ef7eb2e8f9f7 326 */
<> 144:ef7eb2e8f9f7 327 extern uint32_t SystemCoreClock;
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 /**
<> 144:ef7eb2e8f9f7 330 * @brief Setup the microcontroller system.
<> 144:ef7eb2e8f9f7 331 *
<> 144:ef7eb2e8f9f7 332 * Typically this function configures the oscillator (PLL) that is part of the
<> 144:ef7eb2e8f9f7 333 * microcontroller device. For systems with variable clock speed it also updates
<> 144:ef7eb2e8f9f7 334 * the variable SystemCoreClock. SystemInit is called from startup_device file.
<> 144:ef7eb2e8f9f7 335 */
<> 144:ef7eb2e8f9f7 336 void SystemInit (void);
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338 /**
<> 144:ef7eb2e8f9f7 339 * @brief Updates the SystemCoreClock variable.
<> 144:ef7eb2e8f9f7 340 *
<> 144:ef7eb2e8f9f7 341 * It must be called whenever the core clock is changed during program
<> 144:ef7eb2e8f9f7 342 * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
<> 144:ef7eb2e8f9f7 343 * the current core clock.
<> 144:ef7eb2e8f9f7 344 */
<> 144:ef7eb2e8f9f7 345 void SystemCoreClockUpdate (void);
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 348 }
<> 144:ef7eb2e8f9f7 349 #endif
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351 #endif /* #if !defined(SYSTEM_MKL26Z4_H_) */