Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/system_CMSDK_BEETLE.c@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * SPDX-License-Identifier: Apache-2.0
<> 144:ef7eb2e8f9f7 5 *
<> 144:ef7eb2e8f9f7 6 * Licensed under the Apache License, Version 2.0 (the License); you may
<> 144:ef7eb2e8f9f7 7 * not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 8 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 11 *
<> 144:ef7eb2e8f9f7 12 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
<> 144:ef7eb2e8f9f7 14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 15 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 16 * limitations under the License.
<> 144:ef7eb2e8f9f7 17 */
<> 144:ef7eb2e8f9f7 18 /*
<> 144:ef7eb2e8f9f7 19 * This file is derivative of CMSIS V5.00 system_ARMCM3.c
<> 144:ef7eb2e8f9f7 20 */
<> 144:ef7eb2e8f9f7 21
<> 144:ef7eb2e8f9f7 22 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 /*----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 25 * Define clocks
<> 144:ef7eb2e8f9f7 26 *----------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 27 #define __XTAL (48000000UL) /* Oscillator frequency */
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 #define __SYSTEM_CLOCK (__XTAL / 2)
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 /*----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 32 * Clock Variable definitions
<> 144:ef7eb2e8f9f7 33 *----------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 34 /* !< System Clock Frequency (Core Clock) */
<> 144:ef7eb2e8f9f7 35 uint32_t SystemCoreClock = __SYSTEM_CLOCK;
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 /*----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 38 * Clock functions
<> 144:ef7eb2e8f9f7 39 *----------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 40 /**
<> 144:ef7eb2e8f9f7 41 * Update SystemCoreClock variable
<> 144:ef7eb2e8f9f7 42 *
<> 144:ef7eb2e8f9f7 43 * @param none
<> 144:ef7eb2e8f9f7 44 * @return none
<> 144:ef7eb2e8f9f7 45 *
<> 144:ef7eb2e8f9f7 46 * @brief Updates the SystemCoreClock with current core Clock
<> 144:ef7eb2e8f9f7 47 * retrieved from cpu registers.
<> 144:ef7eb2e8f9f7 48 */
<> 144:ef7eb2e8f9f7 49 void SystemCoreClockUpdate (void)
<> 144:ef7eb2e8f9f7 50 {
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 SystemCoreClock = __SYSTEM_CLOCK;
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 }
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 /**
<> 144:ef7eb2e8f9f7 57 * Initialize the system
<> 144:ef7eb2e8f9f7 58 *
<> 144:ef7eb2e8f9f7 59 * @param none
<> 144:ef7eb2e8f9f7 60 * @return none
<> 144:ef7eb2e8f9f7 61 *
<> 144:ef7eb2e8f9f7 62 * @brief Setup the microcontroller system.
<> 144:ef7eb2e8f9f7 63 * Initialize the System.
<> 144:ef7eb2e8f9f7 64 */
<> 144:ef7eb2e8f9f7 65 void SystemInit (void)
<> 144:ef7eb2e8f9f7 66 {
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 #ifdef UNALIGNED_SUPPORT_DISABLE
<> 144:ef7eb2e8f9f7 69 SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
<> 144:ef7eb2e8f9f7 70 #endif
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 SystemCoreClock = __SYSTEM_CLOCK;
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 // Enable AHB and APB clock
<> 144:ef7eb2e8f9f7 75 /* GPIO */
<> 144:ef7eb2e8f9f7 76 CMSDK_SYSCON->AHBCLKCFG0SET = 0xF;
<> 144:ef7eb2e8f9f7 77 /*
<> 144:ef7eb2e8f9f7 78 * Activate clock for: I2C1, SPI1, SPIO, QUADSPI, WDOG,
<> 144:ef7eb2e8f9f7 79 * I2C0, UART0, UART1, TIMER0, TIMER1, DUAL TIMER, TRNG
<> 144:ef7eb2e8f9f7 80 */
<> 144:ef7eb2e8f9f7 81 CMSDK_SYSCON->APBCLKCFG0SET = SYSTEM_CORE_TIMER0
<> 144:ef7eb2e8f9f7 82 | SYSTEM_CORE_TIMER1
<> 144:ef7eb2e8f9f7 83 | SYSTEM_CORE_DUALTIMER0
<> 144:ef7eb2e8f9f7 84 | SYSTEM_CORE_UART0
<> 144:ef7eb2e8f9f7 85 | SYSTEM_CORE_UART1
<> 144:ef7eb2e8f9f7 86 | SYSTEM_CORE_I2C0
<> 144:ef7eb2e8f9f7 87 | SYSTEM_CORE_WDOG
<> 144:ef7eb2e8f9f7 88 | SYSTEM_CORE_QSPI
<> 144:ef7eb2e8f9f7 89 | SYSTEM_CORE_SPI0
<> 144:ef7eb2e8f9f7 90 | SYSTEM_CORE_SPI1
<> 144:ef7eb2e8f9f7 91 | SYSTEM_CORE_I2C1
<> 144:ef7eb2e8f9f7 92 | SYSTEM_CORE_TRNG;
<> 144:ef7eb2e8f9f7 93 /* Beetle System Core Config */
<> 144:ef7eb2e8f9f7 94 SystemCoreConfig();
<> 144:ef7eb2e8f9f7 95 }