Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_ARM_SSG/TARGET_BEETLE/eflash_api.c@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16
<> 144:ef7eb2e8f9f7 17 #include "eflash_api.h"
<> 144:ef7eb2e8f9f7 18
<> 144:ef7eb2e8f9f7 19 /* EFlash Private Data */
<> 144:ef7eb2e8f9f7 20 typedef struct {
<> 144:ef7eb2e8f9f7 21 /* basebank0 start address */
<> 144:ef7eb2e8f9f7 22 unsigned int basebank0;
<> 144:ef7eb2e8f9f7 23 /* basebank0 mass erase + info pages address */
<> 144:ef7eb2e8f9f7 24 unsigned int basebank0_me;
<> 144:ef7eb2e8f9f7 25 /* basebank1 start address */
<> 144:ef7eb2e8f9f7 26 unsigned int basebank1;
<> 144:ef7eb2e8f9f7 27 /* basebank1 mass erase + info pages address */
<> 144:ef7eb2e8f9f7 28 unsigned int basebank1_me;
<> 144:ef7eb2e8f9f7 29 } eflash_t;
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 static eflash_t eflash;
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 /* EFlash_IdCheck: Detect the part number to see if device is present */
<> 144:ef7eb2e8f9f7 34 int EFlash_IdCheck()
<> 144:ef7eb2e8f9f7 35 {
<> 144:ef7eb2e8f9f7 36 unsigned int eflash_id;
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 eflash_id = EFlash_Readl(SYS_EFLASH_PIDR2) & (EFLASH_DES_1 | EFLASH_JEDEC);
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 if (EFlash_Readl(SYS_EFLASH_PIDR0) != FLS_PID0
<> 144:ef7eb2e8f9f7 41 || EFlash_Readl(SYS_EFLASH_PIDR1) != FLS_PID1
<> 144:ef7eb2e8f9f7 42 || eflash_id != FLS_PID2)
<> 144:ef7eb2e8f9f7 43 /* port ID and ARM ID does not match */
<> 144:ef7eb2e8f9f7 44 return 1;
<> 144:ef7eb2e8f9f7 45 else
<> 144:ef7eb2e8f9f7 46 return 0;
<> 144:ef7eb2e8f9f7 47 }
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /* EFlash_ReturnBank1BaseAddress: Returns start address of bank 1 */
<> 144:ef7eb2e8f9f7 50 int EFlash_ReturnBank1BaseAddress()
<> 144:ef7eb2e8f9f7 51 {
<> 144:ef7eb2e8f9f7 52 unsigned int hwparams0;
<> 144:ef7eb2e8f9f7 53 int baseaddr;
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 hwparams0 = EFlash_Readl(SYS_EFLASH_HWPARAMS0) & EFLASH_FLASHSIZE;
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 switch(hwparams0)
<> 144:ef7eb2e8f9f7 58 {
<> 144:ef7eb2e8f9f7 59 case 0x11:
<> 144:ef7eb2e8f9f7 60 /* 128kb flash size - first page of bank 1 is 0x20000 */
<> 144:ef7eb2e8f9f7 61 baseaddr = 0x20000;
<> 144:ef7eb2e8f9f7 62 break;
<> 144:ef7eb2e8f9f7 63 case 0x12:
<> 144:ef7eb2e8f9f7 64 /* 256kb flash size - first page of bank 1 is 0x40000 */
<> 144:ef7eb2e8f9f7 65 baseaddr = 0x40000;
<> 144:ef7eb2e8f9f7 66 break;
<> 144:ef7eb2e8f9f7 67 default:
<> 144:ef7eb2e8f9f7 68 /* unsupported flash size */
<> 144:ef7eb2e8f9f7 69 baseaddr = -1;
<> 144:ef7eb2e8f9f7 70 break;
<> 144:ef7eb2e8f9f7 71 }
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 return baseaddr;
<> 144:ef7eb2e8f9f7 74 }
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 /* EFlash_DriverInitialize: eFlash Driver Initialize function */
<> 144:ef7eb2e8f9f7 77 void EFlash_DriverInitialize()
<> 144:ef7eb2e8f9f7 78 {
<> 144:ef7eb2e8f9f7 79 /* Find the start address of banks */
<> 144:ef7eb2e8f9f7 80 eflash.basebank0 = 0x0;
<> 144:ef7eb2e8f9f7 81 eflash.basebank0_me = 0x40000000;
<> 144:ef7eb2e8f9f7 82 eflash.basebank1 = EFlash_ReturnBank1BaseAddress();
<> 144:ef7eb2e8f9f7 83 eflash.basebank1_me = 0x80000000;
<> 144:ef7eb2e8f9f7 84 }
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 /* EFlash_ClockConfig: eFlash Clock Configuration */
<> 144:ef7eb2e8f9f7 87 void EFlash_ClockConfig()
<> 144:ef7eb2e8f9f7 88 {
<> 144:ef7eb2e8f9f7 89 /* Wait until eFlash controller gets unlocked */
<> 144:ef7eb2e8f9f7 90 while ((EFlash_Readl(SYS_EFLASH_STATUS) & EFLASH_LOCK_MASK) == EFLASH_LOCK);
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 /*
<> 144:ef7eb2e8f9f7 93 * Configure to use external clock
<> 144:ef7eb2e8f9f7 94 * EXTCL = 31250 ns ->
<> 144:ef7eb2e8f9f7 95 * 1 ms = 32 clock count 32khz ext_clk -> ER_CLK_COUNT = 32
<> 144:ef7eb2e8f9f7 96 * 1 us = 84 clock count system_clk -> WR_CLK_COUNT = 84
<> 144:ef7eb2e8f9f7 97 * EXT_CLK_CONF = 0x1 [Erase] External clock used for erase counters (>1ms)
<> 144:ef7eb2e8f9f7 98 * HCLK used for write counters
<> 144:ef7eb2e8f9f7 99 * RD_CLK_COUNT = 0x3
<> 144:ef7eb2e8f9f7 100 */
<> 144:ef7eb2e8f9f7 101 EFlash_Writel(SYS_EFLASH_CONFIG0, 0x00200B43);
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 /* Wait until eFlash controller gets unlocked */
<> 144:ef7eb2e8f9f7 104 while ((EFlash_Readl(SYS_EFLASH_STATUS) & EFLASH_BUSY_MASK) == EFLASH_BUSY);
<> 144:ef7eb2e8f9f7 105 }
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 /*
<> 144:ef7eb2e8f9f7 108 * EFlash_Erase: Erases flash banks
<> 144:ef7eb2e8f9f7 109 * Mode:
<> 144:ef7eb2e8f9f7 110 * 0 - erases bank 0
<> 144:ef7eb2e8f9f7 111 * 1 - erases bank 1
<> 144:ef7eb2e8f9f7 112 * 2 - erases bank 0 + info pages
<> 144:ef7eb2e8f9f7 113 * 3 - erases bank 1 + info pages
<> 144:ef7eb2e8f9f7 114 * 4 - erases bank 0 + 1
<> 144:ef7eb2e8f9f7 115 * 5 - erases bank 0 + 1 with info pages
<> 144:ef7eb2e8f9f7 116 */
<> 144:ef7eb2e8f9f7 117 void EFlash_Erase(int mode)
<> 144:ef7eb2e8f9f7 118 {
<> 144:ef7eb2e8f9f7 119 switch (mode)
<> 144:ef7eb2e8f9f7 120 {
<> 144:ef7eb2e8f9f7 121 case 0:
<> 144:ef7eb2e8f9f7 122 /* Wait until eFlash controller gets unlocked */
<> 144:ef7eb2e8f9f7 123 while ((EFlash_Readl(SYS_EFLASH_STATUS)
<> 144:ef7eb2e8f9f7 124 & EFLASH_LOCK_MASK) == EFLASH_LOCK);
<> 144:ef7eb2e8f9f7 125 /* Erase Block #0 */
<> 144:ef7eb2e8f9f7 126 EFlash_Writel(SYS_EFLASH_WADDR, eflash.basebank0);
<> 144:ef7eb2e8f9f7 127 EFlash_Writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE);
<> 144:ef7eb2e8f9f7 128 /* Wait until eFlash controller is not busy */
<> 144:ef7eb2e8f9f7 129 while ((EFlash_Readl(SYS_EFLASH_STATUS)
<> 144:ef7eb2e8f9f7 130 & EFLASH_BUSY_MASK) == EFLASH_BUSY);
<> 144:ef7eb2e8f9f7 131 break;
<> 144:ef7eb2e8f9f7 132 case 1:
<> 144:ef7eb2e8f9f7 133 /* Wait until eFlash controller gets unlocked */
<> 144:ef7eb2e8f9f7 134 while ((EFlash_Readl(SYS_EFLASH_STATUS)
<> 144:ef7eb2e8f9f7 135 & EFLASH_LOCK_MASK) == EFLASH_LOCK);
<> 144:ef7eb2e8f9f7 136 /* Erase Block #1 */
<> 144:ef7eb2e8f9f7 137 EFlash_Writel(SYS_EFLASH_WADDR, eflash.basebank1);
<> 144:ef7eb2e8f9f7 138 EFlash_Writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE);
<> 144:ef7eb2e8f9f7 139 /* Wait until eFlash controller is not busy */
<> 144:ef7eb2e8f9f7 140 while ((EFlash_Readl(SYS_EFLASH_STATUS)
<> 144:ef7eb2e8f9f7 141 & EFLASH_BUSY_MASK) == EFLASH_BUSY);
<> 144:ef7eb2e8f9f7 142 break;
<> 144:ef7eb2e8f9f7 143 case 2:
<> 144:ef7eb2e8f9f7 144 /* Wait until eFlash controller gets unlocked */
<> 144:ef7eb2e8f9f7 145 while ((EFlash_Readl(SYS_EFLASH_STATUS)
<> 144:ef7eb2e8f9f7 146 & EFLASH_LOCK_MASK) == EFLASH_LOCK);
<> 144:ef7eb2e8f9f7 147 /* Erase Block #0 + info pages */
<> 144:ef7eb2e8f9f7 148 EFlash_Writel(SYS_EFLASH_WADDR, eflash.basebank0_me);
<> 144:ef7eb2e8f9f7 149 EFlash_Writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE);
<> 144:ef7eb2e8f9f7 150 /* Wait until eFlash controller is not busy */
<> 144:ef7eb2e8f9f7 151 while ((EFlash_Readl(SYS_EFLASH_STATUS)
<> 144:ef7eb2e8f9f7 152 & EFLASH_BUSY_MASK) == EFLASH_BUSY);
<> 144:ef7eb2e8f9f7 153 break;
<> 144:ef7eb2e8f9f7 154 case 3:
<> 144:ef7eb2e8f9f7 155 /* Wait until eFlash controller gets unlocked */
<> 144:ef7eb2e8f9f7 156 while ((EFlash_Readl(SYS_EFLASH_STATUS)
<> 144:ef7eb2e8f9f7 157 & EFLASH_LOCK_MASK) == EFLASH_LOCK);
<> 144:ef7eb2e8f9f7 158 /* Erase Block #1 + info pages */
<> 144:ef7eb2e8f9f7 159 EFlash_Writel(SYS_EFLASH_WADDR, eflash.basebank1_me);
<> 144:ef7eb2e8f9f7 160 EFlash_Writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE);
<> 144:ef7eb2e8f9f7 161 /* Wait until eFlash controller is not busy */
<> 144:ef7eb2e8f9f7 162 while ((EFlash_Readl(SYS_EFLASH_STATUS)
<> 144:ef7eb2e8f9f7 163 & EFLASH_BUSY_MASK) == EFLASH_BUSY);
<> 144:ef7eb2e8f9f7 164 break;
<> 144:ef7eb2e8f9f7 165 case 4:
<> 144:ef7eb2e8f9f7 166 /* Wait until eFlash controller gets unlocked */
<> 144:ef7eb2e8f9f7 167 while ((EFlash_Readl(SYS_EFLASH_STATUS)
<> 144:ef7eb2e8f9f7 168 & EFLASH_LOCK_MASK) == EFLASH_LOCK);
<> 144:ef7eb2e8f9f7 169 /* Erase Block #0 */
<> 144:ef7eb2e8f9f7 170 EFlash_Writel(SYS_EFLASH_WADDR, eflash.basebank0);
<> 144:ef7eb2e8f9f7 171 EFlash_Writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE);
<> 144:ef7eb2e8f9f7 172 /* Wait until eFlash controller is not busy */
<> 144:ef7eb2e8f9f7 173 while ((EFlash_Readl(SYS_EFLASH_STATUS)
<> 144:ef7eb2e8f9f7 174 & EFLASH_BUSY_MASK) == EFLASH_BUSY);
<> 144:ef7eb2e8f9f7 175 /* Wait until eFlash controller gets unlocked */
<> 144:ef7eb2e8f9f7 176 while ((EFlash_Readl(SYS_EFLASH_STATUS)
<> 144:ef7eb2e8f9f7 177 & EFLASH_LOCK_MASK) == EFLASH_LOCK);
<> 144:ef7eb2e8f9f7 178 /* Erase Block #1 */
<> 144:ef7eb2e8f9f7 179 EFlash_Writel(SYS_EFLASH_WADDR, eflash.basebank1);
<> 144:ef7eb2e8f9f7 180 EFlash_Writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE);
<> 144:ef7eb2e8f9f7 181 /* Wait until eFlash controller gets unlocked */
<> 144:ef7eb2e8f9f7 182 /* Wait until eFlash controller is not busy */
<> 144:ef7eb2e8f9f7 183 while ((EFlash_Readl(SYS_EFLASH_STATUS)
<> 144:ef7eb2e8f9f7 184 & EFLASH_BUSY_MASK) == EFLASH_BUSY);
<> 144:ef7eb2e8f9f7 185 break;
<> 144:ef7eb2e8f9f7 186 case 5:
<> 144:ef7eb2e8f9f7 187 /* Wait until eFlash controller gets unlocked */
<> 144:ef7eb2e8f9f7 188 while ((EFlash_Readl(SYS_EFLASH_STATUS)
<> 144:ef7eb2e8f9f7 189 & EFLASH_LOCK_MASK) == EFLASH_LOCK);
<> 144:ef7eb2e8f9f7 190 /* Erase Block #0 + info pages */
<> 144:ef7eb2e8f9f7 191 EFlash_Writel(SYS_EFLASH_WADDR, eflash.basebank0_me);
<> 144:ef7eb2e8f9f7 192 EFlash_Writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE);
<> 144:ef7eb2e8f9f7 193 /* Wait until eFlash controller is not busy */
<> 144:ef7eb2e8f9f7 194 while ((EFlash_Readl(SYS_EFLASH_STATUS)
<> 144:ef7eb2e8f9f7 195 & EFLASH_BUSY_MASK) == EFLASH_BUSY);
<> 144:ef7eb2e8f9f7 196 /* Wait until eFlash controller gets unlocked */
<> 144:ef7eb2e8f9f7 197 while ((EFlash_Readl(SYS_EFLASH_STATUS)
<> 144:ef7eb2e8f9f7 198 & EFLASH_LOCK_MASK) == EFLASH_LOCK);
<> 144:ef7eb2e8f9f7 199 /* Erase Block #1 + info pages */
<> 144:ef7eb2e8f9f7 200 EFlash_Writel(SYS_EFLASH_WADDR, eflash.basebank1_me);
<> 144:ef7eb2e8f9f7 201 EFlash_Writel(SYS_EFLASH_CTRL, EFLASH_MASS_ERASE);
<> 144:ef7eb2e8f9f7 202 /* Wait until eFlash controller is not busy */
<> 144:ef7eb2e8f9f7 203 while ((EFlash_Readl(SYS_EFLASH_STATUS)
<> 144:ef7eb2e8f9f7 204 & EFLASH_BUSY_MASK) == EFLASH_BUSY);
<> 144:ef7eb2e8f9f7 205 break;
<> 144:ef7eb2e8f9f7 206 default:
<> 144:ef7eb2e8f9f7 207 break;
<> 144:ef7eb2e8f9f7 208 }
<> 144:ef7eb2e8f9f7 209 }
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 /* EFlash_ErasePage: Erase a Page */
<> 144:ef7eb2e8f9f7 212 void EFlash_ErasePage(unsigned int waddr)
<> 144:ef7eb2e8f9f7 213 {
<> 144:ef7eb2e8f9f7 214 /* Erase the page starting a waddr */
<> 144:ef7eb2e8f9f7 215 EFlash_Writel(SYS_EFLASH_WADDR, waddr);
<> 144:ef7eb2e8f9f7 216 EFlash_Writel(SYS_EFLASH_CTRL, EFLASH_ERASE);
<> 144:ef7eb2e8f9f7 217 /* Wait until eFlash controller gets unlocked */
<> 144:ef7eb2e8f9f7 218 while ((EFlash_Readl(SYS_EFLASH_STATUS)
<> 144:ef7eb2e8f9f7 219 & EFLASH_BUSY_MASK) == EFLASH_BUSY);
<> 144:ef7eb2e8f9f7 220 }
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 /*
<> 144:ef7eb2e8f9f7 223 * EFlash_Write: Write function
<> 144:ef7eb2e8f9f7 224 * Parameters:
<> 144:ef7eb2e8f9f7 225 * waddr - address in flash
<> 144:ef7eb2e8f9f7 226 * data - data to be written
<> 144:ef7eb2e8f9f7 227 */
<> 144:ef7eb2e8f9f7 228 void EFlash_Write(unsigned int waddr, unsigned int data)
<> 144:ef7eb2e8f9f7 229 {
<> 144:ef7eb2e8f9f7 230 /* Set Write Data Register */
<> 144:ef7eb2e8f9f7 231 EFlash_Writel(SYS_EFLASH_WDATA, data);
<> 144:ef7eb2e8f9f7 232 /* Set Write Address Register */
<> 144:ef7eb2e8f9f7 233 EFlash_Writel(SYS_EFLASH_WADDR, waddr);
<> 144:ef7eb2e8f9f7 234 /* Start Write Operation through CTRL register */
<> 144:ef7eb2e8f9f7 235 EFlash_Writel(SYS_EFLASH_CTRL, EFLASH_WRITE);
<> 144:ef7eb2e8f9f7 236 /* Wait until eFlash controller gets unlocked */
<> 144:ef7eb2e8f9f7 237 while ((EFlash_Readl(SYS_EFLASH_STATUS)
<> 144:ef7eb2e8f9f7 238 & EFLASH_BUSY_MASK) == EFLASH_BUSY);
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 /* Flash Cache invalidate if FCache enabled */
<> 144:ef7eb2e8f9f7 241 if (FCache_isEnabled() == 1)
<> 144:ef7eb2e8f9f7 242 FCache_Invalidate();
<> 144:ef7eb2e8f9f7 243 }
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 /*
<> 144:ef7eb2e8f9f7 246 * EFlash_WritePage: Write Page function
<> 144:ef7eb2e8f9f7 247 * Parameters:
<> 144:ef7eb2e8f9f7 248 * waddr - address in flash
<> 144:ef7eb2e8f9f7 249 * page_size - data to be written
<> 144:ef7eb2e8f9f7 250 * buf - buffer containing the data
<> 144:ef7eb2e8f9f7 251 */
<> 144:ef7eb2e8f9f7 252 int EFlash_WritePage(unsigned int waddr, unsigned int page_size,
<> 144:ef7eb2e8f9f7 253 unsigned char *buf)
<> 144:ef7eb2e8f9f7 254 {
<> 144:ef7eb2e8f9f7 255 unsigned int page_index;
<> 144:ef7eb2e8f9f7 256 unsigned int data;
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 /* To be verified */
<> 144:ef7eb2e8f9f7 259 for(page_index = 0; page_index < page_size; page_index = page_index + 4) {
<> 144:ef7eb2e8f9f7 260 /* Recreate the 32 bit word */
<> 144:ef7eb2e8f9f7 261 data = ((unsigned int) buf[page_index + 3]) << 24 |
<> 144:ef7eb2e8f9f7 262 ((unsigned int) buf[page_index + 2]) << 16 |
<> 144:ef7eb2e8f9f7 263 ((unsigned int) buf[page_index + 1]) << 8 |
<> 144:ef7eb2e8f9f7 264 ((unsigned int) buf[page_index]);
<> 144:ef7eb2e8f9f7 265 /* Write the word in memory */
<> 144:ef7eb2e8f9f7 266 EFlash_Write(waddr, data);
<> 144:ef7eb2e8f9f7 267 waddr += 4;
<> 144:ef7eb2e8f9f7 268 }
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 return 0;
<> 144:ef7eb2e8f9f7 271 }
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 /*
<> 144:ef7eb2e8f9f7 274 * EFlash_Read: Read function
<> 144:ef7eb2e8f9f7 275 * Parameters:
<> 144:ef7eb2e8f9f7 276 * waddr - address in flash
<> 144:ef7eb2e8f9f7 277 * Returns:
<> 144:ef7eb2e8f9f7 278 * the vaule read at address waddr
<> 144:ef7eb2e8f9f7 279 */
<> 144:ef7eb2e8f9f7 280 unsigned int EFlash_Read(unsigned int waddr)
<> 144:ef7eb2e8f9f7 281 {
<> 144:ef7eb2e8f9f7 282 unsigned int eflash_read = EFlash_Readl(waddr);
<> 144:ef7eb2e8f9f7 283 return eflash_read;
<> 144:ef7eb2e8f9f7 284 }
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 /*
<> 144:ef7eb2e8f9f7 287 * EFlash_Verify: Verifies if the eFlash has been written correctly.
<> 144:ef7eb2e8f9f7 288 * Parameters:
<> 144:ef7eb2e8f9f7 289 * waddr - address in flash
<> 144:ef7eb2e8f9f7 290 * page_size - data to be written
<> 144:ef7eb2e8f9f7 291 * buf - buffer containing the data
<> 144:ef7eb2e8f9f7 292 * Returns:
<> 144:ef7eb2e8f9f7 293 * (waddr+page_size) - OK or Failed Address
<> 144:ef7eb2e8f9f7 294 */
<> 144:ef7eb2e8f9f7 295 unsigned int EFlash_Verify(unsigned int waddr, unsigned int page_size,
<> 144:ef7eb2e8f9f7 296 unsigned char *buf)
<> 144:ef7eb2e8f9f7 297 {
<> 144:ef7eb2e8f9f7 298 unsigned int page_index;
<> 144:ef7eb2e8f9f7 299 unsigned int eflash_data, buf_data;
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 /* To be verified */
<> 144:ef7eb2e8f9f7 302 for(page_index = 0; page_index < page_size; page_index = page_index + 4) {
<> 144:ef7eb2e8f9f7 303 /* Recreate the 32 bit word */
<> 144:ef7eb2e8f9f7 304 buf_data = ((unsigned int) buf[page_index + 3]) << 24 |
<> 144:ef7eb2e8f9f7 305 ((unsigned int) buf[page_index + 2]) << 16 |
<> 144:ef7eb2e8f9f7 306 ((unsigned int) buf[page_index + 1]) << 8 |
<> 144:ef7eb2e8f9f7 307 ((unsigned int) buf[page_index]);
<> 144:ef7eb2e8f9f7 308 /* Read the word in memory */
<> 144:ef7eb2e8f9f7 309 eflash_data = EFlash_Read(waddr);
<> 144:ef7eb2e8f9f7 310 if (eflash_data != buf_data)
<> 144:ef7eb2e8f9f7 311 break;
<> 144:ef7eb2e8f9f7 312 waddr += 4;
<> 144:ef7eb2e8f9f7 313 }
<> 144:ef7eb2e8f9f7 314
<> 144:ef7eb2e8f9f7 315 /* Allign the address before return */
<> 144:ef7eb2e8f9f7 316 return (waddr);
<> 144:ef7eb2e8f9f7 317 }
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 /*
<> 144:ef7eb2e8f9f7 320 * EFlash_BlankCheck: Verifies if there is any Blank Block in eFlash
<> 144:ef7eb2e8f9f7 321 * Parameters:
<> 144:ef7eb2e8f9f7 322 * waddr - address in flash
<> 144:ef7eb2e8f9f7 323 * page_size - data to be written
<> 144:ef7eb2e8f9f7 324 * pat - pattern of a blank block
<> 144:ef7eb2e8f9f7 325 * Returns:
<> 144:ef7eb2e8f9f7 326 * 0 - OK or 1- Failed
<> 144:ef7eb2e8f9f7 327 */
<> 144:ef7eb2e8f9f7 328 int EFlash_BlankCheck(unsigned int waddr, unsigned int page_size,
<> 144:ef7eb2e8f9f7 329 unsigned char pat)
<> 144:ef7eb2e8f9f7 330 {
<> 144:ef7eb2e8f9f7 331 unsigned int page_index;
<> 144:ef7eb2e8f9f7 332 unsigned int eflash_data, buf_data;
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 /* Page size div by 4 */
<> 144:ef7eb2e8f9f7 335 page_size = page_size >> 2;
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 /* To be verified */
<> 144:ef7eb2e8f9f7 338 for(page_index = 0; page_index < page_size; page_index = page_index + 4) {
<> 144:ef7eb2e8f9f7 339 /* Recreate the 32 bit word */
<> 144:ef7eb2e8f9f7 340 buf_data = ((unsigned int) pat) << 24 |
<> 144:ef7eb2e8f9f7 341 ((unsigned int) pat) << 16 |
<> 144:ef7eb2e8f9f7 342 ((unsigned int) pat) << 8 |
<> 144:ef7eb2e8f9f7 343 ((unsigned int) pat);
<> 144:ef7eb2e8f9f7 344 /* Read the word in memory */
<> 144:ef7eb2e8f9f7 345 eflash_data = EFlash_Read(waddr);
<> 144:ef7eb2e8f9f7 346 if (eflash_data != buf_data)
<> 144:ef7eb2e8f9f7 347 return 1;
<> 144:ef7eb2e8f9f7 348 waddr += 4;
<> 144:ef7eb2e8f9f7 349 }
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351 return 0;
<> 144:ef7eb2e8f9f7 352 }
<> 144:ef7eb2e8f9f7 353
<> 144:ef7eb2e8f9f7 354 /*
<> 144:ef7eb2e8f9f7 355 * Delay ns (uncalibrated delay)
<> 144:ef7eb2e8f9f7 356 */
<> 144:ef7eb2e8f9f7 357 void EFlash_Delay(unsigned int period) {
<> 144:ef7eb2e8f9f7 358 int loop;
<> 144:ef7eb2e8f9f7 359 for (loop = 0; loop < period; loop++)
<> 144:ef7eb2e8f9f7 360 continue;
<> 144:ef7eb2e8f9f7 361 }