Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

hal/spi_api.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2006-2013 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16 #ifndef MBED_SPI_API_H
<> 144:ef7eb2e8f9f7 17 #define MBED_SPI_API_H
<> 144:ef7eb2e8f9f7 18
<> 144:ef7eb2e8f9f7 19 #include "device.h"
<> 144:ef7eb2e8f9f7 20 #include "dma_api.h"
<> 144:ef7eb2e8f9f7 21 #include "buffer.h"
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 #if DEVICE_SPI
<> 144:ef7eb2e8f9f7 24
<> 144:ef7eb2e8f9f7 25 #define SPI_EVENT_ERROR (1 << 1)
<> 144:ef7eb2e8f9f7 26 #define SPI_EVENT_COMPLETE (1 << 2)
<> 144:ef7eb2e8f9f7 27 #define SPI_EVENT_RX_OVERFLOW (1 << 3)
<> 144:ef7eb2e8f9f7 28 #define SPI_EVENT_ALL (SPI_EVENT_ERROR | SPI_EVENT_COMPLETE | SPI_EVENT_RX_OVERFLOW)
<> 144:ef7eb2e8f9f7 29
<> 144:ef7eb2e8f9f7 30 #define SPI_EVENT_INTERNAL_TRANSFER_COMPLETE (1 << 30) // Internal flag to report that an event occurred
<> 144:ef7eb2e8f9f7 31
<> 144:ef7eb2e8f9f7 32 #define SPI_FILL_WORD (0xFFFF)
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #if DEVICE_SPI_ASYNCH
<> 144:ef7eb2e8f9f7 35 /** Asynch SPI HAL structure
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37 typedef struct {
<> 144:ef7eb2e8f9f7 38 struct spi_s spi; /**< Target specific SPI structure */
<> 144:ef7eb2e8f9f7 39 struct buffer_s tx_buff; /**< Tx buffer */
<> 144:ef7eb2e8f9f7 40 struct buffer_s rx_buff; /**< Rx buffer */
<> 144:ef7eb2e8f9f7 41 } spi_t;
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 #else
<> 144:ef7eb2e8f9f7 44 /** Non-asynch SPI HAL structure
<> 144:ef7eb2e8f9f7 45 */
<> 144:ef7eb2e8f9f7 46 typedef struct spi_s spi_t;
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 #endif
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 51 extern "C" {
<> 144:ef7eb2e8f9f7 52 #endif
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 /**
<> 144:ef7eb2e8f9f7 55 * \defgroup hal_GeneralSPI SPI Configuration Functions
<> 144:ef7eb2e8f9f7 56 * @{
<> 144:ef7eb2e8f9f7 57 */
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /** Initialize the SPI peripheral
<> 144:ef7eb2e8f9f7 60 *
<> 144:ef7eb2e8f9f7 61 * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
<> 144:ef7eb2e8f9f7 62 * @param[out] obj The SPI object to initialize
<> 144:ef7eb2e8f9f7 63 * @param[in] mosi The pin to use for MOSI
<> 144:ef7eb2e8f9f7 64 * @param[in] miso The pin to use for MISO
<> 144:ef7eb2e8f9f7 65 * @param[in] sclk The pin to use for SCLK
<> 144:ef7eb2e8f9f7 66 * @param[in] ssel The pin to use for SSEL
<> 144:ef7eb2e8f9f7 67 */
<> 144:ef7eb2e8f9f7 68 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel);
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 /** Release a SPI object
<> 144:ef7eb2e8f9f7 71 *
<> 144:ef7eb2e8f9f7 72 * TODO: spi_free is currently unimplemented
<> 144:ef7eb2e8f9f7 73 * This will require reference counting at the C++ level to be safe
<> 144:ef7eb2e8f9f7 74 *
<> 144:ef7eb2e8f9f7 75 * Return the pins owned by the SPI object to their reset state
<> 144:ef7eb2e8f9f7 76 * Disable the SPI peripheral
<> 144:ef7eb2e8f9f7 77 * Disable the SPI clock
<> 144:ef7eb2e8f9f7 78 * @param[in] obj The SPI object to deinitialize
<> 144:ef7eb2e8f9f7 79 */
<> 144:ef7eb2e8f9f7 80 void spi_free(spi_t *obj);
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 /** Configure the SPI format
<> 144:ef7eb2e8f9f7 83 *
<> 144:ef7eb2e8f9f7 84 * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode.
<> 144:ef7eb2e8f9f7 85 * The default bit order is MSB.
<> 144:ef7eb2e8f9f7 86 * @param[in,out] obj The SPI object to configure
<> 144:ef7eb2e8f9f7 87 * @param[in] bits The number of bits per frame
<> 144:ef7eb2e8f9f7 88 * @param[in] mode The SPI mode (clock polarity, phase, and shift direction)
<> 144:ef7eb2e8f9f7 89 * @param[in] slave Zero for master mode or non-zero for slave mode
<> 144:ef7eb2e8f9f7 90 */
<> 144:ef7eb2e8f9f7 91 void spi_format(spi_t *obj, int bits, int mode, int slave);
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 /** Set the SPI baud rate
<> 144:ef7eb2e8f9f7 94 *
<> 144:ef7eb2e8f9f7 95 * Actual frequency may differ from the desired frequency due to available dividers and bus clock
<> 144:ef7eb2e8f9f7 96 * Configures the SPI peripheral's baud rate
<> 144:ef7eb2e8f9f7 97 * @param[in,out] obj The SPI object to configure
<> 144:ef7eb2e8f9f7 98 * @param[in] hz The baud rate in Hz
<> 144:ef7eb2e8f9f7 99 */
<> 144:ef7eb2e8f9f7 100 void spi_frequency(spi_t *obj, int hz);
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 /**@}*/
<> 144:ef7eb2e8f9f7 103 /**
<> 144:ef7eb2e8f9f7 104 * \defgroup SynchSPI Synchronous SPI Hardware Abstraction Layer
<> 144:ef7eb2e8f9f7 105 * @{
<> 144:ef7eb2e8f9f7 106 */
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 /** Write a byte out in master mode and receive a value
<> 144:ef7eb2e8f9f7 109 *
<> 144:ef7eb2e8f9f7 110 * @param[in] obj The SPI peripheral to use for sending
<> 144:ef7eb2e8f9f7 111 * @param[in] value The value to send
<> 144:ef7eb2e8f9f7 112 * @return Returns the value received during send
<> 144:ef7eb2e8f9f7 113 */
<> 144:ef7eb2e8f9f7 114 int spi_master_write(spi_t *obj, int value);
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 /** Check if a value is available to read
<> 144:ef7eb2e8f9f7 117 *
<> 144:ef7eb2e8f9f7 118 * @param[in] obj The SPI peripheral to check
<> 144:ef7eb2e8f9f7 119 * @return non-zero if a value is available
<> 144:ef7eb2e8f9f7 120 */
<> 144:ef7eb2e8f9f7 121 int spi_slave_receive(spi_t *obj);
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 /** Get a received value out of the SPI receive buffer in slave mode
<> 144:ef7eb2e8f9f7 124 *
<> 144:ef7eb2e8f9f7 125 * Blocks until a value is available
<> 144:ef7eb2e8f9f7 126 * @param[in] obj The SPI peripheral to read
<> 144:ef7eb2e8f9f7 127 * @return The value received
<> 144:ef7eb2e8f9f7 128 */
<> 144:ef7eb2e8f9f7 129 int spi_slave_read(spi_t *obj);
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 /** Write a value to the SPI peripheral in slave mode
<> 144:ef7eb2e8f9f7 132 *
<> 144:ef7eb2e8f9f7 133 * Blocks until the SPI peripheral can be written to
<> 144:ef7eb2e8f9f7 134 * @param[in] obj The SPI peripheral to write
<> 144:ef7eb2e8f9f7 135 * @param[in] value The value to write
<> 144:ef7eb2e8f9f7 136 */
<> 144:ef7eb2e8f9f7 137 void spi_slave_write(spi_t *obj, int value);
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 /** Checks if the specified SPI peripheral is in use
<> 144:ef7eb2e8f9f7 140 *
<> 144:ef7eb2e8f9f7 141 * @param[in] obj The SPI peripheral to check
<> 144:ef7eb2e8f9f7 142 * @return non-zero if the peripheral is currently transmitting
<> 144:ef7eb2e8f9f7 143 */
<> 144:ef7eb2e8f9f7 144 int spi_busy(spi_t *obj);
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 /** Get the module number
<> 144:ef7eb2e8f9f7 147 *
<> 144:ef7eb2e8f9f7 148 * @param[in] obj The SPI peripheral to check
<> 144:ef7eb2e8f9f7 149 * @return The module number
<> 144:ef7eb2e8f9f7 150 */
<> 144:ef7eb2e8f9f7 151 uint8_t spi_get_module(spi_t *obj);
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 /**@}*/
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 #if DEVICE_SPI_ASYNCH
<> 144:ef7eb2e8f9f7 156 /**
<> 144:ef7eb2e8f9f7 157 * \defgroup AsynchSPI Asynchronous SPI Hardware Abstraction Layer
<> 144:ef7eb2e8f9f7 158 * @{
<> 144:ef7eb2e8f9f7 159 */
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 /** Begin the SPI transfer. Buffer pointers and lengths are specified in tx_buff and rx_buff
<> 144:ef7eb2e8f9f7 162 *
<> 144:ef7eb2e8f9f7 163 * @param[in] obj The SPI object that holds the transfer information
<> 144:ef7eb2e8f9f7 164 * @param[in] tx The transmit buffer
<> 144:ef7eb2e8f9f7 165 * @param[in] tx_length The number of bytes to transmit
<> 144:ef7eb2e8f9f7 166 * @param[in] rx The receive buffer
<> 144:ef7eb2e8f9f7 167 * @param[in] rx_length The number of bytes to receive
<> 144:ef7eb2e8f9f7 168 * @param[in] bit_width The bit width of buffer words
<> 144:ef7eb2e8f9f7 169 * @param[in] event The logical OR of events to be registered
<> 144:ef7eb2e8f9f7 170 * @param[in] handler SPI interrupt handler
<> 144:ef7eb2e8f9f7 171 * @param[in] hint A suggestion for how to use DMA with this transfer
<> 144:ef7eb2e8f9f7 172 */
<> 144:ef7eb2e8f9f7 173 void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint);
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 /** The asynchronous IRQ handler
<> 144:ef7eb2e8f9f7 176 *
<> 144:ef7eb2e8f9f7 177 * Reads the received values out of the RX FIFO, writes values into the TX FIFO and checks for transfer termination
<> 144:ef7eb2e8f9f7 178 * conditions, such as buffer overflows or transfer complete.
<> 144:ef7eb2e8f9f7 179 * @param[in] obj The SPI object that holds the transfer information
<> 144:ef7eb2e8f9f7 180 * @return Event flags if a transfer termination condition was met; otherwise 0.
<> 144:ef7eb2e8f9f7 181 */
<> 144:ef7eb2e8f9f7 182 uint32_t spi_irq_handler_asynch(spi_t *obj);
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 /** Attempts to determine if the SPI peripheral is already in use
<> 144:ef7eb2e8f9f7 185 *
<> 144:ef7eb2e8f9f7 186 * If a temporary DMA channel has been allocated, peripheral is in use.
<> 144:ef7eb2e8f9f7 187 * If a permanent DMA channel has been allocated, check if the DMA channel is in use. If not, proceed as though no DMA
<> 144:ef7eb2e8f9f7 188 * channel were allocated.
<> 144:ef7eb2e8f9f7 189 * If no DMA channel is allocated, check whether tx and rx buffers have been assigned. For each assigned buffer, check
<> 144:ef7eb2e8f9f7 190 * if the corresponding buffer position is less than the buffer length. If buffers do not indicate activity, check if
<> 144:ef7eb2e8f9f7 191 * there are any bytes in the FIFOs.
<> 144:ef7eb2e8f9f7 192 * @param[in] obj The SPI object to check for activity
<> 144:ef7eb2e8f9f7 193 * @return Non-zero if the SPI port is active or zero if it is not.
<> 144:ef7eb2e8f9f7 194 */
<> 144:ef7eb2e8f9f7 195 uint8_t spi_active(spi_t *obj);
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 /** Abort an SPI transfer
<> 144:ef7eb2e8f9f7 198 *
<> 144:ef7eb2e8f9f7 199 * @param obj The SPI peripheral to stop
<> 144:ef7eb2e8f9f7 200 */
<> 144:ef7eb2e8f9f7 201 void spi_abort_asynch(spi_t *obj);
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 #endif
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 /**@}*/
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 209 }
<> 144:ef7eb2e8f9f7 210 #endif // __cplusplus
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 #endif // SPI_DEVICE
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 #endif // MBED_SPI_API_H