mbed-dev - added prescaler for 16 bit pwm in LPC1347 target

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Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_cmu.c@50:a417edff4437, 2016-01-15 (annotated)

Committer:: mbed_official
Date:: Fri Jan 15 07:45:16 2016 +0000
Revision:: 50:a417edff4437
Parent:: 0:9b334a45a8ff
Child:: 144:ef7eb2e8f9f7

Synchronized with git revision 6010f32619bfcbb01cc73747d4ff9040863482d9

Full URL: https://github.com/mbedmicro/mbed/commit/6010f32619bfcbb01cc73747d4ff9040863482d9/

Remove doubling of buffer size in realiseEndpoint()

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/*************************************************************************//
bogdanm	0:9b334a45a8ff	2	* @file em_cmu.c
bogdanm	0:9b334a45a8ff	3	* @brief Clock management unit (CMU) Peripheral API
mbed_official	50:a417edff4437	4	* @version 4.2.1
bogdanm	0:9b334a45a8ff	5	*******************************************************************************
bogdanm	0:9b334a45a8ff	6	* @section License
mbed_official	50:a417edff4437	7	* <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
bogdanm	0:9b334a45a8ff	8	*******************************************************************************
bogdanm	0:9b334a45a8ff	9	*
bogdanm	0:9b334a45a8ff	10	* Permission is granted to anyone to use this software for any purpose,
bogdanm	0:9b334a45a8ff	11	* including commercial applications, and to alter it and redistribute it
bogdanm	0:9b334a45a8ff	12	* freely, subject to the following restrictions:
bogdanm	0:9b334a45a8ff	13	*
bogdanm	0:9b334a45a8ff	14	* 1. The origin of this software must not be misrepresented; you must not
bogdanm	0:9b334a45a8ff	15	* claim that you wrote the original software.
bogdanm	0:9b334a45a8ff	16	* 2. Altered source versions must be plainly marked as such, and must not be
bogdanm	0:9b334a45a8ff	17	* misrepresented as being the original software.
bogdanm	0:9b334a45a8ff	18	* 3. This notice may not be removed or altered from any source distribution.
bogdanm	0:9b334a45a8ff	19	*
bogdanm	0:9b334a45a8ff	20	* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
bogdanm	0:9b334a45a8ff	21	* obligation to support this Software. Silicon Labs is providing the
bogdanm	0:9b334a45a8ff	22	* Software "AS IS", with no express or implied warranties of any kind,
bogdanm	0:9b334a45a8ff	23	* including, but not limited to, any implied warranties of merchantability
bogdanm	0:9b334a45a8ff	24	* or fitness for any particular purpose or warranties against infringement
bogdanm	0:9b334a45a8ff	25	* of any proprietary rights of a third party.
bogdanm	0:9b334a45a8ff	26	*
bogdanm	0:9b334a45a8ff	27	* Silicon Labs will not be liable for any consequential, incidental, or
bogdanm	0:9b334a45a8ff	28	* special damages, or any other relief, or for any claim by any third party,
bogdanm	0:9b334a45a8ff	29	* arising from your use of this Software.
bogdanm	0:9b334a45a8ff	30	*
bogdanm	0:9b334a45a8ff	31	******************************************************************************/
bogdanm	0:9b334a45a8ff	32	#include "em_cmu.h"
bogdanm	0:9b334a45a8ff	33	#if defined( CMU_PRESENT )
bogdanm	0:9b334a45a8ff	34
mbed_official	50:a417edff4437	35	#include <stddef.h>
mbed_official	50:a417edff4437	36	#include <limits.h>
bogdanm	0:9b334a45a8ff	37	#include "em_assert.h"
mbed_official	50:a417edff4437	38	#include "em_bus.h"
bogdanm	0:9b334a45a8ff	39	#include "em_emu.h"
mbed_official	50:a417edff4437	40	#include "em_system.h"
bogdanm	0:9b334a45a8ff	41
bogdanm	0:9b334a45a8ff	42	/*************************************************************************//
bogdanm	0:9b334a45a8ff	43	* @addtogroup EM_Library
bogdanm	0:9b334a45a8ff	44	* @{
bogdanm	0:9b334a45a8ff	45	******************************************************************************/
bogdanm	0:9b334a45a8ff	46
bogdanm	0:9b334a45a8ff	47	/*************************************************************************//
bogdanm	0:9b334a45a8ff	48	* @addtogroup CMU
bogdanm	0:9b334a45a8ff	49	* @brief Clock management unit (CMU) Peripheral API
bogdanm	0:9b334a45a8ff	50	* @{
bogdanm	0:9b334a45a8ff	51	******************************************************************************/
bogdanm	0:9b334a45a8ff	52
bogdanm	0:9b334a45a8ff	53	/*******************************************************************************
bogdanm	0:9b334a45a8ff	54	**************************** DEFINES **********************************
bogdanm	0:9b334a45a8ff	55	******************************************************************************/
bogdanm	0:9b334a45a8ff	56
bogdanm	0:9b334a45a8ff	57	/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
bogdanm	0:9b334a45a8ff	58
mbed_official	50:a417edff4437	59	#if defined( _SILICON_LABS_32B_PLATFORM_2 )
mbed_official	50:a417edff4437	60	/** Maximum allowed core frequency when using 0 wait-states on flash access. */
mbed_official	50:a417edff4437	61	#define CMU_MAX_FREQ_0WS 26000000
mbed_official	50:a417edff4437	62	/** Maximum allowed core frequency when using 1 wait-states on flash access */
mbed_official	50:a417edff4437	63	#define CMU_MAX_FREQ_1WS 40000000
mbed_official	50:a417edff4437	64	#elif defined( _SILICON_LABS_32B_PLATFORM_1 )
mbed_official	50:a417edff4437	65	/** Maximum allowed core frequency when using 0 wait-states on flash access. */
bogdanm	0:9b334a45a8ff	66	#define CMU_MAX_FREQ_0WS 16000000
mbed_official	50:a417edff4437	67	/** Maximum allowed core frequency when using 1 wait-states on flash access */
bogdanm	0:9b334a45a8ff	68	#define CMU_MAX_FREQ_1WS 32000000
mbed_official	50:a417edff4437	69	#else
mbed_official	50:a417edff4437	70	#error "Unkown MCU platform."
mbed_official	50:a417edff4437	71	#endif
bogdanm	0:9b334a45a8ff	72
bogdanm	0:9b334a45a8ff	73	#if defined( CMU_CTRL_HFLE )
bogdanm	0:9b334a45a8ff	74	/** Maximum frequency for HFLE needs to be enabled on Giant, Leopard and
bogdanm	0:9b334a45a8ff	75	Wonder. */
mbed_official	50:a417edff4437	76	#if defined( _EFM32_WONDER_FAMILY ) \
mbed_official	50:a417edff4437	77	\|\| defined( _EZR32_LEOPARD_FAMILY ) \
mbed_official	50:a417edff4437	78	\|\| defined( _EZR32_WONDER_FAMILY )
mbed_official	50:a417edff4437	79	#define CMU_MAX_FREQ_HFLE() 24000000
bogdanm	0:9b334a45a8ff	80	#elif defined ( _EFM32_GIANT_FAMILY )
mbed_official	50:a417edff4437	81	#define CMU_MAX_FREQ_HFLE() (maxFreqHfle())
bogdanm	0:9b334a45a8ff	82	#else
bogdanm	0:9b334a45a8ff	83	#error Invalid part/device.
bogdanm	0:9b334a45a8ff	84	#endif
bogdanm	0:9b334a45a8ff	85	#endif
bogdanm	0:9b334a45a8ff	86
mbed_official	50:a417edff4437	87	/*******************************************************************************
mbed_official	50:a417edff4437	88	************************ LOCAL VARIABLES ******************************
mbed_official	50:a417edff4437	89	******************************************************************************/
mbed_official	50:a417edff4437	90
mbed_official	50:a417edff4437	91	#if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
mbed_official	50:a417edff4437	92	static CMU_AUXHFRCOFreq_TypeDef auxHfrcoFreq = cmuAUXHFRCOFreq_19M0Hz;
mbed_official	50:a417edff4437	93	#endif
bogdanm	0:9b334a45a8ff	94
bogdanm	0:9b334a45a8ff	95	/** @endcond */
bogdanm	0:9b334a45a8ff	96
bogdanm	0:9b334a45a8ff	97	/*******************************************************************************
bogdanm	0:9b334a45a8ff	98	************************ LOCAL FUNCTIONS ******************************
bogdanm	0:9b334a45a8ff	99	******************************************************************************/
bogdanm	0:9b334a45a8ff	100
bogdanm	0:9b334a45a8ff	101	/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
bogdanm	0:9b334a45a8ff	102
mbed_official	50:a417edff4437	103	/*************************************************************************//
mbed_official	50:a417edff4437	104	* @brief
mbed_official	50:a417edff4437	105	* Get the AUX clock frequency. Used by MSC flash programming and LESENSE,
mbed_official	50:a417edff4437	106	* by default also as debug clock.
mbed_official	50:a417edff4437	107	*
mbed_official	50:a417edff4437	108	* @return
mbed_official	50:a417edff4437	109	* AUX Frequency in Hz
mbed_official	50:a417edff4437	110	******************************************************************************/
mbed_official	50:a417edff4437	111	static uint32_t auxClkGet(void)
mbed_official	50:a417edff4437	112	{
mbed_official	50:a417edff4437	113	uint32_t ret;
mbed_official	50:a417edff4437	114
mbed_official	50:a417edff4437	115	#if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
mbed_official	50:a417edff4437	116	ret = auxHfrcoFreq;
mbed_official	50:a417edff4437	117
mbed_official	50:a417edff4437	118	#elif defined( _CMU_AUXHFRCOCTRL_BAND_MASK )
mbed_official	50:a417edff4437	119	/* All Geckos from TG and newer */
mbed_official	50:a417edff4437	120	switch(CMU->AUXHFRCOCTRL & _CMU_AUXHFRCOCTRL_BAND_MASK)
mbed_official	50:a417edff4437	121	{
mbed_official	50:a417edff4437	122	case CMU_AUXHFRCOCTRL_BAND_1MHZ:
mbed_official	50:a417edff4437	123	ret = 1000000;
mbed_official	50:a417edff4437	124	break;
mbed_official	50:a417edff4437	125
mbed_official	50:a417edff4437	126	case CMU_AUXHFRCOCTRL_BAND_7MHZ:
mbed_official	50:a417edff4437	127	ret = 7000000;
mbed_official	50:a417edff4437	128	break;
mbed_official	50:a417edff4437	129
mbed_official	50:a417edff4437	130	case CMU_AUXHFRCOCTRL_BAND_11MHZ:
mbed_official	50:a417edff4437	131	ret = 11000000;
mbed_official	50:a417edff4437	132	break;
mbed_official	50:a417edff4437	133
mbed_official	50:a417edff4437	134	case CMU_AUXHFRCOCTRL_BAND_14MHZ:
mbed_official	50:a417edff4437	135	ret = 14000000;
mbed_official	50:a417edff4437	136	break;
mbed_official	50:a417edff4437	137
mbed_official	50:a417edff4437	138	case CMU_AUXHFRCOCTRL_BAND_21MHZ:
mbed_official	50:a417edff4437	139	ret = 21000000;
mbed_official	50:a417edff4437	140	break;
mbed_official	50:a417edff4437	141
mbed_official	50:a417edff4437	142	#if defined( _CMU_AUXHFRCOCTRL_BAND_28MHZ )
mbed_official	50:a417edff4437	143	case CMU_AUXHFRCOCTRL_BAND_28MHZ:
mbed_official	50:a417edff4437	144	ret = 28000000;
mbed_official	50:a417edff4437	145	break;
mbed_official	50:a417edff4437	146	#endif
mbed_official	50:a417edff4437	147
mbed_official	50:a417edff4437	148	default:
mbed_official	50:a417edff4437	149	EFM_ASSERT(0);
mbed_official	50:a417edff4437	150	ret = 0;
mbed_official	50:a417edff4437	151	break;
mbed_official	50:a417edff4437	152	}
mbed_official	50:a417edff4437	153
mbed_official	50:a417edff4437	154	#else
mbed_official	50:a417edff4437	155	/* Gecko has a fixed 14Mhz AUXHFRCO clock */
mbed_official	50:a417edff4437	156	ret = 14000000;
mbed_official	50:a417edff4437	157
mbed_official	50:a417edff4437	158	#endif
mbed_official	50:a417edff4437	159
mbed_official	50:a417edff4437	160	return ret;
mbed_official	50:a417edff4437	161	}
mbed_official	50:a417edff4437	162
bogdanm	0:9b334a45a8ff	163
bogdanm	0:9b334a45a8ff	164	/*************************************************************************//
bogdanm	0:9b334a45a8ff	165	* @brief
mbed_official	50:a417edff4437	166	* Get the Debug Trace clock frequency
mbed_official	50:a417edff4437	167	*
mbed_official	50:a417edff4437	168	* @return
mbed_official	50:a417edff4437	169	* Debug Trace frequency in Hz
bogdanm	0:9b334a45a8ff	170	******************************************************************************/
mbed_official	50:a417edff4437	171	static uint32_t dbgClkGet(void)
bogdanm	0:9b334a45a8ff	172	{
mbed_official	50:a417edff4437	173	uint32_t ret;
mbed_official	50:a417edff4437	174	CMU_Select_TypeDef clk;
mbed_official	50:a417edff4437	175
mbed_official	50:a417edff4437	176	/* Get selected clock source */
mbed_official	50:a417edff4437	177	clk = CMU_ClockSelectGet(cmuClock_DBG);
mbed_official	50:a417edff4437	178
mbed_official	50:a417edff4437	179	switch(clk)
bogdanm	0:9b334a45a8ff	180	{
mbed_official	50:a417edff4437	181	case cmuSelect_HFCLK:
mbed_official	50:a417edff4437	182	ret = SystemHFClockGet();
mbed_official	50:a417edff4437	183	#if defined( _CMU_CTRL_HFCLKDIV_MASK )
mbed_official	50:a417edff4437	184	/* Family with an additional divider. */
mbed_official	50:a417edff4437	185	ret = ret / (1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK)
mbed_official	50:a417edff4437	186	>> _CMU_CTRL_HFCLKDIV_SHIFT));
mbed_official	50:a417edff4437	187	#endif
mbed_official	50:a417edff4437	188	break;
mbed_official	50:a417edff4437	189
mbed_official	50:a417edff4437	190	case cmuSelect_AUXHFRCO:
mbed_official	50:a417edff4437	191	ret = auxClkGet();
mbed_official	50:a417edff4437	192	break;
mbed_official	50:a417edff4437	193
mbed_official	50:a417edff4437	194	default:
mbed_official	50:a417edff4437	195	EFM_ASSERT(0);
mbed_official	50:a417edff4437	196	ret = 0;
mbed_official	50:a417edff4437	197	break;
bogdanm	0:9b334a45a8ff	198	}
mbed_official	50:a417edff4437	199	return ret;
bogdanm	0:9b334a45a8ff	200	}
bogdanm	0:9b334a45a8ff	201
bogdanm	0:9b334a45a8ff	202
bogdanm	0:9b334a45a8ff	203	/*************************************************************************//
bogdanm	0:9b334a45a8ff	204	* @brief
bogdanm	0:9b334a45a8ff	205	* Configure flash access wait states in order to support given core clock
bogdanm	0:9b334a45a8ff	206	* frequency.
bogdanm	0:9b334a45a8ff	207	*
mbed_official	50:a417edff4437	208	* @param[in] coreFreq
bogdanm	0:9b334a45a8ff	209	* Core clock frequency to configure flash wait-states for
bogdanm	0:9b334a45a8ff	210	******************************************************************************/
mbed_official	50:a417edff4437	211	static void flashWaitStateControl(uint32_t coreFreq)
bogdanm	0:9b334a45a8ff	212	{
bogdanm	0:9b334a45a8ff	213	uint32_t mode;
bogdanm	0:9b334a45a8ff	214	bool mscLocked;
bogdanm	0:9b334a45a8ff	215	#if defined( MSC_READCTRL_MODE_WS0SCBTP )
mbed_official	50:a417edff4437	216	bool scbtpEn; /* Suppressed Conditional Branch Target Prefetch setting. */
bogdanm	0:9b334a45a8ff	217	#endif
bogdanm	0:9b334a45a8ff	218
bogdanm	0:9b334a45a8ff	219	/* Make sure the MSC is unlocked */
bogdanm	0:9b334a45a8ff	220	mscLocked = MSC->LOCK;
bogdanm	0:9b334a45a8ff	221	MSC->LOCK = MSC_UNLOCK_CODE;
bogdanm	0:9b334a45a8ff	222
bogdanm	0:9b334a45a8ff	223	/* Get mode and SCBTP enable */
bogdanm	0:9b334a45a8ff	224	mode = MSC->READCTRL & _MSC_READCTRL_MODE_MASK;
bogdanm	0:9b334a45a8ff	225	#if defined( MSC_READCTRL_MODE_WS0SCBTP )
bogdanm	0:9b334a45a8ff	226	switch(mode)
bogdanm	0:9b334a45a8ff	227	{
bogdanm	0:9b334a45a8ff	228	case MSC_READCTRL_MODE_WS0:
bogdanm	0:9b334a45a8ff	229	case MSC_READCTRL_MODE_WS1:
bogdanm	0:9b334a45a8ff	230	#if defined( MSC_READCTRL_MODE_WS2 )
bogdanm	0:9b334a45a8ff	231	case MSC_READCTRL_MODE_WS2:
bogdanm	0:9b334a45a8ff	232	#endif
bogdanm	0:9b334a45a8ff	233	scbtpEn = false;
bogdanm	0:9b334a45a8ff	234	break;
bogdanm	0:9b334a45a8ff	235
bogdanm	0:9b334a45a8ff	236	default: /* WSxSCBTP */
bogdanm	0:9b334a45a8ff	237	scbtpEn = true;
bogdanm	0:9b334a45a8ff	238	break;
bogdanm	0:9b334a45a8ff	239	}
bogdanm	0:9b334a45a8ff	240	#endif
bogdanm	0:9b334a45a8ff	241
bogdanm	0:9b334a45a8ff	242
bogdanm	0:9b334a45a8ff	243	/* Set mode based on the core clock frequency and SCBTP enable */
bogdanm	0:9b334a45a8ff	244	#if defined( MSC_READCTRL_MODE_WS0SCBTP )
bogdanm	0:9b334a45a8ff	245	if (false)
bogdanm	0:9b334a45a8ff	246	{
bogdanm	0:9b334a45a8ff	247	}
bogdanm	0:9b334a45a8ff	248	#if defined( MSC_READCTRL_MODE_WS2 )
mbed_official	50:a417edff4437	249	else if (coreFreq > CMU_MAX_FREQ_1WS)
bogdanm	0:9b334a45a8ff	250	{
bogdanm	0:9b334a45a8ff	251	mode = (scbtpEn ? MSC_READCTRL_MODE_WS2SCBTP : MSC_READCTRL_MODE_WS2);
bogdanm	0:9b334a45a8ff	252	}
bogdanm	0:9b334a45a8ff	253	#endif
mbed_official	50:a417edff4437	254	else if ((coreFreq <= CMU_MAX_FREQ_1WS) && (coreFreq > CMU_MAX_FREQ_0WS))
bogdanm	0:9b334a45a8ff	255	{
bogdanm	0:9b334a45a8ff	256	mode = (scbtpEn ? MSC_READCTRL_MODE_WS1SCBTP : MSC_READCTRL_MODE_WS1);
bogdanm	0:9b334a45a8ff	257	}
bogdanm	0:9b334a45a8ff	258	else
bogdanm	0:9b334a45a8ff	259	{
bogdanm	0:9b334a45a8ff	260	mode = (scbtpEn ? MSC_READCTRL_MODE_WS0SCBTP : MSC_READCTRL_MODE_WS0);
bogdanm	0:9b334a45a8ff	261	}
bogdanm	0:9b334a45a8ff	262
bogdanm	0:9b334a45a8ff	263	#else /* If MODE and SCBTP is in separate register fields */
bogdanm	0:9b334a45a8ff	264
bogdanm	0:9b334a45a8ff	265	if (false)
bogdanm	0:9b334a45a8ff	266	{
bogdanm	0:9b334a45a8ff	267	}
bogdanm	0:9b334a45a8ff	268	#if defined( MSC_READCTRL_MODE_WS2 )
mbed_official	50:a417edff4437	269	else if (coreFreq > CMU_MAX_FREQ_1WS)
bogdanm	0:9b334a45a8ff	270	{
bogdanm	0:9b334a45a8ff	271	mode = MSC_READCTRL_MODE_WS2;
bogdanm	0:9b334a45a8ff	272	}
bogdanm	0:9b334a45a8ff	273	#endif
mbed_official	50:a417edff4437	274	else if ((coreFreq <= CMU_MAX_FREQ_1WS) && (coreFreq > CMU_MAX_FREQ_0WS))
bogdanm	0:9b334a45a8ff	275	{
bogdanm	0:9b334a45a8ff	276	mode = MSC_READCTRL_MODE_WS1;
bogdanm	0:9b334a45a8ff	277	}
bogdanm	0:9b334a45a8ff	278	else
bogdanm	0:9b334a45a8ff	279	{
bogdanm	0:9b334a45a8ff	280	mode = MSC_READCTRL_MODE_WS0;
bogdanm	0:9b334a45a8ff	281	}
bogdanm	0:9b334a45a8ff	282	#endif
bogdanm	0:9b334a45a8ff	283
bogdanm	0:9b334a45a8ff	284	/* BUS_RegMaskedWrite cannot be used here as it would temporarely set the
bogdanm	0:9b334a45a8ff	285	mode field to WS0 */
bogdanm	0:9b334a45a8ff	286	MSC->READCTRL = (MSC->READCTRL &~_MSC_READCTRL_MODE_MASK) \| mode;
bogdanm	0:9b334a45a8ff	287
bogdanm	0:9b334a45a8ff	288	if (mscLocked)
bogdanm	0:9b334a45a8ff	289	{
bogdanm	0:9b334a45a8ff	290	MSC->LOCK = 0;
bogdanm	0:9b334a45a8ff	291	}
bogdanm	0:9b334a45a8ff	292	}
bogdanm	0:9b334a45a8ff	293
bogdanm	0:9b334a45a8ff	294
bogdanm	0:9b334a45a8ff	295	/*************************************************************************//
bogdanm	0:9b334a45a8ff	296	* @brief
bogdanm	0:9b334a45a8ff	297	* Configure flash access wait states to most conservative setting for
mbed_official	50:a417edff4437	298	* this target. Retain SCBTP (Suppressed Conditional Branch Target Prefetch)
mbed_official	50:a417edff4437	299	* setting.
bogdanm	0:9b334a45a8ff	300	******************************************************************************/
mbed_official	50:a417edff4437	301	static void flashWaitStateMax(void)
bogdanm	0:9b334a45a8ff	302	{
mbed_official	50:a417edff4437	303	flashWaitStateControl(SystemMaxCoreClockGet());
bogdanm	0:9b334a45a8ff	304	}
bogdanm	0:9b334a45a8ff	305
bogdanm	0:9b334a45a8ff	306
bogdanm	0:9b334a45a8ff	307	/*************************************************************************//
mbed_official	50:a417edff4437	308	* @brief
mbed_official	50:a417edff4437	309	* Get the LFnCLK frequency based on current configuration.
mbed_official	50:a417edff4437	310	*
mbed_official	50:a417edff4437	311	* @param[in] lfClkBranch
mbed_official	50:a417edff4437	312	* Selected LF branch
mbed_official	50:a417edff4437	313	*
mbed_official	50:a417edff4437	314	* @return
mbed_official	50:a417edff4437	315	* The LFnCLK frequency in Hz. If no LFnCLK is selected (disabled), 0 is
mbed_official	50:a417edff4437	316	* returned.
bogdanm	0:9b334a45a8ff	317	******************************************************************************/
mbed_official	50:a417edff4437	318	static uint32_t lfClkGet(CMU_Clock_TypeDef lfClkBranch)
bogdanm	0:9b334a45a8ff	319	{
mbed_official	50:a417edff4437	320	uint32_t sel;
mbed_official	50:a417edff4437	321	uint32_t ret = 0;
mbed_official	50:a417edff4437	322
mbed_official	50:a417edff4437	323	switch (lfClkBranch)
mbed_official	50:a417edff4437	324	{
mbed_official	50:a417edff4437	325	case cmuClock_LFA:
mbed_official	50:a417edff4437	326	case cmuClock_LFB:
mbed_official	50:a417edff4437	327	#if defined( _CMU_LFCCLKEN0_MASK )
mbed_official	50:a417edff4437	328	case cmuClock_LFC:
mbed_official	50:a417edff4437	329	#endif
mbed_official	50:a417edff4437	330	#if defined( _CMU_LFECLKSEL_MASK )
mbed_official	50:a417edff4437	331	case cmuClock_LFE:
mbed_official	50:a417edff4437	332	#endif
mbed_official	50:a417edff4437	333	break;
mbed_official	50:a417edff4437	334
mbed_official	50:a417edff4437	335	default:
mbed_official	50:a417edff4437	336	EFM_ASSERT(0);
mbed_official	50:a417edff4437	337	break;
mbed_official	50:a417edff4437	338	}
mbed_official	50:a417edff4437	339
mbed_official	50:a417edff4437	340	sel = CMU_ClockSelectGet(lfClkBranch);
mbed_official	50:a417edff4437	341
mbed_official	50:a417edff4437	342	/* Get clock select field */
mbed_official	50:a417edff4437	343	switch (lfClkBranch)
mbed_official	50:a417edff4437	344	{
mbed_official	50:a417edff4437	345	case cmuClock_LFA:
mbed_official	50:a417edff4437	346	#if defined( _CMU_LFCLKSEL_MASK )
mbed_official	50:a417edff4437	347	sel = (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFA_MASK) >> _CMU_LFCLKSEL_LFA_SHIFT;
mbed_official	50:a417edff4437	348	#elif defined( _CMU_LFACLKSEL_MASK )
mbed_official	50:a417edff4437	349	sel = (CMU->LFACLKSEL & _CMU_LFACLKSEL_LFA_MASK) >> _CMU_LFACLKSEL_LFA_SHIFT;
mbed_official	50:a417edff4437	350	#else
mbed_official	50:a417edff4437	351	EFM_ASSERT(0);
mbed_official	50:a417edff4437	352	#endif
mbed_official	50:a417edff4437	353	break;
mbed_official	50:a417edff4437	354
mbed_official	50:a417edff4437	355	case cmuClock_LFB:
mbed_official	50:a417edff4437	356	#if defined( _CMU_LFCLKSEL_MASK )
mbed_official	50:a417edff4437	357	sel = (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFB_MASK) >> _CMU_LFCLKSEL_LFB_SHIFT;
mbed_official	50:a417edff4437	358	#elif defined( _CMU_LFBCLKSEL_MASK )
mbed_official	50:a417edff4437	359	sel = (CMU->LFBCLKSEL & _CMU_LFBCLKSEL_LFB_MASK) >> _CMU_LFBCLKSEL_LFB_SHIFT;
mbed_official	50:a417edff4437	360	#else
mbed_official	50:a417edff4437	361	EFM_ASSERT(0);
mbed_official	50:a417edff4437	362	#endif
mbed_official	50:a417edff4437	363	break;
mbed_official	50:a417edff4437	364
mbed_official	50:a417edff4437	365	#if defined( _CMU_LFCCLKEN0_MASK )
mbed_official	50:a417edff4437	366	case cmuClock_LFC:
mbed_official	50:a417edff4437	367	sel = (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFC_MASK) >> _CMU_LFCLKSEL_LFC_SHIFT;
mbed_official	50:a417edff4437	368	break;
mbed_official	50:a417edff4437	369	#endif
mbed_official	50:a417edff4437	370
mbed_official	50:a417edff4437	371	#if defined( _CMU_LFECLKSEL_MASK )
mbed_official	50:a417edff4437	372	case cmuClock_LFE:
mbed_official	50:a417edff4437	373	sel = (CMU->LFECLKSEL & _CMU_LFECLKSEL_LFE_MASK) >> _CMU_LFECLKSEL_LFE_SHIFT;
mbed_official	50:a417edff4437	374	break;
mbed_official	50:a417edff4437	375	#endif
mbed_official	50:a417edff4437	376
mbed_official	50:a417edff4437	377	default:
mbed_official	50:a417edff4437	378	EFM_ASSERT(0);
mbed_official	50:a417edff4437	379	break;
mbed_official	50:a417edff4437	380	}
mbed_official	50:a417edff4437	381
mbed_official	50:a417edff4437	382	/* Get clock frequency */
mbed_official	50:a417edff4437	383	#if defined( _CMU_LFCLKSEL_MASK )
mbed_official	50:a417edff4437	384	switch (sel)
mbed_official	50:a417edff4437	385	{
mbed_official	50:a417edff4437	386	case _CMU_LFCLKSEL_LFA_LFRCO:
mbed_official	50:a417edff4437	387	ret = SystemLFRCOClockGet();
mbed_official	50:a417edff4437	388	break;
mbed_official	50:a417edff4437	389
mbed_official	50:a417edff4437	390	case _CMU_LFCLKSEL_LFA_LFXO:
mbed_official	50:a417edff4437	391	ret = SystemLFXOClockGet();
mbed_official	50:a417edff4437	392	break;
mbed_official	50:a417edff4437	393
mbed_official	50:a417edff4437	394	#if defined( _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 )
mbed_official	50:a417edff4437	395	case _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2:
mbed_official	50:a417edff4437	396	#if defined( CMU_CTRL_HFLE )
mbed_official	50:a417edff4437	397	/* Family which can use an extra div 4 divider */
mbed_official	50:a417edff4437	398	/* (and must if >32MHz) or HFLE is set. */
mbed_official	50:a417edff4437	399	if(((CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK)
mbed_official	50:a417edff4437	400	== CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4)
mbed_official	50:a417edff4437	401	\|\| (CMU->CTRL & CMU_CTRL_HFLE))
mbed_official	50:a417edff4437	402	{
mbed_official	50:a417edff4437	403	ret = SystemCoreClockGet() / 4U;
mbed_official	50:a417edff4437	404	}
mbed_official	50:a417edff4437	405	else
mbed_official	50:a417edff4437	406	{
mbed_official	50:a417edff4437	407	ret = SystemCoreClockGet() / 2U;
mbed_official	50:a417edff4437	408	}
mbed_official	50:a417edff4437	409	#else
mbed_official	50:a417edff4437	410	ret = SystemCoreClockGet() / 2U;
mbed_official	50:a417edff4437	411	#endif
mbed_official	50:a417edff4437	412	break;
mbed_official	50:a417edff4437	413	#endif
mbed_official	50:a417edff4437	414
mbed_official	50:a417edff4437	415	case _CMU_LFCLKSEL_LFA_DISABLED:
mbed_official	50:a417edff4437	416	ret = 0;
mbed_official	50:a417edff4437	417	#if defined( CMU_LFCLKSEL_LFAE )
mbed_official	50:a417edff4437	418	/* Check LF Extended bit setting for LFA or LFB ULFRCO clock */
mbed_official	50:a417edff4437	419	if ((lfClkBranch == cmuClock_LFA) \|\| (lfClkBranch == cmuClock_LFB))
mbed_official	50:a417edff4437	420	{
mbed_official	50:a417edff4437	421	if (CMU->LFCLKSEL >> (lfClkBranch == cmuClock_LFA
mbed_official	50:a417edff4437	422	? _CMU_LFCLKSEL_LFAE_SHIFT
mbed_official	50:a417edff4437	423	: _CMU_LFCLKSEL_LFBE_SHIFT))
mbed_official	50:a417edff4437	424	{
mbed_official	50:a417edff4437	425	ret = SystemULFRCOClockGet();
mbed_official	50:a417edff4437	426	}
mbed_official	50:a417edff4437	427	}
mbed_official	50:a417edff4437	428	#endif
mbed_official	50:a417edff4437	429	break;
mbed_official	50:a417edff4437	430
mbed_official	50:a417edff4437	431	default:
mbed_official	50:a417edff4437	432	EFM_ASSERT(0);
mbed_official	50:a417edff4437	433	ret = 0U;
mbed_official	50:a417edff4437	434	break;
mbed_official	50:a417edff4437	435	}
mbed_official	50:a417edff4437	436	#endif /* _CMU_LFCLKSEL_MASK */
mbed_official	50:a417edff4437	437
mbed_official	50:a417edff4437	438	#if defined( _CMU_LFACLKSEL_MASK )
mbed_official	50:a417edff4437	439	switch (sel)
mbed_official	50:a417edff4437	440	{
mbed_official	50:a417edff4437	441	case _CMU_LFACLKSEL_LFA_LFRCO:
mbed_official	50:a417edff4437	442	ret = SystemLFRCOClockGet();
mbed_official	50:a417edff4437	443	break;
mbed_official	50:a417edff4437	444
mbed_official	50:a417edff4437	445	case _CMU_LFACLKSEL_LFA_LFXO:
mbed_official	50:a417edff4437	446	ret = SystemLFXOClockGet();
mbed_official	50:a417edff4437	447	break;
mbed_official	50:a417edff4437	448
mbed_official	50:a417edff4437	449	case _CMU_LFACLKSEL_LFA_ULFRCO:
mbed_official	50:a417edff4437	450	ret = SystemULFRCOClockGet();
mbed_official	50:a417edff4437	451	break;
mbed_official	50:a417edff4437	452
mbed_official	50:a417edff4437	453	#if defined( _CMU_LFACLKSEL_LFA_HFCLKLE )
mbed_official	50:a417edff4437	454	case _CMU_LFACLKSEL_LFA_HFCLKLE:
mbed_official	50:a417edff4437	455	ret = ((CMU->HFPRESC & _CMU_HFPRESC_HFCLKLEPRESC_MASK)
mbed_official	50:a417edff4437	456	== CMU_HFPRESC_HFCLKLEPRESC_DIV4)
mbed_official	50:a417edff4437	457	? SystemCoreClockGet() / 4U
mbed_official	50:a417edff4437	458	: SystemCoreClockGet() / 2U;
mbed_official	50:a417edff4437	459	break;
mbed_official	50:a417edff4437	460	#elif defined( _CMU_LFBCLKSEL_LFB_HFCLKLE )
mbed_official	50:a417edff4437	461	case _CMU_LFBCLKSEL_LFB_HFCLKLE:
mbed_official	50:a417edff4437	462	ret = ((CMU->HFPRESC & _CMU_HFPRESC_HFCLKLEPRESC_MASK)
mbed_official	50:a417edff4437	463	== CMU_HFPRESC_HFCLKLEPRESC_DIV4)
mbed_official	50:a417edff4437	464	? SystemCoreClockGet() / 4U
mbed_official	50:a417edff4437	465	: SystemCoreClockGet() / 2U;
mbed_official	50:a417edff4437	466	break;
mbed_official	50:a417edff4437	467	#endif
mbed_official	50:a417edff4437	468
mbed_official	50:a417edff4437	469	case _CMU_LFACLKSEL_LFA_DISABLED:
mbed_official	50:a417edff4437	470	ret = 0;
mbed_official	50:a417edff4437	471	break;
mbed_official	50:a417edff4437	472	}
mbed_official	50:a417edff4437	473	#endif
mbed_official	50:a417edff4437	474
mbed_official	50:a417edff4437	475	return ret;
bogdanm	0:9b334a45a8ff	476	}
bogdanm	0:9b334a45a8ff	477
bogdanm	0:9b334a45a8ff	478
mbed_official	50:a417edff4437	479	#if defined( CMU_CTRL_HFLE ) \
mbed_official	50:a417edff4437	480	&& !defined( _EFM32_WONDER_FAMILY ) \
mbed_official	50:a417edff4437	481	&& !defined( _EZR32_LEOPARD_FAMILY ) \
mbed_official	50:a417edff4437	482	&& !defined( _EZR32_WONDER_FAMILY )
mbed_official	50:a417edff4437	483	/*************************************************************************//
mbed_official	50:a417edff4437	484	* @brief
mbed_official	50:a417edff4437	485	* Return max allowed frequency for low energy peripherals.
mbed_official	50:a417edff4437	486	******************************************************************************/
mbed_official	50:a417edff4437	487	static uint32_t maxFreqHfle(void)
mbed_official	50:a417edff4437	488	{
mbed_official	50:a417edff4437	489	uint16_t majorMinorRev;
mbed_official	50:a417edff4437	490
mbed_official	50:a417edff4437	491	switch (SYSTEM_GetFamily())
mbed_official	50:a417edff4437	492	{
mbed_official	50:a417edff4437	493	case systemPartFamilyEfm32Leopard:
mbed_official	50:a417edff4437	494	/* CHIP MAJOR bit [5:0] */
mbed_official	50:a417edff4437	495	majorMinorRev = (((ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK)
mbed_official	50:a417edff4437	496	>> _ROMTABLE_PID0_REVMAJOR_SHIFT) << 8);
mbed_official	50:a417edff4437	497	/* CHIP MINOR bit [7:4] */
mbed_official	50:a417edff4437	498	majorMinorRev \|= (((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK)
mbed_official	50:a417edff4437	499	>> _ROMTABLE_PID2_REVMINORMSB_SHIFT) << 4);
mbed_official	50:a417edff4437	500	/* CHIP MINOR bit [3:0] */
mbed_official	50:a417edff4437	501	majorMinorRev \|= ((ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK)
mbed_official	50:a417edff4437	502	>> _ROMTABLE_PID3_REVMINORLSB_SHIFT);
mbed_official	50:a417edff4437	503
mbed_official	50:a417edff4437	504	if (majorMinorRev >= 0x0204)
mbed_official	50:a417edff4437	505	return 24000000;
mbed_official	50:a417edff4437	506	else
mbed_official	50:a417edff4437	507	return 32000000;
mbed_official	50:a417edff4437	508
mbed_official	50:a417edff4437	509	case systemPartFamilyEfm32Giant:
mbed_official	50:a417edff4437	510	return 32000000;
mbed_official	50:a417edff4437	511
mbed_official	50:a417edff4437	512	default:
mbed_official	50:a417edff4437	513	/* Invalid device family. */
mbed_official	50:a417edff4437	514	EFM_ASSERT(false);
mbed_official	50:a417edff4437	515	return 0;
mbed_official	50:a417edff4437	516	}
mbed_official	50:a417edff4437	517	}
mbed_official	50:a417edff4437	518	#endif
mbed_official	50:a417edff4437	519
mbed_official	50:a417edff4437	520
bogdanm	0:9b334a45a8ff	521	/*************************************************************************//
mbed_official	50:a417edff4437	522	* @brief
mbed_official	50:a417edff4437	523	* Wait for ongoing sync of register(s) to low frequency domain to complete.
mbed_official	50:a417edff4437	524	*
mbed_official	50:a417edff4437	525	* @param[in] mask
mbed_official	50:a417edff4437	526	* Bitmask corresponding to SYNCBUSY register defined bits, indicating
mbed_official	50:a417edff4437	527	* registers that must complete any ongoing synchronization.
bogdanm	0:9b334a45a8ff	528	******************************************************************************/
mbed_official	50:a417edff4437	529	__STATIC_INLINE void syncReg(uint32_t mask)
bogdanm	0:9b334a45a8ff	530	{
mbed_official	50:a417edff4437	531	/* Avoid deadlock if modifying the same register twice when freeze mode is */
mbed_official	50:a417edff4437	532	/* activated. */
mbed_official	50:a417edff4437	533	if (CMU->FREEZE & CMU_FREEZE_REGFREEZE)
mbed_official	50:a417edff4437	534	return;
mbed_official	50:a417edff4437	535
mbed_official	50:a417edff4437	536	/* Wait for any pending previous write operation to have been completed */
mbed_official	50:a417edff4437	537	/* in low frequency domain */
mbed_official	50:a417edff4437	538	while (CMU->SYNCBUSY & mask)
mbed_official	50:a417edff4437	539	{
mbed_official	50:a417edff4437	540	}
bogdanm	0:9b334a45a8ff	541	}
bogdanm	0:9b334a45a8ff	542
bogdanm	0:9b334a45a8ff	543
bogdanm	0:9b334a45a8ff	544	#if defined(USB_PRESENT)
bogdanm	0:9b334a45a8ff	545	/*************************************************************************//
bogdanm	0:9b334a45a8ff	546	* @brief
bogdanm	0:9b334a45a8ff	547	* Get the USBC frequency
bogdanm	0:9b334a45a8ff	548	*
bogdanm	0:9b334a45a8ff	549	* @return
bogdanm	0:9b334a45a8ff	550	* USBC frequency in Hz
bogdanm	0:9b334a45a8ff	551	******************************************************************************/
mbed_official	50:a417edff4437	552	static uint32_t usbCClkGet(void)
bogdanm	0:9b334a45a8ff	553	{
bogdanm	0:9b334a45a8ff	554	uint32_t ret;
bogdanm	0:9b334a45a8ff	555	CMU_Select_TypeDef clk;
bogdanm	0:9b334a45a8ff	556
bogdanm	0:9b334a45a8ff	557	/* Get selected clock source */
bogdanm	0:9b334a45a8ff	558	clk = CMU_ClockSelectGet(cmuClock_USBC);
bogdanm	0:9b334a45a8ff	559
bogdanm	0:9b334a45a8ff	560	switch(clk)
bogdanm	0:9b334a45a8ff	561	{
mbed_official	50:a417edff4437	562	case cmuSelect_LFXO:
mbed_official	50:a417edff4437	563	ret = SystemLFXOClockGet();
mbed_official	50:a417edff4437	564	break;
mbed_official	50:a417edff4437	565	case cmuSelect_LFRCO:
mbed_official	50:a417edff4437	566	ret = SystemLFRCOClockGet();
mbed_official	50:a417edff4437	567	break;
mbed_official	50:a417edff4437	568	case cmuSelect_HFCLK:
mbed_official	50:a417edff4437	569	ret = SystemHFClockGet();
mbed_official	50:a417edff4437	570	break;
mbed_official	50:a417edff4437	571	default:
mbed_official	50:a417edff4437	572	/* Clock is not enabled */
mbed_official	50:a417edff4437	573	ret = 0;
mbed_official	50:a417edff4437	574	break;
bogdanm	0:9b334a45a8ff	575	}
bogdanm	0:9b334a45a8ff	576	return ret;
bogdanm	0:9b334a45a8ff	577	}
bogdanm	0:9b334a45a8ff	578	#endif
bogdanm	0:9b334a45a8ff	579
bogdanm	0:9b334a45a8ff	580
bogdanm	0:9b334a45a8ff	581	/** @endcond */
bogdanm	0:9b334a45a8ff	582
bogdanm	0:9b334a45a8ff	583	/*******************************************************************************
bogdanm	0:9b334a45a8ff	584	************************ GLOBAL FUNCTIONS *****************************
bogdanm	0:9b334a45a8ff	585	******************************************************************************/
bogdanm	0:9b334a45a8ff	586
mbed_official	50:a417edff4437	587	#if defined( _CMU_AUXHFRCOCTRL_BAND_MASK )
mbed_official	50:a417edff4437	588	/*************************************************************************//
mbed_official	50:a417edff4437	589	* @brief
mbed_official	50:a417edff4437	590	* Get AUXHFRCO band in use.
mbed_official	50:a417edff4437	591	*
mbed_official	50:a417edff4437	592	* @return
mbed_official	50:a417edff4437	593	* AUXHFRCO band in use.
mbed_official	50:a417edff4437	594	******************************************************************************/
mbed_official	50:a417edff4437	595	CMU_AUXHFRCOBand_TypeDef CMU_AUXHFRCOBandGet(void)
mbed_official	50:a417edff4437	596	{
mbed_official	50:a417edff4437	597	return (CMU_AUXHFRCOBand_TypeDef)((CMU->AUXHFRCOCTRL
mbed_official	50:a417edff4437	598	& _CMU_AUXHFRCOCTRL_BAND_MASK)
mbed_official	50:a417edff4437	599	>> _CMU_AUXHFRCOCTRL_BAND_SHIFT);
mbed_official	50:a417edff4437	600	}
mbed_official	50:a417edff4437	601	#endif /* _CMU_AUXHFRCOCTRL_BAND_MASK */
mbed_official	50:a417edff4437	602
mbed_official	50:a417edff4437	603
mbed_official	50:a417edff4437	604	#if defined( _CMU_AUXHFRCOCTRL_BAND_MASK )
mbed_official	50:a417edff4437	605	/*************************************************************************//
mbed_official	50:a417edff4437	606	* @brief
mbed_official	50:a417edff4437	607	* Set AUXHFRCO band and the tuning value based on the value in the
mbed_official	50:a417edff4437	608	* calibration table made during production.
mbed_official	50:a417edff4437	609	*
mbed_official	50:a417edff4437	610	* @param[in] band
mbed_official	50:a417edff4437	611	* AUXHFRCO band to activate.
mbed_official	50:a417edff4437	612	******************************************************************************/
mbed_official	50:a417edff4437	613	void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOBand_TypeDef band)
mbed_official	50:a417edff4437	614	{
mbed_official	50:a417edff4437	615	uint32_t tuning;
mbed_official	50:a417edff4437	616
mbed_official	50:a417edff4437	617	/* Read tuning value from calibration table */
mbed_official	50:a417edff4437	618	switch (band)
mbed_official	50:a417edff4437	619	{
mbed_official	50:a417edff4437	620	case cmuAUXHFRCOBand_1MHz:
mbed_official	50:a417edff4437	621	tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND1_MASK)
mbed_official	50:a417edff4437	622	>> _DEVINFO_AUXHFRCOCAL0_BAND1_SHIFT;
mbed_official	50:a417edff4437	623	break;
mbed_official	50:a417edff4437	624
mbed_official	50:a417edff4437	625	case cmuAUXHFRCOBand_7MHz:
mbed_official	50:a417edff4437	626	tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND7_MASK)
mbed_official	50:a417edff4437	627	>> _DEVINFO_AUXHFRCOCAL0_BAND7_SHIFT;
mbed_official	50:a417edff4437	628	break;
mbed_official	50:a417edff4437	629
mbed_official	50:a417edff4437	630	case cmuAUXHFRCOBand_11MHz:
mbed_official	50:a417edff4437	631	tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND11_MASK)
mbed_official	50:a417edff4437	632	>> _DEVINFO_AUXHFRCOCAL0_BAND11_SHIFT;
mbed_official	50:a417edff4437	633	break;
mbed_official	50:a417edff4437	634
mbed_official	50:a417edff4437	635	case cmuAUXHFRCOBand_14MHz:
mbed_official	50:a417edff4437	636	tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND14_MASK)
mbed_official	50:a417edff4437	637	>> _DEVINFO_AUXHFRCOCAL0_BAND14_SHIFT;
mbed_official	50:a417edff4437	638	break;
mbed_official	50:a417edff4437	639
mbed_official	50:a417edff4437	640	case cmuAUXHFRCOBand_21MHz:
mbed_official	50:a417edff4437	641	tuning = (DEVINFO->AUXHFRCOCAL1 & _DEVINFO_AUXHFRCOCAL1_BAND21_MASK)
mbed_official	50:a417edff4437	642	>> _DEVINFO_AUXHFRCOCAL1_BAND21_SHIFT;
mbed_official	50:a417edff4437	643	break;
mbed_official	50:a417edff4437	644
mbed_official	50:a417edff4437	645	#if defined( _CMU_AUXHFRCOCTRL_BAND_28MHZ )
mbed_official	50:a417edff4437	646	case cmuAUXHFRCOBand_28MHz:
mbed_official	50:a417edff4437	647	tuning = (DEVINFO->AUXHFRCOCAL1 & _DEVINFO_AUXHFRCOCAL1_BAND28_MASK)
mbed_official	50:a417edff4437	648	>> _DEVINFO_AUXHFRCOCAL1_BAND28_SHIFT;
mbed_official	50:a417edff4437	649	break;
mbed_official	50:a417edff4437	650	#endif
mbed_official	50:a417edff4437	651
mbed_official	50:a417edff4437	652	default:
mbed_official	50:a417edff4437	653	EFM_ASSERT(0);
mbed_official	50:a417edff4437	654	return;
mbed_official	50:a417edff4437	655	}
mbed_official	50:a417edff4437	656
mbed_official	50:a417edff4437	657	/* Set band/tuning */
mbed_official	50:a417edff4437	658	CMU->AUXHFRCOCTRL = (CMU->AUXHFRCOCTRL &
mbed_official	50:a417edff4437	659	~(_CMU_AUXHFRCOCTRL_BAND_MASK
mbed_official	50:a417edff4437	660	\| _CMU_AUXHFRCOCTRL_TUNING_MASK))
mbed_official	50:a417edff4437	661	\| (band << _CMU_AUXHFRCOCTRL_BAND_SHIFT)
mbed_official	50:a417edff4437	662	\| (tuning << _CMU_AUXHFRCOCTRL_TUNING_SHIFT);
mbed_official	50:a417edff4437	663
mbed_official	50:a417edff4437	664	}
mbed_official	50:a417edff4437	665	#endif /* _CMU_AUXHFRCOCTRL_BAND_MASK */
mbed_official	50:a417edff4437	666
mbed_official	50:a417edff4437	667
mbed_official	50:a417edff4437	668	#if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
mbed_official	50:a417edff4437	669	/************************************************************************//
mbed_official	50:a417edff4437	670	* @brief
mbed_official	50:a417edff4437	671	* Get a pointer to the AUXHFRCO frequency calibration word in DEVINFO
mbed_official	50:a417edff4437	672	*
mbed_official	50:a417edff4437	673	* @param[in] freq
mbed_official	50:a417edff4437	674	* Frequency in Hz
mbed_official	50:a417edff4437	675	*
mbed_official	50:a417edff4437	676	* @return
mbed_official	50:a417edff4437	677	* AUXHFRCO calibration word for a given frequency
mbed_official	50:a417edff4437	678	*****************************************************************************/
mbed_official	50:a417edff4437	679	static uint32_t CMU_AUXHFRCODevinfoGet(CMU_AUXHFRCOFreq_TypeDef freq)
mbed_official	50:a417edff4437	680	{
mbed_official	50:a417edff4437	681	switch (freq)
mbed_official	50:a417edff4437	682	{
mbed_official	50:a417edff4437	683	/* 1, 2 and 4MHz share the same calibration word */
mbed_official	50:a417edff4437	684	case cmuAUXHFRCOFreq_1M0Hz:
mbed_official	50:a417edff4437	685	case cmuAUXHFRCOFreq_2M0Hz:
mbed_official	50:a417edff4437	686	case cmuAUXHFRCOFreq_4M0Hz:
mbed_official	50:a417edff4437	687	return DEVINFO->AUXHFRCOCAL0;
mbed_official	50:a417edff4437	688
mbed_official	50:a417edff4437	689	case cmuAUXHFRCOFreq_7M0Hz:
mbed_official	50:a417edff4437	690	return DEVINFO->AUXHFRCOCAL3;
mbed_official	50:a417edff4437	691
mbed_official	50:a417edff4437	692	case cmuAUXHFRCOFreq_13M0Hz:
mbed_official	50:a417edff4437	693	return DEVINFO->AUXHFRCOCAL6;
mbed_official	50:a417edff4437	694
mbed_official	50:a417edff4437	695	case cmuAUXHFRCOFreq_16M0Hz:
mbed_official	50:a417edff4437	696	return DEVINFO->AUXHFRCOCAL7;
mbed_official	50:a417edff4437	697
mbed_official	50:a417edff4437	698	case cmuAUXHFRCOFreq_19M0Hz:
mbed_official	50:a417edff4437	699	return DEVINFO->AUXHFRCOCAL8;
mbed_official	50:a417edff4437	700
mbed_official	50:a417edff4437	701	case cmuAUXHFRCOFreq_26M0Hz:
mbed_official	50:a417edff4437	702	return DEVINFO->AUXHFRCOCAL10;
mbed_official	50:a417edff4437	703
mbed_official	50:a417edff4437	704	case cmuAUXHFRCOFreq_32M0Hz:
mbed_official	50:a417edff4437	705	return DEVINFO->AUXHFRCOCAL11;
mbed_official	50:a417edff4437	706
mbed_official	50:a417edff4437	707	case cmuAUXHFRCOFreq_38M0Hz:
mbed_official	50:a417edff4437	708	return DEVINFO->AUXHFRCOCAL12;
mbed_official	50:a417edff4437	709
mbed_official	50:a417edff4437	710	default: /* cmuAUXHFRCOFreq_UserDefined */
mbed_official	50:a417edff4437	711	return 0;
mbed_official	50:a417edff4437	712	}
mbed_official	50:a417edff4437	713	}
mbed_official	50:a417edff4437	714	#endif /* _CMU_AUXHFRCOCTRL_FREQRANGE_MASK */
mbed_official	50:a417edff4437	715
mbed_official	50:a417edff4437	716
mbed_official	50:a417edff4437	717	#if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
mbed_official	50:a417edff4437	718	/*************************************************************************//
mbed_official	50:a417edff4437	719	* @brief
mbed_official	50:a417edff4437	720	* Get AUXHFRCO frequency enumeration in use
mbed_official	50:a417edff4437	721	*
mbed_official	50:a417edff4437	722	* @return
mbed_official	50:a417edff4437	723	* AUXHFRCO frequency enumeration in use
mbed_official	50:a417edff4437	724	******************************************************************************/
mbed_official	50:a417edff4437	725	CMU_AUXHFRCOFreq_TypeDef CMU_AUXHFRCOFreqGet(void)
mbed_official	50:a417edff4437	726	{
mbed_official	50:a417edff4437	727	return auxHfrcoFreq;
mbed_official	50:a417edff4437	728	}
mbed_official	50:a417edff4437	729	#endif /* _CMU_AUXHFRCOCTRL_FREQRANGE_MASK */
mbed_official	50:a417edff4437	730
mbed_official	50:a417edff4437	731
mbed_official	50:a417edff4437	732	#if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
mbed_official	50:a417edff4437	733	/*************************************************************************//
mbed_official	50:a417edff4437	734	* @brief
mbed_official	50:a417edff4437	735	* Set AUXHFRCO calibration for the selected target frequency
mbed_official	50:a417edff4437	736	*
mbed_official	50:a417edff4437	737	* @param[in] frequency
mbed_official	50:a417edff4437	738	* AUXHFRCO frequency to set
mbed_official	50:a417edff4437	739	******************************************************************************/
mbed_official	50:a417edff4437	740	void CMU_AUXHFRCOFreqSet(CMU_AUXHFRCOFreq_TypeDef freq)
mbed_official	50:a417edff4437	741	{
mbed_official	50:a417edff4437	742	uint32_t freqCal;
mbed_official	50:a417edff4437	743
mbed_official	50:a417edff4437	744	/* Get DEVINFO index, set global auxHfrcoFreq */
mbed_official	50:a417edff4437	745	freqCal = CMU_AUXHFRCODevinfoGet(freq);
mbed_official	50:a417edff4437	746	EFM_ASSERT((freqCal != 0) && (freqCal != UINT_MAX));
mbed_official	50:a417edff4437	747	auxHfrcoFreq = freq;
mbed_official	50:a417edff4437	748
mbed_official	50:a417edff4437	749	/* Wait for any previous sync to complete, and then set calibration data
mbed_official	50:a417edff4437	750	for the selected frequency. */
mbed_official	50:a417edff4437	751	while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT));
mbed_official	50:a417edff4437	752
mbed_official	50:a417edff4437	753	/* Set divider in AUXHFRCOCTRL for 1, 2 and 4MHz */
mbed_official	50:a417edff4437	754	switch(freq)
mbed_official	50:a417edff4437	755	{
mbed_official	50:a417edff4437	756	case cmuAUXHFRCOFreq_1M0Hz:
mbed_official	50:a417edff4437	757	freqCal = (freqCal & ~_CMU_AUXHFRCOCTRL_CLKDIV_MASK)
mbed_official	50:a417edff4437	758	\| CMU_AUXHFRCOCTRL_CLKDIV_DIV4;
mbed_official	50:a417edff4437	759	break;
mbed_official	50:a417edff4437	760
mbed_official	50:a417edff4437	761	case cmuAUXHFRCOFreq_2M0Hz:
mbed_official	50:a417edff4437	762	freqCal = (freqCal & ~_CMU_AUXHFRCOCTRL_CLKDIV_MASK)
mbed_official	50:a417edff4437	763	\| CMU_AUXHFRCOCTRL_CLKDIV_DIV2;
mbed_official	50:a417edff4437	764	break;
mbed_official	50:a417edff4437	765
mbed_official	50:a417edff4437	766	case cmuAUXHFRCOFreq_4M0Hz:
mbed_official	50:a417edff4437	767	freqCal = (freqCal & ~_CMU_AUXHFRCOCTRL_CLKDIV_MASK)
mbed_official	50:a417edff4437	768	\| CMU_AUXHFRCOCTRL_CLKDIV_DIV1;
mbed_official	50:a417edff4437	769	break;
mbed_official	50:a417edff4437	770
mbed_official	50:a417edff4437	771	default:
mbed_official	50:a417edff4437	772	break;
mbed_official	50:a417edff4437	773	}
mbed_official	50:a417edff4437	774	CMU->AUXHFRCOCTRL = freqCal;
mbed_official	50:a417edff4437	775	}
mbed_official	50:a417edff4437	776	#endif /* _CMU_AUXHFRCOCTRL_FREQRANGE_MASK */
mbed_official	50:a417edff4437	777
mbed_official	50:a417edff4437	778
bogdanm	0:9b334a45a8ff	779	/*************************************************************************//
bogdanm	0:9b334a45a8ff	780	* @brief
bogdanm	0:9b334a45a8ff	781	* Calibrate clock.
bogdanm	0:9b334a45a8ff	782	*
bogdanm	0:9b334a45a8ff	783	* @details
bogdanm	0:9b334a45a8ff	784	* Run a calibration for HFCLK against a selectable reference clock. Please
mbed_official	50:a417edff4437	785	* refer to the reference manual, CMU chapter, for further details.
bogdanm	0:9b334a45a8ff	786	*
bogdanm	0:9b334a45a8ff	787	* @note
bogdanm	0:9b334a45a8ff	788	* This function will not return until calibration measurement is completed.
bogdanm	0:9b334a45a8ff	789	*
bogdanm	0:9b334a45a8ff	790	* @param[in] HFCycles
bogdanm	0:9b334a45a8ff	791	* The number of HFCLK cycles to run calibration. Increasing this number
bogdanm	0:9b334a45a8ff	792	* increases precision, but the calibration will take more time.
bogdanm	0:9b334a45a8ff	793	*
bogdanm	0:9b334a45a8ff	794	* @param[in] ref
bogdanm	0:9b334a45a8ff	795	* The reference clock used to compare HFCLK with.
bogdanm	0:9b334a45a8ff	796	*
bogdanm	0:9b334a45a8ff	797	* @return
bogdanm	0:9b334a45a8ff	798	* The number of ticks the reference clock after HFCycles ticks on the HF
bogdanm	0:9b334a45a8ff	799	* clock.
bogdanm	0:9b334a45a8ff	800	******************************************************************************/
bogdanm	0:9b334a45a8ff	801	uint32_t CMU_Calibrate(uint32_t HFCycles, CMU_Osc_TypeDef ref)
bogdanm	0:9b334a45a8ff	802	{
bogdanm	0:9b334a45a8ff	803	EFM_ASSERT(HFCycles <= (_CMU_CALCNT_CALCNT_MASK >> _CMU_CALCNT_CALCNT_SHIFT));
bogdanm	0:9b334a45a8ff	804
bogdanm	0:9b334a45a8ff	805	/* Set reference clock source */
bogdanm	0:9b334a45a8ff	806	switch (ref)
bogdanm	0:9b334a45a8ff	807	{
mbed_official	50:a417edff4437	808	case cmuOsc_LFXO:
mbed_official	50:a417edff4437	809	CMU->CALCTRL = CMU_CALCTRL_UPSEL_LFXO;
mbed_official	50:a417edff4437	810	break;
mbed_official	50:a417edff4437	811
mbed_official	50:a417edff4437	812	case cmuOsc_LFRCO:
mbed_official	50:a417edff4437	813	CMU->CALCTRL = CMU_CALCTRL_UPSEL_LFRCO;
mbed_official	50:a417edff4437	814	break;
mbed_official	50:a417edff4437	815
mbed_official	50:a417edff4437	816	case cmuOsc_HFXO:
mbed_official	50:a417edff4437	817	CMU->CALCTRL = CMU_CALCTRL_UPSEL_HFXO;
mbed_official	50:a417edff4437	818	break;
mbed_official	50:a417edff4437	819
mbed_official	50:a417edff4437	820	case cmuOsc_HFRCO:
mbed_official	50:a417edff4437	821	CMU->CALCTRL = CMU_CALCTRL_UPSEL_HFRCO;
mbed_official	50:a417edff4437	822	break;
mbed_official	50:a417edff4437	823
mbed_official	50:a417edff4437	824	case cmuOsc_AUXHFRCO:
mbed_official	50:a417edff4437	825	CMU->CALCTRL = CMU_CALCTRL_UPSEL_AUXHFRCO;
mbed_official	50:a417edff4437	826	break;
mbed_official	50:a417edff4437	827
mbed_official	50:a417edff4437	828	default:
mbed_official	50:a417edff4437	829	EFM_ASSERT(0);
mbed_official	50:a417edff4437	830	return 0;
bogdanm	0:9b334a45a8ff	831	}
bogdanm	0:9b334a45a8ff	832
bogdanm	0:9b334a45a8ff	833	/* Set top value */
bogdanm	0:9b334a45a8ff	834	CMU->CALCNT = HFCycles;
bogdanm	0:9b334a45a8ff	835
bogdanm	0:9b334a45a8ff	836	/* Start calibration */
bogdanm	0:9b334a45a8ff	837	CMU->CMD = CMU_CMD_CALSTART;
bogdanm	0:9b334a45a8ff	838
mbed_official	50:a417edff4437	839	#if defined( CMU_STATUS_CALRDY )
bogdanm	0:9b334a45a8ff	840	/* Wait until calibration completes */
mbed_official	50:a417edff4437	841	while (!BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALRDY_SHIFT))
mbed_official	50:a417edff4437	842	{
mbed_official	50:a417edff4437	843	}
mbed_official	50:a417edff4437	844	#else
mbed_official	50:a417edff4437	845	/* Wait until calibration completes */
mbed_official	50:a417edff4437	846	while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALBSY_SHIFT))
mbed_official	50:a417edff4437	847	{
mbed_official	50:a417edff4437	848	}
mbed_official	50:a417edff4437	849	#endif
bogdanm	0:9b334a45a8ff	850
bogdanm	0:9b334a45a8ff	851	return CMU->CALCNT;
bogdanm	0:9b334a45a8ff	852	}
bogdanm	0:9b334a45a8ff	853
bogdanm	0:9b334a45a8ff	854
bogdanm	0:9b334a45a8ff	855	#if defined( _CMU_CALCTRL_UPSEL_MASK ) && defined( _CMU_CALCTRL_DOWNSEL_MASK )
bogdanm	0:9b334a45a8ff	856	/*************************************************************************//
bogdanm	0:9b334a45a8ff	857	* @brief
bogdanm	0:9b334a45a8ff	858	* Configure clock calibration
bogdanm	0:9b334a45a8ff	859	*
bogdanm	0:9b334a45a8ff	860	* @details
bogdanm	0:9b334a45a8ff	861	* Configure a calibration for a selectable clock source against another
bogdanm	0:9b334a45a8ff	862	* selectable reference clock.
mbed_official	50:a417edff4437	863	* Refer to the reference manual, CMU chapter, for further details.
bogdanm	0:9b334a45a8ff	864	*
bogdanm	0:9b334a45a8ff	865	* @note
bogdanm	0:9b334a45a8ff	866	* After configuration, a call to CMU_CalibrateStart() is required, and
bogdanm	0:9b334a45a8ff	867	* the resulting calibration value can be read out with the
bogdanm	0:9b334a45a8ff	868	* CMU_CalibrateCountGet() function call.
bogdanm	0:9b334a45a8ff	869	*
bogdanm	0:9b334a45a8ff	870	* @param[in] downCycles
bogdanm	0:9b334a45a8ff	871	* The number of downSel clock cycles to run calibration. Increasing this
bogdanm	0:9b334a45a8ff	872	* number increases precision, but the calibration will take more time.
bogdanm	0:9b334a45a8ff	873	*
bogdanm	0:9b334a45a8ff	874	* @param[in] downSel
bogdanm	0:9b334a45a8ff	875	* The clock which will be counted down downCycles
bogdanm	0:9b334a45a8ff	876	*
bogdanm	0:9b334a45a8ff	877	* @param[in] upSel
bogdanm	0:9b334a45a8ff	878	* The reference clock, the number of cycles generated by this clock will
bogdanm	0:9b334a45a8ff	879	* be counted and added up, the result can be given with the
bogdanm	0:9b334a45a8ff	880	* CMU_CalibrateCountGet() function call.
bogdanm	0:9b334a45a8ff	881	******************************************************************************/
bogdanm	0:9b334a45a8ff	882	void CMU_CalibrateConfig(uint32_t downCycles, CMU_Osc_TypeDef downSel,
bogdanm	0:9b334a45a8ff	883	CMU_Osc_TypeDef upSel)
bogdanm	0:9b334a45a8ff	884	{
bogdanm	0:9b334a45a8ff	885	/* Keep untouched configuration settings */
mbed_official	50:a417edff4437	886	uint32_t calCtrl = CMU->CALCTRL
mbed_official	50:a417edff4437	887	& ~(_CMU_CALCTRL_UPSEL_MASK \| _CMU_CALCTRL_DOWNSEL_MASK);
bogdanm	0:9b334a45a8ff	888
bogdanm	0:9b334a45a8ff	889	/* 20 bits of precision to calibration count register */
bogdanm	0:9b334a45a8ff	890	EFM_ASSERT(downCycles <= (_CMU_CALCNT_CALCNT_MASK >> _CMU_CALCNT_CALCNT_SHIFT));
bogdanm	0:9b334a45a8ff	891
bogdanm	0:9b334a45a8ff	892	/* Set down counting clock source - down counter */
bogdanm	0:9b334a45a8ff	893	switch (downSel)
bogdanm	0:9b334a45a8ff	894	{
mbed_official	50:a417edff4437	895	case cmuOsc_LFXO:
mbed_official	50:a417edff4437	896	calCtrl \|= CMU_CALCTRL_DOWNSEL_LFXO;
mbed_official	50:a417edff4437	897	break;
mbed_official	50:a417edff4437	898
mbed_official	50:a417edff4437	899	case cmuOsc_LFRCO:
mbed_official	50:a417edff4437	900	calCtrl \|= CMU_CALCTRL_DOWNSEL_LFRCO;
mbed_official	50:a417edff4437	901	break;
mbed_official	50:a417edff4437	902
mbed_official	50:a417edff4437	903	case cmuOsc_HFXO:
mbed_official	50:a417edff4437	904	calCtrl \|= CMU_CALCTRL_DOWNSEL_HFXO;
mbed_official	50:a417edff4437	905	break;
mbed_official	50:a417edff4437	906
mbed_official	50:a417edff4437	907	case cmuOsc_HFRCO:
mbed_official	50:a417edff4437	908	calCtrl \|= CMU_CALCTRL_DOWNSEL_HFRCO;
mbed_official	50:a417edff4437	909	break;
mbed_official	50:a417edff4437	910
mbed_official	50:a417edff4437	911	case cmuOsc_AUXHFRCO:
mbed_official	50:a417edff4437	912	calCtrl \|= CMU_CALCTRL_DOWNSEL_AUXHFRCO;
mbed_official	50:a417edff4437	913	break;
mbed_official	50:a417edff4437	914
mbed_official	50:a417edff4437	915	default:
mbed_official	50:a417edff4437	916	EFM_ASSERT(0);
mbed_official	50:a417edff4437	917	break;
bogdanm	0:9b334a45a8ff	918	}
bogdanm	0:9b334a45a8ff	919
bogdanm	0:9b334a45a8ff	920	/* Set top value to be counted down by the downSel clock */
bogdanm	0:9b334a45a8ff	921	CMU->CALCNT = downCycles;
bogdanm	0:9b334a45a8ff	922
bogdanm	0:9b334a45a8ff	923	/* Set reference clock source - up counter */
bogdanm	0:9b334a45a8ff	924	switch (upSel)
bogdanm	0:9b334a45a8ff	925	{
mbed_official	50:a417edff4437	926	case cmuOsc_LFXO:
mbed_official	50:a417edff4437	927	calCtrl \|= CMU_CALCTRL_UPSEL_LFXO;
mbed_official	50:a417edff4437	928	break;
mbed_official	50:a417edff4437	929
mbed_official	50:a417edff4437	930	case cmuOsc_LFRCO:
mbed_official	50:a417edff4437	931	calCtrl \|= CMU_CALCTRL_UPSEL_LFRCO;
mbed_official	50:a417edff4437	932	break;
mbed_official	50:a417edff4437	933
mbed_official	50:a417edff4437	934	case cmuOsc_HFXO:
mbed_official	50:a417edff4437	935	calCtrl \|= CMU_CALCTRL_UPSEL_HFXO;
mbed_official	50:a417edff4437	936	break;
mbed_official	50:a417edff4437	937
mbed_official	50:a417edff4437	938	case cmuOsc_HFRCO:
mbed_official	50:a417edff4437	939	calCtrl \|= CMU_CALCTRL_UPSEL_HFRCO;
mbed_official	50:a417edff4437	940	break;
mbed_official	50:a417edff4437	941
mbed_official	50:a417edff4437	942	case cmuOsc_AUXHFRCO:
mbed_official	50:a417edff4437	943	calCtrl \|= CMU_CALCTRL_UPSEL_AUXHFRCO;
mbed_official	50:a417edff4437	944	break;
mbed_official	50:a417edff4437	945
mbed_official	50:a417edff4437	946	default:
mbed_official	50:a417edff4437	947	EFM_ASSERT(0);
mbed_official	50:a417edff4437	948	break;
bogdanm	0:9b334a45a8ff	949	}
bogdanm	0:9b334a45a8ff	950
bogdanm	0:9b334a45a8ff	951	CMU->CALCTRL = calCtrl;
bogdanm	0:9b334a45a8ff	952	}
bogdanm	0:9b334a45a8ff	953	#endif
bogdanm	0:9b334a45a8ff	954
bogdanm	0:9b334a45a8ff	955
bogdanm	0:9b334a45a8ff	956	/*************************************************************************//
bogdanm	0:9b334a45a8ff	957	* @brief
mbed_official	50:a417edff4437	958	* Get calibration count register
mbed_official	50:a417edff4437	959	* @note
mbed_official	50:a417edff4437	960	* If continuous calibrartion mode is active, calibration busy will almost
mbed_official	50:a417edff4437	961	* always be off, and we just need to read the value, where the normal case
mbed_official	50:a417edff4437	962	* would be that this function call has been triggered by the CALRDY
mbed_official	50:a417edff4437	963	* interrupt flag.
mbed_official	50:a417edff4437	964	* @return
mbed_official	50:a417edff4437	965	* Calibration count, the number of UPSEL clocks (see CMU_CalibrateConfig)
mbed_official	50:a417edff4437	966	* in the period of DOWNSEL oscillator clock cycles configured by a previous
mbed_official	50:a417edff4437	967	* write operation to CMU->CALCNT
mbed_official	50:a417edff4437	968	******************************************************************************/
mbed_official	50:a417edff4437	969	uint32_t CMU_CalibrateCountGet(void)
mbed_official	50:a417edff4437	970	{
mbed_official	50:a417edff4437	971	/* Wait until calibration completes, UNLESS continuous calibration mode is */
mbed_official	50:a417edff4437	972	/* active */
mbed_official	50:a417edff4437	973	#if defined( CMU_CALCTRL_CONT )
mbed_official	50:a417edff4437	974	if (!BUS_RegBitRead(&CMU->CALCTRL, _CMU_CALCTRL_CONT_SHIFT))
mbed_official	50:a417edff4437	975	{
mbed_official	50:a417edff4437	976	#if defined( CMU_STATUS_CALRDY )
mbed_official	50:a417edff4437	977	/* Wait until calibration completes */
mbed_official	50:a417edff4437	978	while (!BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALRDY_SHIFT))
mbed_official	50:a417edff4437	979	{
mbed_official	50:a417edff4437	980	}
mbed_official	50:a417edff4437	981	#else
mbed_official	50:a417edff4437	982	/* Wait until calibration completes */
mbed_official	50:a417edff4437	983	while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALBSY_SHIFT))
mbed_official	50:a417edff4437	984	{
mbed_official	50:a417edff4437	985	}
mbed_official	50:a417edff4437	986	#endif
mbed_official	50:a417edff4437	987	}
mbed_official	50:a417edff4437	988	#else
mbed_official	50:a417edff4437	989	while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALBSY_SHIFT))
mbed_official	50:a417edff4437	990	{
mbed_official	50:a417edff4437	991	}
mbed_official	50:a417edff4437	992	#endif
mbed_official	50:a417edff4437	993	return CMU->CALCNT;
mbed_official	50:a417edff4437	994	}
mbed_official	50:a417edff4437	995
mbed_official	50:a417edff4437	996
mbed_official	50:a417edff4437	997	/*************************************************************************//
mbed_official	50:a417edff4437	998	* @brief
bogdanm	0:9b334a45a8ff	999	* Get clock divisor/prescaler.
bogdanm	0:9b334a45a8ff	1000	*
bogdanm	0:9b334a45a8ff	1001	* @param[in] clock
bogdanm	0:9b334a45a8ff	1002	* Clock point to get divisor/prescaler for. Notice that not all clock points
bogdanm	0:9b334a45a8ff	1003	* have a divisor/prescaler. Please refer to CMU overview in reference manual.
bogdanm	0:9b334a45a8ff	1004	*
bogdanm	0:9b334a45a8ff	1005	* @return
bogdanm	0:9b334a45a8ff	1006	* The current clock point divisor/prescaler. 1 is returned
bogdanm	0:9b334a45a8ff	1007	* if @p clock specifies a clock point without a divisor/prescaler.
bogdanm	0:9b334a45a8ff	1008	******************************************************************************/
bogdanm	0:9b334a45a8ff	1009	CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock)
bogdanm	0:9b334a45a8ff	1010	{
mbed_official	50:a417edff4437	1011	#if defined( _SILICON_LABS_32B_PLATFORM_2 )
mbed_official	50:a417edff4437	1012	return 1 + (uint32_t)CMU_ClockPrescGet(clock);
mbed_official	50:a417edff4437	1013
mbed_official	50:a417edff4437	1014	#elif defined( _SILICON_LABS_32B_PLATFORM_1 )
bogdanm	0:9b334a45a8ff	1015	uint32_t divReg;
bogdanm	0:9b334a45a8ff	1016	CMU_ClkDiv_TypeDef ret;
bogdanm	0:9b334a45a8ff	1017
bogdanm	0:9b334a45a8ff	1018	/* Get divisor reg id */
bogdanm	0:9b334a45a8ff	1019	divReg = (clock >> CMU_DIV_REG_POS) & CMU_DIV_REG_MASK;
bogdanm	0:9b334a45a8ff	1020
bogdanm	0:9b334a45a8ff	1021	switch (divReg)
bogdanm	0:9b334a45a8ff	1022	{
bogdanm	0:9b334a45a8ff	1023	#if defined( _CMU_CTRL_HFCLKDIV_MASK )
mbed_official	50:a417edff4437	1024	case CMU_HFCLKDIV_REG:
mbed_official	50:a417edff4437	1025	ret = 1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK)
mbed_official	50:a417edff4437	1026	>> _CMU_CTRL_HFCLKDIV_SHIFT);
mbed_official	50:a417edff4437	1027	break;
bogdanm	0:9b334a45a8ff	1028	#endif
bogdanm	0:9b334a45a8ff	1029
mbed_official	50:a417edff4437	1030	case CMU_HFPERCLKDIV_REG:
mbed_official	50:a417edff4437	1031	ret = (CMU_ClkDiv_TypeDef)((CMU->HFPERCLKDIV
mbed_official	50:a417edff4437	1032	& _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK)
mbed_official	50:a417edff4437	1033	>> _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT);
bogdanm	0:9b334a45a8ff	1034	ret = CMU_Log2ToDiv(ret);
bogdanm	0:9b334a45a8ff	1035	break;
bogdanm	0:9b334a45a8ff	1036
mbed_official	50:a417edff4437	1037	case CMU_HFCORECLKDIV_REG:
mbed_official	50:a417edff4437	1038	ret = (CMU_ClkDiv_TypeDef)((CMU->HFCORECLKDIV
mbed_official	50:a417edff4437	1039	& _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK)
mbed_official	50:a417edff4437	1040	>> _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT);
bogdanm	0:9b334a45a8ff	1041	ret = CMU_Log2ToDiv(ret);
bogdanm	0:9b334a45a8ff	1042	break;
mbed_official	50:a417edff4437	1043
mbed_official	50:a417edff4437	1044	case CMU_LFAPRESC0_REG:
mbed_official	50:a417edff4437	1045	switch (clock)
mbed_official	50:a417edff4437	1046	{
mbed_official	50:a417edff4437	1047	case cmuClock_RTC:
mbed_official	50:a417edff4437	1048	ret = (CMU_ClkDiv_TypeDef)((CMU->LFAPRESC0 & _CMU_LFAPRESC0_RTC_MASK)
mbed_official	50:a417edff4437	1049	>> _CMU_LFAPRESC0_RTC_SHIFT);
mbed_official	50:a417edff4437	1050	ret = CMU_Log2ToDiv(ret);
mbed_official	50:a417edff4437	1051	break;
mbed_official	50:a417edff4437	1052
mbed_official	50:a417edff4437	1053	#if defined(_CMU_LFAPRESC0_LETIMER0_MASK)
mbed_official	50:a417edff4437	1054	case cmuClock_LETIMER0:
mbed_official	50:a417edff4437	1055	ret = (CMU_ClkDiv_TypeDef)((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK)
mbed_official	50:a417edff4437	1056	>> _CMU_LFAPRESC0_LETIMER0_SHIFT);
mbed_official	50:a417edff4437	1057	ret = CMU_Log2ToDiv(ret);
mbed_official	50:a417edff4437	1058	break;
bogdanm	0:9b334a45a8ff	1059	#endif
bogdanm	0:9b334a45a8ff	1060
bogdanm	0:9b334a45a8ff	1061	#if defined(_CMU_LFAPRESC0_LCD_MASK)
mbed_official	50:a417edff4437	1062	case cmuClock_LCDpre:
mbed_official	50:a417edff4437	1063	ret = (CMU_ClkDiv_TypeDef)(((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK)
mbed_official	50:a417edff4437	1064	>> _CMU_LFAPRESC0_LCD_SHIFT)
mbed_official	50:a417edff4437	1065	+ CMU_DivToLog2(cmuClkDiv_16));
mbed_official	50:a417edff4437	1066	ret = CMU_Log2ToDiv(ret);
mbed_official	50:a417edff4437	1067	break;
bogdanm	0:9b334a45a8ff	1068	#endif
bogdanm	0:9b334a45a8ff	1069
bogdanm	0:9b334a45a8ff	1070	#if defined(_CMU_LFAPRESC0_LESENSE_MASK)
mbed_official	50:a417edff4437	1071	case cmuClock_LESENSE:
mbed_official	50:a417edff4437	1072	ret = (CMU_ClkDiv_TypeDef)((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LESENSE_MASK)
mbed_official	50:a417edff4437	1073	>> _CMU_LFAPRESC0_LESENSE_SHIFT);
mbed_official	50:a417edff4437	1074	ret = CMU_Log2ToDiv(ret);
mbed_official	50:a417edff4437	1075	break;
mbed_official	50:a417edff4437	1076	#endif
mbed_official	50:a417edff4437	1077
mbed_official	50:a417edff4437	1078	default:
mbed_official	50:a417edff4437	1079	EFM_ASSERT(0);
mbed_official	50:a417edff4437	1080	ret = cmuClkDiv_1;
mbed_official	50:a417edff4437	1081	break;
mbed_official	50:a417edff4437	1082	}
bogdanm	0:9b334a45a8ff	1083	break;
mbed_official	50:a417edff4437	1084
mbed_official	50:a417edff4437	1085	case CMU_LFBPRESC0_REG:
mbed_official	50:a417edff4437	1086	switch (clock)
mbed_official	50:a417edff4437	1087	{
mbed_official	50:a417edff4437	1088	#if defined(_CMU_LFBPRESC0_LEUART0_MASK)
mbed_official	50:a417edff4437	1089	case cmuClock_LEUART0:
mbed_official	50:a417edff4437	1090	ret = (CMU_ClkDiv_TypeDef)((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK)
mbed_official	50:a417edff4437	1091	>> _CMU_LFBPRESC0_LEUART0_SHIFT);
mbed_official	50:a417edff4437	1092	ret = CMU_Log2ToDiv(ret);
mbed_official	50:a417edff4437	1093	break;
bogdanm	0:9b334a45a8ff	1094	#endif
bogdanm	0:9b334a45a8ff	1095
mbed_official	50:a417edff4437	1096	#if defined(_CMU_LFBPRESC0_LEUART1_MASK)
mbed_official	50:a417edff4437	1097	case cmuClock_LEUART1:
mbed_official	50:a417edff4437	1098	ret = (CMU_ClkDiv_TypeDef)((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK)
mbed_official	50:a417edff4437	1099	>> _CMU_LFBPRESC0_LEUART1_SHIFT);
mbed_official	50:a417edff4437	1100	ret = CMU_Log2ToDiv(ret);
mbed_official	50:a417edff4437	1101	break;
mbed_official	50:a417edff4437	1102	#endif
mbed_official	50:a417edff4437	1103
mbed_official	50:a417edff4437	1104	default:
mbed_official	50:a417edff4437	1105	EFM_ASSERT(0);
mbed_official	50:a417edff4437	1106	ret = cmuClkDiv_1;
mbed_official	50:a417edff4437	1107	break;
mbed_official	50:a417edff4437	1108	}
mbed_official	50:a417edff4437	1109	break;
mbed_official	50:a417edff4437	1110
bogdanm	0:9b334a45a8ff	1111	default:
bogdanm	0:9b334a45a8ff	1112	EFM_ASSERT(0);
bogdanm	0:9b334a45a8ff	1113	ret = cmuClkDiv_1;
bogdanm	0:9b334a45a8ff	1114	break;
mbed_official	50:a417edff4437	1115	}
mbed_official	50:a417edff4437	1116
mbed_official	50:a417edff4437	1117	return ret;
bogdanm	0:9b334a45a8ff	1118	#endif
bogdanm	0:9b334a45a8ff	1119	}
bogdanm	0:9b334a45a8ff	1120
bogdanm	0:9b334a45a8ff	1121
bogdanm	0:9b334a45a8ff	1122	/*************************************************************************//
bogdanm	0:9b334a45a8ff	1123	* @brief
bogdanm	0:9b334a45a8ff	1124	* Set clock divisor/prescaler.
bogdanm	0:9b334a45a8ff	1125	*
bogdanm	0:9b334a45a8ff	1126	* @note
bogdanm	0:9b334a45a8ff	1127	* If setting a LF clock prescaler, synchronization into the low frequency
bogdanm	0:9b334a45a8ff	1128	* domain is required. If the same register is modified before a previous
bogdanm	0:9b334a45a8ff	1129	* update has completed, this function will stall until the previous
bogdanm	0:9b334a45a8ff	1130	* synchronization has completed. Please refer to CMU_FreezeEnable() for
bogdanm	0:9b334a45a8ff	1131	* a suggestion on how to reduce stalling time in some use cases.
bogdanm	0:9b334a45a8ff	1132	*
bogdanm	0:9b334a45a8ff	1133	* @param[in] clock
bogdanm	0:9b334a45a8ff	1134	* Clock point to set divisor/prescaler for. Notice that not all clock points
bogdanm	0:9b334a45a8ff	1135	* have a divisor/prescaler, please refer to CMU overview in the reference
bogdanm	0:9b334a45a8ff	1136	* manual.
bogdanm	0:9b334a45a8ff	1137	*
bogdanm	0:9b334a45a8ff	1138	* @param[in] div
bogdanm	0:9b334a45a8ff	1139	* The clock divisor to use (<= cmuClkDiv_512).
bogdanm	0:9b334a45a8ff	1140	******************************************************************************/
bogdanm	0:9b334a45a8ff	1141	void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div)
bogdanm	0:9b334a45a8ff	1142	{
mbed_official	50:a417edff4437	1143	#if defined( _SILICON_LABS_32B_PLATFORM_2 )
mbed_official	50:a417edff4437	1144	CMU_ClockPrescSet(clock, (CMU_ClkPresc_TypeDef)(div - 1));
mbed_official	50:a417edff4437	1145
mbed_official	50:a417edff4437	1146	#elif defined( _SILICON_LABS_32B_PLATFORM_1 )
bogdanm	0:9b334a45a8ff	1147	uint32_t freq;
bogdanm	0:9b334a45a8ff	1148	uint32_t divReg;
bogdanm	0:9b334a45a8ff	1149
bogdanm	0:9b334a45a8ff	1150	/* Get divisor reg id */
bogdanm	0:9b334a45a8ff	1151	divReg = (clock >> CMU_DIV_REG_POS) & CMU_DIV_REG_MASK;
bogdanm	0:9b334a45a8ff	1152
bogdanm	0:9b334a45a8ff	1153	switch (divReg)
bogdanm	0:9b334a45a8ff	1154	{
bogdanm	0:9b334a45a8ff	1155	#if defined( _CMU_CTRL_HFCLKDIV_MASK )
mbed_official	50:a417edff4437	1156	case CMU_HFCLKDIV_REG:
mbed_official	50:a417edff4437	1157	EFM_ASSERT((div>=cmuClkDiv_1) && (div<=cmuClkDiv_8));
mbed_official	50:a417edff4437	1158
mbed_official	50:a417edff4437	1159	/* Configure worst case wait states for flash access before setting divisor */
mbed_official	50:a417edff4437	1160	flashWaitStateMax();
mbed_official	50:a417edff4437	1161
mbed_official	50:a417edff4437	1162	/* Set divider */
mbed_official	50:a417edff4437	1163	CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFCLKDIV_MASK)
mbed_official	50:a417edff4437	1164	\| ((div-1) << _CMU_CTRL_HFCLKDIV_SHIFT);
mbed_official	50:a417edff4437	1165
mbed_official	50:a417edff4437	1166	/* Update CMSIS core clock variable */
mbed_official	50:a417edff4437	1167	/* (The function will update the global variable) */
mbed_official	50:a417edff4437	1168	freq = SystemCoreClockGet();
mbed_official	50:a417edff4437	1169
mbed_official	50:a417edff4437	1170	/* Optimize flash access wait state setting for current core clk */
mbed_official	50:a417edff4437	1171	flashWaitStateControl(freq);
mbed_official	50:a417edff4437	1172	break;
bogdanm	0:9b334a45a8ff	1173	#endif
bogdanm	0:9b334a45a8ff	1174
mbed_official	50:a417edff4437	1175	case CMU_HFPERCLKDIV_REG:
mbed_official	50:a417edff4437	1176	EFM_ASSERT((div >= cmuClkDiv_1) && (div <= cmuClkDiv_512));
mbed_official	50:a417edff4437	1177	/* Convert to correct scale */
mbed_official	50:a417edff4437	1178	div = CMU_DivToLog2(div);
mbed_official	50:a417edff4437	1179	CMU->HFPERCLKDIV = (CMU->HFPERCLKDIV & ~_CMU_HFPERCLKDIV_HFPERCLKDIV_MASK)
mbed_official	50:a417edff4437	1180	\| (div << _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT);
mbed_official	50:a417edff4437	1181	break;
mbed_official	50:a417edff4437	1182
mbed_official	50:a417edff4437	1183	case CMU_HFCORECLKDIV_REG:
mbed_official	50:a417edff4437	1184	EFM_ASSERT(div <= cmuClkDiv_512);
mbed_official	50:a417edff4437	1185
mbed_official	50:a417edff4437	1186	/* Configure worst case wait states for flash access before setting divisor */
mbed_official	50:a417edff4437	1187	flashWaitStateMax();
bogdanm	0:9b334a45a8ff	1188
bogdanm	0:9b334a45a8ff	1189	#if defined( CMU_CTRL_HFLE )
mbed_official	50:a417edff4437	1190	/* Clear HFLE and set DIV2 factor for peripheral clock
mbed_official	50:a417edff4437	1191	when running at frequencies lower than or equal to CMU_MAX_FREQ_HFLE. */
mbed_official	50:a417edff4437	1192	if ((CMU_ClockFreqGet(cmuClock_HF) / div) <= CMU_MAX_FREQ_HFLE())
mbed_official	50:a417edff4437	1193	{
mbed_official	50:a417edff4437	1194	/* Clear CMU HFLE */
mbed_official	50:a417edff4437	1195	BUS_RegBitWrite(&CMU->CTRL, _CMU_CTRL_HFLE_SHIFT, 0);
mbed_official	50:a417edff4437	1196
mbed_official	50:a417edff4437	1197	/* Set DIV2 factor for peripheral clock */
mbed_official	50:a417edff4437	1198	BUS_RegBitWrite(&CMU->HFCORECLKDIV,
mbed_official	50:a417edff4437	1199	_CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 0);
mbed_official	50:a417edff4437	1200	}
mbed_official	50:a417edff4437	1201	else
mbed_official	50:a417edff4437	1202	{
mbed_official	50:a417edff4437	1203	/* Set CMU HFLE */
mbed_official	50:a417edff4437	1204	BUS_RegBitWrite(&CMU->CTRL, _CMU_CTRL_HFLE_SHIFT, 1);
mbed_official	50:a417edff4437	1205
mbed_official	50:a417edff4437	1206	/* Set DIV4 factor for peripheral clock */
mbed_official	50:a417edff4437	1207	BUS_RegBitWrite(&CMU->HFCORECLKDIV,
mbed_official	50:a417edff4437	1208	_CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 1);
mbed_official	50:a417edff4437	1209	}
bogdanm	0:9b334a45a8ff	1210	#endif
bogdanm	0:9b334a45a8ff	1211
bogdanm	0:9b334a45a8ff	1212	/* Convert to correct scale */
bogdanm	0:9b334a45a8ff	1213	div = CMU_DivToLog2(div);
bogdanm	0:9b334a45a8ff	1214
mbed_official	50:a417edff4437	1215	CMU->HFCORECLKDIV = (CMU->HFCORECLKDIV
mbed_official	50:a417edff4437	1216	& ~_CMU_HFCORECLKDIV_HFCORECLKDIV_MASK)
mbed_official	50:a417edff4437	1217	\| (div << _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT);
mbed_official	50:a417edff4437	1218
mbed_official	50:a417edff4437	1219	/* Update CMSIS core clock variable */
mbed_official	50:a417edff4437	1220	/* (The function will update the global variable) */
mbed_official	50:a417edff4437	1221	freq = SystemCoreClockGet();
mbed_official	50:a417edff4437	1222
mbed_official	50:a417edff4437	1223	/* Optimize flash access wait state setting for current core clk */
mbed_official	50:a417edff4437	1224	flashWaitStateControl(freq);
bogdanm	0:9b334a45a8ff	1225	break;
bogdanm	0:9b334a45a8ff	1226
mbed_official	50:a417edff4437	1227	case CMU_LFAPRESC0_REG:
mbed_official	50:a417edff4437	1228	switch (clock)
mbed_official	50:a417edff4437	1229	{
mbed_official	50:a417edff4437	1230	case cmuClock_RTC:
mbed_official	50:a417edff4437	1231	EFM_ASSERT(div <= cmuClkDiv_32768);
mbed_official	50:a417edff4437	1232
mbed_official	50:a417edff4437	1233	/* LF register about to be modified require sync. busy check */
mbed_official	50:a417edff4437	1234	syncReg(CMU_SYNCBUSY_LFAPRESC0);
mbed_official	50:a417edff4437	1235
mbed_official	50:a417edff4437	1236	/* Convert to correct scale */
mbed_official	50:a417edff4437	1237	div = CMU_DivToLog2(div);
mbed_official	50:a417edff4437	1238
mbed_official	50:a417edff4437	1239	CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTC_MASK)
mbed_official	50:a417edff4437	1240	\| (div << _CMU_LFAPRESC0_RTC_SHIFT);
mbed_official	50:a417edff4437	1241	break;
mbed_official	50:a417edff4437	1242
bogdanm	0:9b334a45a8ff	1243	#if defined(_CMU_LFAPRESC0_LETIMER0_MASK)
mbed_official	50:a417edff4437	1244	case cmuClock_LETIMER0:
mbed_official	50:a417edff4437	1245	EFM_ASSERT(div <= cmuClkDiv_32768);
mbed_official	50:a417edff4437	1246
mbed_official	50:a417edff4437	1247	/* LF register about to be modified require sync. busy check */
mbed_official	50:a417edff4437	1248	syncReg(CMU_SYNCBUSY_LFAPRESC0);
mbed_official	50:a417edff4437	1249
mbed_official	50:a417edff4437	1250	/* Convert to correct scale */
mbed_official	50:a417edff4437	1251	div = CMU_DivToLog2(div);
mbed_official	50:a417edff4437	1252
mbed_official	50:a417edff4437	1253	CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LETIMER0_MASK)
mbed_official	50:a417edff4437	1254	\| (div << _CMU_LFAPRESC0_LETIMER0_SHIFT);
mbed_official	50:a417edff4437	1255	break;
bogdanm	0:9b334a45a8ff	1256	#endif
bogdanm	0:9b334a45a8ff	1257
bogdanm	0:9b334a45a8ff	1258	#if defined(LCD_PRESENT)
mbed_official	50:a417edff4437	1259	case cmuClock_LCDpre:
mbed_official	50:a417edff4437	1260	EFM_ASSERT((div >= cmuClkDiv_16) && (div <= cmuClkDiv_128));
mbed_official	50:a417edff4437	1261
mbed_official	50:a417edff4437	1262	/* LF register about to be modified require sync. busy check */
mbed_official	50:a417edff4437	1263	syncReg(CMU_SYNCBUSY_LFAPRESC0);
mbed_official	50:a417edff4437	1264
mbed_official	50:a417edff4437	1265	/* Convert to correct scale */
mbed_official	50:a417edff4437	1266	div = CMU_DivToLog2(div);
mbed_official	50:a417edff4437	1267
mbed_official	50:a417edff4437	1268	CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LCD_MASK)
mbed_official	50:a417edff4437	1269	\| ((div - CMU_DivToLog2(cmuClkDiv_16))
mbed_official	50:a417edff4437	1270	<< _CMU_LFAPRESC0_LCD_SHIFT);
mbed_official	50:a417edff4437	1271	break;
bogdanm	0:9b334a45a8ff	1272	#endif /* defined(LCD_PRESENT) */
bogdanm	0:9b334a45a8ff	1273
bogdanm	0:9b334a45a8ff	1274	#if defined(LESENSE_PRESENT)
mbed_official	50:a417edff4437	1275	case cmuClock_LESENSE:
mbed_official	50:a417edff4437	1276	EFM_ASSERT(div <= cmuClkDiv_8);
mbed_official	50:a417edff4437	1277
mbed_official	50:a417edff4437	1278	/* LF register about to be modified require sync. busy check */
mbed_official	50:a417edff4437	1279	syncReg(CMU_SYNCBUSY_LFAPRESC0);
mbed_official	50:a417edff4437	1280
mbed_official	50:a417edff4437	1281	/* Convert to correct scale */
mbed_official	50:a417edff4437	1282	div = CMU_DivToLog2(div);
mbed_official	50:a417edff4437	1283
mbed_official	50:a417edff4437	1284	CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LESENSE_MASK)
mbed_official	50:a417edff4437	1285	\| (div << _CMU_LFAPRESC0_LESENSE_SHIFT);
mbed_official	50:a417edff4437	1286	break;
mbed_official	50:a417edff4437	1287	#endif /* defined(LESENSE_PRESENT) */
mbed_official	50:a417edff4437	1288
mbed_official	50:a417edff4437	1289	default:
mbed_official	50:a417edff4437	1290	EFM_ASSERT(0);
mbed_official	50:a417edff4437	1291	break;
mbed_official	50:a417edff4437	1292	}
bogdanm	0:9b334a45a8ff	1293	break;
mbed_official	50:a417edff4437	1294
mbed_official	50:a417edff4437	1295	case CMU_LFBPRESC0_REG:
mbed_official	50:a417edff4437	1296	switch (clock)
mbed_official	50:a417edff4437	1297	{
mbed_official	50:a417edff4437	1298	#if defined(_CMU_LFBPRESC0_LEUART0_MASK)
mbed_official	50:a417edff4437	1299	case cmuClock_LEUART0:
mbed_official	50:a417edff4437	1300	EFM_ASSERT(div <= cmuClkDiv_8);
mbed_official	50:a417edff4437	1301
mbed_official	50:a417edff4437	1302	/* LF register about to be modified require sync. busy check */
mbed_official	50:a417edff4437	1303	syncReg(CMU_SYNCBUSY_LFBPRESC0);
mbed_official	50:a417edff4437	1304
mbed_official	50:a417edff4437	1305	/* Convert to correct scale */
mbed_official	50:a417edff4437	1306	div = CMU_DivToLog2(div);
mbed_official	50:a417edff4437	1307
mbed_official	50:a417edff4437	1308	CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART0_MASK)
mbed_official	50:a417edff4437	1309	\| (((uint32_t)div) << _CMU_LFBPRESC0_LEUART0_SHIFT);
mbed_official	50:a417edff4437	1310	break;
mbed_official	50:a417edff4437	1311	#endif
mbed_official	50:a417edff4437	1312
mbed_official	50:a417edff4437	1313	#if defined(_CMU_LFBPRESC0_LEUART1_MASK)
mbed_official	50:a417edff4437	1314	case cmuClock_LEUART1:
mbed_official	50:a417edff4437	1315	EFM_ASSERT(div <= cmuClkDiv_8);
mbed_official	50:a417edff4437	1316
mbed_official	50:a417edff4437	1317	/* LF register about to be modified require sync. busy check */
mbed_official	50:a417edff4437	1318	syncReg(CMU_SYNCBUSY_LFBPRESC0);
mbed_official	50:a417edff4437	1319
mbed_official	50:a417edff4437	1320	/* Convert to correct scale */
mbed_official	50:a417edff4437	1321	div = CMU_DivToLog2(div);
mbed_official	50:a417edff4437	1322
mbed_official	50:a417edff4437	1323	CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART1_MASK)
mbed_official	50:a417edff4437	1324	\| (((uint32_t)div) << _CMU_LFBPRESC0_LEUART1_SHIFT);
mbed_official	50:a417edff4437	1325	break;
mbed_official	50:a417edff4437	1326	#endif
mbed_official	50:a417edff4437	1327
mbed_official	50:a417edff4437	1328	default:
mbed_official	50:a417edff4437	1329	EFM_ASSERT(0);
mbed_official	50:a417edff4437	1330	break;
mbed_official	50:a417edff4437	1331	}
mbed_official	50:a417edff4437	1332	break;
bogdanm	0:9b334a45a8ff	1333
bogdanm	0:9b334a45a8ff	1334	default:
bogdanm	0:9b334a45a8ff	1335	EFM_ASSERT(0);
bogdanm	0:9b334a45a8ff	1336	break;
mbed_official	50:a417edff4437	1337	}
bogdanm	0:9b334a45a8ff	1338	#endif
bogdanm	0:9b334a45a8ff	1339	}
bogdanm	0:9b334a45a8ff	1340
bogdanm	0:9b334a45a8ff	1341
bogdanm	0:9b334a45a8ff	1342	/*************************************************************************//
bogdanm	0:9b334a45a8ff	1343	* @brief
bogdanm	0:9b334a45a8ff	1344	* Enable/disable a clock.
bogdanm	0:9b334a45a8ff	1345	*
bogdanm	0:9b334a45a8ff	1346	* @details
bogdanm	0:9b334a45a8ff	1347	* In general, module clocking is disabled after a reset. If a module
bogdanm	0:9b334a45a8ff	1348	* clock is disabled, the registers of that module are not accessible and
bogdanm	0:9b334a45a8ff	1349	* reading from such registers may return undefined values. Writing to
bogdanm	0:9b334a45a8ff	1350	* registers of clock disabled modules have no effect. One should normally
bogdanm	0:9b334a45a8ff	1351	* avoid accessing module registers of a module with a disabled clock.
bogdanm	0:9b334a45a8ff	1352	*
bogdanm	0:9b334a45a8ff	1353	* @note
bogdanm	0:9b334a45a8ff	1354	* If enabling/disabling a LF clock, synchronization into the low frequency
bogdanm	0:9b334a45a8ff	1355	* domain is required. If the same register is modified before a previous
bogdanm	0:9b334a45a8ff	1356	* update has completed, this function will stall until the previous
bogdanm	0:9b334a45a8ff	1357	* synchronization has completed. Please refer to CMU_FreezeEnable() for
bogdanm	0:9b334a45a8ff	1358	* a suggestion on how to reduce stalling time in some use cases.
bogdanm	0:9b334a45a8ff	1359	*
bogdanm	0:9b334a45a8ff	1360	* @param[in] clock
bogdanm	0:9b334a45a8ff	1361	* The clock to enable/disable. Notice that not all defined clock
bogdanm	0:9b334a45a8ff	1362	* points have separate enable/disable control, please refer to CMU overview
bogdanm	0:9b334a45a8ff	1363	* in reference manual.
bogdanm	0:9b334a45a8ff	1364	*
bogdanm	0:9b334a45a8ff	1365	* @param[in] enable
bogdanm	0:9b334a45a8ff	1366	* @li true - enable specified clock.
bogdanm	0:9b334a45a8ff	1367	* @li false - disable specified clock.
bogdanm	0:9b334a45a8ff	1368	******************************************************************************/
bogdanm	0:9b334a45a8ff	1369	void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable)
bogdanm	0:9b334a45a8ff	1370	{
bogdanm	0:9b334a45a8ff	1371	volatile uint32_t *reg;
bogdanm	0:9b334a45a8ff	1372	uint32_t bit;
bogdanm	0:9b334a45a8ff	1373	uint32_t sync = 0;
bogdanm	0:9b334a45a8ff	1374
bogdanm	0:9b334a45a8ff	1375	/* Identify enable register */
bogdanm	0:9b334a45a8ff	1376	switch ((clock >> CMU_EN_REG_POS) & CMU_EN_REG_MASK)
bogdanm	0:9b334a45a8ff	1377	{
mbed_official	50:a417edff4437	1378	#if defined( _SILICON_LABS_32B_PLATFORM_2 )
mbed_official	50:a417edff4437	1379	case CMU_CTRL_EN_REG:
mbed_official	50:a417edff4437	1380	reg = &CMU->CTRL;
mbed_official	50:a417edff4437	1381	break;
mbed_official	50:a417edff4437	1382	#endif
mbed_official	50:a417edff4437	1383
mbed_official	50:a417edff4437	1384	#if defined( _SILICON_LABS_32B_PLATFORM_1 )
mbed_official	50:a417edff4437	1385	case CMU_HFCORECLKEN0_EN_REG:
mbed_official	50:a417edff4437	1386	reg = &CMU->HFCORECLKEN0;
bogdanm	0:9b334a45a8ff	1387	#if defined( CMU_CTRL_HFLE )
mbed_official	50:a417edff4437	1388	/* Set HFLE and DIV4 factor for peripheral clock when
mbed_official	50:a417edff4437	1389	running at frequencies higher than or equal to CMU_MAX_FREQ_HFLE. */
mbed_official	50:a417edff4437	1390	if ( CMU_ClockFreqGet(cmuClock_CORE) > CMU_MAX_FREQ_HFLE())
mbed_official	50:a417edff4437	1391	{
mbed_official	50:a417edff4437	1392	/* Enable CMU HFLE */
mbed_official	50:a417edff4437	1393	BUS_RegBitWrite(&CMU->CTRL, _CMU_CTRL_HFLE_SHIFT, 1);
mbed_official	50:a417edff4437	1394
mbed_official	50:a417edff4437	1395	/* Set DIV4 factor for peripheral clock */
mbed_official	50:a417edff4437	1396	BUS_RegBitWrite(&CMU->HFCORECLKDIV,
mbed_official	50:a417edff4437	1397	_CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 1);
mbed_official	50:a417edff4437	1398	}
mbed_official	50:a417edff4437	1399	#endif
mbed_official	50:a417edff4437	1400	break;
mbed_official	50:a417edff4437	1401	#endif
mbed_official	50:a417edff4437	1402
mbed_official	50:a417edff4437	1403	#if defined( _CMU_HFBUSCLKEN0_MASK )
mbed_official	50:a417edff4437	1404	case CMU_HFBUSCLKEN0_EN_REG:
mbed_official	50:a417edff4437	1405	reg = &CMU->HFBUSCLKEN0;
mbed_official	50:a417edff4437	1406	break;
bogdanm	0:9b334a45a8ff	1407	#endif
mbed_official	50:a417edff4437	1408
mbed_official	50:a417edff4437	1409	#if defined( _CMU_HFRADIOCLKEN0_MASK )
mbed_official	50:a417edff4437	1410	case CMU_HFRADIOCLKEN0_EN_REG:
mbed_official	50:a417edff4437	1411	reg = &CMU->HFRADIOCLKEN0;
mbed_official	50:a417edff4437	1412	break;
mbed_official	50:a417edff4437	1413	#endif
mbed_official	50:a417edff4437	1414
mbed_official	50:a417edff4437	1415	#if defined( _CMU_HFPERCLKDIV_MASK )
mbed_official	50:a417edff4437	1416	case CMU_HFPERCLKDIV_EN_REG:
mbed_official	50:a417edff4437	1417	reg = &CMU->HFPERCLKDIV;
mbed_official	50:a417edff4437	1418	break;
mbed_official	50:a417edff4437	1419	#endif
mbed_official	50:a417edff4437	1420
mbed_official	50:a417edff4437	1421	case CMU_HFPERCLKEN0_EN_REG:
mbed_official	50:a417edff4437	1422	reg = &CMU->HFPERCLKEN0;
mbed_official	50:a417edff4437	1423	break;
mbed_official	50:a417edff4437	1424
mbed_official	50:a417edff4437	1425	case CMU_LFACLKEN0_EN_REG:
mbed_official	50:a417edff4437	1426	reg = &CMU->LFACLKEN0;
mbed_official	50:a417edff4437	1427	sync = CMU_SYNCBUSY_LFACLKEN0;
mbed_official	50:a417edff4437	1428	break;
mbed_official	50:a417edff4437	1429
mbed_official	50:a417edff4437	1430	case CMU_LFBCLKEN0_EN_REG:
mbed_official	50:a417edff4437	1431	reg = &CMU->LFBCLKEN0;
mbed_official	50:a417edff4437	1432	sync = CMU_SYNCBUSY_LFBCLKEN0;
mbed_official	50:a417edff4437	1433	break;
bogdanm	0:9b334a45a8ff	1434
bogdanm	0:9b334a45a8ff	1435	#if defined( _CMU_LFCCLKEN0_MASK )
mbed_official	50:a417edff4437	1436	case CMU_LFCCLKEN0_EN_REG:
mbed_official	50:a417edff4437	1437	reg = &CMU->LFCCLKEN0;
mbed_official	50:a417edff4437	1438	sync = CMU_SYNCBUSY_LFCCLKEN0;
mbed_official	50:a417edff4437	1439	break;
bogdanm	0:9b334a45a8ff	1440	#endif
bogdanm	0:9b334a45a8ff	1441
mbed_official	50:a417edff4437	1442	#if defined( _CMU_LFECLKEN0_MASK )
mbed_official	50:a417edff4437	1443	case CMU_LFECLKEN0_EN_REG:
mbed_official	50:a417edff4437	1444	reg = &CMU->LFECLKEN0;
mbed_official	50:a417edff4437	1445	sync = CMU_SYNCBUSY_LFECLKEN0;
mbed_official	50:a417edff4437	1446	break;
mbed_official	50:a417edff4437	1447	#endif
mbed_official	50:a417edff4437	1448
mbed_official	50:a417edff4437	1449	case CMU_PCNT_EN_REG:
mbed_official	50:a417edff4437	1450	reg = &CMU->PCNTCTRL;
mbed_official	50:a417edff4437	1451	break;
mbed_official	50:a417edff4437	1452
mbed_official	50:a417edff4437	1453	default: /* Cannot enable/disable clock point */
mbed_official	50:a417edff4437	1454	EFM_ASSERT(0);
mbed_official	50:a417edff4437	1455	return;
bogdanm	0:9b334a45a8ff	1456	}
bogdanm	0:9b334a45a8ff	1457
bogdanm	0:9b334a45a8ff	1458	/* Get bit position used to enable/disable */
bogdanm	0:9b334a45a8ff	1459	bit = (clock >> CMU_EN_BIT_POS) & CMU_EN_BIT_MASK;
bogdanm	0:9b334a45a8ff	1460
bogdanm	0:9b334a45a8ff	1461	/* LF synchronization required? */
bogdanm	0:9b334a45a8ff	1462	if (sync)
bogdanm	0:9b334a45a8ff	1463	{
mbed_official	50:a417edff4437	1464	syncReg(sync);
bogdanm	0:9b334a45a8ff	1465	}
bogdanm	0:9b334a45a8ff	1466
bogdanm	0:9b334a45a8ff	1467	/* Set/clear bit as requested */
mbed_official	50:a417edff4437	1468	BUS_RegBitWrite(reg, bit, enable);
bogdanm	0:9b334a45a8ff	1469	}
bogdanm	0:9b334a45a8ff	1470
bogdanm	0:9b334a45a8ff	1471
bogdanm	0:9b334a45a8ff	1472	/*************************************************************************//
bogdanm	0:9b334a45a8ff	1473	* @brief
bogdanm	0:9b334a45a8ff	1474	* Get clock frequency for a clock point.
bogdanm	0:9b334a45a8ff	1475	*
bogdanm	0:9b334a45a8ff	1476	* @param[in] clock
bogdanm	0:9b334a45a8ff	1477	* Clock point to fetch frequency for.
bogdanm	0:9b334a45a8ff	1478	*
bogdanm	0:9b334a45a8ff	1479	* @return
bogdanm	0:9b334a45a8ff	1480	* The current frequency in Hz.
bogdanm	0:9b334a45a8ff	1481	******************************************************************************/
bogdanm	0:9b334a45a8ff	1482	uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock)
bogdanm	0:9b334a45a8ff	1483	{
bogdanm	0:9b334a45a8ff	1484	uint32_t ret;
bogdanm	0:9b334a45a8ff	1485
bogdanm	0:9b334a45a8ff	1486	switch(clock & (CMU_CLK_BRANCH_MASK << CMU_CLK_BRANCH_POS))
bogdanm	0:9b334a45a8ff	1487	{
bogdanm	0:9b334a45a8ff	1488	case (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS):
bogdanm	0:9b334a45a8ff	1489	ret = SystemHFClockGet();
bogdanm	0:9b334a45a8ff	1490	#if defined( _CMU_CTRL_HFCLKDIV_MASK )
mbed_official	50:a417edff4437	1491	/* Family with an additional divider. */
mbed_official	50:a417edff4437	1492	ret = ret / (1U + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK)
mbed_official	50:a417edff4437	1493	>> _CMU_CTRL_HFCLKDIV_SHIFT));
mbed_official	50:a417edff4437	1494	#endif
mbed_official	50:a417edff4437	1495	#if defined( _CMU_HFPRESC_MASK )
mbed_official	50:a417edff4437	1496	ret = ret / (1U + ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK)
mbed_official	50:a417edff4437	1497	>> _CMU_HFPRESC_PRESC_SHIFT));
mbed_official	50:a417edff4437	1498	#endif
mbed_official	50:a417edff4437	1499	break;
mbed_official	50:a417edff4437	1500
mbed_official	50:a417edff4437	1501	case (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS):
mbed_official	50:a417edff4437	1502	ret = SystemHFClockGet();
mbed_official	50:a417edff4437	1503	#if defined( _SILICON_LABS_32B_PLATFORM_1 )
mbed_official	50:a417edff4437	1504	#if defined( _CMU_CTRL_HFCLKDIV_MASK )
mbed_official	50:a417edff4437	1505	/* Family with an additional divider. */
mbed_official	50:a417edff4437	1506	ret = ret / (1U + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK)
mbed_official	50:a417edff4437	1507	>> _CMU_CTRL_HFCLKDIV_SHIFT));
mbed_official	50:a417edff4437	1508	#endif
mbed_official	50:a417edff4437	1509	ret >>= (CMU->HFPERCLKDIV & _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK)
mbed_official	50:a417edff4437	1510	>> _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT;
mbed_official	50:a417edff4437	1511	#elif defined( _SILICON_LABS_32B_PLATFORM_2 )
mbed_official	50:a417edff4437	1512	ret /= 1U + ((CMU->HFPERPRESC & _CMU_HFPERPRESC_PRESC_MASK)
mbed_official	50:a417edff4437	1513	>> _CMU_HFPERPRESC_PRESC_SHIFT);
bogdanm	0:9b334a45a8ff	1514	#endif
mbed_official	50:a417edff4437	1515	break;
mbed_official	50:a417edff4437	1516
mbed_official	50:a417edff4437	1517	#if defined( _SILICON_LABS_32B_PLATFORM_2 )
mbed_official	50:a417edff4437	1518	#if defined( _CMU_HFRADIOPRESC_PRESC_MASK )
mbed_official	50:a417edff4437	1519	case (CMU_HFRADIO_CLK_BRANCH << CMU_CLK_BRANCH_POS):
mbed_official	50:a417edff4437	1520	ret = SystemHFClockGet();
mbed_official	50:a417edff4437	1521	ret /= 1U + ((CMU->HFRADIOPRESC & _CMU_HFRADIOPRESC_PRESC_MASK)
mbed_official	50:a417edff4437	1522	>> _CMU_HFRADIOPRESC_PRESC_SHIFT);
mbed_official	50:a417edff4437	1523	break;
mbed_official	50:a417edff4437	1524	#endif
mbed_official	50:a417edff4437	1525
mbed_official	50:a417edff4437	1526	#if defined( CRYPTO_PRESENT ) \
mbed_official	50:a417edff4437	1527	\|\| defined( LDMA_PRESENT ) \
mbed_official	50:a417edff4437	1528	\|\| defined( GPCRC_PRESENT ) \
mbed_official	50:a417edff4437	1529	\|\| defined( PRS_PRESENT ) \
mbed_official	50:a417edff4437	1530	\|\| defined( GPIO_PRESENT )
mbed_official	50:a417edff4437	1531	case (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS):
mbed_official	50:a417edff4437	1532	ret = SystemHFClockGet();
mbed_official	50:a417edff4437	1533	break;
bogdanm	0:9b334a45a8ff	1534	#endif
mbed_official	50:a417edff4437	1535
mbed_official	50:a417edff4437	1536	case (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS):
mbed_official	50:a417edff4437	1537	ret = SystemHFClockGet();
mbed_official	50:a417edff4437	1538	ret /= 1U + ((CMU->HFCOREPRESC & _CMU_HFCOREPRESC_PRESC_MASK)
mbed_official	50:a417edff4437	1539	>> _CMU_HFCOREPRESC_PRESC_SHIFT);
mbed_official	50:a417edff4437	1540	break;
mbed_official	50:a417edff4437	1541
mbed_official	50:a417edff4437	1542	case (CMU_HFEXP_CLK_BRANCH << CMU_CLK_BRANCH_POS):
mbed_official	50:a417edff4437	1543	ret = SystemHFClockGet();
mbed_official	50:a417edff4437	1544	ret /= 1U + ((CMU->HFEXPPRESC & _CMU_HFEXPPRESC_PRESC_MASK)
mbed_official	50:a417edff4437	1545	>> _CMU_HFEXPPRESC_PRESC_SHIFT);
mbed_official	50:a417edff4437	1546	break;
bogdanm	0:9b334a45a8ff	1547	#endif
bogdanm	0:9b334a45a8ff	1548
mbed_official	50:a417edff4437	1549	#if defined( _SILICON_LABS_32B_PLATFORM_1 )
mbed_official	50:a417edff4437	1550	#if defined(AES_PRESENT) \
mbed_official	50:a417edff4437	1551	\|\| defined(DMA_PRESENT) \
mbed_official	50:a417edff4437	1552	\|\| defined(EBI_PRESENT) \
mbed_official	50:a417edff4437	1553	\|\| defined(USB_PRESENT)
bogdanm	0:9b334a45a8ff	1554	case (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS):
bogdanm	0:9b334a45a8ff	1555	{
bogdanm	0:9b334a45a8ff	1556	ret = SystemCoreClockGet();
bogdanm	0:9b334a45a8ff	1557	} break;
bogdanm	0:9b334a45a8ff	1558	#endif
mbed_official	50:a417edff4437	1559	#endif
bogdanm	0:9b334a45a8ff	1560
bogdanm	0:9b334a45a8ff	1561	case (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS):
mbed_official	50:a417edff4437	1562	ret = lfClkGet(cmuClock_LFA);
mbed_official	50:a417edff4437	1563	break;
mbed_official	50:a417edff4437	1564
mbed_official	50:a417edff4437	1565	#if defined( _CMU_LFACLKEN0_RTC_MASK )
bogdanm	0:9b334a45a8ff	1566	case (CMU_RTC_CLK_BRANCH << CMU_CLK_BRANCH_POS):
mbed_official	50:a417edff4437	1567	ret = lfClkGet(cmuClock_LFA);
mbed_official	50:a417edff4437	1568	ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_RTC_MASK)
mbed_official	50:a417edff4437	1569	>> _CMU_LFAPRESC0_RTC_SHIFT;
mbed_official	50:a417edff4437	1570	break;
mbed_official	50:a417edff4437	1571	#endif
mbed_official	50:a417edff4437	1572
mbed_official	50:a417edff4437	1573	#if defined( _CMU_LFECLKEN0_RTCC_MASK )
mbed_official	50:a417edff4437	1574	case (CMU_RTCC_CLK_BRANCH << CMU_CLK_BRANCH_POS):
mbed_official	50:a417edff4437	1575	ret = lfClkGet(cmuClock_LFE);
mbed_official	50:a417edff4437	1576	break;
bogdanm	0:9b334a45a8ff	1577	#endif
mbed_official	50:a417edff4437	1578
mbed_official	50:a417edff4437	1579	#if defined( _CMU_LFACLKEN0_LETIMER0_MASK )
mbed_official	50:a417edff4437	1580	case (CMU_LETIMER0_CLK_BRANCH << CMU_CLK_BRANCH_POS):
mbed_official	50:a417edff4437	1581	ret = lfClkGet(cmuClock_LFA);
mbed_official	50:a417edff4437	1582	#if defined( _SILICON_LABS_32B_PLATFORM_1 )
mbed_official	50:a417edff4437	1583	ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK)
mbed_official	50:a417edff4437	1584	>> _CMU_LFAPRESC0_LETIMER0_SHIFT;
mbed_official	50:a417edff4437	1585	#elif defined( _SILICON_LABS_32B_PLATFORM_2 )
mbed_official	50:a417edff4437	1586	ret /= CMU_Log2ToDiv((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK)
mbed_official	50:a417edff4437	1587	>> _CMU_LFAPRESC0_LETIMER0_SHIFT);
bogdanm	0:9b334a45a8ff	1588	#endif
mbed_official	50:a417edff4437	1589	break;
mbed_official	50:a417edff4437	1590	#endif
mbed_official	50:a417edff4437	1591
bogdanm	0:9b334a45a8ff	1592	#if defined(_CMU_LFACLKEN0_LCD_MASK)
bogdanm	0:9b334a45a8ff	1593	case (CMU_LCDPRE_CLK_BRANCH << CMU_CLK_BRANCH_POS):
mbed_official	50:a417edff4437	1594	ret = lfClkGet(cmuClock_LFA);
mbed_official	50:a417edff4437	1595	ret >>= ((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK)
mbed_official	50:a417edff4437	1596	>> _CMU_LFAPRESC0_LCD_SHIFT)
mbed_official	50:a417edff4437	1597	+ CMU_DivToLog2(cmuClkDiv_16);
mbed_official	50:a417edff4437	1598	break;
bogdanm	0:9b334a45a8ff	1599
bogdanm	0:9b334a45a8ff	1600	case (CMU_LCD_CLK_BRANCH << CMU_CLK_BRANCH_POS):
mbed_official	50:a417edff4437	1601	ret = lfClkGet(cmuClock_LFA);
mbed_official	50:a417edff4437	1602	ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK)
mbed_official	50:a417edff4437	1603	>> _CMU_LFAPRESC0_LCD_SHIFT;
mbed_official	50:a417edff4437	1604	ret /= 1U + ((CMU->LCDCTRL & _CMU_LCDCTRL_FDIV_MASK)
mbed_official	50:a417edff4437	1605	>> _CMU_LCDCTRL_FDIV_SHIFT);
mbed_official	50:a417edff4437	1606	break;
bogdanm	0:9b334a45a8ff	1607	#endif
mbed_official	50:a417edff4437	1608
bogdanm	0:9b334a45a8ff	1609	#if defined(_CMU_LFACLKEN0_LESENSE_MASK)
bogdanm	0:9b334a45a8ff	1610	case (CMU_LESENSE_CLK_BRANCH << CMU_CLK_BRANCH_POS):
mbed_official	50:a417edff4437	1611	ret = lfClkGet(cmuClock_LFA);
mbed_official	50:a417edff4437	1612	ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LESENSE_MASK)
mbed_official	50:a417edff4437	1613	>> _CMU_LFAPRESC0_LESENSE_SHIFT;
mbed_official	50:a417edff4437	1614	break;
bogdanm	0:9b334a45a8ff	1615	#endif
mbed_official	50:a417edff4437	1616
bogdanm	0:9b334a45a8ff	1617	case (CMU_LFB_CLK_BRANCH << CMU_CLK_BRANCH_POS):
mbed_official	50:a417edff4437	1618	ret = lfClkGet(cmuClock_LFB);
mbed_official	50:a417edff4437	1619	break;
mbed_official	50:a417edff4437	1620
mbed_official	50:a417edff4437	1621	#if defined( _CMU_LFBCLKEN0_LEUART0_MASK )
bogdanm	0:9b334a45a8ff	1622	case (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS):
mbed_official	50:a417edff4437	1623	ret = lfClkGet(cmuClock_LFB);
mbed_official	50:a417edff4437	1624	#if defined( _SILICON_LABS_32B_PLATFORM_1 )
mbed_official	50:a417edff4437	1625	ret >>= (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK)
mbed_official	50:a417edff4437	1626	>> _CMU_LFBPRESC0_LEUART0_SHIFT;
mbed_official	50:a417edff4437	1627	#elif defined( _SILICON_LABS_32B_PLATFORM_2 )
mbed_official	50:a417edff4437	1628	ret /= CMU_Log2ToDiv((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK)
mbed_official	50:a417edff4437	1629	>> _CMU_LFBPRESC0_LEUART0_SHIFT);
mbed_official	50:a417edff4437	1630	#endif
mbed_official	50:a417edff4437	1631	break;
bogdanm	0:9b334a45a8ff	1632	#endif
mbed_official	50:a417edff4437	1633
mbed_official	50:a417edff4437	1634	#if defined( _CMU_LFBCLKEN0_LEUART1_MASK )
bogdanm	0:9b334a45a8ff	1635	case (CMU_LEUART1_CLK_BRANCH << CMU_CLK_BRANCH_POS):
mbed_official	50:a417edff4437	1636	ret = lfClkGet(cmuClock_LFB);
mbed_official	50:a417edff4437	1637	#if defined( _SILICON_LABS_32B_PLATFORM_1 )
mbed_official	50:a417edff4437	1638	ret >>= (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK)
mbed_official	50:a417edff4437	1639	>> _CMU_LFBPRESC0_LEUART1_SHIFT;
mbed_official	50:a417edff4437	1640	#elif defined( _SILICON_LABS_32B_PLATFORM_2 )
mbed_official	50:a417edff4437	1641	ret /= CMU_Log2ToDiv((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK)
mbed_official	50:a417edff4437	1642	>> _CMU_LFBPRESC0_LEUART1_SHIFT);
mbed_official	50:a417edff4437	1643	#endif
mbed_official	50:a417edff4437	1644	break;
mbed_official	50:a417edff4437	1645	#endif
mbed_official	50:a417edff4437	1646
mbed_official	50:a417edff4437	1647	#if defined( _SILICON_LABS_32B_PLATFORM_2 )
mbed_official	50:a417edff4437	1648	case (CMU_LFE_CLK_BRANCH << CMU_CLK_BRANCH_POS):
mbed_official	50:a417edff4437	1649	ret = lfClkGet(cmuClock_LFE);
mbed_official	50:a417edff4437	1650	break;
bogdanm	0:9b334a45a8ff	1651	#endif
bogdanm	0:9b334a45a8ff	1652
bogdanm	0:9b334a45a8ff	1653	case (CMU_DBG_CLK_BRANCH << CMU_CLK_BRANCH_POS):
mbed_official	50:a417edff4437	1654	ret = dbgClkGet();
mbed_official	50:a417edff4437	1655	break;
bogdanm	0:9b334a45a8ff	1656
bogdanm	0:9b334a45a8ff	1657	case (CMU_AUX_CLK_BRANCH << CMU_CLK_BRANCH_POS):
mbed_official	50:a417edff4437	1658	ret = auxClkGet();
mbed_official	50:a417edff4437	1659	break;
bogdanm	0:9b334a45a8ff	1660
bogdanm	0:9b334a45a8ff	1661	#if defined(USB_PRESENT)
bogdanm	0:9b334a45a8ff	1662	case (CMU_USBC_CLK_BRANCH << CMU_CLK_BRANCH_POS):
mbed_official	50:a417edff4437	1663	ret = usbCClkGet();
mbed_official	50:a417edff4437	1664	break;
bogdanm	0:9b334a45a8ff	1665	#endif
mbed_official	50:a417edff4437	1666
bogdanm	0:9b334a45a8ff	1667	default:
bogdanm	0:9b334a45a8ff	1668	EFM_ASSERT(0);
bogdanm	0:9b334a45a8ff	1669	ret = 0;
mbed_official	50:a417edff4437	1670	break;
bogdanm	0:9b334a45a8ff	1671	}
mbed_official	50:a417edff4437	1672
mbed_official	50:a417edff4437	1673	return ret;
mbed_official	50:a417edff4437	1674	}
mbed_official	50:a417edff4437	1675
mbed_official	50:a417edff4437	1676
mbed_official	50:a417edff4437	1677	#if defined( _SILICON_LABS_32B_PLATFORM_2 )
mbed_official	50:a417edff4437	1678	/*************************************************************************//
mbed_official	50:a417edff4437	1679	* @brief
mbed_official	50:a417edff4437	1680	* Get clock prescaler.
mbed_official	50:a417edff4437	1681	*
mbed_official	50:a417edff4437	1682	* @param[in] clock
mbed_official	50:a417edff4437	1683	* Clock point to get the prescaler for. Notice that not all clock points
mbed_official	50:a417edff4437	1684	* have a prescaler. Please refer to CMU overview in reference manual.
mbed_official	50:a417edff4437	1685	*
mbed_official	50:a417edff4437	1686	* @return
mbed_official	50:a417edff4437	1687	* The prescaler value of the current clock point. 0 is returned
mbed_official	50:a417edff4437	1688	* if @p clock specifies a clock point without a prescaler.
mbed_official	50:a417edff4437	1689	******************************************************************************/
mbed_official	50:a417edff4437	1690	uint32_t CMU_ClockPrescGet(CMU_Clock_TypeDef clock)
mbed_official	50:a417edff4437	1691	{
mbed_official	50:a417edff4437	1692	uint32_t prescReg;
mbed_official	50:a417edff4437	1693	uint32_t ret;
mbed_official	50:a417edff4437	1694
mbed_official	50:a417edff4437	1695	/* Get prescaler register id. */
mbed_official	50:a417edff4437	1696	prescReg = (clock >> CMU_PRESC_REG_POS) & CMU_PRESC_REG_MASK;
mbed_official	50:a417edff4437	1697
mbed_official	50:a417edff4437	1698	switch (prescReg)
mbed_official	50:a417edff4437	1699	{
mbed_official	50:a417edff4437	1700	case CMU_HFPRESC_REG:
mbed_official	50:a417edff4437	1701	ret = ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK)
mbed_official	50:a417edff4437	1702	>> _CMU_HFPRESC_PRESC_SHIFT);
mbed_official	50:a417edff4437	1703	break;
mbed_official	50:a417edff4437	1704
mbed_official	50:a417edff4437	1705	case CMU_HFEXPPRESC_REG:
mbed_official	50:a417edff4437	1706	ret = ((CMU->HFEXPPRESC & _CMU_HFEXPPRESC_PRESC_MASK)
mbed_official	50:a417edff4437	1707	>> _CMU_HFEXPPRESC_PRESC_SHIFT);
mbed_official	50:a417edff4437	1708	break;
mbed_official	50:a417edff4437	1709
mbed_official	50:a417edff4437	1710	case CMU_HFCLKLEPRESC_REG:
mbed_official	50:a417edff4437	1711	ret = ((CMU->HFPRESC & _CMU_HFPRESC_HFCLKLEPRESC_MASK)
mbed_official	50:a417edff4437	1712	>> _CMU_HFPRESC_HFCLKLEPRESC_SHIFT);
mbed_official	50:a417edff4437	1713	break;
mbed_official	50:a417edff4437	1714
mbed_official	50:a417edff4437	1715	case CMU_HFPERPRESC_REG:
mbed_official	50:a417edff4437	1716	ret = ((CMU->HFPERPRESC & _CMU_HFPERPRESC_PRESC_MASK)
mbed_official	50:a417edff4437	1717	>> _CMU_HFPERPRESC_PRESC_SHIFT);
mbed_official	50:a417edff4437	1718	break;
mbed_official	50:a417edff4437	1719
mbed_official	50:a417edff4437	1720	#if defined( _CMU_HFRADIOPRESC_PRESC_MASK )
mbed_official	50:a417edff4437	1721	case CMU_HFRADIOPRESC_REG:
mbed_official	50:a417edff4437	1722	ret = ((CMU->HFRADIOPRESC & _CMU_HFRADIOPRESC_PRESC_MASK)
mbed_official	50:a417edff4437	1723	>> _CMU_HFRADIOPRESC_PRESC_SHIFT);
mbed_official	50:a417edff4437	1724	break;
mbed_official	50:a417edff4437	1725	#endif
mbed_official	50:a417edff4437	1726
mbed_official	50:a417edff4437	1727	case CMU_HFCOREPRESC_REG:
mbed_official	50:a417edff4437	1728	ret = ((CMU->HFCOREPRESC & _CMU_HFCOREPRESC_PRESC_MASK)
mbed_official	50:a417edff4437	1729	>> _CMU_HFCOREPRESC_PRESC_SHIFT);
mbed_official	50:a417edff4437	1730	break;
mbed_official	50:a417edff4437	1731
mbed_official	50:a417edff4437	1732	case CMU_LFAPRESC0_REG:
mbed_official	50:a417edff4437	1733	switch (clock)
mbed_official	50:a417edff4437	1734	{
mbed_official	50:a417edff4437	1735	#if defined( _CMU_LFAPRESC0_LETIMER0_MASK )
mbed_official	50:a417edff4437	1736	case cmuClock_LETIMER0:
mbed_official	50:a417edff4437	1737	ret = (((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK)
mbed_official	50:a417edff4437	1738	>> _CMU_LFAPRESC0_LETIMER0_SHIFT));
mbed_official	50:a417edff4437	1739	/* Convert the exponent to prescaler value. */
mbed_official	50:a417edff4437	1740	ret = CMU_Log2ToDiv(ret) - 1U;
mbed_official	50:a417edff4437	1741	break;
mbed_official	50:a417edff4437	1742	#endif
mbed_official	50:a417edff4437	1743
mbed_official	50:a417edff4437	1744	default:
mbed_official	50:a417edff4437	1745	EFM_ASSERT(0);
mbed_official	50:a417edff4437	1746	ret = 0U;
mbed_official	50:a417edff4437	1747	break;
mbed_official	50:a417edff4437	1748	}
mbed_official	50:a417edff4437	1749	break;
mbed_official	50:a417edff4437	1750
mbed_official	50:a417edff4437	1751	case CMU_LFBPRESC0_REG:
mbed_official	50:a417edff4437	1752	switch (clock)
mbed_official	50:a417edff4437	1753	{
mbed_official	50:a417edff4437	1754	#if defined( _CMU_LFBPRESC0_LEUART0_MASK )
mbed_official	50:a417edff4437	1755	case cmuClock_LEUART0:
mbed_official	50:a417edff4437	1756	ret = (((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK)
mbed_official	50:a417edff4437	1757	>> _CMU_LFBPRESC0_LEUART0_SHIFT));
mbed_official	50:a417edff4437	1758	/* Convert the exponent to prescaler value. */
mbed_official	50:a417edff4437	1759	ret = CMU_Log2ToDiv(ret) - 1U;
mbed_official	50:a417edff4437	1760	break;
mbed_official	50:a417edff4437	1761	#endif
mbed_official	50:a417edff4437	1762
mbed_official	50:a417edff4437	1763	#if defined( _CMU_LFBPRESC0_LEUART1_MASK )
mbed_official	50:a417edff4437	1764	case cmuClock_LEUART1:
mbed_official	50:a417edff4437	1765	ret = (((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK)
mbed_official	50:a417edff4437	1766	>> _CMU_LFBPRESC0_LEUART1_SHIFT));
mbed_official	50:a417edff4437	1767	/* Convert the exponent to prescaler value. */
mbed_official	50:a417edff4437	1768	ret = CMU_Log2ToDiv(ret) - 1U;
mbed_official	50:a417edff4437	1769	break;
mbed_official	50:a417edff4437	1770	#endif
mbed_official	50:a417edff4437	1771
mbed_official	50:a417edff4437	1772	default:
mbed_official	50:a417edff4437	1773	EFM_ASSERT(0);
mbed_official	50:a417edff4437	1774	ret = 0U;
mbed_official	50:a417edff4437	1775	break;
mbed_official	50:a417edff4437	1776	}
mbed_official	50:a417edff4437	1777	break;
mbed_official	50:a417edff4437	1778
mbed_official	50:a417edff4437	1779	case CMU_LFEPRESC0_REG:
mbed_official	50:a417edff4437	1780	switch (clock)
mbed_official	50:a417edff4437	1781	{
mbed_official	50:a417edff4437	1782	#if defined( RTCC_PRESENT )
mbed_official	50:a417edff4437	1783	case cmuClock_RTCC:
mbed_official	50:a417edff4437	1784	/* No need to compute with LFEPRESC0_RTCC - DIV1 is the only */
mbed_official	50:a417edff4437	1785	/* allowed value. Convert the exponent to prescaler value. */
mbed_official	50:a417edff4437	1786	ret = _CMU_LFEPRESC0_RTCC_DIV1;
mbed_official	50:a417edff4437	1787	break;
mbed_official	50:a417edff4437	1788
mbed_official	50:a417edff4437	1789	default:
mbed_official	50:a417edff4437	1790	EFM_ASSERT(0);
mbed_official	50:a417edff4437	1791	ret = 0U;
mbed_official	50:a417edff4437	1792	break;
mbed_official	50:a417edff4437	1793	#endif
mbed_official	50:a417edff4437	1794	}
mbed_official	50:a417edff4437	1795	break;
mbed_official	50:a417edff4437	1796
mbed_official	50:a417edff4437	1797	default:
mbed_official	50:a417edff4437	1798	EFM_ASSERT(0);
mbed_official	50:a417edff4437	1799	ret = 0U;
mbed_official	50:a417edff4437	1800	break;
mbed_official	50:a417edff4437	1801	}
mbed_official	50:a417edff4437	1802
bogdanm	0:9b334a45a8ff	1803	return ret;
bogdanm	0:9b334a45a8ff	1804	}
mbed_official	50:a417edff4437	1805	#endif
mbed_official	50:a417edff4437	1806
mbed_official	50:a417edff4437	1807
mbed_official	50:a417edff4437	1808	#if defined( _SILICON_LABS_32B_PLATFORM_2 )
mbed_official	50:a417edff4437	1809	/*************************************************************************//
mbed_official	50:a417edff4437	1810	* @brief
mbed_official	50:a417edff4437	1811	* Set clock prescaler.
mbed_official	50:a417edff4437	1812	*
mbed_official	50:a417edff4437	1813	* @note
mbed_official	50:a417edff4437	1814	* If setting a LF clock prescaler, synchronization into the low frequency
mbed_official	50:a417edff4437	1815	* domain is required. If the same register is modified before a previous
mbed_official	50:a417edff4437	1816	* update has completed, this function will stall until the previous
mbed_official	50:a417edff4437	1817	* synchronization has completed. Please refer to CMU_FreezeEnable() for
mbed_official	50:a417edff4437	1818	* a suggestion on how to reduce stalling time in some use cases.
mbed_official	50:a417edff4437	1819	*
mbed_official	50:a417edff4437	1820	* @param[in] clock
mbed_official	50:a417edff4437	1821	* Clock point to set prescaler for. Notice that not all clock points
mbed_official	50:a417edff4437	1822	* have a prescaler, please refer to CMU overview in the reference manual.
mbed_official	50:a417edff4437	1823	*
mbed_official	50:a417edff4437	1824	* @param[in] presc
mbed_official	50:a417edff4437	1825	* The clock prescaler to use.
mbed_official	50:a417edff4437	1826	******************************************************************************/
mbed_official	50:a417edff4437	1827	void CMU_ClockPrescSet(CMU_Clock_TypeDef clock, CMU_ClkPresc_TypeDef presc)
mbed_official	50:a417edff4437	1828	{
mbed_official	50:a417edff4437	1829	uint32_t freq;
mbed_official	50:a417edff4437	1830	uint32_t prescReg;
mbed_official	50:a417edff4437	1831
mbed_official	50:a417edff4437	1832	/* Get divisor reg id */
mbed_official	50:a417edff4437	1833	prescReg = (clock >> CMU_PRESC_REG_POS) & CMU_PRESC_REG_MASK;
mbed_official	50:a417edff4437	1834
mbed_official	50:a417edff4437	1835	switch (prescReg)
mbed_official	50:a417edff4437	1836	{
mbed_official	50:a417edff4437	1837	case CMU_HFPRESC_REG:
mbed_official	50:a417edff4437	1838	EFM_ASSERT(presc < 32U);
mbed_official	50:a417edff4437	1839
mbed_official	50:a417edff4437	1840	CMU->HFPRESC = (CMU->HFPRESC & ~_CMU_HFPRESC_PRESC_MASK)
mbed_official	50:a417edff4437	1841	\| (presc << _CMU_HFPRESC_PRESC_SHIFT);
mbed_official	50:a417edff4437	1842	break;
mbed_official	50:a417edff4437	1843
mbed_official	50:a417edff4437	1844	case CMU_HFEXPPRESC_REG:
mbed_official	50:a417edff4437	1845	EFM_ASSERT(presc < 32U);
mbed_official	50:a417edff4437	1846
mbed_official	50:a417edff4437	1847	CMU->HFEXPPRESC = (CMU->HFEXPPRESC & ~_CMU_HFEXPPRESC_PRESC_MASK)
mbed_official	50:a417edff4437	1848	\| (presc << _CMU_HFEXPPRESC_PRESC_SHIFT);
mbed_official	50:a417edff4437	1849	break;
mbed_official	50:a417edff4437	1850
mbed_official	50:a417edff4437	1851	case CMU_HFCLKLEPRESC_REG:
mbed_official	50:a417edff4437	1852	EFM_ASSERT(presc < 2U);
mbed_official	50:a417edff4437	1853
mbed_official	50:a417edff4437	1854	/* Specifies the clock divider for HFCLKLE. When running at frequencies
mbed_official	50:a417edff4437	1855	* higher than 32 MHz, this must be set to DIV4. */
mbed_official	50:a417edff4437	1856	CMU->HFPRESC = (CMU->HFPRESC & ~_CMU_HFPRESC_HFCLKLEPRESC_MASK)
mbed_official	50:a417edff4437	1857	\| (presc << _CMU_HFPRESC_HFCLKLEPRESC_SHIFT);
mbed_official	50:a417edff4437	1858	break;
mbed_official	50:a417edff4437	1859
mbed_official	50:a417edff4437	1860	case CMU_HFPERPRESC_REG:
mbed_official	50:a417edff4437	1861	EFM_ASSERT(presc < 512U);
mbed_official	50:a417edff4437	1862
mbed_official	50:a417edff4437	1863	CMU->HFPERPRESC = (CMU->HFPERPRESC & ~_CMU_HFPERPRESC_PRESC_MASK)
mbed_official	50:a417edff4437	1864	\| (presc << _CMU_HFPERPRESC_PRESC_SHIFT);
mbed_official	50:a417edff4437	1865	break;
mbed_official	50:a417edff4437	1866
mbed_official	50:a417edff4437	1867	#if defined( _CMU_HFRADIOPRESC_PRESC_MASK )
mbed_official	50:a417edff4437	1868	case CMU_HFRADIOPRESC_REG:
mbed_official	50:a417edff4437	1869	EFM_ASSERT(presc < 512U);
mbed_official	50:a417edff4437	1870
mbed_official	50:a417edff4437	1871	CMU->HFRADIOPRESC = (CMU->HFRADIOPRESC & ~_CMU_HFRADIOPRESC_PRESC_MASK)
mbed_official	50:a417edff4437	1872	\| (presc << _CMU_HFRADIOPRESC_PRESC_SHIFT);
mbed_official	50:a417edff4437	1873	break;
mbed_official	50:a417edff4437	1874	#endif
mbed_official	50:a417edff4437	1875
mbed_official	50:a417edff4437	1876	case CMU_HFCOREPRESC_REG:
mbed_official	50:a417edff4437	1877	EFM_ASSERT(presc < 512U);
mbed_official	50:a417edff4437	1878
mbed_official	50:a417edff4437	1879	/* Configure worst case wait states for flash access before setting
mbed_official	50:a417edff4437	1880	* the prescaler. */
mbed_official	50:a417edff4437	1881	flashWaitStateControl(CMU_MAX_FREQ_0WS + 1);
mbed_official	50:a417edff4437	1882
mbed_official	50:a417edff4437	1883	CMU->HFCOREPRESC = (CMU->HFCOREPRESC & ~_CMU_HFCOREPRESC_PRESC_MASK)
mbed_official	50:a417edff4437	1884	\| (presc << _CMU_HFCOREPRESC_PRESC_SHIFT);
mbed_official	50:a417edff4437	1885
mbed_official	50:a417edff4437	1886	/* Update CMSIS core clock variable */
mbed_official	50:a417edff4437	1887	/* (The function will update the global variable) */
mbed_official	50:a417edff4437	1888	freq = SystemCoreClockGet();
mbed_official	50:a417edff4437	1889
mbed_official	50:a417edff4437	1890	/* Optimize flash access wait state setting for current core clk */
mbed_official	50:a417edff4437	1891	flashWaitStateControl(freq);
mbed_official	50:a417edff4437	1892	break;
mbed_official	50:a417edff4437	1893
mbed_official	50:a417edff4437	1894	case CMU_LFAPRESC0_REG:
mbed_official	50:a417edff4437	1895	switch (clock)
mbed_official	50:a417edff4437	1896	{
mbed_official	50:a417edff4437	1897	#if defined( RTC_PRESENT )
mbed_official	50:a417edff4437	1898	case cmuClock_RTC:
mbed_official	50:a417edff4437	1899	EFM_ASSERT(presc <= 32768U);
mbed_official	50:a417edff4437	1900
mbed_official	50:a417edff4437	1901	/* Convert prescaler value to DIV exponent scale. */
mbed_official	50:a417edff4437	1902	presc = CMU_PrescToLog2(presc);
mbed_official	50:a417edff4437	1903
mbed_official	50:a417edff4437	1904	/* LF register about to be modified require sync. Busy check. */
mbed_official	50:a417edff4437	1905	syncReg(CMU_SYNCBUSY_LFAPRESC0);
mbed_official	50:a417edff4437	1906
mbed_official	50:a417edff4437	1907	CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTC_MASK)
mbed_official	50:a417edff4437	1908	\| (presc << _CMU_LFAPRESC0_RTC_SHIFT);
mbed_official	50:a417edff4437	1909	break;
mbed_official	50:a417edff4437	1910	#endif
mbed_official	50:a417edff4437	1911
mbed_official	50:a417edff4437	1912	#if defined( RTCC_PRESENT )
mbed_official	50:a417edff4437	1913	case cmuClock_RTCC:
mbed_official	50:a417edff4437	1914	#if defined( _CMU_LFEPRESC0_RTCC_MASK )
mbed_official	50:a417edff4437	1915	/* DIV1 is the only accepted value. */
mbed_official	50:a417edff4437	1916	EFM_ASSERT(presc <= 0U);
mbed_official	50:a417edff4437	1917
mbed_official	50:a417edff4437	1918	/* LF register about to be modified require sync. Busy check.. */
mbed_official	50:a417edff4437	1919	syncReg(CMU_SYNCBUSY_LFEPRESC0);
mbed_official	50:a417edff4437	1920
mbed_official	50:a417edff4437	1921	CMU->LFEPRESC0 = (CMU->LFEPRESC0 & ~_CMU_LFEPRESC0_RTCC_MASK)
mbed_official	50:a417edff4437	1922	\| (presc << _CMU_LFEPRESC0_RTCC_SHIFT);
mbed_official	50:a417edff4437	1923	#else
mbed_official	50:a417edff4437	1924	EFM_ASSERT(presc <= 32768U);
mbed_official	50:a417edff4437	1925
mbed_official	50:a417edff4437	1926	/* Convert prescaler value to DIV exponent scale. */
mbed_official	50:a417edff4437	1927	presc = CMU_PrescToLog2(presc);
mbed_official	50:a417edff4437	1928
mbed_official	50:a417edff4437	1929	/* LF register about to be modified require sync. Busy check. */
mbed_official	50:a417edff4437	1930	syncReg(CMU_SYNCBUSY_LFAPRESC0);
mbed_official	50:a417edff4437	1931
mbed_official	50:a417edff4437	1932	CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTCC_MASK)
mbed_official	50:a417edff4437	1933	\| (presc << _CMU_LFAPRESC0_RTCC_SHIFT);
mbed_official	50:a417edff4437	1934	#endif
mbed_official	50:a417edff4437	1935	break;
mbed_official	50:a417edff4437	1936	#endif
mbed_official	50:a417edff4437	1937
mbed_official	50:a417edff4437	1938	#if defined( _CMU_LFAPRESC0_LETIMER0_MASK )
mbed_official	50:a417edff4437	1939	case cmuClock_LETIMER0:
mbed_official	50:a417edff4437	1940	EFM_ASSERT(presc <= 32768U);
mbed_official	50:a417edff4437	1941
mbed_official	50:a417edff4437	1942	/* Convert prescaler value to DIV exponent scale. */
mbed_official	50:a417edff4437	1943	presc = CMU_PrescToLog2(presc);
mbed_official	50:a417edff4437	1944
mbed_official	50:a417edff4437	1945	/* LF register about to be modified require sync. Busy check. */
mbed_official	50:a417edff4437	1946	syncReg(CMU_SYNCBUSY_LFAPRESC0);
mbed_official	50:a417edff4437	1947
mbed_official	50:a417edff4437	1948	CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LETIMER0_MASK)
mbed_official	50:a417edff4437	1949	\| (presc << _CMU_LFAPRESC0_LETIMER0_SHIFT);
mbed_official	50:a417edff4437	1950	break;
mbed_official	50:a417edff4437	1951	#endif
mbed_official	50:a417edff4437	1952
mbed_official	50:a417edff4437	1953	default:
mbed_official	50:a417edff4437	1954	EFM_ASSERT(0);
mbed_official	50:a417edff4437	1955	break;
mbed_official	50:a417edff4437	1956	}
mbed_official	50:a417edff4437	1957	break;
mbed_official	50:a417edff4437	1958
mbed_official	50:a417edff4437	1959	case CMU_LFBPRESC0_REG:
mbed_official	50:a417edff4437	1960	switch (clock)
mbed_official	50:a417edff4437	1961	{
mbed_official	50:a417edff4437	1962	#if defined( _CMU_LFBPRESC0_LEUART0_MASK )
mbed_official	50:a417edff4437	1963	case cmuClock_LEUART0:
mbed_official	50:a417edff4437	1964	EFM_ASSERT(presc <= 8U);
mbed_official	50:a417edff4437	1965
mbed_official	50:a417edff4437	1966	/* Convert prescaler value to DIV exponent scale. */
mbed_official	50:a417edff4437	1967	presc = CMU_PrescToLog2(presc);
mbed_official	50:a417edff4437	1968
mbed_official	50:a417edff4437	1969	/* LF register about to be modified require sync. Busy check. */
mbed_official	50:a417edff4437	1970	syncReg(CMU_SYNCBUSY_LFBPRESC0);
mbed_official	50:a417edff4437	1971
mbed_official	50:a417edff4437	1972	CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART0_MASK)
mbed_official	50:a417edff4437	1973	\| (presc << _CMU_LFBPRESC0_LEUART0_SHIFT);
mbed_official	50:a417edff4437	1974	break;
mbed_official	50:a417edff4437	1975	#endif
mbed_official	50:a417edff4437	1976
mbed_official	50:a417edff4437	1977	#if defined( _CMU_LFBPRESC0_LEUART1_MASK )
mbed_official	50:a417edff4437	1978	case cmuClock_LEUART1:
mbed_official	50:a417edff4437	1979	EFM_ASSERT(presc <= 8U);
mbed_official	50:a417edff4437	1980
mbed_official	50:a417edff4437	1981	/* Convert prescaler value to DIV exponent scale. */
mbed_official	50:a417edff4437	1982	presc = CMU_PrescToLog2(presc);
mbed_official	50:a417edff4437	1983
mbed_official	50:a417edff4437	1984	/* LF register about to be modified require sync. Busy check. */
mbed_official	50:a417edff4437	1985	syncReg(CMU_SYNCBUSY_LFBPRESC0);
mbed_official	50:a417edff4437	1986
mbed_official	50:a417edff4437	1987	CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART1_MASK)
mbed_official	50:a417edff4437	1988	\| (presc << _CMU_LFBPRESC0_LEUART1_SHIFT);
mbed_official	50:a417edff4437	1989	break;
mbed_official	50:a417edff4437	1990	#endif
mbed_official	50:a417edff4437	1991
mbed_official	50:a417edff4437	1992	default:
mbed_official	50:a417edff4437	1993	EFM_ASSERT(0);
mbed_official	50:a417edff4437	1994	break;
mbed_official	50:a417edff4437	1995	}
mbed_official	50:a417edff4437	1996	break;
mbed_official	50:a417edff4437	1997
mbed_official	50:a417edff4437	1998	case CMU_LFEPRESC0_REG:
mbed_official	50:a417edff4437	1999	switch (clock)
mbed_official	50:a417edff4437	2000	{
mbed_official	50:a417edff4437	2001	#if defined( _CMU_LFEPRESC0_RTCC_MASK )
mbed_official	50:a417edff4437	2002	case cmuClock_RTCC:
mbed_official	50:a417edff4437	2003	EFM_ASSERT(presc <= 0U);
mbed_official	50:a417edff4437	2004
mbed_official	50:a417edff4437	2005	/* LF register about to be modified require sync. Busy check. */
mbed_official	50:a417edff4437	2006	syncReg(CMU_SYNCBUSY_LFEPRESC0);
mbed_official	50:a417edff4437	2007
mbed_official	50:a417edff4437	2008	CMU->LFEPRESC0 = (CMU->LFEPRESC0 & ~_CMU_LFEPRESC0_RTCC_MASK)
mbed_official	50:a417edff4437	2009	\| (presc << _CMU_LFEPRESC0_RTCC_SHIFT);
mbed_official	50:a417edff4437	2010	break;
mbed_official	50:a417edff4437	2011	#endif
mbed_official	50:a417edff4437	2012
mbed_official	50:a417edff4437	2013	default:
mbed_official	50:a417edff4437	2014	EFM_ASSERT(0);
mbed_official	50:a417edff4437	2015	break;
mbed_official	50:a417edff4437	2016	}
mbed_official	50:a417edff4437	2017	break;
mbed_official	50:a417edff4437	2018
mbed_official	50:a417edff4437	2019	default:
mbed_official	50:a417edff4437	2020	EFM_ASSERT(0);
mbed_official	50:a417edff4437	2021	break;
mbed_official	50:a417edff4437	2022	}
mbed_official	50:a417edff4437	2023	}
mbed_official	50:a417edff4437	2024	#endif
mbed_official	50:a417edff4437	2025
mbed_official	50:a417edff4437	2026
mbed_official	50:a417edff4437	2027	/*************************************************************************//
bogdanm	0:9b334a45a8ff	2028	* @brief
bogdanm	0:9b334a45a8ff	2029	* Get currently selected reference clock used for a clock branch.
bogdanm	0:9b334a45a8ff	2030	*
bogdanm	0:9b334a45a8ff	2031	* @param[in] clock
bogdanm	0:9b334a45a8ff	2032	* Clock branch to fetch selected ref. clock for. One of:
bogdanm	0:9b334a45a8ff	2033	* @li #cmuClock_HF
bogdanm	0:9b334a45a8ff	2034	* @li #cmuClock_LFA
mbed_official	50:a417edff4437	2035	* @li #cmuClock_LFB @if _CMU_LFCLKSEL_LFAE_ULFRCO
mbed_official	50:a417edff4437	2036	* @li #cmuClock_LFC
mbed_official	50:a417edff4437	2037	* @endif @if _SILICON_LABS_32B_PLATFORM_2
mbed_official	50:a417edff4437	2038	* @li #cmuClock_LFE
mbed_official	50:a417edff4437	2039	* @endif
bogdanm	0:9b334a45a8ff	2040	* @li #cmuClock_DBG @if DOXYDOC_USB_PRESENT
bogdanm	0:9b334a45a8ff	2041	* @li #cmuClock_USBC
bogdanm	0:9b334a45a8ff	2042	* @endif
bogdanm	0:9b334a45a8ff	2043	*
bogdanm	0:9b334a45a8ff	2044	* @return
bogdanm	0:9b334a45a8ff	2045	* Reference clock used for clocking selected branch, #cmuSelect_Error if
bogdanm	0:9b334a45a8ff	2046	* invalid @p clock provided.
mbed_official	50:a417edff4437	2047	******************************************************************************/
bogdanm	0:9b334a45a8ff	2048	CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock)
bogdanm	0:9b334a45a8ff	2049	{
bogdanm	0:9b334a45a8ff	2050	CMU_Select_TypeDef ret = cmuSelect_Disabled;
mbed_official	50:a417edff4437	2051	uint32_t selReg;
bogdanm	0:9b334a45a8ff	2052
bogdanm	0:9b334a45a8ff	2053	selReg = (clock >> CMU_SEL_REG_POS) & CMU_SEL_REG_MASK;
bogdanm	0:9b334a45a8ff	2054
bogdanm	0:9b334a45a8ff	2055	switch (selReg)
bogdanm	0:9b334a45a8ff	2056	{
mbed_official	50:a417edff4437	2057	case CMU_HFCLKSEL_REG:
mbed_official	50:a417edff4437	2058	#if defined( _CMU_HFCLKSEL_HF_MASK )
mbed_official	50:a417edff4437	2059	switch (CMU->HFCLKSEL & _CMU_HFCLKSEL_HF_MASK)
mbed_official	50:a417edff4437	2060	{
mbed_official	50:a417edff4437	2061	case CMU_HFCLKSEL_HF_LFXO:
mbed_official	50:a417edff4437	2062	ret = cmuSelect_LFXO;
mbed_official	50:a417edff4437	2063	break;
mbed_official	50:a417edff4437	2064
mbed_official	50:a417edff4437	2065	case CMU_HFCLKSEL_HF_LFRCO:
mbed_official	50:a417edff4437	2066	ret = cmuSelect_LFRCO;
mbed_official	50:a417edff4437	2067	break;
mbed_official	50:a417edff4437	2068
mbed_official	50:a417edff4437	2069	case CMU_HFCLKSEL_HF_HFXO:
mbed_official	50:a417edff4437	2070	ret = cmuSelect_HFXO;
mbed_official	50:a417edff4437	2071	break;
mbed_official	50:a417edff4437	2072
mbed_official	50:a417edff4437	2073	default:
mbed_official	50:a417edff4437	2074	ret = cmuSelect_HFRCO;
mbed_official	50:a417edff4437	2075	break;
mbed_official	50:a417edff4437	2076	}
mbed_official	50:a417edff4437	2077	#else
mbed_official	50:a417edff4437	2078	switch (CMU->STATUS
mbed_official	50:a417edff4437	2079	& (CMU_STATUS_HFRCOSEL
mbed_official	50:a417edff4437	2080	\| CMU_STATUS_HFXOSEL
mbed_official	50:a417edff4437	2081	\| CMU_STATUS_LFRCOSEL
mbed_official	50:a417edff4437	2082	#if defined( CMU_STATUS_USHFRCODIV2SEL )
mbed_official	50:a417edff4437	2083	\| CMU_STATUS_USHFRCODIV2SEL
mbed_official	50:a417edff4437	2084	#endif
mbed_official	50:a417edff4437	2085	\| CMU_STATUS_LFXOSEL))
mbed_official	50:a417edff4437	2086	{
mbed_official	50:a417edff4437	2087	case CMU_STATUS_LFXOSEL:
mbed_official	50:a417edff4437	2088	ret = cmuSelect_LFXO;
mbed_official	50:a417edff4437	2089	break;
mbed_official	50:a417edff4437	2090
mbed_official	50:a417edff4437	2091	case CMU_STATUS_LFRCOSEL:
mbed_official	50:a417edff4437	2092	ret = cmuSelect_LFRCO;
mbed_official	50:a417edff4437	2093	break;
mbed_official	50:a417edff4437	2094
mbed_official	50:a417edff4437	2095	case CMU_STATUS_HFXOSEL:
mbed_official	50:a417edff4437	2096	ret = cmuSelect_HFXO;
mbed_official	50:a417edff4437	2097	break;
bogdanm	0:9b334a45a8ff	2098
bogdanm	0:9b334a45a8ff	2099	#if defined( CMU_STATUS_USHFRCODIV2SEL )
mbed_official	50:a417edff4437	2100	case CMU_STATUS_USHFRCODIV2SEL:
mbed_official	50:a417edff4437	2101	ret = cmuSelect_USHFRCODIV2;
mbed_official	50:a417edff4437	2102	break;
mbed_official	50:a417edff4437	2103	#endif
mbed_official	50:a417edff4437	2104
mbed_official	50:a417edff4437	2105	default:
mbed_official	50:a417edff4437	2106	ret = cmuSelect_HFRCO;
mbed_official	50:a417edff4437	2107	break;
mbed_official	50:a417edff4437	2108	}
mbed_official	50:a417edff4437	2109	#endif
mbed_official	50:a417edff4437	2110	break;
mbed_official	50:a417edff4437	2111
mbed_official	50:a417edff4437	2112	case CMU_LFACLKSEL_REG:
mbed_official	50:a417edff4437	2113	#if defined( _CMU_LFCLKSEL_MASK )
mbed_official	50:a417edff4437	2114	switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFA_MASK)
mbed_official	50:a417edff4437	2115	{
mbed_official	50:a417edff4437	2116	case CMU_LFCLKSEL_LFA_LFRCO:
mbed_official	50:a417edff4437	2117	ret = cmuSelect_LFRCO;
mbed_official	50:a417edff4437	2118	break;
mbed_official	50:a417edff4437	2119
mbed_official	50:a417edff4437	2120	case CMU_LFCLKSEL_LFA_LFXO:
mbed_official	50:a417edff4437	2121	ret = cmuSelect_LFXO;
mbed_official	50:a417edff4437	2122	break;
mbed_official	50:a417edff4437	2123
mbed_official	50:a417edff4437	2124	#if defined( CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 )
mbed_official	50:a417edff4437	2125	case CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2:
mbed_official	50:a417edff4437	2126	ret = cmuSelect_CORELEDIV2;
mbed_official	50:a417edff4437	2127	break;
mbed_official	50:a417edff4437	2128	#endif
mbed_official	50:a417edff4437	2129
mbed_official	50:a417edff4437	2130	default:
mbed_official	50:a417edff4437	2131	#if defined( CMU_LFCLKSEL_LFAE )
mbed_official	50:a417edff4437	2132	if (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFAE_MASK)
mbed_official	50:a417edff4437	2133	{
mbed_official	50:a417edff4437	2134	ret = cmuSelect_ULFRCO;
mbed_official	50:a417edff4437	2135	break;
mbed_official	50:a417edff4437	2136	}
mbed_official	50:a417edff4437	2137	#else
mbed_official	50:a417edff4437	2138	ret = cmuSelect_Disabled;
mbed_official	50:a417edff4437	2139	#endif
mbed_official	50:a417edff4437	2140	break;
mbed_official	50:a417edff4437	2141	}
mbed_official	50:a417edff4437	2142	#endif /* _CMU_LFCLKSEL_MASK */
mbed_official	50:a417edff4437	2143
mbed_official	50:a417edff4437	2144	#if defined( _CMU_LFACLKSEL_MASK )
mbed_official	50:a417edff4437	2145	switch (CMU->LFACLKSEL & _CMU_LFACLKSEL_LFA_MASK)
mbed_official	50:a417edff4437	2146	{
mbed_official	50:a417edff4437	2147	case CMU_LFACLKSEL_LFA_LFRCO:
mbed_official	50:a417edff4437	2148	ret = cmuSelect_LFRCO;
mbed_official	50:a417edff4437	2149	break;
mbed_official	50:a417edff4437	2150
mbed_official	50:a417edff4437	2151	case CMU_LFACLKSEL_LFA_LFXO:
mbed_official	50:a417edff4437	2152	ret = cmuSelect_LFXO;
mbed_official	50:a417edff4437	2153	break;
mbed_official	50:a417edff4437	2154
mbed_official	50:a417edff4437	2155	case CMU_LFACLKSEL_LFA_ULFRCO:
mbed_official	50:a417edff4437	2156	ret = cmuSelect_ULFRCO;
mbed_official	50:a417edff4437	2157	break;
mbed_official	50:a417edff4437	2158
mbed_official	50:a417edff4437	2159	#if defined( _CMU_LFACLKSEL_LFA_HFCLKLE )
mbed_official	50:a417edff4437	2160	case CMU_LFACLKSEL_LFA_HFCLKLE:
mbed_official	50:a417edff4437	2161	ret = cmuSelect_HFCLKLE;
mbed_official	50:a417edff4437	2162	break;
mbed_official	50:a417edff4437	2163	#endif
mbed_official	50:a417edff4437	2164
mbed_official	50:a417edff4437	2165	default:
mbed_official	50:a417edff4437	2166	ret = cmuSelect_Disabled;
mbed_official	50:a417edff4437	2167	break;
mbed_official	50:a417edff4437	2168	}
mbed_official	50:a417edff4437	2169	#endif
mbed_official	50:a417edff4437	2170	break;
mbed_official	50:a417edff4437	2171
mbed_official	50:a417edff4437	2172	case CMU_LFBCLKSEL_REG:
mbed_official	50:a417edff4437	2173	#if defined( _CMU_LFCLKSEL_MASK )
mbed_official	50:a417edff4437	2174	switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFB_MASK)
mbed_official	50:a417edff4437	2175	{
mbed_official	50:a417edff4437	2176	case CMU_LFCLKSEL_LFB_LFRCO:
mbed_official	50:a417edff4437	2177	ret = cmuSelect_LFRCO;
mbed_official	50:a417edff4437	2178	break;
mbed_official	50:a417edff4437	2179
mbed_official	50:a417edff4437	2180	case CMU_LFCLKSEL_LFB_LFXO:
mbed_official	50:a417edff4437	2181	ret = cmuSelect_LFXO;
mbed_official	50:a417edff4437	2182	break;
mbed_official	50:a417edff4437	2183
mbed_official	50:a417edff4437	2184	#if defined( CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 )
mbed_official	50:a417edff4437	2185	case CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2:
mbed_official	50:a417edff4437	2186	ret = cmuSelect_CORELEDIV2;
mbed_official	50:a417edff4437	2187	break;
mbed_official	50:a417edff4437	2188	#endif
mbed_official	50:a417edff4437	2189
mbed_official	50:a417edff4437	2190	#if defined( CMU_LFCLKSEL_LFB_HFCLKLE )
mbed_official	50:a417edff4437	2191	case CMU_LFCLKSEL_LFB_HFCLKLE:
mbed_official	50:a417edff4437	2192	ret = cmuSelect_HFCLKLE;
mbed_official	50:a417edff4437	2193	break;
mbed_official	50:a417edff4437	2194	#endif
mbed_official	50:a417edff4437	2195
mbed_official	50:a417edff4437	2196	default:
mbed_official	50:a417edff4437	2197	#if defined( CMU_LFCLKSEL_LFBE )
mbed_official	50:a417edff4437	2198	if (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFBE_MASK)
mbed_official	50:a417edff4437	2199	{
mbed_official	50:a417edff4437	2200	ret = cmuSelect_ULFRCO;
mbed_official	50:a417edff4437	2201	break;
mbed_official	50:a417edff4437	2202	}
mbed_official	50:a417edff4437	2203	#else
mbed_official	50:a417edff4437	2204	ret = cmuSelect_Disabled;
mbed_official	50:a417edff4437	2205	#endif
mbed_official	50:a417edff4437	2206	break;
mbed_official	50:a417edff4437	2207	}
mbed_official	50:a417edff4437	2208	#endif /* _CMU_LFCLKSEL_MASK */
mbed_official	50:a417edff4437	2209
mbed_official	50:a417edff4437	2210	#if defined( _CMU_LFBCLKSEL_MASK )
mbed_official	50:a417edff4437	2211	switch (CMU->LFBCLKSEL & _CMU_LFBCLKSEL_LFB_MASK)
mbed_official	50:a417edff4437	2212	{
mbed_official	50:a417edff4437	2213	case CMU_LFBCLKSEL_LFB_LFRCO:
mbed_official	50:a417edff4437	2214	ret = cmuSelect_LFRCO;
mbed_official	50:a417edff4437	2215	break;
mbed_official	50:a417edff4437	2216
mbed_official	50:a417edff4437	2217	case CMU_LFBCLKSEL_LFB_LFXO:
mbed_official	50:a417edff4437	2218	ret = cmuSelect_LFXO;
mbed_official	50:a417edff4437	2219	break;
mbed_official	50:a417edff4437	2220
mbed_official	50:a417edff4437	2221	case CMU_LFBCLKSEL_LFB_ULFRCO:
mbed_official	50:a417edff4437	2222	ret = cmuSelect_ULFRCO;
mbed_official	50:a417edff4437	2223	break;
mbed_official	50:a417edff4437	2224
mbed_official	50:a417edff4437	2225	case CMU_LFBCLKSEL_LFB_HFCLKLE:
mbed_official	50:a417edff4437	2226	ret = cmuSelect_HFCLKLE;
mbed_official	50:a417edff4437	2227	break;
mbed_official	50:a417edff4437	2228
mbed_official	50:a417edff4437	2229	default:
mbed_official	50:a417edff4437	2230	ret = cmuSelect_Disabled;
mbed_official	50:a417edff4437	2231	break;
mbed_official	50:a417edff4437	2232	}
mbed_official	50:a417edff4437	2233	#endif
mbed_official	50:a417edff4437	2234	break;
mbed_official	50:a417edff4437	2235
mbed_official	50:a417edff4437	2236	#if defined( _CMU_LFCLKSEL_LFC_MASK )
mbed_official	50:a417edff4437	2237	case CMU_LFCCLKSEL_REG:
mbed_official	50:a417edff4437	2238	switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFC_MASK)
mbed_official	50:a417edff4437	2239	{
mbed_official	50:a417edff4437	2240	case CMU_LFCLKSEL_LFC_LFRCO:
mbed_official	50:a417edff4437	2241	ret = cmuSelect_LFRCO;
mbed_official	50:a417edff4437	2242	break;
mbed_official	50:a417edff4437	2243
mbed_official	50:a417edff4437	2244	case CMU_LFCLKSEL_LFC_LFXO:
mbed_official	50:a417edff4437	2245	ret = cmuSelect_LFXO;
mbed_official	50:a417edff4437	2246	break;
mbed_official	50:a417edff4437	2247
mbed_official	50:a417edff4437	2248	default:
mbed_official	50:a417edff4437	2249	ret = cmuSelect_Disabled;
mbed_official	50:a417edff4437	2250	break;
mbed_official	50:a417edff4437	2251	}
mbed_official	50:a417edff4437	2252	break;
mbed_official	50:a417edff4437	2253	#endif
mbed_official	50:a417edff4437	2254
mbed_official	50:a417edff4437	2255	#if defined( _CMU_LFECLKSEL_LFE_MASK )
mbed_official	50:a417edff4437	2256	case CMU_LFECLKSEL_REG:
mbed_official	50:a417edff4437	2257	switch (CMU->LFECLKSEL & _CMU_LFECLKSEL_LFE_MASK)
mbed_official	50:a417edff4437	2258	{
mbed_official	50:a417edff4437	2259	case CMU_LFECLKSEL_LFE_LFRCO:
mbed_official	50:a417edff4437	2260	ret = cmuSelect_LFRCO;
mbed_official	50:a417edff4437	2261	break;
mbed_official	50:a417edff4437	2262
mbed_official	50:a417edff4437	2263	case CMU_LFECLKSEL_LFE_LFXO:
mbed_official	50:a417edff4437	2264	ret = cmuSelect_LFXO;
mbed_official	50:a417edff4437	2265	break;
mbed_official	50:a417edff4437	2266
mbed_official	50:a417edff4437	2267	case CMU_LFECLKSEL_LFE_ULFRCO:
mbed_official	50:a417edff4437	2268	ret = cmuSelect_ULFRCO;
mbed_official	50:a417edff4437	2269	break;
mbed_official	50:a417edff4437	2270
mbed_official	50:a417edff4437	2271	#if defined ( _CMU_LFECLKSEL_LFE_HFCLKLE )
mbed_official	50:a417edff4437	2272	case CMU_LFECLKSEL_LFE_HFCLKLE:
mbed_official	50:a417edff4437	2273	ret = cmuSelect_HFCLKLE;
mbed_official	50:a417edff4437	2274	break;
mbed_official	50:a417edff4437	2275	#endif
mbed_official	50:a417edff4437	2276
mbed_official	50:a417edff4437	2277	default:
mbed_official	50:a417edff4437	2278	ret = cmuSelect_Disabled;
mbed_official	50:a417edff4437	2279	break;
mbed_official	50:a417edff4437	2280	}
mbed_official	50:a417edff4437	2281	break;
mbed_official	50:a417edff4437	2282	#endif /* CMU_LFECLKSEL_REG */
mbed_official	50:a417edff4437	2283
mbed_official	50:a417edff4437	2284	case CMU_DBGCLKSEL_REG:
mbed_official	50:a417edff4437	2285	#if defined( _CMU_DBGCLKSEL_DBG_MASK )
mbed_official	50:a417edff4437	2286	switch (CMU->DBGCLKSEL & _CMU_DBGCLKSEL_DBG_MASK)
mbed_official	50:a417edff4437	2287	{
mbed_official	50:a417edff4437	2288	case CMU_DBGCLKSEL_DBG_HFCLK:
mbed_official	50:a417edff4437	2289	ret = cmuSelect_HFCLK;
mbed_official	50:a417edff4437	2290	break;
mbed_official	50:a417edff4437	2291
mbed_official	50:a417edff4437	2292	case CMU_DBGCLKSEL_DBG_AUXHFRCO:
mbed_official	50:a417edff4437	2293	ret = cmuSelect_AUXHFRCO;
mbed_official	50:a417edff4437	2294	break;
mbed_official	50:a417edff4437	2295	}
mbed_official	50:a417edff4437	2296	#else
mbed_official	50:a417edff4437	2297	ret = cmuSelect_AUXHFRCO;
mbed_official	50:a417edff4437	2298	#endif /* CMU_DBGCLKSEL_DBG */
mbed_official	50:a417edff4437	2299
mbed_official	50:a417edff4437	2300	#if defined( _CMU_CTRL_DBGCLK_MASK )
mbed_official	50:a417edff4437	2301	switch(CMU->CTRL & _CMU_CTRL_DBGCLK_MASK)
mbed_official	50:a417edff4437	2302	{
mbed_official	50:a417edff4437	2303	case CMU_CTRL_DBGCLK_AUXHFRCO:
mbed_official	50:a417edff4437	2304	ret = cmuSelect_AUXHFRCO;
mbed_official	50:a417edff4437	2305	break;
mbed_official	50:a417edff4437	2306
mbed_official	50:a417edff4437	2307	case CMU_CTRL_DBGCLK_HFCLK:
mbed_official	50:a417edff4437	2308	ret = cmuSelect_HFCLK;
mbed_official	50:a417edff4437	2309	break;
mbed_official	50:a417edff4437	2310	}
mbed_official	50:a417edff4437	2311	#else
mbed_official	50:a417edff4437	2312	ret = cmuSelect_AUXHFRCO;
mbed_official	50:a417edff4437	2313	#endif
mbed_official	50:a417edff4437	2314	break;
mbed_official	50:a417edff4437	2315
mbed_official	50:a417edff4437	2316
mbed_official	50:a417edff4437	2317	#if defined( USB_PRESENT )
mbed_official	50:a417edff4437	2318	case CMU_USBCCLKSEL_REG:
mbed_official	50:a417edff4437	2319	switch (CMU->STATUS
mbed_official	50:a417edff4437	2320	& (CMU_STATUS_USBCLFXOSEL
mbed_official	50:a417edff4437	2321	#if defined(_CMU_STATUS_USBCHFCLKSEL_MASK)
mbed_official	50:a417edff4437	2322	\| CMU_STATUS_USBCHFCLKSEL
mbed_official	50:a417edff4437	2323	#endif
mbed_official	50:a417edff4437	2324	#if defined(_CMU_STATUS_USBCUSHFRCOSEL_MASK)
mbed_official	50:a417edff4437	2325	\| CMU_STATUS_USBCUSHFRCOSEL
mbed_official	50:a417edff4437	2326	#endif
mbed_official	50:a417edff4437	2327	\| CMU_STATUS_USBCLFRCOSEL))
mbed_official	50:a417edff4437	2328	{
mbed_official	50:a417edff4437	2329	#if defined(_CMU_STATUS_USBCHFCLKSEL_MASK)
mbed_official	50:a417edff4437	2330	case CMU_STATUS_USBCHFCLKSEL:
mbed_official	50:a417edff4437	2331	ret = cmuSelect_HFCLK;
mbed_official	50:a417edff4437	2332	break;
mbed_official	50:a417edff4437	2333	#endif
mbed_official	50:a417edff4437	2334
mbed_official	50:a417edff4437	2335	#if defined(_CMU_STATUS_USBCUSHFRCOSEL_MASK)
mbed_official	50:a417edff4437	2336	case CMU_STATUS_USBCUSHFRCOSEL:
mbed_official	50:a417edff4437	2337	ret = cmuSelect_USHFRCO;
mbed_official	50:a417edff4437	2338	break;
mbed_official	50:a417edff4437	2339	#endif
mbed_official	50:a417edff4437	2340
mbed_official	50:a417edff4437	2341	case CMU_STATUS_USBCLFXOSEL:
mbed_official	50:a417edff4437	2342	ret = cmuSelect_LFXO;
mbed_official	50:a417edff4437	2343	break;
mbed_official	50:a417edff4437	2344
mbed_official	50:a417edff4437	2345	case CMU_STATUS_USBCLFRCOSEL:
mbed_official	50:a417edff4437	2346	ret = cmuSelect_LFRCO;
mbed_official	50:a417edff4437	2347	break;
mbed_official	50:a417edff4437	2348
mbed_official	50:a417edff4437	2349	default:
mbed_official	50:a417edff4437	2350	ret = cmuSelect_Disabled;
mbed_official	50:a417edff4437	2351	break;
mbed_official	50:a417edff4437	2352	}
bogdanm	0:9b334a45a8ff	2353	break;
bogdanm	0:9b334a45a8ff	2354	#endif
bogdanm	0:9b334a45a8ff	2355
bogdanm	0:9b334a45a8ff	2356	default:
mbed_official	50:a417edff4437	2357	EFM_ASSERT(0);
mbed_official	50:a417edff4437	2358	ret = cmuSelect_Error;
bogdanm	0:9b334a45a8ff	2359	break;
bogdanm	0:9b334a45a8ff	2360	}
bogdanm	0:9b334a45a8ff	2361
bogdanm	0:9b334a45a8ff	2362	return ret;
bogdanm	0:9b334a45a8ff	2363	}
bogdanm	0:9b334a45a8ff	2364
bogdanm	0:9b334a45a8ff	2365
mbed_official	50:a417edff4437	2366	/*************************************************************************//
bogdanm	0:9b334a45a8ff	2367	* @brief
bogdanm	0:9b334a45a8ff	2368	* Select reference clock/oscillator used for a clock branch.
bogdanm	0:9b334a45a8ff	2369	*
bogdanm	0:9b334a45a8ff	2370	* @details
bogdanm	0:9b334a45a8ff	2371	* Notice that if a selected reference is not enabled prior to selecting its
bogdanm	0:9b334a45a8ff	2372	* use, it will be enabled, and this function will wait for the selected
bogdanm	0:9b334a45a8ff	2373	* oscillator to be stable. It will however NOT be disabled if another
bogdanm	0:9b334a45a8ff	2374	* reference clock is selected later.
bogdanm	0:9b334a45a8ff	2375	*
bogdanm	0:9b334a45a8ff	2376	* This feature is particularly important if selecting a new reference
bogdanm	0:9b334a45a8ff	2377	* clock for the clock branch clocking the core, otherwise the system
bogdanm	0:9b334a45a8ff	2378	* may halt.
bogdanm	0:9b334a45a8ff	2379	*
bogdanm	0:9b334a45a8ff	2380	* @param[in] clock
bogdanm	0:9b334a45a8ff	2381	* Clock branch to select reference clock for. One of:
bogdanm	0:9b334a45a8ff	2382	* @li #cmuClock_HF
bogdanm	0:9b334a45a8ff	2383	* @li #cmuClock_LFA
mbed_official	50:a417edff4437	2384	* @li #cmuClock_LFB @if _CMU_LFCLKSEL_LFAE_ULFRCO
mbed_official	50:a417edff4437	2385	* @li #cmuClock_LFC
mbed_official	50:a417edff4437	2386	* @endif @if _SILICON_LABS_32B_PLATFORM_2
mbed_official	50:a417edff4437	2387	* @li #cmuClock_LFE
mbed_official	50:a417edff4437	2388	* @endif
bogdanm	0:9b334a45a8ff	2389	* @li #cmuClock_DBG @if DOXYDOC_USB_PRESENT
bogdanm	0:9b334a45a8ff	2390	* @li #cmuClock_USBC
bogdanm	0:9b334a45a8ff	2391	* @endif
bogdanm	0:9b334a45a8ff	2392	*
bogdanm	0:9b334a45a8ff	2393	* @param[in] ref
bogdanm	0:9b334a45a8ff	2394	* Reference selected for clocking, please refer to reference manual for
bogdanm	0:9b334a45a8ff	2395	* for details on which reference is available for a specific clock branch.
bogdanm	0:9b334a45a8ff	2396	* @li #cmuSelect_HFRCO
bogdanm	0:9b334a45a8ff	2397	* @li #cmuSelect_LFRCO
bogdanm	0:9b334a45a8ff	2398	* @li #cmuSelect_HFXO
bogdanm	0:9b334a45a8ff	2399	* @li #cmuSelect_LFXO
bogdanm	0:9b334a45a8ff	2400	* @li #cmuSelect_CORELEDIV2
bogdanm	0:9b334a45a8ff	2401	* @li #cmuSelect_AUXHFRCO
bogdanm	0:9b334a45a8ff	2402	* @li #cmuSelect_HFCLK @ifnot DOXYDOC_EFM32_GECKO_FAMILY
bogdanm	0:9b334a45a8ff	2403	* @li #cmuSelect_ULFRCO
bogdanm	0:9b334a45a8ff	2404	* @endif
mbed_official	50:a417edff4437	2405	******************************************************************************/
bogdanm	0:9b334a45a8ff	2406	void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref)
bogdanm	0:9b334a45a8ff	2407	{
bogdanm	0:9b334a45a8ff	2408	uint32_t select = cmuOsc_HFRCO;
bogdanm	0:9b334a45a8ff	2409	CMU_Osc_TypeDef osc = cmuOsc_HFRCO;
bogdanm	0:9b334a45a8ff	2410	uint32_t freq;
mbed_official	50:a417edff4437	2411	uint32_t tmp;
mbed_official	50:a417edff4437	2412	uint32_t selRegId;
mbed_official	50:a417edff4437	2413	#if defined( _SILICON_LABS_32B_PLATFORM_2 )
mbed_official	50:a417edff4437	2414	volatile uint32_t *selReg = NULL;
mbed_official	50:a417edff4437	2415	#endif
mbed_official	50:a417edff4437	2416	#if defined( CMU_LFCLKSEL_LFAE_ULFRCO )
bogdanm	0:9b334a45a8ff	2417	uint32_t lfExtended = 0;
bogdanm	0:9b334a45a8ff	2418	#endif
mbed_official	50:a417edff4437	2419
mbed_official	50:a417edff4437	2420	selRegId = (clock >> CMU_SEL_REG_POS) & CMU_SEL_REG_MASK;
mbed_official	50:a417edff4437	2421
mbed_official	50:a417edff4437	2422	switch (selRegId)
bogdanm	0:9b334a45a8ff	2423	{
mbed_official	50:a417edff4437	2424	case CMU_HFCLKSEL_REG:
mbed_official	50:a417edff4437	2425	switch (ref)
mbed_official	50:a417edff4437	2426	{
mbed_official	50:a417edff4437	2427	case cmuSelect_LFXO:
mbed_official	50:a417edff4437	2428	#if defined( _SILICON_LABS_32B_PLATFORM_2 )
mbed_official	50:a417edff4437	2429	select = CMU_HFCLKSEL_HF_LFXO;
mbed_official	50:a417edff4437	2430	#elif defined( _SILICON_LABS_32B_PLATFORM_1 )
mbed_official	50:a417edff4437	2431	select = CMU_CMD_HFCLKSEL_LFXO;
mbed_official	50:a417edff4437	2432	#endif
mbed_official	50:a417edff4437	2433	osc = cmuOsc_LFXO;
mbed_official	50:a417edff4437	2434	break;
mbed_official	50:a417edff4437	2435
mbed_official	50:a417edff4437	2436	case cmuSelect_LFRCO:
mbed_official	50:a417edff4437	2437	#if defined( _SILICON_LABS_32B_PLATFORM_2 )
mbed_official	50:a417edff4437	2438	select = CMU_HFCLKSEL_HF_LFRCO;
mbed_official	50:a417edff4437	2439	#elif defined( _SILICON_LABS_32B_PLATFORM_1 )
mbed_official	50:a417edff4437	2440	select = CMU_CMD_HFCLKSEL_LFRCO;
mbed_official	50:a417edff4437	2441	#endif
mbed_official	50:a417edff4437	2442	osc = cmuOsc_LFRCO;
mbed_official	50:a417edff4437	2443	break;
mbed_official	50:a417edff4437	2444
mbed_official	50:a417edff4437	2445	case cmuSelect_HFXO:
mbed_official	50:a417edff4437	2446	osc = cmuOsc_HFXO;
mbed_official	50:a417edff4437	2447	#if defined( _SILICON_LABS_32B_PLATFORM_2 )
mbed_official	50:a417edff4437	2448	select = CMU_HFCLKSEL_HF_HFXO;
mbed_official	50:a417edff4437	2449	/* Adjust HFXO buffer current for high frequencies, */
mbed_official	50:a417edff4437	2450	/* enable WSHFLE for frequencies above 32MHz. */
mbed_official	50:a417edff4437	2451	if (SystemHFXOClockGet() > 32000000)
mbed_official	50:a417edff4437	2452	{
mbed_official	50:a417edff4437	2453	CMU->CTRL \|= CMU_CTRL_WSHFLE;
mbed_official	50:a417edff4437	2454	}
mbed_official	50:a417edff4437	2455	#elif defined( _SILICON_LABS_32B_PLATFORM_1 )
mbed_official	50:a417edff4437	2456	select = CMU_CMD_HFCLKSEL_HFXO;
bogdanm	0:9b334a45a8ff	2457	#if defined( CMU_CTRL_HFLE )
mbed_official	50:a417edff4437	2458	/* Adjust HFXO buffer current for high frequencies, */
mbed_official	50:a417edff4437	2459	/* enable HFLE for frequencies above CMU_MAX_FREQ_HFLE. */
mbed_official	50:a417edff4437	2460	if(SystemHFXOClockGet() > CMU_MAX_FREQ_HFLE())
mbed_official	50:a417edff4437	2461	{
mbed_official	50:a417edff4437	2462	CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK)
mbed_official	50:a417edff4437	2463	\| CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ
mbed_official	50:a417edff4437	2464	/* Must have HFLE enabled to access some LE peripherals >=32MHz */
mbed_official	50:a417edff4437	2465	\| CMU_CTRL_HFLE;
mbed_official	50:a417edff4437	2466
mbed_official	50:a417edff4437	2467	/* Set HFLE and DIV4 factor for peripheral clock if HFCORE */
mbed_official	50:a417edff4437	2468	/* clock for LE is enabled. */
mbed_official	50:a417edff4437	2469	if (CMU->HFCORECLKEN0 & CMU_HFCORECLKEN0_LE)
mbed_official	50:a417edff4437	2470	{
mbed_official	50:a417edff4437	2471	BUS_RegBitWrite(&CMU->HFCORECLKDIV,
mbed_official	50:a417edff4437	2472	_CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 1);
mbed_official	50:a417edff4437	2473	}
mbed_official	50:a417edff4437	2474	}
mbed_official	50:a417edff4437	2475	else
mbed_official	50:a417edff4437	2476	{
mbed_official	50:a417edff4437	2477	/* This can happen if the user configures the EFM32_HFXO_FREQ to */
mbed_official	50:a417edff4437	2478	/* use another oscillator frequency */
mbed_official	50:a417edff4437	2479	CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK)
mbed_official	50:a417edff4437	2480	\| CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ;
mbed_official	50:a417edff4437	2481	}
bogdanm	0:9b334a45a8ff	2482	#endif
mbed_official	50:a417edff4437	2483	#endif
mbed_official	50:a417edff4437	2484	break;
mbed_official	50:a417edff4437	2485
mbed_official	50:a417edff4437	2486	case cmuSelect_HFRCO:
mbed_official	50:a417edff4437	2487	#if defined( _SILICON_LABS_32B_PLATFORM_2 )
mbed_official	50:a417edff4437	2488	select = CMU_HFCLKSEL_HF_HFRCO;
mbed_official	50:a417edff4437	2489	#elif defined( _SILICON_LABS_32B_PLATFORM_1 )
mbed_official	50:a417edff4437	2490	select = CMU_CMD_HFCLKSEL_HFRCO;
mbed_official	50:a417edff4437	2491	#endif
mbed_official	50:a417edff4437	2492	osc = cmuOsc_HFRCO;
mbed_official	50:a417edff4437	2493	break;
bogdanm	0:9b334a45a8ff	2494
bogdanm	0:9b334a45a8ff	2495	#if defined( CMU_CMD_HFCLKSEL_USHFRCODIV2 )
mbed_official	50:a417edff4437	2496	case cmuSelect_USHFRCODIV2:
mbed_official	50:a417edff4437	2497	select = CMU_CMD_HFCLKSEL_USHFRCODIV2;
mbed_official	50:a417edff4437	2498	osc = cmuOsc_USHFRCO;
mbed_official	50:a417edff4437	2499	break;
mbed_official	50:a417edff4437	2500	#endif
mbed_official	50:a417edff4437	2501
mbed_official	50:a417edff4437	2502	#if defined( CMU_LFCLKSEL_LFAE_ULFRCO ) \|\| defined( CMU_LFACLKSEL_LFA_ULFRCO )
mbed_official	50:a417edff4437	2503	case cmuSelect_ULFRCO:
mbed_official	50:a417edff4437	2504	/* ULFRCO cannot be used as HFCLK */
mbed_official	50:a417edff4437	2505	EFM_ASSERT(0);
mbed_official	50:a417edff4437	2506	return;
mbed_official	50:a417edff4437	2507	#endif
mbed_official	50:a417edff4437	2508
mbed_official	50:a417edff4437	2509	default:
mbed_official	50:a417edff4437	2510	EFM_ASSERT(0);
mbed_official	50:a417edff4437	2511	return;
mbed_official	50:a417edff4437	2512	}
mbed_official	50:a417edff4437	2513
mbed_official	50:a417edff4437	2514	/* Ensure selected oscillator is enabled, waiting for it to stabilize */
mbed_official	50:a417edff4437	2515	CMU_OscillatorEnable(osc, true, true);
mbed_official	50:a417edff4437	2516
mbed_official	50:a417edff4437	2517	/* Configure worst case wait states for flash access before selecting */
mbed_official	50:a417edff4437	2518	flashWaitStateMax();
mbed_official	50:a417edff4437	2519
mbed_official	50:a417edff4437	2520	/* Switch to selected oscillator */
mbed_official	50:a417edff4437	2521	#if defined( _SILICON_LABS_32B_PLATFORM_2 )
mbed_official	50:a417edff4437	2522	CMU->HFCLKSEL = select;
mbed_official	50:a417edff4437	2523	#elif defined( _SILICON_LABS_32B_PLATFORM_1 )
mbed_official	50:a417edff4437	2524	CMU->CMD = select;
mbed_official	50:a417edff4437	2525	#endif
mbed_official	50:a417edff4437	2526
mbed_official	50:a417edff4437	2527	/* Keep EMU module informed */
mbed_official	50:a417edff4437	2528	EMU_UpdateOscConfig();
mbed_official	50:a417edff4437	2529
mbed_official	50:a417edff4437	2530	/* Update CMSIS core clock variable */
mbed_official	50:a417edff4437	2531	/* (The function will update the global variable) */
mbed_official	50:a417edff4437	2532	freq = SystemCoreClockGet();
mbed_official	50:a417edff4437	2533
mbed_official	50:a417edff4437	2534	/* Optimize flash access wait state setting for currently selected core clk */
mbed_official	50:a417edff4437	2535	flashWaitStateControl(freq);
mbed_official	50:a417edff4437	2536	break;
mbed_official	50:a417edff4437	2537
mbed_official	50:a417edff4437	2538	#if defined( _SILICON_LABS_32B_PLATFORM_2 )
mbed_official	50:a417edff4437	2539	case CMU_LFACLKSEL_REG:
mbed_official	50:a417edff4437	2540	selReg = (selReg == NULL) ? &CMU->LFACLKSEL : selReg;
mbed_official	50:a417edff4437	2541	#if !defined( _CMU_LFACLKSEL_LFA_HFCLKLE )
mbed_official	50:a417edff4437	2542	/* HFCLKCLE can not be used as LFACLK */
mbed_official	50:a417edff4437	2543	EFM_ASSERT(ref != cmuSelect_HFCLKLE);
mbed_official	50:a417edff4437	2544	#endif
mbed_official	50:a417edff4437	2545	case CMU_LFECLKSEL_REG:
mbed_official	50:a417edff4437	2546	selReg = (selReg == NULL) ? &CMU->LFECLKSEL : selReg;
mbed_official	50:a417edff4437	2547	#if !defined( _CMU_LFECLKSEL_LFE_HFCLKLE )
mbed_official	50:a417edff4437	2548	/* HFCLKCLE can not be used as LFECLK */
mbed_official	50:a417edff4437	2549	EFM_ASSERT(ref != cmuSelect_HFCLKLE);
mbed_official	50:a417edff4437	2550	#endif
mbed_official	50:a417edff4437	2551	case CMU_LFBCLKSEL_REG:
mbed_official	50:a417edff4437	2552	selReg = (selReg == NULL) ? &CMU->LFBCLKSEL : selReg;
mbed_official	50:a417edff4437	2553	switch (ref)
mbed_official	50:a417edff4437	2554	{
mbed_official	50:a417edff4437	2555	case cmuSelect_Disabled:
mbed_official	50:a417edff4437	2556	tmp = _CMU_LFACLKSEL_LFA_DISABLED;
mbed_official	50:a417edff4437	2557	break;
mbed_official	50:a417edff4437	2558
mbed_official	50:a417edff4437	2559	case cmuSelect_LFXO:
mbed_official	50:a417edff4437	2560	/* Ensure selected oscillator is enabled, waiting for it to stabilize */
mbed_official	50:a417edff4437	2561	CMU_OscillatorEnable(cmuOsc_LFXO, true, true);
mbed_official	50:a417edff4437	2562	tmp = _CMU_LFACLKSEL_LFA_LFXO;
mbed_official	50:a417edff4437	2563	break;
mbed_official	50:a417edff4437	2564
mbed_official	50:a417edff4437	2565	case cmuSelect_LFRCO:
mbed_official	50:a417edff4437	2566	/* Ensure selected oscillator is enabled, waiting for it to stabilize */
mbed_official	50:a417edff4437	2567	CMU_OscillatorEnable(cmuOsc_LFRCO, true, true);
mbed_official	50:a417edff4437	2568	tmp = _CMU_LFACLKSEL_LFA_LFRCO;
mbed_official	50:a417edff4437	2569	break;
mbed_official	50:a417edff4437	2570
mbed_official	50:a417edff4437	2571	case cmuSelect_HFCLKLE:
mbed_official	50:a417edff4437	2572	/* Ensure HFCORE to LE clocking is enabled */
mbed_official	50:a417edff4437	2573	BUS_RegBitWrite(&CMU->HFBUSCLKEN0, _CMU_HFBUSCLKEN0_LE_SHIFT, 1);
mbed_official	50:a417edff4437	2574	tmp = _CMU_LFBCLKSEL_LFB_HFCLKLE;
mbed_official	50:a417edff4437	2575
mbed_official	50:a417edff4437	2576	/* If core frequency is > 32MHz enable WSHFLE */
mbed_official	50:a417edff4437	2577	freq = SystemCoreClockGet();
mbed_official	50:a417edff4437	2578	if (freq > 32000000U)
mbed_official	50:a417edff4437	2579	{
mbed_official	50:a417edff4437	2580	/* Enable CMU HFLE */
mbed_official	50:a417edff4437	2581	BUS_RegBitWrite(&CMU->CTRL, _CMU_CTRL_WSHFLE_SHIFT, 1);
mbed_official	50:a417edff4437	2582
mbed_official	50:a417edff4437	2583	/* Enable DIV4 factor for peripheral clock */
mbed_official	50:a417edff4437	2584	BUS_RegBitWrite(&CMU->HFPRESC, _CMU_HFPRESC_HFCLKLEPRESC_SHIFT, 1);
mbed_official	50:a417edff4437	2585	}
mbed_official	50:a417edff4437	2586	break;
mbed_official	50:a417edff4437	2587
mbed_official	50:a417edff4437	2588	case cmuSelect_ULFRCO:
mbed_official	50:a417edff4437	2589	/* ULFRCO is always on, there is no need to enable it. */
mbed_official	50:a417edff4437	2590	tmp = _CMU_LFACLKSEL_LFA_ULFRCO;
mbed_official	50:a417edff4437	2591	break;
mbed_official	50:a417edff4437	2592
mbed_official	50:a417edff4437	2593	default:
mbed_official	50:a417edff4437	2594	EFM_ASSERT(0);
mbed_official	50:a417edff4437	2595	return;
mbed_official	50:a417edff4437	2596	}
mbed_official	50:a417edff4437	2597	*selReg = tmp;
mbed_official	50:a417edff4437	2598	break;
mbed_official	50:a417edff4437	2599
mbed_official	50:a417edff4437	2600	#elif defined( _SILICON_LABS_32B_PLATFORM_1 )
mbed_official	50:a417edff4437	2601	case CMU_LFACLKSEL_REG:
mbed_official	50:a417edff4437	2602	case CMU_LFBCLKSEL_REG:
mbed_official	50:a417edff4437	2603	switch (ref)
mbed_official	50:a417edff4437	2604	{
mbed_official	50:a417edff4437	2605	case cmuSelect_Disabled:
mbed_official	50:a417edff4437	2606	tmp = _CMU_LFCLKSEL_LFA_DISABLED;
mbed_official	50:a417edff4437	2607	break;
mbed_official	50:a417edff4437	2608
mbed_official	50:a417edff4437	2609	case cmuSelect_LFXO:
mbed_official	50:a417edff4437	2610	/* Ensure selected oscillator is enabled, waiting for it to stabilize */
mbed_official	50:a417edff4437	2611	CMU_OscillatorEnable(cmuOsc_LFXO, true, true);
mbed_official	50:a417edff4437	2612	tmp = _CMU_LFCLKSEL_LFA_LFXO;
mbed_official	50:a417edff4437	2613	break;
mbed_official	50:a417edff4437	2614
mbed_official	50:a417edff4437	2615	case cmuSelect_LFRCO:
mbed_official	50:a417edff4437	2616	/* Ensure selected oscillator is enabled, waiting for it to stabilize */
mbed_official	50:a417edff4437	2617	CMU_OscillatorEnable(cmuOsc_LFRCO, true, true);
mbed_official	50:a417edff4437	2618	tmp = _CMU_LFCLKSEL_LFA_LFRCO;
mbed_official	50:a417edff4437	2619	break;
mbed_official	50:a417edff4437	2620
mbed_official	50:a417edff4437	2621	case cmuSelect_CORELEDIV2:
mbed_official	50:a417edff4437	2622	/* Ensure HFCORE to LE clocking is enabled */
mbed_official	50:a417edff4437	2623	BUS_RegBitWrite(&(CMU->HFCORECLKEN0), _CMU_HFCORECLKEN0_LE_SHIFT, 1);
mbed_official	50:a417edff4437	2624	tmp = _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2;
mbed_official	50:a417edff4437	2625	#if defined( CMU_CTRL_HFLE )
mbed_official	50:a417edff4437	2626	/* If core frequency is higher than CMU_MAX_FREQ_HFLE on
mbed_official	50:a417edff4437	2627	Giant/Leopard/Wonder, enable HFLE and DIV4. */
mbed_official	50:a417edff4437	2628	freq = SystemCoreClockGet();
mbed_official	50:a417edff4437	2629	if(freq > CMU_MAX_FREQ_HFLE())
mbed_official	50:a417edff4437	2630	{
mbed_official	50:a417edff4437	2631	/* Enable CMU HFLE */
mbed_official	50:a417edff4437	2632	BUS_RegBitWrite(&CMU->CTRL, _CMU_CTRL_HFLE_SHIFT, 1);
mbed_official	50:a417edff4437	2633
mbed_official	50:a417edff4437	2634	/* Enable DIV4 factor for peripheral clock */
mbed_official	50:a417edff4437	2635	BUS_RegBitWrite(&CMU->HFCORECLKDIV,
mbed_official	50:a417edff4437	2636	_CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 1);
mbed_official	50:a417edff4437	2637	}
mbed_official	50:a417edff4437	2638	#endif
mbed_official	50:a417edff4437	2639	break;
mbed_official	50:a417edff4437	2640
mbed_official	50:a417edff4437	2641	#if defined( CMU_LFCLKSEL_LFAE_ULFRCO )
mbed_official	50:a417edff4437	2642	case cmuSelect_ULFRCO:
mbed_official	50:a417edff4437	2643	/* ULFRCO is always enabled */
mbed_official	50:a417edff4437	2644	tmp = _CMU_LFCLKSEL_LFA_DISABLED;
mbed_official	50:a417edff4437	2645	lfExtended = 1;
mbed_official	50:a417edff4437	2646	break;
mbed_official	50:a417edff4437	2647	#endif
mbed_official	50:a417edff4437	2648
mbed_official	50:a417edff4437	2649	default:
mbed_official	50:a417edff4437	2650	/* Illegal clock source for LFA/LFB selected */
mbed_official	50:a417edff4437	2651	EFM_ASSERT(0);
mbed_official	50:a417edff4437	2652	return;
mbed_official	50:a417edff4437	2653	}
mbed_official	50:a417edff4437	2654
mbed_official	50:a417edff4437	2655	/* Apply select */
mbed_official	50:a417edff4437	2656	if (selRegId == CMU_LFACLKSEL_REG)
mbed_official	50:a417edff4437	2657	{
mbed_official	50:a417edff4437	2658	#if defined( _CMU_LFCLKSEL_LFAE_MASK )
mbed_official	50:a417edff4437	2659	CMU->LFCLKSEL = (CMU->LFCLKSEL
mbed_official	50:a417edff4437	2660	& ~(_CMU_LFCLKSEL_LFA_MASK \| _CMU_LFCLKSEL_LFAE_MASK))
mbed_official	50:a417edff4437	2661	\| (tmp << _CMU_LFCLKSEL_LFA_SHIFT)
mbed_official	50:a417edff4437	2662	\| (lfExtended << _CMU_LFCLKSEL_LFAE_SHIFT);
mbed_official	50:a417edff4437	2663	#else
mbed_official	50:a417edff4437	2664	CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK)
mbed_official	50:a417edff4437	2665	\| (tmp << _CMU_LFCLKSEL_LFA_SHIFT);
mbed_official	50:a417edff4437	2666	#endif
mbed_official	50:a417edff4437	2667	}
mbed_official	50:a417edff4437	2668	else
mbed_official	50:a417edff4437	2669	{
mbed_official	50:a417edff4437	2670	#if defined( _CMU_LFCLKSEL_LFBE_MASK )
mbed_official	50:a417edff4437	2671	CMU->LFCLKSEL = (CMU->LFCLKSEL
mbed_official	50:a417edff4437	2672	& ~(_CMU_LFCLKSEL_LFB_MASK \| _CMU_LFCLKSEL_LFBE_MASK))
mbed_official	50:a417edff4437	2673	\| (tmp << _CMU_LFCLKSEL_LFB_SHIFT)
mbed_official	50:a417edff4437	2674	\| (lfExtended << _CMU_LFCLKSEL_LFBE_SHIFT);
mbed_official	50:a417edff4437	2675	#else
mbed_official	50:a417edff4437	2676	CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK)
mbed_official	50:a417edff4437	2677	\| (tmp << _CMU_LFCLKSEL_LFB_SHIFT);
mbed_official	50:a417edff4437	2678	#endif
mbed_official	50:a417edff4437	2679	}
mbed_official	50:a417edff4437	2680	break;
mbed_official	50:a417edff4437	2681
mbed_official	50:a417edff4437	2682	#if defined( _CMU_LFCLKSEL_LFC_MASK )
mbed_official	50:a417edff4437	2683	case CMU_LFCCLKSEL_REG:
mbed_official	50:a417edff4437	2684	switch(ref)
mbed_official	50:a417edff4437	2685	{
mbed_official	50:a417edff4437	2686	case cmuSelect_Disabled:
mbed_official	50:a417edff4437	2687	tmp = _CMU_LFCLKSEL_LFA_DISABLED;
mbed_official	50:a417edff4437	2688	break;
mbed_official	50:a417edff4437	2689
mbed_official	50:a417edff4437	2690	case cmuSelect_LFXO:
mbed_official	50:a417edff4437	2691	/* Ensure selected oscillator is enabled, waiting for it to stabilize */
mbed_official	50:a417edff4437	2692	CMU_OscillatorEnable(cmuOsc_LFXO, true, true);
mbed_official	50:a417edff4437	2693	tmp = _CMU_LFCLKSEL_LFC_LFXO;
mbed_official	50:a417edff4437	2694	break;
mbed_official	50:a417edff4437	2695
mbed_official	50:a417edff4437	2696	case cmuSelect_LFRCO:
mbed_official	50:a417edff4437	2697	/* Ensure selected oscillator is enabled, waiting for it to stabilize */
mbed_official	50:a417edff4437	2698	CMU_OscillatorEnable(cmuOsc_LFRCO, true, true);
mbed_official	50:a417edff4437	2699	tmp = _CMU_LFCLKSEL_LFC_LFRCO;
mbed_official	50:a417edff4437	2700	break;
mbed_official	50:a417edff4437	2701
mbed_official	50:a417edff4437	2702	default:
mbed_official	50:a417edff4437	2703	/* Illegal clock source for LFC selected */
mbed_official	50:a417edff4437	2704	EFM_ASSERT(0);
mbed_official	50:a417edff4437	2705	return;
mbed_official	50:a417edff4437	2706	}
mbed_official	50:a417edff4437	2707
mbed_official	50:a417edff4437	2708	/* Apply select */
mbed_official	50:a417edff4437	2709	CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFC_MASK)
mbed_official	50:a417edff4437	2710	\| (tmp << _CMU_LFCLKSEL_LFC_SHIFT);
bogdanm	0:9b334a45a8ff	2711	break;
bogdanm	0:9b334a45a8ff	2712	#endif
mbed_official	50:a417edff4437	2713	#endif
mbed_official	50:a417edff4437	2714
mbed_official	50:a417edff4437	2715	#if defined( CMU_DBGCLKSEL_DBG ) \|\| defined( CMU_CTRL_DBGCLK )
mbed_official	50:a417edff4437	2716	case CMU_DBGCLKSEL_REG:
mbed_official	50:a417edff4437	2717	switch(ref)
mbed_official	50:a417edff4437	2718	{
mbed_official	50:a417edff4437	2719	#if defined( CMU_DBGCLKSEL_DBG )
mbed_official	50:a417edff4437	2720	case cmuSelect_AUXHFRCO:
mbed_official	50:a417edff4437	2721	/* Select AUXHFRCO as debug clock */
mbed_official	50:a417edff4437	2722	CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_AUXHFRCO;
mbed_official	50:a417edff4437	2723	break;
mbed_official	50:a417edff4437	2724
mbed_official	50:a417edff4437	2725	case cmuSelect_HFCLK:
mbed_official	50:a417edff4437	2726	/* Select divided HFCLK as debug clock */
mbed_official	50:a417edff4437	2727	CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_HFCLK;
mbed_official	50:a417edff4437	2728	break;
mbed_official	50:a417edff4437	2729	#endif
mbed_official	50:a417edff4437	2730
mbed_official	50:a417edff4437	2731	#if defined( CMU_CTRL_DBGCLK )
mbed_official	50:a417edff4437	2732	case cmuSelect_AUXHFRCO:
mbed_official	50:a417edff4437	2733	/* Select AUXHFRCO as debug clock */
mbed_official	50:a417edff4437	2734	CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK))
mbed_official	50:a417edff4437	2735	\| CMU_CTRL_DBGCLK_AUXHFRCO;
mbed_official	50:a417edff4437	2736	break;
mbed_official	50:a417edff4437	2737
mbed_official	50:a417edff4437	2738	case cmuSelect_HFCLK:
mbed_official	50:a417edff4437	2739	/* Select divided HFCLK as debug clock */
mbed_official	50:a417edff4437	2740	CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK))
mbed_official	50:a417edff4437	2741	\| CMU_CTRL_DBGCLK_HFCLK;
mbed_official	50:a417edff4437	2742	break;
mbed_official	50:a417edff4437	2743	#endif
mbed_official	50:a417edff4437	2744
mbed_official	50:a417edff4437	2745	default:
mbed_official	50:a417edff4437	2746	/* Illegal clock source for debug selected */
mbed_official	50:a417edff4437	2747	EFM_ASSERT(0);
mbed_official	50:a417edff4437	2748	return;
mbed_official	50:a417edff4437	2749	}
mbed_official	50:a417edff4437	2750	break;
mbed_official	50:a417edff4437	2751	#endif
mbed_official	50:a417edff4437	2752
mbed_official	50:a417edff4437	2753	#if defined(USB_PRESENT)
mbed_official	50:a417edff4437	2754	case CMU_USBCCLKSEL_REG:
mbed_official	50:a417edff4437	2755	switch(ref)
mbed_official	50:a417edff4437	2756	{
mbed_official	50:a417edff4437	2757	case cmuSelect_LFXO:
mbed_official	50:a417edff4437	2758	/* Select LFXO as clock source for USB, can only be used in sleep mode */
mbed_official	50:a417edff4437	2759	/* Ensure selected oscillator is enabled, waiting for it to stabilize */
mbed_official	50:a417edff4437	2760	CMU_OscillatorEnable(cmuOsc_LFXO, true, true);
mbed_official	50:a417edff4437	2761
mbed_official	50:a417edff4437	2762	/* Switch oscillator */
mbed_official	50:a417edff4437	2763	CMU->CMD = CMU_CMD_USBCCLKSEL_LFXO;
mbed_official	50:a417edff4437	2764
mbed_official	50:a417edff4437	2765	/* Wait until clock is activated */
mbed_official	50:a417edff4437	2766	while((CMU->STATUS & CMU_STATUS_USBCLFXOSEL)==0)
mbed_official	50:a417edff4437	2767	{
mbed_official	50:a417edff4437	2768	}
mbed_official	50:a417edff4437	2769	break;
mbed_official	50:a417edff4437	2770
mbed_official	50:a417edff4437	2771	case cmuSelect_LFRCO:
mbed_official	50:a417edff4437	2772	/* Select LFRCO as clock source for USB, can only be used in sleep mode */
mbed_official	50:a417edff4437	2773	/* Ensure selected oscillator is enabled, waiting for it to stabilize */
mbed_official	50:a417edff4437	2774	CMU_OscillatorEnable(cmuOsc_LFRCO, true, true);
mbed_official	50:a417edff4437	2775
mbed_official	50:a417edff4437	2776	/* Switch oscillator */
mbed_official	50:a417edff4437	2777	CMU->CMD = CMU_CMD_USBCCLKSEL_LFRCO;
mbed_official	50:a417edff4437	2778
mbed_official	50:a417edff4437	2779	/* Wait until clock is activated */
mbed_official	50:a417edff4437	2780	while((CMU->STATUS & CMU_STATUS_USBCLFRCOSEL)==0)
mbed_official	50:a417edff4437	2781	{
mbed_official	50:a417edff4437	2782	}
mbed_official	50:a417edff4437	2783	break;
mbed_official	50:a417edff4437	2784
mbed_official	50:a417edff4437	2785	#if defined( CMU_STATUS_USBCHFCLKSEL )
mbed_official	50:a417edff4437	2786	case cmuSelect_HFCLK:
mbed_official	50:a417edff4437	2787	/* Select undivided HFCLK as clock source for USB */
mbed_official	50:a417edff4437	2788	/* Oscillator must already be enabled to avoid a core lockup */
mbed_official	50:a417edff4437	2789	CMU->CMD = CMU_CMD_USBCCLKSEL_HFCLKNODIV;
mbed_official	50:a417edff4437	2790	/* Wait until clock is activated */
mbed_official	50:a417edff4437	2791	while((CMU->STATUS & CMU_STATUS_USBCHFCLKSEL)==0)
mbed_official	50:a417edff4437	2792	{
mbed_official	50:a417edff4437	2793	}
mbed_official	50:a417edff4437	2794	break;
mbed_official	50:a417edff4437	2795	#endif
mbed_official	50:a417edff4437	2796
mbed_official	50:a417edff4437	2797	#if defined( CMU_CMD_USBCCLKSEL_USHFRCO )
mbed_official	50:a417edff4437	2798	case cmuSelect_USHFRCO:
mbed_official	50:a417edff4437	2799	/* Select USHFRCO as clock source for USB */
mbed_official	50:a417edff4437	2800	/* Ensure selected oscillator is enabled, waiting for it to stabilize */
mbed_official	50:a417edff4437	2801	CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true);
mbed_official	50:a417edff4437	2802
mbed_official	50:a417edff4437	2803	/* Switch oscillator */
mbed_official	50:a417edff4437	2804	CMU->CMD = CMU_CMD_USBCCLKSEL_USHFRCO;
mbed_official	50:a417edff4437	2805
mbed_official	50:a417edff4437	2806	/* Wait until clock is activated */
mbed_official	50:a417edff4437	2807	while((CMU->STATUS & CMU_STATUS_USBCUSHFRCOSEL)==0)
mbed_official	50:a417edff4437	2808	{
mbed_official	50:a417edff4437	2809	}
mbed_official	50:a417edff4437	2810	break;
mbed_official	50:a417edff4437	2811	#endif
mbed_official	50:a417edff4437	2812
mbed_official	50:a417edff4437	2813	default:
mbed_official	50:a417edff4437	2814	/* Illegal clock source for USB */
mbed_official	50:a417edff4437	2815	EFM_ASSERT(0);
mbed_official	50:a417edff4437	2816	return;
mbed_official	50:a417edff4437	2817	}
bogdanm	0:9b334a45a8ff	2818	break;
bogdanm	0:9b334a45a8ff	2819	#endif
bogdanm	0:9b334a45a8ff	2820
bogdanm	0:9b334a45a8ff	2821	default:
bogdanm	0:9b334a45a8ff	2822	EFM_ASSERT(0);
bogdanm	0:9b334a45a8ff	2823	break;
bogdanm	0:9b334a45a8ff	2824	}
bogdanm	0:9b334a45a8ff	2825	}
bogdanm	0:9b334a45a8ff	2826
bogdanm	0:9b334a45a8ff	2827
bogdanm	0:9b334a45a8ff	2828	/************************************************************************//
bogdanm	0:9b334a45a8ff	2829	* @brief
bogdanm	0:9b334a45a8ff	2830	* CMU low frequency register synchronization freeze control.
bogdanm	0:9b334a45a8ff	2831	*
bogdanm	0:9b334a45a8ff	2832	* @details
bogdanm	0:9b334a45a8ff	2833	* Some CMU registers requires synchronization into the low frequency (LF)
bogdanm	0:9b334a45a8ff	2834	* domain. The freeze feature allows for several such registers to be
bogdanm	0:9b334a45a8ff	2835	* modified before passing them to the LF domain simultaneously (which
bogdanm	0:9b334a45a8ff	2836	* takes place when the freeze mode is disabled).
bogdanm	0:9b334a45a8ff	2837	*
bogdanm	0:9b334a45a8ff	2838	* Another usage scenario of this feature, is when using an API (such
bogdanm	0:9b334a45a8ff	2839	* as the CMU API) for modifying several bit fields consecutively in the
bogdanm	0:9b334a45a8ff	2840	* same register. If freeze mode is enabled during this sequence, stalling
bogdanm	0:9b334a45a8ff	2841	* can be avoided.
bogdanm	0:9b334a45a8ff	2842	*
bogdanm	0:9b334a45a8ff	2843	* @note
bogdanm	0:9b334a45a8ff	2844	* When enabling freeze mode, this function will wait for all current
bogdanm	0:9b334a45a8ff	2845	* ongoing CMU synchronization to LF domain to complete (Normally
bogdanm	0:9b334a45a8ff	2846	* synchronization will not be in progress.) However for this reason, when
bogdanm	0:9b334a45a8ff	2847	* using freeze mode, modifications of registers requiring LF synchronization
bogdanm	0:9b334a45a8ff	2848	* should be done within one freeze enable/disable block to avoid unecessary
bogdanm	0:9b334a45a8ff	2849	* stalling.
bogdanm	0:9b334a45a8ff	2850	*
bogdanm	0:9b334a45a8ff	2851	* @param[in] enable
bogdanm	0:9b334a45a8ff	2852	* @li true - enable freeze, modified registers are not propagated to the
bogdanm	0:9b334a45a8ff	2853	* LF domain
bogdanm	0:9b334a45a8ff	2854	* @li false - disable freeze, modified registers are propagated to LF
bogdanm	0:9b334a45a8ff	2855	* domain
bogdanm	0:9b334a45a8ff	2856	*****************************************************************************/
bogdanm	0:9b334a45a8ff	2857	void CMU_FreezeEnable(bool enable)
bogdanm	0:9b334a45a8ff	2858	{
bogdanm	0:9b334a45a8ff	2859	if (enable)
bogdanm	0:9b334a45a8ff	2860	{
bogdanm	0:9b334a45a8ff	2861	/* Wait for any ongoing LF synchronization to complete. This is just to */
bogdanm	0:9b334a45a8ff	2862	/* protect against the rare case when a user */
bogdanm	0:9b334a45a8ff	2863	/* - modifies a register requiring LF sync */
bogdanm	0:9b334a45a8ff	2864	/* - then enables freeze before LF sync completed */
bogdanm	0:9b334a45a8ff	2865	/* - then modifies the same register again */
bogdanm	0:9b334a45a8ff	2866	/* since modifying a register while it is in sync progress should be */
bogdanm	0:9b334a45a8ff	2867	/* avoided. */
bogdanm	0:9b334a45a8ff	2868	while (CMU->SYNCBUSY)
mbed_official	50:a417edff4437	2869	{
mbed_official	50:a417edff4437	2870	}
bogdanm	0:9b334a45a8ff	2871
bogdanm	0:9b334a45a8ff	2872	CMU->FREEZE = CMU_FREEZE_REGFREEZE;
bogdanm	0:9b334a45a8ff	2873	}
bogdanm	0:9b334a45a8ff	2874	else
bogdanm	0:9b334a45a8ff	2875	{
bogdanm	0:9b334a45a8ff	2876	CMU->FREEZE = 0;
bogdanm	0:9b334a45a8ff	2877	}
bogdanm	0:9b334a45a8ff	2878	}
bogdanm	0:9b334a45a8ff	2879
bogdanm	0:9b334a45a8ff	2880
mbed_official	50:a417edff4437	2881	#if defined( _CMU_HFRCOCTRL_BAND_MASK )
bogdanm	0:9b334a45a8ff	2882	/*************************************************************************//
bogdanm	0:9b334a45a8ff	2883	* @brief
bogdanm	0:9b334a45a8ff	2884	* Get HFRCO band in use.
bogdanm	0:9b334a45a8ff	2885	*
bogdanm	0:9b334a45a8ff	2886	* @return
bogdanm	0:9b334a45a8ff	2887	* HFRCO band in use.
bogdanm	0:9b334a45a8ff	2888	******************************************************************************/
bogdanm	0:9b334a45a8ff	2889	CMU_HFRCOBand_TypeDef CMU_HFRCOBandGet(void)
bogdanm	0:9b334a45a8ff	2890	{
mbed_official	50:a417edff4437	2891	return (CMU_HFRCOBand_TypeDef)((CMU->HFRCOCTRL & _CMU_HFRCOCTRL_BAND_MASK)
mbed_official	50:a417edff4437	2892	>> _CMU_HFRCOCTRL_BAND_SHIFT);
bogdanm	0:9b334a45a8ff	2893	}
mbed_official	50:a417edff4437	2894	#endif /* _CMU_HFRCOCTRL_BAND_MASK */
mbed_official	50:a417edff4437	2895
mbed_official	50:a417edff4437	2896
mbed_official	50:a417edff4437	2897	#if defined( _CMU_HFRCOCTRL_BAND_MASK )
bogdanm	0:9b334a45a8ff	2898	/*************************************************************************//
bogdanm	0:9b334a45a8ff	2899	* @brief
bogdanm	0:9b334a45a8ff	2900	* Set HFRCO band and the tuning value based on the value in the calibration
bogdanm	0:9b334a45a8ff	2901	* table made during production.
bogdanm	0:9b334a45a8ff	2902	*
bogdanm	0:9b334a45a8ff	2903	* @param[in] band
bogdanm	0:9b334a45a8ff	2904	* HFRCO band to activate.
bogdanm	0:9b334a45a8ff	2905	******************************************************************************/
bogdanm	0:9b334a45a8ff	2906	void CMU_HFRCOBandSet(CMU_HFRCOBand_TypeDef band)
bogdanm	0:9b334a45a8ff	2907	{
bogdanm	0:9b334a45a8ff	2908	uint32_t tuning;
bogdanm	0:9b334a45a8ff	2909	uint32_t freq;
bogdanm	0:9b334a45a8ff	2910	CMU_Select_TypeDef osc;
bogdanm	0:9b334a45a8ff	2911
bogdanm	0:9b334a45a8ff	2912	/* Read tuning value from calibration table */
bogdanm	0:9b334a45a8ff	2913	switch (band)
bogdanm	0:9b334a45a8ff	2914	{
mbed_official	50:a417edff4437	2915	case cmuHFRCOBand_1MHz:
mbed_official	50:a417edff4437	2916	tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND1_MASK)
mbed_official	50:a417edff4437	2917	>> _DEVINFO_HFRCOCAL0_BAND1_SHIFT;
mbed_official	50:a417edff4437	2918	break;
mbed_official	50:a417edff4437	2919
mbed_official	50:a417edff4437	2920	case cmuHFRCOBand_7MHz:
mbed_official	50:a417edff4437	2921	tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND7_MASK)
mbed_official	50:a417edff4437	2922	>> _DEVINFO_HFRCOCAL0_BAND7_SHIFT;
mbed_official	50:a417edff4437	2923	break;
mbed_official	50:a417edff4437	2924
mbed_official	50:a417edff4437	2925	case cmuHFRCOBand_11MHz:
mbed_official	50:a417edff4437	2926	tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND11_MASK)
mbed_official	50:a417edff4437	2927	>> _DEVINFO_HFRCOCAL0_BAND11_SHIFT;
mbed_official	50:a417edff4437	2928	break;
mbed_official	50:a417edff4437	2929
mbed_official	50:a417edff4437	2930	case cmuHFRCOBand_14MHz:
mbed_official	50:a417edff4437	2931	tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND14_MASK)
mbed_official	50:a417edff4437	2932	>> _DEVINFO_HFRCOCAL0_BAND14_SHIFT;
mbed_official	50:a417edff4437	2933	break;
mbed_official	50:a417edff4437	2934
mbed_official	50:a417edff4437	2935	case cmuHFRCOBand_21MHz:
mbed_official	50:a417edff4437	2936	tuning = (DEVINFO->HFRCOCAL1 & _DEVINFO_HFRCOCAL1_BAND21_MASK)
mbed_official	50:a417edff4437	2937	>> _DEVINFO_HFRCOCAL1_BAND21_SHIFT;
mbed_official	50:a417edff4437	2938	break;
bogdanm	0:9b334a45a8ff	2939
bogdanm	0:9b334a45a8ff	2940	#if defined( _CMU_HFRCOCTRL_BAND_28MHZ )
mbed_official	50:a417edff4437	2941	case cmuHFRCOBand_28MHz:
mbed_official	50:a417edff4437	2942	tuning = (DEVINFO->HFRCOCAL1 & _DEVINFO_HFRCOCAL1_BAND28_MASK)
mbed_official	50:a417edff4437	2943	>> _DEVINFO_HFRCOCAL1_BAND28_SHIFT;
mbed_official	50:a417edff4437	2944	break;
bogdanm	0:9b334a45a8ff	2945	#endif
bogdanm	0:9b334a45a8ff	2946
mbed_official	50:a417edff4437	2947	default:
mbed_official	50:a417edff4437	2948	EFM_ASSERT(0);
mbed_official	50:a417edff4437	2949	return;
bogdanm	0:9b334a45a8ff	2950	}
bogdanm	0:9b334a45a8ff	2951
bogdanm	0:9b334a45a8ff	2952	/* If HFRCO is used for core clock, we have to consider flash access WS. */
bogdanm	0:9b334a45a8ff	2953	osc = CMU_ClockSelectGet(cmuClock_HF);
bogdanm	0:9b334a45a8ff	2954	if (osc == cmuSelect_HFRCO)
bogdanm	0:9b334a45a8ff	2955	{
bogdanm	0:9b334a45a8ff	2956	/* Configure worst case wait states for flash access before setting divider */
mbed_official	50:a417edff4437	2957	flashWaitStateMax();
bogdanm	0:9b334a45a8ff	2958	}
bogdanm	0:9b334a45a8ff	2959
bogdanm	0:9b334a45a8ff	2960	/* Set band/tuning */
bogdanm	0:9b334a45a8ff	2961	CMU->HFRCOCTRL = (CMU->HFRCOCTRL &
mbed_official	50:a417edff4437	2962	~(_CMU_HFRCOCTRL_BAND_MASK \| _CMU_HFRCOCTRL_TUNING_MASK))
mbed_official	50:a417edff4437	2963	\| (band << _CMU_HFRCOCTRL_BAND_SHIFT)
mbed_official	50:a417edff4437	2964	\| (tuning << _CMU_HFRCOCTRL_TUNING_SHIFT);
bogdanm	0:9b334a45a8ff	2965
bogdanm	0:9b334a45a8ff	2966	/* If HFRCO is used for core clock, optimize flash WS */
bogdanm	0:9b334a45a8ff	2967	if (osc == cmuSelect_HFRCO)
bogdanm	0:9b334a45a8ff	2968	{
bogdanm	0:9b334a45a8ff	2969	/* Update CMSIS core clock variable and get current core clock */
bogdanm	0:9b334a45a8ff	2970	/* (The function will update the global variable) */
bogdanm	0:9b334a45a8ff	2971	/* NOTE! We need at least 21 cycles before setting zero wait state to flash */
bogdanm	0:9b334a45a8ff	2972	/* (i.e. WS0) when going from the 28MHz to 1MHz in the HFRCO band */
bogdanm	0:9b334a45a8ff	2973	freq = SystemCoreClockGet();
bogdanm	0:9b334a45a8ff	2974
bogdanm	0:9b334a45a8ff	2975	/* Optimize flash access wait state setting for current core clk */
mbed_official	50:a417edff4437	2976	flashWaitStateControl(freq);
mbed_official	50:a417edff4437	2977	}
mbed_official	50:a417edff4437	2978	}
mbed_official	50:a417edff4437	2979	#endif /* _CMU_HFRCOCTRL_BAND_MASK */
mbed_official	50:a417edff4437	2980
mbed_official	50:a417edff4437	2981
mbed_official	50:a417edff4437	2982	#if defined( _CMU_HFRCOCTRL_FREQRANGE_MASK )
mbed_official	50:a417edff4437	2983	/************************************************************************//
mbed_official	50:a417edff4437	2984	* @brief
mbed_official	50:a417edff4437	2985	* Get a pointer to the HFRCO frequency calibration word in DEVINFO
mbed_official	50:a417edff4437	2986	*
mbed_official	50:a417edff4437	2987	* @param[in] freq
mbed_official	50:a417edff4437	2988	* Frequency in Hz
mbed_official	50:a417edff4437	2989	*
mbed_official	50:a417edff4437	2990	* @return
mbed_official	50:a417edff4437	2991	* HFRCO calibration word for a given frequency
mbed_official	50:a417edff4437	2992	*****************************************************************************/
mbed_official	50:a417edff4437	2993	static uint32_t CMU_HFRCODevinfoGet(CMU_HFRCOFreq_TypeDef freq)
mbed_official	50:a417edff4437	2994	{
mbed_official	50:a417edff4437	2995	switch (freq)
mbed_official	50:a417edff4437	2996	{
mbed_official	50:a417edff4437	2997	/* 1, 2 and 4MHz share the same calibration word */
mbed_official	50:a417edff4437	2998	case cmuHFRCOFreq_1M0Hz:
mbed_official	50:a417edff4437	2999	case cmuHFRCOFreq_2M0Hz:
mbed_official	50:a417edff4437	3000	case cmuHFRCOFreq_4M0Hz:
mbed_official	50:a417edff4437	3001	return DEVINFO->HFRCOCAL0;
mbed_official	50:a417edff4437	3002
mbed_official	50:a417edff4437	3003	case cmuHFRCOFreq_7M0Hz:
mbed_official	50:a417edff4437	3004	return DEVINFO->HFRCOCAL3;
mbed_official	50:a417edff4437	3005
mbed_official	50:a417edff4437	3006	case cmuHFRCOFreq_13M0Hz:
mbed_official	50:a417edff4437	3007	return DEVINFO->HFRCOCAL6;
mbed_official	50:a417edff4437	3008
mbed_official	50:a417edff4437	3009	case cmuHFRCOFreq_16M0Hz:
mbed_official	50:a417edff4437	3010	return DEVINFO->HFRCOCAL7;
mbed_official	50:a417edff4437	3011
mbed_official	50:a417edff4437	3012	case cmuHFRCOFreq_19M0Hz:
mbed_official	50:a417edff4437	3013	return DEVINFO->HFRCOCAL8;
mbed_official	50:a417edff4437	3014
mbed_official	50:a417edff4437	3015	case cmuHFRCOFreq_26M0Hz:
mbed_official	50:a417edff4437	3016	return DEVINFO->HFRCOCAL10;
mbed_official	50:a417edff4437	3017
mbed_official	50:a417edff4437	3018	case cmuHFRCOFreq_32M0Hz:
mbed_official	50:a417edff4437	3019	return DEVINFO->HFRCOCAL11;
mbed_official	50:a417edff4437	3020
mbed_official	50:a417edff4437	3021	case cmuHFRCOFreq_38M0Hz:
mbed_official	50:a417edff4437	3022	return DEVINFO->HFRCOCAL12;
mbed_official	50:a417edff4437	3023
mbed_official	50:a417edff4437	3024	default: /* cmuHFRCOFreq_UserDefined */
mbed_official	50:a417edff4437	3025	return 0;
bogdanm	0:9b334a45a8ff	3026	}
bogdanm	0:9b334a45a8ff	3027	}
bogdanm	0:9b334a45a8ff	3028
bogdanm	0:9b334a45a8ff	3029
bogdanm	0:9b334a45a8ff	3030	/*************************************************************************//
bogdanm	0:9b334a45a8ff	3031	* @brief
mbed_official	50:a417edff4437	3032	* Get HFRCO frequency enumeration in use
mbed_official	50:a417edff4437	3033	*
mbed_official	50:a417edff4437	3034	* @return
mbed_official	50:a417edff4437	3035	* HFRCO frequency enumeration in use
mbed_official	50:a417edff4437	3036	******************************************************************************/
mbed_official	50:a417edff4437	3037	CMU_HFRCOFreq_TypeDef CMU_HFRCOFreqGet(void)
mbed_official	50:a417edff4437	3038	{
mbed_official	50:a417edff4437	3039	return (CMU_HFRCOFreq_TypeDef)SystemHfrcoFreq;
mbed_official	50:a417edff4437	3040	}
mbed_official	50:a417edff4437	3041
mbed_official	50:a417edff4437	3042
mbed_official	50:a417edff4437	3043	/*************************************************************************//
mbed_official	50:a417edff4437	3044	* @brief
mbed_official	50:a417edff4437	3045	* Set HFRCO calibration for the selected target frequency
mbed_official	50:a417edff4437	3046	*
mbed_official	50:a417edff4437	3047	* @param[in] freq
mbed_official	50:a417edff4437	3048	* HFRCO frequency band to set
mbed_official	50:a417edff4437	3049	******************************************************************************/
mbed_official	50:a417edff4437	3050	void CMU_HFRCOFreqSet(CMU_HFRCOFreq_TypeDef freq)
mbed_official	50:a417edff4437	3051	{
mbed_official	50:a417edff4437	3052	uint32_t freqCal;
mbed_official	50:a417edff4437	3053
mbed_official	50:a417edff4437	3054	/* Get DEVINFO index, set CMSIS frequency SystemHfrcoFreq */
mbed_official	50:a417edff4437	3055	freqCal = CMU_HFRCODevinfoGet(freq);
mbed_official	50:a417edff4437	3056	EFM_ASSERT((freqCal != 0) && (freqCal != UINT_MAX));
mbed_official	50:a417edff4437	3057	SystemHfrcoFreq = (uint32_t)freq;
mbed_official	50:a417edff4437	3058
mbed_official	50:a417edff4437	3059	/* Set max wait-states while changing core clock */
mbed_official	50:a417edff4437	3060	if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO)
mbed_official	50:a417edff4437	3061	{
mbed_official	50:a417edff4437	3062	flashWaitStateMax();
mbed_official	50:a417edff4437	3063	}
mbed_official	50:a417edff4437	3064
mbed_official	50:a417edff4437	3065	/* Wait for any previous sync to complete, and then set calibration data
mbed_official	50:a417edff4437	3066	for the selected frequency. */
mbed_official	50:a417edff4437	3067	while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_HFRCOBSY_SHIFT));
mbed_official	50:a417edff4437	3068
mbed_official	50:a417edff4437	3069	/* Check for valid calibration data */
mbed_official	50:a417edff4437	3070	EFM_ASSERT(freqCal != UINT_MAX);
mbed_official	50:a417edff4437	3071
mbed_official	50:a417edff4437	3072	/* Set divider in HFRCOCTRL for 1, 2 and 4MHz */
mbed_official	50:a417edff4437	3073	switch(freq)
mbed_official	50:a417edff4437	3074	{
mbed_official	50:a417edff4437	3075	case cmuHFRCOFreq_1M0Hz:
mbed_official	50:a417edff4437	3076	freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK)
mbed_official	50:a417edff4437	3077	\| CMU_HFRCOCTRL_CLKDIV_DIV4;
mbed_official	50:a417edff4437	3078	break;
mbed_official	50:a417edff4437	3079
mbed_official	50:a417edff4437	3080	case cmuHFRCOFreq_2M0Hz:
mbed_official	50:a417edff4437	3081	freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK)
mbed_official	50:a417edff4437	3082	\| CMU_HFRCOCTRL_CLKDIV_DIV2;
mbed_official	50:a417edff4437	3083	break;
mbed_official	50:a417edff4437	3084
mbed_official	50:a417edff4437	3085	case cmuHFRCOFreq_4M0Hz:
mbed_official	50:a417edff4437	3086	freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK)
mbed_official	50:a417edff4437	3087	\| CMU_HFRCOCTRL_CLKDIV_DIV1;
mbed_official	50:a417edff4437	3088	break;
mbed_official	50:a417edff4437	3089
mbed_official	50:a417edff4437	3090	default:
mbed_official	50:a417edff4437	3091	break;
mbed_official	50:a417edff4437	3092	}
mbed_official	50:a417edff4437	3093	CMU->HFRCOCTRL = freqCal;
mbed_official	50:a417edff4437	3094
mbed_official	50:a417edff4437	3095	/* Optimize flash access wait-state configuration for this frequency, */
mbed_official	50:a417edff4437	3096	/* if HFRCO is reference for core clock. */
mbed_official	50:a417edff4437	3097	if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO)
mbed_official	50:a417edff4437	3098	{
mbed_official	50:a417edff4437	3099	flashWaitStateControl((uint32_t)freq);
mbed_official	50:a417edff4437	3100	}
mbed_official	50:a417edff4437	3101	}
mbed_official	50:a417edff4437	3102	#endif /* _CMU_HFRCOCTRL_FREQRANGE_MASK */
mbed_official	50:a417edff4437	3103
mbed_official	50:a417edff4437	3104	#if defined( _CMU_HFRCOCTRL_SUDELAY_MASK )
mbed_official	50:a417edff4437	3105	/*************************************************************************//
mbed_official	50:a417edff4437	3106	* @brief
bogdanm	0:9b334a45a8ff	3107	* Get the HFRCO startup delay.
bogdanm	0:9b334a45a8ff	3108	*
bogdanm	0:9b334a45a8ff	3109	* @details
bogdanm	0:9b334a45a8ff	3110	* Please refer to the reference manual for further details.
bogdanm	0:9b334a45a8ff	3111	*
bogdanm	0:9b334a45a8ff	3112	* @return
bogdanm	0:9b334a45a8ff	3113	* The startup delay in use.
bogdanm	0:9b334a45a8ff	3114	******************************************************************************/
bogdanm	0:9b334a45a8ff	3115	uint32_t CMU_HFRCOStartupDelayGet(void)
bogdanm	0:9b334a45a8ff	3116	{
mbed_official	50:a417edff4437	3117	return (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_SUDELAY_MASK)
mbed_official	50:a417edff4437	3118	>> _CMU_HFRCOCTRL_SUDELAY_SHIFT;
bogdanm	0:9b334a45a8ff	3119	}
bogdanm	0:9b334a45a8ff	3120
bogdanm	0:9b334a45a8ff	3121
bogdanm	0:9b334a45a8ff	3122	/*************************************************************************//
bogdanm	0:9b334a45a8ff	3123	* @brief
bogdanm	0:9b334a45a8ff	3124	* Set the HFRCO startup delay.
bogdanm	0:9b334a45a8ff	3125	*
bogdanm	0:9b334a45a8ff	3126	* @details
bogdanm	0:9b334a45a8ff	3127	* Please refer to the reference manual for further details.
bogdanm	0:9b334a45a8ff	3128	*
bogdanm	0:9b334a45a8ff	3129	* @param[in] delay
bogdanm	0:9b334a45a8ff	3130	* The startup delay to set (<= 31).
bogdanm	0:9b334a45a8ff	3131	******************************************************************************/
bogdanm	0:9b334a45a8ff	3132	void CMU_HFRCOStartupDelaySet(uint32_t delay)
bogdanm	0:9b334a45a8ff	3133	{
bogdanm	0:9b334a45a8ff	3134	EFM_ASSERT(delay <= 31);
bogdanm	0:9b334a45a8ff	3135
mbed_official	50:a417edff4437	3136	delay &= _CMU_HFRCOCTRL_SUDELAY_MASK >> _CMU_HFRCOCTRL_SUDELAY_SHIFT;
mbed_official	50:a417edff4437	3137	CMU->HFRCOCTRL = (CMU->HFRCOCTRL & ~(_CMU_HFRCOCTRL_SUDELAY_MASK))
mbed_official	50:a417edff4437	3138	\| (delay << _CMU_HFRCOCTRL_SUDELAY_SHIFT);
mbed_official	50:a417edff4437	3139	}
mbed_official	50:a417edff4437	3140	#endif
mbed_official	50:a417edff4437	3141
mbed_official	50:a417edff4437	3142
mbed_official	50:a417edff4437	3143	#if defined( _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK )
mbed_official	50:a417edff4437	3144	/*************************************************************************//
mbed_official	50:a417edff4437	3145	* @brief
mbed_official	50:a417edff4437	3146	* Enable or disable HFXO autostart
mbed_official	50:a417edff4437	3147	*
mbed_official	50:a417edff4437	3148	* @param[in] enRACStartSel
mbed_official	50:a417edff4437	3149	* If true, HFXO is automatically started and selected upon RAC wakeup.
mbed_official	50:a417edff4437	3150	* If false, HFXO is not started or selected automatically upon RAC wakeup.
mbed_official	50:a417edff4437	3151	*
mbed_official	50:a417edff4437	3152	* @param[in] enEM0EM1Start
mbed_official	50:a417edff4437	3153	* If true, HFXO is automatically started upon entering EM0/EM1 entry from
mbed_official	50:a417edff4437	3154	* EM2/EM3. HFXO selection has to be handled by the user.
mbed_official	50:a417edff4437	3155	* If false, HFXO is not started automatically when entering EM0/EM1.
mbed_official	50:a417edff4437	3156	*
mbed_official	50:a417edff4437	3157	* @param[in] enEM0EM1StartSel
mbed_official	50:a417edff4437	3158	* If true, HFXO is automatically started and immediately selected upon
mbed_official	50:a417edff4437	3159	* entering EM0/EM1 entry from EM2/EM3. Note that this option stalls the use of
mbed_official	50:a417edff4437	3160	* HFSRCCLK until HFXO becomes ready.
mbed_official	50:a417edff4437	3161	* If false, HFXO is not started or selected automatically when entering
mbed_official	50:a417edff4437	3162	* EM0/EM1.
mbed_official	50:a417edff4437	3163	******************************************************************************/
mbed_official	50:a417edff4437	3164	void CMU_HFXOAutostartEnable(bool enRACStartSel,
mbed_official	50:a417edff4437	3165	bool enEM0EM1Start,
mbed_official	50:a417edff4437	3166	bool enEM0EM1StartSel)
mbed_official	50:a417edff4437	3167	{
mbed_official	50:a417edff4437	3168	uint32_t hfxoCtrl;
mbed_official	50:a417edff4437	3169	hfxoCtrl = CMU->HFXOCTRL & ~(_CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK
mbed_official	50:a417edff4437	3170	\| _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK
mbed_official	50:a417edff4437	3171	\| _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK);
mbed_official	50:a417edff4437	3172
mbed_official	50:a417edff4437	3173	hfxoCtrl \|= (enRACStartSel ? CMU_HFXOCTRL_AUTOSTARTRDYSELRAC : 0)
mbed_official	50:a417edff4437	3174	\| (enEM0EM1Start ? CMU_HFXOCTRL_AUTOSTARTEM0EM1 : 0)
mbed_official	50:a417edff4437	3175	\| (enEM0EM1StartSel ? CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 : 0);
mbed_official	50:a417edff4437	3176
mbed_official	50:a417edff4437	3177	CMU->HFXOCTRL = hfxoCtrl;
bogdanm	0:9b334a45a8ff	3178	}
mbed_official	50:a417edff4437	3179	#endif /* _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK */
mbed_official	50:a417edff4437	3180
mbed_official	50:a417edff4437	3181
mbed_official	50:a417edff4437	3182	#if defined( _CMU_HFXOCTRL_MASK )
mbed_official	50:a417edff4437	3183	/************************************************************************//
mbed_official	50:a417edff4437	3184	* @brief
mbed_official	50:a417edff4437	3185	* Set HFXO control registers
mbed_official	50:a417edff4437	3186	*
mbed_official	50:a417edff4437	3187	* @note
mbed_official	50:a417edff4437	3188	* HFXO configuration should be obtained from a configuration tool,
mbed_official	50:a417edff4437	3189	* app note or xtal datasheet. This function disables the HFXO to ensure
mbed_official	50:a417edff4437	3190	* a valid state before update.
mbed_official	50:a417edff4437	3191	*
mbed_official	50:a417edff4437	3192	* @param[in] hfxoInit
mbed_official	50:a417edff4437	3193	* HFXO setup parameters
mbed_official	50:a417edff4437	3194	*****************************************************************************/
mbed_official	50:a417edff4437	3195	void CMU_HFXOInit(CMU_HFXOInit_TypeDef *hfxoInit)
mbed_official	50:a417edff4437	3196	{
mbed_official	50:a417edff4437	3197	uint32_t ishReg;
mbed_official	50:a417edff4437	3198	uint32_t ishMax;
mbed_official	50:a417edff4437	3199
mbed_official	50:a417edff4437	3200	/* Do not disable HFXO if it is currently selected as HF/Core clock */
mbed_official	50:a417edff4437	3201	EFM_ASSERT(CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_HFXO);
mbed_official	50:a417edff4437	3202
mbed_official	50:a417edff4437	3203	/* HFXO must be disabled before reconfiguration */
mbed_official	50:a417edff4437	3204	CMU_OscillatorEnable(cmuOsc_HFXO, false, false);
mbed_official	50:a417edff4437	3205
mbed_official	50:a417edff4437	3206	/* Apply control settings */
mbed_official	50:a417edff4437	3207	BUS_RegMaskedWrite(&CMU->HFXOCTRL,
mbed_official	50:a417edff4437	3208	_CMU_HFXOCTRL_LOWPOWER_MASK
mbed_official	50:a417edff4437	3209	#if defined( _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK )
mbed_official	50:a417edff4437	3210	\| _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK
mbed_official	50:a417edff4437	3211	#endif
mbed_official	50:a417edff4437	3212	\| _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK
mbed_official	50:a417edff4437	3213	\| _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK,
mbed_official	50:a417edff4437	3214	(hfxoInit->lowPowerMode
mbed_official	50:a417edff4437	3215	? CMU_HFXOCTRL_LOWPOWER : 0)
mbed_official	50:a417edff4437	3216	#if defined( _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK )
mbed_official	50:a417edff4437	3217	\| (hfxoInit->autoStartSelOnRacWakeup
mbed_official	50:a417edff4437	3218	? CMU_HFXOCTRL_AUTOSTARTRDYSELRAC : 0)
mbed_official	50:a417edff4437	3219	#endif
mbed_official	50:a417edff4437	3220	\| (hfxoInit->autoStartEm01
mbed_official	50:a417edff4437	3221	? CMU_HFXOCTRL_AUTOSTARTEM0EM1 : 0)
mbed_official	50:a417edff4437	3222	\| (hfxoInit->autoSelEm01
mbed_official	50:a417edff4437	3223	? CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 : 0));
mbed_official	50:a417edff4437	3224
mbed_official	50:a417edff4437	3225	/* Set XTAL tuning parameters */
mbed_official	50:a417edff4437	3226
mbed_official	50:a417edff4437	3227	/* Set peak detection threshold in CMU_HFXOCTRL1_PEAKDETTHR[2:0] (hidden). */
mbed_official	50:a417edff4437	3228	BUS_RegMaskedWrite((volatile uint32_t *)0x400E4028, 0x7, hfxoInit->thresholdPeakDetect);
mbed_official	50:a417edff4437	3229
mbed_official	50:a417edff4437	3230	/* Set tuning for startup and steady state */
mbed_official	50:a417edff4437	3231	BUS_RegMaskedWrite(&CMU->HFXOSTARTUPCTRL,
mbed_official	50:a417edff4437	3232	_CMU_HFXOSTARTUPCTRL_CTUNE_MASK
mbed_official	50:a417edff4437	3233	\| _CMU_HFXOSTARTUPCTRL_REGISHWARM_MASK
mbed_official	50:a417edff4437	3234	\| _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK
mbed_official	50:a417edff4437	3235	\| _CMU_HFXOSTARTUPCTRL_IBTRIMXOCOREWARM_MASK,
mbed_official	50:a417edff4437	3236	(hfxoInit->ctuneStartup
mbed_official	50:a417edff4437	3237	<< _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT)
mbed_official	50:a417edff4437	3238	\| (hfxoInit->regIshStartup
mbed_official	50:a417edff4437	3239	<< _CMU_HFXOSTARTUPCTRL_REGISHWARM_SHIFT)
mbed_official	50:a417edff4437	3240	\| (hfxoInit->xoCoreBiasTrimStartup
mbed_official	50:a417edff4437	3241	<< _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT)
mbed_official	50:a417edff4437	3242	\| 0x4 /* Recommended tuning */
mbed_official	50:a417edff4437	3243	<< _CMU_HFXOSTARTUPCTRL_IBTRIMXOCOREWARM_SHIFT);
mbed_official	50:a417edff4437	3244
mbed_official	50:a417edff4437	3245	/* Adjust CMU_HFXOSTEADYSTATECTRL_REGISHUPPER according to regIshSteadyState.
mbed_official	50:a417edff4437	3246	Saturate at max value. Please see the reference manual page 433 and Section
mbed_official	50:a417edff4437	3247	12.5.10 CMU_HFXOSTEADYSTATECTRL for more details. */
mbed_official	50:a417edff4437	3248	ishReg = hfxoInit->regIshSteadyState + 3;
mbed_official	50:a417edff4437	3249	ishMax = _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK
mbed_official	50:a417edff4437	3250	>> _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT;
mbed_official	50:a417edff4437	3251	ishReg = ishReg > ishMax ? ishMax : ishReg;
mbed_official	50:a417edff4437	3252	ishReg <<= _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT;
mbed_official	50:a417edff4437	3253
mbed_official	50:a417edff4437	3254	BUS_RegMaskedWrite(&CMU->HFXOSTEADYSTATECTRL,
mbed_official	50:a417edff4437	3255	_CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK
mbed_official	50:a417edff4437	3256	\| _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK
mbed_official	50:a417edff4437	3257	\| _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK
mbed_official	50:a417edff4437	3258	\| _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK,
mbed_official	50:a417edff4437	3259	(hfxoInit->ctuneSteadyState
mbed_official	50:a417edff4437	3260	<< _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT)
mbed_official	50:a417edff4437	3261	\| (hfxoInit->regIshSteadyState
mbed_official	50:a417edff4437	3262	<< _CMU_HFXOSTEADYSTATECTRL_REGISH_SHIFT)
mbed_official	50:a417edff4437	3263	\| (hfxoInit->xoCoreBiasTrimSteadyState
mbed_official	50:a417edff4437	3264	<< _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT)
mbed_official	50:a417edff4437	3265	\| ishReg);
mbed_official	50:a417edff4437	3266
mbed_official	50:a417edff4437	3267	/* Set timeouts */
mbed_official	50:a417edff4437	3268	BUS_RegMaskedWrite(&CMU->HFXOTIMEOUTCTRL,
mbed_official	50:a417edff4437	3269	_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_MASK
mbed_official	50:a417edff4437	3270	\| _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK
mbed_official	50:a417edff4437	3271	\| _CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_MASK
mbed_official	50:a417edff4437	3272	\| _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK
mbed_official	50:a417edff4437	3273	\| _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK,
mbed_official	50:a417edff4437	3274	(hfxoInit->timeoutShuntOptimization
mbed_official	50:a417edff4437	3275	<< _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_SHIFT)
mbed_official	50:a417edff4437	3276	\| (hfxoInit->timeoutPeakDetect
mbed_official	50:a417edff4437	3277	<< _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT)
mbed_official	50:a417edff4437	3278	\| (hfxoInit->timeoutWarmSteady
mbed_official	50:a417edff4437	3279	<< _CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_SHIFT)
mbed_official	50:a417edff4437	3280	\| (hfxoInit->timeoutSteady
mbed_official	50:a417edff4437	3281	<< _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT)
mbed_official	50:a417edff4437	3282	\| (hfxoInit->timeoutStartup
mbed_official	50:a417edff4437	3283	<< _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT));
mbed_official	50:a417edff4437	3284	}
mbed_official	50:a417edff4437	3285	#endif
bogdanm	0:9b334a45a8ff	3286
bogdanm	0:9b334a45a8ff	3287
bogdanm	0:9b334a45a8ff	3288	/*************************************************************************//
bogdanm	0:9b334a45a8ff	3289	* @brief
bogdanm	0:9b334a45a8ff	3290	* Get the LCD framerate divisor (FDIV) setting.
bogdanm	0:9b334a45a8ff	3291	*
bogdanm	0:9b334a45a8ff	3292	* @return
bogdanm	0:9b334a45a8ff	3293	* The LCD framerate divisor.
bogdanm	0:9b334a45a8ff	3294	******************************************************************************/
bogdanm	0:9b334a45a8ff	3295	uint32_t CMU_LCDClkFDIVGet(void)
bogdanm	0:9b334a45a8ff	3296	{
mbed_official	50:a417edff4437	3297	#if defined( LCD_PRESENT )
mbed_official	50:a417edff4437	3298	return (CMU->LCDCTRL & _CMU_LCDCTRL_FDIV_MASK) >> _CMU_LCDCTRL_FDIV_SHIFT;
bogdanm	0:9b334a45a8ff	3299	#else
bogdanm	0:9b334a45a8ff	3300	return 0;
bogdanm	0:9b334a45a8ff	3301	#endif /* defined(LCD_PRESENT) */
bogdanm	0:9b334a45a8ff	3302	}
bogdanm	0:9b334a45a8ff	3303
bogdanm	0:9b334a45a8ff	3304
bogdanm	0:9b334a45a8ff	3305	/*************************************************************************//
bogdanm	0:9b334a45a8ff	3306	* @brief
bogdanm	0:9b334a45a8ff	3307	* Set the LCD framerate divisor (FDIV) setting.
bogdanm	0:9b334a45a8ff	3308	*
bogdanm	0:9b334a45a8ff	3309	* @note
bogdanm	0:9b334a45a8ff	3310	* The FDIV field (CMU LCDCTRL register) should only be modified while the
bogdanm	0:9b334a45a8ff	3311	* LCD module is clock disabled (CMU LFACLKEN0.LCD bit is 0). This function
bogdanm	0:9b334a45a8ff	3312	* will NOT modify FDIV if the LCD module clock is enabled. Please refer to
bogdanm	0:9b334a45a8ff	3313	* CMU_ClockEnable() for disabling/enabling LCD clock.
bogdanm	0:9b334a45a8ff	3314	*
bogdanm	0:9b334a45a8ff	3315	* @param[in] div
bogdanm	0:9b334a45a8ff	3316	* The FDIV setting to use.
bogdanm	0:9b334a45a8ff	3317	******************************************************************************/
bogdanm	0:9b334a45a8ff	3318	void CMU_LCDClkFDIVSet(uint32_t div)
bogdanm	0:9b334a45a8ff	3319	{
mbed_official	50:a417edff4437	3320	#if defined( LCD_PRESENT )
bogdanm	0:9b334a45a8ff	3321	EFM_ASSERT(div <= cmuClkDiv_128);
bogdanm	0:9b334a45a8ff	3322
bogdanm	0:9b334a45a8ff	3323	/* Do not allow modification if LCD clock enabled */
bogdanm	0:9b334a45a8ff	3324	if (CMU->LFACLKEN0 & CMU_LFACLKEN0_LCD)
bogdanm	0:9b334a45a8ff	3325	{
bogdanm	0:9b334a45a8ff	3326	return;
bogdanm	0:9b334a45a8ff	3327	}
bogdanm	0:9b334a45a8ff	3328
bogdanm	0:9b334a45a8ff	3329	div <<= _CMU_LCDCTRL_FDIV_SHIFT;
bogdanm	0:9b334a45a8ff	3330	div &= _CMU_LCDCTRL_FDIV_MASK;
bogdanm	0:9b334a45a8ff	3331	CMU->LCDCTRL = (CMU->LCDCTRL & ~_CMU_LCDCTRL_FDIV_MASK) \| div;
bogdanm	0:9b334a45a8ff	3332	#else
bogdanm	0:9b334a45a8ff	3333	(void)div; /* Unused parameter */
bogdanm	0:9b334a45a8ff	3334	#endif /* defined(LCD_PRESENT) */
bogdanm	0:9b334a45a8ff	3335	}
bogdanm	0:9b334a45a8ff	3336
bogdanm	0:9b334a45a8ff	3337
mbed_official	50:a417edff4437	3338	#if defined( _CMU_LFXOCTRL_MASK )
mbed_official	50:a417edff4437	3339	/************************************************************************//
mbed_official	50:a417edff4437	3340	* @brief
mbed_official	50:a417edff4437	3341	* Set LFXO control registers
mbed_official	50:a417edff4437	3342	*
mbed_official	50:a417edff4437	3343	* @note
mbed_official	50:a417edff4437	3344	* LFXO configuration should be obtained from a configuration tool,
mbed_official	50:a417edff4437	3345	* app note or xtal datasheet. This function disables the LFXO to ensure
mbed_official	50:a417edff4437	3346	* a valid state before update.
mbed_official	50:a417edff4437	3347	*
mbed_official	50:a417edff4437	3348	* @param[in] lfxoInit
mbed_official	50:a417edff4437	3349	* LFXO setup parameters
mbed_official	50:a417edff4437	3350	*****************************************************************************/
mbed_official	50:a417edff4437	3351	void CMU_LFXOInit(CMU_LFXOInit_TypeDef *lfxoInit)
mbed_official	50:a417edff4437	3352	{
mbed_official	50:a417edff4437	3353	/* Do not disable LFXO if it is currently selected as HF/Core clock */
mbed_official	50:a417edff4437	3354	EFM_ASSERT(CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_LFXO);
mbed_official	50:a417edff4437	3355
mbed_official	50:a417edff4437	3356	/* LFXO must be disabled before reconfiguration */
mbed_official	50:a417edff4437	3357	CMU_OscillatorEnable(cmuOsc_LFXO, false, false);
mbed_official	50:a417edff4437	3358
mbed_official	50:a417edff4437	3359	BUS_RegMaskedWrite(&CMU->LFXOCTRL,
mbed_official	50:a417edff4437	3360	_CMU_LFXOCTRL_TUNING_MASK
mbed_official	50:a417edff4437	3361	\| _CMU_LFXOCTRL_GAIN_MASK
mbed_official	50:a417edff4437	3362	\| _CMU_LFXOCTRL_TIMEOUT_MASK,
mbed_official	50:a417edff4437	3363	(lfxoInit->ctune << _CMU_LFXOCTRL_TUNING_SHIFT)
mbed_official	50:a417edff4437	3364	\| (lfxoInit->gain << _CMU_LFXOCTRL_GAIN_SHIFT)
mbed_official	50:a417edff4437	3365	\| (lfxoInit->timeout << _CMU_LFXOCTRL_TIMEOUT_SHIFT));
mbed_official	50:a417edff4437	3366	}
mbed_official	50:a417edff4437	3367	#endif
mbed_official	50:a417edff4437	3368
mbed_official	50:a417edff4437	3369
bogdanm	0:9b334a45a8ff	3370	/*************************************************************************//
bogdanm	0:9b334a45a8ff	3371	* @brief
bogdanm	0:9b334a45a8ff	3372	* Enable/disable oscillator.
bogdanm	0:9b334a45a8ff	3373	*
bogdanm	0:9b334a45a8ff	3374	* @note
bogdanm	0:9b334a45a8ff	3375	* WARNING: When this function is called to disable either cmuOsc_LFXO or
bogdanm	0:9b334a45a8ff	3376	* cmuOsc_HFXO the LFXOMODE or HFXOMODE fields of the CMU_CTRL register
bogdanm	0:9b334a45a8ff	3377	* are reset to the reset value. I.e. if external clock sources are selected
bogdanm	0:9b334a45a8ff	3378	* in either LFXOMODE or HFXOMODE fields, the configuration will be cleared
bogdanm	0:9b334a45a8ff	3379	* and needs to be reconfigured if needed later.
bogdanm	0:9b334a45a8ff	3380	*
bogdanm	0:9b334a45a8ff	3381	* @param[in] osc
bogdanm	0:9b334a45a8ff	3382	* The oscillator to enable/disable.
bogdanm	0:9b334a45a8ff	3383	*
bogdanm	0:9b334a45a8ff	3384	* @param[in] enable
bogdanm	0:9b334a45a8ff	3385	* @li true - enable specified oscillator.
bogdanm	0:9b334a45a8ff	3386	* @li false - disable specified oscillator.
bogdanm	0:9b334a45a8ff	3387	*
bogdanm	0:9b334a45a8ff	3388	* @param[in] wait
bogdanm	0:9b334a45a8ff	3389	* Only used if @p enable is true.
bogdanm	0:9b334a45a8ff	3390	* @li true - wait for oscillator start-up time to timeout before returning.
bogdanm	0:9b334a45a8ff	3391	* @li false - do not wait for oscillator start-up time to timeout before
bogdanm	0:9b334a45a8ff	3392	* returning.
bogdanm	0:9b334a45a8ff	3393	******************************************************************************/
bogdanm	0:9b334a45a8ff	3394	void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait)
bogdanm	0:9b334a45a8ff	3395	{
mbed_official	50:a417edff4437	3396	uint32_t rdyBitPos;
mbed_official	50:a417edff4437	3397	#if defined( _SILICON_LABS_32B_PLATFORM_2 )
mbed_official	50:a417edff4437	3398	uint32_t ensBitPos;
mbed_official	50:a417edff4437	3399	#endif
bogdanm	0:9b334a45a8ff	3400	uint32_t enBit;
bogdanm	0:9b334a45a8ff	3401	uint32_t disBit;
bogdanm	0:9b334a45a8ff	3402
bogdanm	0:9b334a45a8ff	3403	switch (osc)
bogdanm	0:9b334a45a8ff	3404	{
mbed_official	50:a417edff4437	3405	case cmuOsc_HFRCO:
mbed_official	50:a417edff4437	3406	enBit = CMU_OSCENCMD_HFRCOEN;
mbed_official	50:a417edff4437	3407	disBit = CMU_OSCENCMD_HFRCODIS;
mbed_official	50:a417edff4437	3408	rdyBitPos = _CMU_STATUS_HFRCORDY_SHIFT;
mbed_official	50:a417edff4437	3409	#if defined( _SILICON_LABS_32B_PLATFORM_2 )
mbed_official	50:a417edff4437	3410	ensBitPos = _CMU_STATUS_HFRCOENS_SHIFT;
mbed_official	50:a417edff4437	3411	#endif
mbed_official	50:a417edff4437	3412	break;
mbed_official	50:a417edff4437	3413
mbed_official	50:a417edff4437	3414	case cmuOsc_HFXO:
mbed_official	50:a417edff4437	3415	enBit = CMU_OSCENCMD_HFXOEN;
mbed_official	50:a417edff4437	3416	disBit = CMU_OSCENCMD_HFXODIS;
mbed_official	50:a417edff4437	3417	rdyBitPos = _CMU_STATUS_HFXORDY_SHIFT;
mbed_official	50:a417edff4437	3418	#if defined( _SILICON_LABS_32B_PLATFORM_2 )
mbed_official	50:a417edff4437	3419	ensBitPos = _CMU_STATUS_HFXOENS_SHIFT;
mbed_official	50:a417edff4437	3420	#endif
mbed_official	50:a417edff4437	3421	break;
mbed_official	50:a417edff4437	3422
mbed_official	50:a417edff4437	3423	case cmuOsc_AUXHFRCO:
mbed_official	50:a417edff4437	3424	enBit = CMU_OSCENCMD_AUXHFRCOEN;
mbed_official	50:a417edff4437	3425	disBit = CMU_OSCENCMD_AUXHFRCODIS;
mbed_official	50:a417edff4437	3426	rdyBitPos = _CMU_STATUS_AUXHFRCORDY_SHIFT;
mbed_official	50:a417edff4437	3427	#if defined( _SILICON_LABS_32B_PLATFORM_2 )
mbed_official	50:a417edff4437	3428	ensBitPos = _CMU_STATUS_AUXHFRCOENS_SHIFT;
mbed_official	50:a417edff4437	3429	#endif
mbed_official	50:a417edff4437	3430	break;
mbed_official	50:a417edff4437	3431
mbed_official	50:a417edff4437	3432	case cmuOsc_LFRCO:
mbed_official	50:a417edff4437	3433	enBit = CMU_OSCENCMD_LFRCOEN;
mbed_official	50:a417edff4437	3434	disBit = CMU_OSCENCMD_LFRCODIS;
mbed_official	50:a417edff4437	3435	rdyBitPos = _CMU_STATUS_LFRCORDY_SHIFT;
mbed_official	50:a417edff4437	3436	#if defined( _SILICON_LABS_32B_PLATFORM_2 )
mbed_official	50:a417edff4437	3437	ensBitPos = _CMU_STATUS_LFRCOENS_SHIFT;
mbed_official	50:a417edff4437	3438	#endif
mbed_official	50:a417edff4437	3439	break;
mbed_official	50:a417edff4437	3440
mbed_official	50:a417edff4437	3441	case cmuOsc_LFXO:
mbed_official	50:a417edff4437	3442	enBit = CMU_OSCENCMD_LFXOEN;
mbed_official	50:a417edff4437	3443	disBit = CMU_OSCENCMD_LFXODIS;
mbed_official	50:a417edff4437	3444	rdyBitPos = _CMU_STATUS_LFXORDY_SHIFT;
mbed_official	50:a417edff4437	3445	#if defined( _SILICON_LABS_32B_PLATFORM_2 )
mbed_official	50:a417edff4437	3446	ensBitPos = _CMU_STATUS_LFXOENS_SHIFT;
mbed_official	50:a417edff4437	3447	#endif
mbed_official	50:a417edff4437	3448	break;
bogdanm	0:9b334a45a8ff	3449
bogdanm	0:9b334a45a8ff	3450	#if defined( _CMU_STATUS_USHFRCOENS_MASK )
mbed_official	50:a417edff4437	3451	case cmuOsc_USHFRCO:
mbed_official	50:a417edff4437	3452	enBit = CMU_OSCENCMD_USHFRCOEN;
mbed_official	50:a417edff4437	3453	disBit = CMU_OSCENCMD_USHFRCODIS;
mbed_official	50:a417edff4437	3454	rdyBitPos = _CMU_STATUS_USHFRCORDY_SHIFT;
mbed_official	50:a417edff4437	3455	#if defined( _SILICON_LABS_32B_PLATFORM_2 )
mbed_official	50:a417edff4437	3456	ensBitPos = _CMU_STATUS_USHFRCOENS_SHIFT;
mbed_official	50:a417edff4437	3457	#endif
mbed_official	50:a417edff4437	3458	break;
bogdanm	0:9b334a45a8ff	3459	#endif
bogdanm	0:9b334a45a8ff	3460
mbed_official	50:a417edff4437	3461	#if defined( CMU_LFCLKSEL_LFAE_ULFRCO )
mbed_official	50:a417edff4437	3462	case cmuOsc_ULFRCO:
mbed_official	50:a417edff4437	3463	/* ULFRCO is always enabled, and cannot be turned off */
mbed_official	50:a417edff4437	3464	return;
bogdanm	0:9b334a45a8ff	3465	#endif
bogdanm	0:9b334a45a8ff	3466
mbed_official	50:a417edff4437	3467	default:
mbed_official	50:a417edff4437	3468	/* Undefined clock source */
mbed_official	50:a417edff4437	3469	EFM_ASSERT(0);
mbed_official	50:a417edff4437	3470	return;
bogdanm	0:9b334a45a8ff	3471	}
bogdanm	0:9b334a45a8ff	3472
bogdanm	0:9b334a45a8ff	3473	if (enable)
bogdanm	0:9b334a45a8ff	3474	{
bogdanm	0:9b334a45a8ff	3475	CMU->OSCENCMD = enBit;
bogdanm	0:9b334a45a8ff	3476
mbed_official	50:a417edff4437	3477	#if defined( _SILICON_LABS_32B_PLATFORM_2 )
mbed_official	50:a417edff4437	3478	/* Always wait for ENS to go high */
mbed_official	50:a417edff4437	3479	while (!BUS_RegBitRead(&CMU->STATUS, ensBitPos))
mbed_official	50:a417edff4437	3480	{
mbed_official	50:a417edff4437	3481	}
mbed_official	50:a417edff4437	3482	#endif
mbed_official	50:a417edff4437	3483
mbed_official	50:a417edff4437	3484	/* Wait for clock to become ready after enable */
bogdanm	0:9b334a45a8ff	3485	if (wait)
bogdanm	0:9b334a45a8ff	3486	{
mbed_official	50:a417edff4437	3487	while (!BUS_RegBitRead(&CMU->STATUS, rdyBitPos));
mbed_official	50:a417edff4437	3488	#if defined( _CMU_STATUS_HFXOSHUNTOPTRDY_MASK )
mbed_official	50:a417edff4437	3489	/* Wait for shunt current optimization to complete */
mbed_official	50:a417edff4437	3490	if ((osc == cmuOsc_HFXO)
mbed_official	50:a417edff4437	3491	&& (BUS_RegMaskedRead(&CMU->HFXOCTRL,
mbed_official	50:a417edff4437	3492	_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK)
mbed_official	50:a417edff4437	3493	== CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD))
mbed_official	50:a417edff4437	3494	{
mbed_official	50:a417edff4437	3495	while (!BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_HFXOSHUNTOPTRDY_SHIFT))
mbed_official	50:a417edff4437	3496	{
mbed_official	50:a417edff4437	3497	}
mbed_official	50:a417edff4437	3498	/* Assert on failed peak detection. Incorrect HFXO initialization parameters
mbed_official	50:a417edff4437	3499	caused startup to fail. Please review parameters. */
mbed_official	50:a417edff4437	3500	EFM_ASSERT(BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_HFXOPEAKDETRDY_SHIFT));
mbed_official	50:a417edff4437	3501	}
mbed_official	50:a417edff4437	3502	#endif
bogdanm	0:9b334a45a8ff	3503	}
bogdanm	0:9b334a45a8ff	3504	}
bogdanm	0:9b334a45a8ff	3505	else
bogdanm	0:9b334a45a8ff	3506	{
bogdanm	0:9b334a45a8ff	3507	CMU->OSCENCMD = disBit;
mbed_official	50:a417edff4437	3508
mbed_official	50:a417edff4437	3509	#if defined( _SILICON_LABS_32B_PLATFORM_2 )
mbed_official	50:a417edff4437	3510	/* Always wait for ENS to go low */
mbed_official	50:a417edff4437	3511	while (BUS_RegBitRead(&CMU->STATUS, ensBitPos))
mbed_official	50:a417edff4437	3512	{
mbed_official	50:a417edff4437	3513	}
mbed_official	50:a417edff4437	3514	#endif
bogdanm	0:9b334a45a8ff	3515	}
bogdanm	0:9b334a45a8ff	3516
bogdanm	0:9b334a45a8ff	3517	/* Keep EMU module informed */
bogdanm	0:9b334a45a8ff	3518	EMU_UpdateOscConfig();
bogdanm	0:9b334a45a8ff	3519	}
bogdanm	0:9b334a45a8ff	3520
bogdanm	0:9b334a45a8ff	3521
bogdanm	0:9b334a45a8ff	3522	/*************************************************************************//
bogdanm	0:9b334a45a8ff	3523	* @brief
bogdanm	0:9b334a45a8ff	3524	* Get oscillator frequency tuning setting.
bogdanm	0:9b334a45a8ff	3525	*
bogdanm	0:9b334a45a8ff	3526	* @param[in] osc
bogdanm	0:9b334a45a8ff	3527	* Oscillator to get tuning value for, one of:
bogdanm	0:9b334a45a8ff	3528	* @li #cmuOsc_LFRCO
bogdanm	0:9b334a45a8ff	3529	* @li #cmuOsc_HFRCO
bogdanm	0:9b334a45a8ff	3530	* @li #cmuOsc_AUXHFRCO
bogdanm	0:9b334a45a8ff	3531	*
bogdanm	0:9b334a45a8ff	3532	* @return
bogdanm	0:9b334a45a8ff	3533	* The oscillator frequency tuning setting in use.
bogdanm	0:9b334a45a8ff	3534	******************************************************************************/
bogdanm	0:9b334a45a8ff	3535	uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc)
bogdanm	0:9b334a45a8ff	3536	{
bogdanm	0:9b334a45a8ff	3537	uint32_t ret;
bogdanm	0:9b334a45a8ff	3538
bogdanm	0:9b334a45a8ff	3539	switch (osc)
bogdanm	0:9b334a45a8ff	3540	{
mbed_official	50:a417edff4437	3541	case cmuOsc_LFRCO:
mbed_official	50:a417edff4437	3542	ret = (CMU->LFRCOCTRL & _CMU_LFRCOCTRL_TUNING_MASK)
mbed_official	50:a417edff4437	3543	>> _CMU_LFRCOCTRL_TUNING_SHIFT;
mbed_official	50:a417edff4437	3544	break;
mbed_official	50:a417edff4437	3545
mbed_official	50:a417edff4437	3546	case cmuOsc_HFRCO:
mbed_official	50:a417edff4437	3547	ret = (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_TUNING_MASK)
mbed_official	50:a417edff4437	3548	>> _CMU_HFRCOCTRL_TUNING_SHIFT;
mbed_official	50:a417edff4437	3549	break;
mbed_official	50:a417edff4437	3550
mbed_official	50:a417edff4437	3551	case cmuOsc_AUXHFRCO:
mbed_official	50:a417edff4437	3552	ret = (CMU->AUXHFRCOCTRL & _CMU_AUXHFRCOCTRL_TUNING_MASK)
mbed_official	50:a417edff4437	3553	>> _CMU_AUXHFRCOCTRL_TUNING_SHIFT;
mbed_official	50:a417edff4437	3554	break;
mbed_official	50:a417edff4437	3555
mbed_official	50:a417edff4437	3556	default:
mbed_official	50:a417edff4437	3557	EFM_ASSERT(0);
mbed_official	50:a417edff4437	3558	ret = 0;
mbed_official	50:a417edff4437	3559	break;
bogdanm	0:9b334a45a8ff	3560	}
bogdanm	0:9b334a45a8ff	3561
mbed_official	50:a417edff4437	3562	return ret;
bogdanm	0:9b334a45a8ff	3563	}
bogdanm	0:9b334a45a8ff	3564
bogdanm	0:9b334a45a8ff	3565
bogdanm	0:9b334a45a8ff	3566	/*************************************************************************//
bogdanm	0:9b334a45a8ff	3567	* @brief
bogdanm	0:9b334a45a8ff	3568	* Set the oscillator frequency tuning control.
bogdanm	0:9b334a45a8ff	3569	*
bogdanm	0:9b334a45a8ff	3570	* @note
bogdanm	0:9b334a45a8ff	3571	* Oscillator tuning is done during production, and the tuning value is
bogdanm	0:9b334a45a8ff	3572	* automatically loaded after a reset. Changing the tuning value from the
bogdanm	0:9b334a45a8ff	3573	* calibrated value is for more advanced use.
bogdanm	0:9b334a45a8ff	3574	*
bogdanm	0:9b334a45a8ff	3575	* @param[in] osc
bogdanm	0:9b334a45a8ff	3576	* Oscillator to set tuning value for, one of:
bogdanm	0:9b334a45a8ff	3577	* @li #cmuOsc_LFRCO
bogdanm	0:9b334a45a8ff	3578	* @li #cmuOsc_HFRCO
bogdanm	0:9b334a45a8ff	3579	* @li #cmuOsc_AUXHFRCO
bogdanm	0:9b334a45a8ff	3580	*
bogdanm	0:9b334a45a8ff	3581	* @param[in] val
bogdanm	0:9b334a45a8ff	3582	* The oscillator frequency tuning setting to use.
bogdanm	0:9b334a45a8ff	3583	******************************************************************************/
bogdanm	0:9b334a45a8ff	3584	void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val)
bogdanm	0:9b334a45a8ff	3585	{
bogdanm	0:9b334a45a8ff	3586	switch (osc)
bogdanm	0:9b334a45a8ff	3587	{
mbed_official	50:a417edff4437	3588	case cmuOsc_LFRCO:
mbed_official	50:a417edff4437	3589	EFM_ASSERT(val <= (_CMU_LFRCOCTRL_TUNING_MASK
mbed_official	50:a417edff4437	3590	>> _CMU_LFRCOCTRL_TUNING_SHIFT));
mbed_official	50:a417edff4437	3591	val &= (_CMU_LFRCOCTRL_TUNING_MASK >> _CMU_LFRCOCTRL_TUNING_SHIFT);
mbed_official	50:a417edff4437	3592	#if defined( _SILICON_LABS_32B_PLATFORM_2 )
mbed_official	50:a417edff4437	3593	while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_LFRCOBSY_SHIFT));
mbed_official	50:a417edff4437	3594	#endif
mbed_official	50:a417edff4437	3595	CMU->LFRCOCTRL = (CMU->LFRCOCTRL & ~(_CMU_LFRCOCTRL_TUNING_MASK))
mbed_official	50:a417edff4437	3596	\| (val << _CMU_LFRCOCTRL_TUNING_SHIFT);
mbed_official	50:a417edff4437	3597	break;
mbed_official	50:a417edff4437	3598
mbed_official	50:a417edff4437	3599	case cmuOsc_HFRCO:
mbed_official	50:a417edff4437	3600	EFM_ASSERT(val <= (_CMU_HFRCOCTRL_TUNING_MASK
mbed_official	50:a417edff4437	3601	>> _CMU_HFRCOCTRL_TUNING_SHIFT));
mbed_official	50:a417edff4437	3602	val &= (_CMU_HFRCOCTRL_TUNING_MASK >> _CMU_HFRCOCTRL_TUNING_SHIFT);
mbed_official	50:a417edff4437	3603	#if defined( _SILICON_LABS_32B_PLATFORM_2 )
mbed_official	50:a417edff4437	3604	while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_HFRCOBSY_SHIFT))
mbed_official	50:a417edff4437	3605	{
mbed_official	50:a417edff4437	3606	}
mbed_official	50:a417edff4437	3607	#endif
mbed_official	50:a417edff4437	3608	CMU->HFRCOCTRL = (CMU->HFRCOCTRL & ~(_CMU_HFRCOCTRL_TUNING_MASK))
mbed_official	50:a417edff4437	3609	\| (val << _CMU_HFRCOCTRL_TUNING_SHIFT);
mbed_official	50:a417edff4437	3610	break;
mbed_official	50:a417edff4437	3611
mbed_official	50:a417edff4437	3612	case cmuOsc_AUXHFRCO:
mbed_official	50:a417edff4437	3613	EFM_ASSERT(val <= (_CMU_AUXHFRCOCTRL_TUNING_MASK
mbed_official	50:a417edff4437	3614	>> _CMU_AUXHFRCOCTRL_TUNING_SHIFT));
mbed_official	50:a417edff4437	3615	val &= (_CMU_AUXHFRCOCTRL_TUNING_MASK >> _CMU_AUXHFRCOCTRL_TUNING_SHIFT);
mbed_official	50:a417edff4437	3616	#if defined( _SILICON_LABS_32B_PLATFORM_2 )
mbed_official	50:a417edff4437	3617	while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT))
mbed_official	50:a417edff4437	3618	{
mbed_official	50:a417edff4437	3619	}
mbed_official	50:a417edff4437	3620	#endif
mbed_official	50:a417edff4437	3621	CMU->AUXHFRCOCTRL = (CMU->AUXHFRCOCTRL & ~(_CMU_AUXHFRCOCTRL_TUNING_MASK))
mbed_official	50:a417edff4437	3622	\| (val << _CMU_AUXHFRCOCTRL_TUNING_SHIFT);
mbed_official	50:a417edff4437	3623	break;
mbed_official	50:a417edff4437	3624
mbed_official	50:a417edff4437	3625	default:
mbed_official	50:a417edff4437	3626	EFM_ASSERT(0);
mbed_official	50:a417edff4437	3627	break;
bogdanm	0:9b334a45a8ff	3628	}
bogdanm	0:9b334a45a8ff	3629	}
bogdanm	0:9b334a45a8ff	3630
bogdanm	0:9b334a45a8ff	3631
bogdanm	0:9b334a45a8ff	3632	/************************************************************************//
bogdanm	0:9b334a45a8ff	3633	* @brief
bogdanm	0:9b334a45a8ff	3634	* Determine if currently selected PCNTn clock used is external or LFBCLK.
bogdanm	0:9b334a45a8ff	3635	*
mbed_official	50:a417edff4437	3636	* @param[in] instance
bogdanm	0:9b334a45a8ff	3637	* PCNT instance number to get currently selected clock source for.
bogdanm	0:9b334a45a8ff	3638	*
bogdanm	0:9b334a45a8ff	3639	* @return
bogdanm	0:9b334a45a8ff	3640	* @li true - selected clock is external clock.
bogdanm	0:9b334a45a8ff	3641	* @li false - selected clock is LFBCLK.
bogdanm	0:9b334a45a8ff	3642	*****************************************************************************/
mbed_official	50:a417edff4437	3643	bool CMU_PCNTClockExternalGet(unsigned int instance)
bogdanm	0:9b334a45a8ff	3644	{
bogdanm	0:9b334a45a8ff	3645	uint32_t setting;
bogdanm	0:9b334a45a8ff	3646
mbed_official	50:a417edff4437	3647	switch (instance)
bogdanm	0:9b334a45a8ff	3648	{
mbed_official	50:a417edff4437	3649	#if defined( _CMU_PCNTCTRL_PCNT0CLKEN_MASK )
mbed_official	50:a417edff4437	3650	case 0:
mbed_official	50:a417edff4437	3651	setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0;
mbed_official	50:a417edff4437	3652	break;
mbed_official	50:a417edff4437	3653
mbed_official	50:a417edff4437	3654	#if defined( _CMU_PCNTCTRL_PCNT1CLKEN_MASK )
mbed_official	50:a417edff4437	3655	case 1:
mbed_official	50:a417edff4437	3656	setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0;
mbed_official	50:a417edff4437	3657	break;
mbed_official	50:a417edff4437	3658
mbed_official	50:a417edff4437	3659	#if defined( _CMU_PCNTCTRL_PCNT2CLKEN_MASK )
mbed_official	50:a417edff4437	3660	case 2:
mbed_official	50:a417edff4437	3661	setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0;
mbed_official	50:a417edff4437	3662	break;
bogdanm	0:9b334a45a8ff	3663	#endif
bogdanm	0:9b334a45a8ff	3664	#endif
bogdanm	0:9b334a45a8ff	3665	#endif
bogdanm	0:9b334a45a8ff	3666
mbed_official	50:a417edff4437	3667	default:
mbed_official	50:a417edff4437	3668	setting = 0;
mbed_official	50:a417edff4437	3669	break;
bogdanm	0:9b334a45a8ff	3670	}
mbed_official	50:a417edff4437	3671	return (setting ? true : false);
bogdanm	0:9b334a45a8ff	3672	}
bogdanm	0:9b334a45a8ff	3673
bogdanm	0:9b334a45a8ff	3674
bogdanm	0:9b334a45a8ff	3675	/************************************************************************//
bogdanm	0:9b334a45a8ff	3676	* @brief
bogdanm	0:9b334a45a8ff	3677	* Select PCNTn clock.
bogdanm	0:9b334a45a8ff	3678	*
mbed_official	50:a417edff4437	3679	* @param[in] instance
bogdanm	0:9b334a45a8ff	3680	* PCNT instance number to set selected clock source for.
bogdanm	0:9b334a45a8ff	3681	*
bogdanm	0:9b334a45a8ff	3682	* @param[in] external
bogdanm	0:9b334a45a8ff	3683	* Set to true to select external clock, false to select LFBCLK.
bogdanm	0:9b334a45a8ff	3684	*****************************************************************************/
mbed_official	50:a417edff4437	3685	void CMU_PCNTClockExternalSet(unsigned int instance, bool external)
bogdanm	0:9b334a45a8ff	3686	{
mbed_official	50:a417edff4437	3687	#if defined( PCNT_PRESENT )
bogdanm	0:9b334a45a8ff	3688	uint32_t setting = 0;
bogdanm	0:9b334a45a8ff	3689
mbed_official	50:a417edff4437	3690	EFM_ASSERT(instance < PCNT_COUNT);
bogdanm	0:9b334a45a8ff	3691
bogdanm	0:9b334a45a8ff	3692	if (external)
bogdanm	0:9b334a45a8ff	3693	{
bogdanm	0:9b334a45a8ff	3694	setting = 1;
bogdanm	0:9b334a45a8ff	3695	}
bogdanm	0:9b334a45a8ff	3696
mbed_official	50:a417edff4437	3697	BUS_RegBitWrite(&(CMU->PCNTCTRL), (instance * 2) + 1, setting);
bogdanm	0:9b334a45a8ff	3698
bogdanm	0:9b334a45a8ff	3699	#else
mbed_official	50:a417edff4437	3700	(void)instance; /* Unused parameter */
bogdanm	0:9b334a45a8ff	3701	(void)external; /* Unused parameter */
bogdanm	0:9b334a45a8ff	3702	#endif
bogdanm	0:9b334a45a8ff	3703	}
bogdanm	0:9b334a45a8ff	3704
bogdanm	0:9b334a45a8ff	3705
mbed_official	50:a417edff4437	3706	#if defined( _CMU_USHFRCOCONF_BAND_MASK )
mbed_official	50:a417edff4437	3707	/*************************************************************************//
mbed_official	50:a417edff4437	3708	* @brief
mbed_official	50:a417edff4437	3709	* Get USHFRCO band in use.
mbed_official	50:a417edff4437	3710	*
mbed_official	50:a417edff4437	3711	* @return
mbed_official	50:a417edff4437	3712	* USHFRCO band in use.
mbed_official	50:a417edff4437	3713	******************************************************************************/
mbed_official	50:a417edff4437	3714	CMU_USHFRCOBand_TypeDef CMU_USHFRCOBandGet(void)
mbed_official	50:a417edff4437	3715	{
mbed_official	50:a417edff4437	3716	return (CMU_USHFRCOBand_TypeDef)((CMU->USHFRCOCONF
mbed_official	50:a417edff4437	3717	& _CMU_USHFRCOCONF_BAND_MASK)
mbed_official	50:a417edff4437	3718	>> _CMU_USHFRCOCONF_BAND_SHIFT);
mbed_official	50:a417edff4437	3719	}
mbed_official	50:a417edff4437	3720	#endif
mbed_official	50:a417edff4437	3721
mbed_official	50:a417edff4437	3722	#if defined( _CMU_USHFRCOCONF_BAND_MASK )
mbed_official	50:a417edff4437	3723	/*************************************************************************//
mbed_official	50:a417edff4437	3724	* @brief
mbed_official	50:a417edff4437	3725	* Set USHFRCO band to use.
mbed_official	50:a417edff4437	3726	*
mbed_official	50:a417edff4437	3727	* @param[in] band
mbed_official	50:a417edff4437	3728	* USHFRCO band to activate.
mbed_official	50:a417edff4437	3729	******************************************************************************/
mbed_official	50:a417edff4437	3730	void CMU_USHFRCOBandSet(CMU_USHFRCOBand_TypeDef band)
mbed_official	50:a417edff4437	3731	{
mbed_official	50:a417edff4437	3732	uint32_t tuning;
mbed_official	50:a417edff4437	3733	uint32_t fineTuning;
mbed_official	50:a417edff4437	3734	CMU_Select_TypeDef osc;
mbed_official	50:a417edff4437	3735
mbed_official	50:a417edff4437	3736	/* Cannot switch band if USHFRCO is already selected as HF clock. */
mbed_official	50:a417edff4437	3737	osc = CMU_ClockSelectGet(cmuClock_HF);
mbed_official	50:a417edff4437	3738	EFM_ASSERT((CMU_USHFRCOBandGet() != band) && (osc != cmuSelect_USHFRCO));
mbed_official	50:a417edff4437	3739
mbed_official	50:a417edff4437	3740	/* Read tuning value from calibration table */
mbed_official	50:a417edff4437	3741	switch (band)
mbed_official	50:a417edff4437	3742	{
mbed_official	50:a417edff4437	3743	case cmuUSHFRCOBand_24MHz:
mbed_official	50:a417edff4437	3744	tuning = (DEVINFO->USHFRCOCAL0 & _DEVINFO_USHFRCOCAL0_BAND24_TUNING_MASK)
mbed_official	50:a417edff4437	3745	>> _DEVINFO_USHFRCOCAL0_BAND24_TUNING_SHIFT;
mbed_official	50:a417edff4437	3746	fineTuning = (DEVINFO->USHFRCOCAL0
mbed_official	50:a417edff4437	3747	& _DEVINFO_USHFRCOCAL0_BAND24_FINETUNING_MASK)
mbed_official	50:a417edff4437	3748	>> _DEVINFO_USHFRCOCAL0_BAND24_FINETUNING_SHIFT;
mbed_official	50:a417edff4437	3749	break;
mbed_official	50:a417edff4437	3750
mbed_official	50:a417edff4437	3751	case cmuUSHFRCOBand_48MHz:
mbed_official	50:a417edff4437	3752	tuning = (DEVINFO->USHFRCOCAL0 & _DEVINFO_USHFRCOCAL0_BAND48_TUNING_MASK)
mbed_official	50:a417edff4437	3753	>> _DEVINFO_USHFRCOCAL0_BAND48_TUNING_SHIFT;
mbed_official	50:a417edff4437	3754	fineTuning = (DEVINFO->USHFRCOCAL0
mbed_official	50:a417edff4437	3755	& _DEVINFO_USHFRCOCAL0_BAND48_FINETUNING_MASK)
mbed_official	50:a417edff4437	3756	>> _DEVINFO_USHFRCOCAL0_BAND48_FINETUNING_SHIFT;
mbed_official	50:a417edff4437	3757	/* Enable the clock divider before switching the band from 24 to 48MHz */
mbed_official	50:a417edff4437	3758	BUS_RegBitWrite(&CMU->USHFRCOCONF, _CMU_USHFRCOCONF_USHFRCODIV2DIS_SHIFT, 0);
mbed_official	50:a417edff4437	3759	break;
mbed_official	50:a417edff4437	3760
mbed_official	50:a417edff4437	3761	default:
mbed_official	50:a417edff4437	3762	EFM_ASSERT(0);
mbed_official	50:a417edff4437	3763	return;
mbed_official	50:a417edff4437	3764	}
mbed_official	50:a417edff4437	3765
mbed_official	50:a417edff4437	3766	/* Set band and tuning */
mbed_official	50:a417edff4437	3767	CMU->USHFRCOCONF = (CMU->USHFRCOCONF & ~_CMU_USHFRCOCONF_BAND_MASK)
mbed_official	50:a417edff4437	3768	\| (band << _CMU_USHFRCOCONF_BAND_SHIFT);
mbed_official	50:a417edff4437	3769	CMU->USHFRCOCTRL = (CMU->USHFRCOCTRL & ~_CMU_USHFRCOCTRL_TUNING_MASK)
mbed_official	50:a417edff4437	3770	\| (tuning << _CMU_USHFRCOCTRL_TUNING_SHIFT);
mbed_official	50:a417edff4437	3771	CMU->USHFRCOTUNE = (CMU->USHFRCOTUNE & ~_CMU_USHFRCOTUNE_FINETUNING_MASK)
mbed_official	50:a417edff4437	3772	\| (fineTuning << _CMU_USHFRCOTUNE_FINETUNING_SHIFT);
mbed_official	50:a417edff4437	3773
mbed_official	50:a417edff4437	3774	/* Disable the clock divider after switching the band from 48 to 24MHz */
mbed_official	50:a417edff4437	3775	if (band == cmuUSHFRCOBand_24MHz)
mbed_official	50:a417edff4437	3776	{
mbed_official	50:a417edff4437	3777	BUS_RegBitWrite(&CMU->USHFRCOCONF, _CMU_USHFRCOCONF_USHFRCODIV2DIS_SHIFT, 1);
mbed_official	50:a417edff4437	3778	}
mbed_official	50:a417edff4437	3779	}
mbed_official	50:a417edff4437	3780	#endif
mbed_official	50:a417edff4437	3781
mbed_official	50:a417edff4437	3782
mbed_official	50:a417edff4437	3783
bogdanm	0:9b334a45a8ff	3784	/** @} (end addtogroup CMU) */
bogdanm	0:9b334a45a8ff	3785	/** @} (end addtogroup EM_Library) */
bogdanm	0:9b334a45a8ff	3786	#endif /* __EM_CMU_H */

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Type:	Library
Created:	10 Sep 2016
Imports:	1
Forks:	0
Commits:	148
Dependents:	0
Dependencies:	0
Followers:	1

targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_cmu.c@50:a417edff4437, 2016-01-15 (annotated)

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