Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/i2c_api.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
50:a417edff4437
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /***************************************************************************//**
bogdanm 0:9b334a45a8ff 2 * @file i2c_api.c
bogdanm 0:9b334a45a8ff 3 *******************************************************************************
bogdanm 0:9b334a45a8ff 4 * @section License
bogdanm 0:9b334a45a8ff 5 * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
bogdanm 0:9b334a45a8ff 6 *******************************************************************************
bogdanm 0:9b334a45a8ff 7 *
bogdanm 0:9b334a45a8ff 8 * Permission is granted to anyone to use this software for any purpose,
bogdanm 0:9b334a45a8ff 9 * including commercial applications, and to alter it and redistribute it
bogdanm 0:9b334a45a8ff 10 * freely, subject to the following restrictions:
bogdanm 0:9b334a45a8ff 11 *
bogdanm 0:9b334a45a8ff 12 * 1. The origin of this software must not be misrepresented; you must not
bogdanm 0:9b334a45a8ff 13 * claim that you wrote the original software.
bogdanm 0:9b334a45a8ff 14 * 2. Altered source versions must be plainly marked as such, and must not be
bogdanm 0:9b334a45a8ff 15 * misrepresented as being the original software.
bogdanm 0:9b334a45a8ff 16 * 3. This notice may not be removed or altered from any source distribution.
bogdanm 0:9b334a45a8ff 17 *
bogdanm 0:9b334a45a8ff 18 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
bogdanm 0:9b334a45a8ff 19 * obligation to support this Software. Silicon Labs is providing the
bogdanm 0:9b334a45a8ff 20 * Software "AS IS", with no express or implied warranties of any kind,
bogdanm 0:9b334a45a8ff 21 * including, but not limited to, any implied warranties of merchantability
bogdanm 0:9b334a45a8ff 22 * or fitness for any particular purpose or warranties against infringement
bogdanm 0:9b334a45a8ff 23 * of any proprietary rights of a third party.
bogdanm 0:9b334a45a8ff 24 *
bogdanm 0:9b334a45a8ff 25 * Silicon Labs will not be liable for any consequential, incidental, or
bogdanm 0:9b334a45a8ff 26 * special damages, or any other relief, or for any claim by any third party,
bogdanm 0:9b334a45a8ff 27 * arising from your use of this Software.
bogdanm 0:9b334a45a8ff 28 *
bogdanm 0:9b334a45a8ff 29 ******************************************************************************/
bogdanm 0:9b334a45a8ff 30
bogdanm 0:9b334a45a8ff 31 #include "device.h"
bogdanm 0:9b334a45a8ff 32 #include "clocking.h"
bogdanm 0:9b334a45a8ff 33 #include <stdio.h>
bogdanm 0:9b334a45a8ff 34
bogdanm 0:9b334a45a8ff 35 #if DEVICE_I2C
bogdanm 0:9b334a45a8ff 36
bogdanm 0:9b334a45a8ff 37 #include "mbed_assert.h"
bogdanm 0:9b334a45a8ff 38 #include "i2c_api.h"
bogdanm 0:9b334a45a8ff 39 #include "PeripheralPins.h"
bogdanm 0:9b334a45a8ff 40 #include "pinmap_function.h"
bogdanm 0:9b334a45a8ff 41 #include "sleepmodes.h"
bogdanm 0:9b334a45a8ff 42
bogdanm 0:9b334a45a8ff 43 #include "em_i2c.h"
bogdanm 0:9b334a45a8ff 44 #include "em_cmu.h"
bogdanm 0:9b334a45a8ff 45
bogdanm 0:9b334a45a8ff 46 /** Error flags indicating I2C transfer has failed somehow. */
bogdanm 0:9b334a45a8ff 47 /* Notice that I2C_IF_TXOF (transmit overflow) is not really possible with */
bogdanm 0:9b334a45a8ff 48 /* this SW supporting master mode. Likewise for I2C_IF_RXUF (receive underflow) */
bogdanm 0:9b334a45a8ff 49 /* RXUF is only likely to occur with this SW if using a debugger peeking into */
bogdanm 0:9b334a45a8ff 50 /* RXDATA register. Thus, we ignore those types of fault. */
bogdanm 0:9b334a45a8ff 51 #define I2C_IF_ERRORS (I2C_IF_BUSERR | I2C_IF_ARBLOST)
bogdanm 0:9b334a45a8ff 52 #define I2C_TIMEOUT 100000
bogdanm 0:9b334a45a8ff 53
bogdanm 0:9b334a45a8ff 54 /* Prototypes */
bogdanm 0:9b334a45a8ff 55 int block_and_wait_for_ack(I2C_TypeDef *i2c);
bogdanm 0:9b334a45a8ff 56 void i2c_enable(i2c_t *obj, uint8_t enable);
bogdanm 0:9b334a45a8ff 57 void i2c_enable_pins(i2c_t *obj, uint8_t enable);
bogdanm 0:9b334a45a8ff 58 void i2c_enable_interrupt(i2c_t *obj, uint32_t address, uint8_t enable);
bogdanm 0:9b334a45a8ff 59
bogdanm 0:9b334a45a8ff 60 static uint8_t i2c_get_index(i2c_t *obj)
bogdanm 0:9b334a45a8ff 61 {
bogdanm 0:9b334a45a8ff 62 uint8_t index = 0;
bogdanm 0:9b334a45a8ff 63 switch ((int)obj->i2c.i2c) {
bogdanm 0:9b334a45a8ff 64 #ifdef I2C0
bogdanm 0:9b334a45a8ff 65 case I2C_0:
bogdanm 0:9b334a45a8ff 66 index = 0;
bogdanm 0:9b334a45a8ff 67 break;
bogdanm 0:9b334a45a8ff 68 #endif
bogdanm 0:9b334a45a8ff 69 #ifdef I2C1
bogdanm 0:9b334a45a8ff 70 case I2C_1:
bogdanm 0:9b334a45a8ff 71 index = 1;
bogdanm 0:9b334a45a8ff 72 break;
bogdanm 0:9b334a45a8ff 73 #endif
bogdanm 0:9b334a45a8ff 74 default:
bogdanm 0:9b334a45a8ff 75 printf("I2C module not available.. Out of bound access.");
bogdanm 0:9b334a45a8ff 76 break;
bogdanm 0:9b334a45a8ff 77 }
bogdanm 0:9b334a45a8ff 78 return index;
bogdanm 0:9b334a45a8ff 79 }
bogdanm 0:9b334a45a8ff 80
bogdanm 0:9b334a45a8ff 81 static CMU_Clock_TypeDef i2c_get_clock(i2c_t *obj)
bogdanm 0:9b334a45a8ff 82 {
bogdanm 0:9b334a45a8ff 83 CMU_Clock_TypeDef clock;
bogdanm 0:9b334a45a8ff 84 switch ((int)obj->i2c.i2c) {
bogdanm 0:9b334a45a8ff 85 #ifdef I2C0
bogdanm 0:9b334a45a8ff 86 case I2C_0:
bogdanm 0:9b334a45a8ff 87 clock = cmuClock_I2C0;
bogdanm 0:9b334a45a8ff 88 break;
bogdanm 0:9b334a45a8ff 89 #endif
bogdanm 0:9b334a45a8ff 90 #ifdef I2C1
bogdanm 0:9b334a45a8ff 91 case I2C_1:
bogdanm 0:9b334a45a8ff 92 clock = cmuClock_I2C1;
bogdanm 0:9b334a45a8ff 93 break;
bogdanm 0:9b334a45a8ff 94 #endif
bogdanm 0:9b334a45a8ff 95 default:
bogdanm 0:9b334a45a8ff 96 printf("I2C module not available.. Out of bound access. (clock)");
bogdanm 0:9b334a45a8ff 97 clock = cmuClock_HFPER;
bogdanm 0:9b334a45a8ff 98 break;
bogdanm 0:9b334a45a8ff 99 }
bogdanm 0:9b334a45a8ff 100 return clock;
bogdanm 0:9b334a45a8ff 101 }
bogdanm 0:9b334a45a8ff 102
bogdanm 0:9b334a45a8ff 103 void i2c_preinit(i2c_t *obj, PinName sda, PinName scl)
bogdanm 0:9b334a45a8ff 104 {
bogdanm 0:9b334a45a8ff 105 I2CName i2c_sda = (I2CName) pinmap_peripheral(sda, PinMap_I2C_SDA);
bogdanm 0:9b334a45a8ff 106 I2CName i2c_scl = (I2CName) pinmap_peripheral(scl, PinMap_I2C_SCL);
bogdanm 0:9b334a45a8ff 107 obj->i2c.i2c = (I2C_TypeDef*) pinmap_merge(i2c_sda, i2c_scl);
bogdanm 0:9b334a45a8ff 108 MBED_ASSERT(((int) obj->i2c.i2c) != NC);
bogdanm 0:9b334a45a8ff 109
bogdanm 0:9b334a45a8ff 110 int loc_sda = pin_location(sda, PinMap_I2C_SDA);
bogdanm 0:9b334a45a8ff 111 int loc_scl = pin_location(scl, PinMap_I2C_SCL);
bogdanm 0:9b334a45a8ff 112 obj->i2c.loc = pinmap_merge(loc_sda, loc_scl);
bogdanm 0:9b334a45a8ff 113 MBED_ASSERT(obj->i2c.loc != NC);
bogdanm 0:9b334a45a8ff 114 obj->i2c.sda = sda;
bogdanm 0:9b334a45a8ff 115 obj->i2c.scl = scl;
bogdanm 0:9b334a45a8ff 116 }
bogdanm 0:9b334a45a8ff 117
bogdanm 0:9b334a45a8ff 118 void i2c_init(i2c_t *obj, PinName sda, PinName scl)
bogdanm 0:9b334a45a8ff 119 {
bogdanm 0:9b334a45a8ff 120 /* Assign mbed pins */
bogdanm 0:9b334a45a8ff 121 i2c_preinit(obj, sda, scl);
bogdanm 0:9b334a45a8ff 122
bogdanm 0:9b334a45a8ff 123 /* Enable clock for the peripheral */
bogdanm 0:9b334a45a8ff 124 CMU_ClockEnable(i2c_get_clock(obj), true);
bogdanm 0:9b334a45a8ff 125
bogdanm 0:9b334a45a8ff 126 /* Initializing the I2C */
bogdanm 0:9b334a45a8ff 127 /* Using default settings */
bogdanm 0:9b334a45a8ff 128 I2C_Init_TypeDef i2cInit = I2C_INIT_DEFAULT;
bogdanm 0:9b334a45a8ff 129 I2C_Init(obj->i2c.i2c, &i2cInit);
bogdanm 0:9b334a45a8ff 130
bogdanm 0:9b334a45a8ff 131 /* Enable pins at correct location */
bogdanm 0:9b334a45a8ff 132 obj->i2c.i2c->ROUTE = I2C_ROUTE_SDAPEN | I2C_ROUTE_SCLPEN | (obj->i2c.loc << _I2C_ROUTE_LOCATION_SHIFT);
bogdanm 0:9b334a45a8ff 133 i2c_enable_pins(obj, true);
bogdanm 0:9b334a45a8ff 134
bogdanm 0:9b334a45a8ff 135 /* Enable General Call Address Mode. That is; we respond to the general address (0x0) */
bogdanm 0:9b334a45a8ff 136 obj->i2c.i2c->CTRL |= _I2C_CTRL_GCAMEN_MASK;
bogdanm 0:9b334a45a8ff 137
bogdanm 0:9b334a45a8ff 138 /* We are assuming that there is only one master. So disable automatic arbitration */
bogdanm 0:9b334a45a8ff 139 obj->i2c.i2c->CTRL |= _I2C_CTRL_ARBDIS_MASK;
bogdanm 0:9b334a45a8ff 140
bogdanm 0:9b334a45a8ff 141 /* Enable i2c */
bogdanm 0:9b334a45a8ff 142 i2c_enable(obj, true);
bogdanm 0:9b334a45a8ff 143 }
bogdanm 0:9b334a45a8ff 144
bogdanm 0:9b334a45a8ff 145 void i2c_enable(i2c_t *obj, uint8_t enable)
bogdanm 0:9b334a45a8ff 146 {
bogdanm 0:9b334a45a8ff 147 I2C_Enable(obj->i2c.i2c, enable);
bogdanm 0:9b334a45a8ff 148 if (!enable) {
bogdanm 0:9b334a45a8ff 149 /* After a reset BUSY is usually set. We assume that we are the only master and call abort,
bogdanm 0:9b334a45a8ff 150 * which sends nothing on the bus, it just allows us to assume that the bus is idle */
bogdanm 0:9b334a45a8ff 151 if (obj->i2c.i2c->STATE & I2C_STATE_BUSY) {
bogdanm 0:9b334a45a8ff 152 obj->i2c.i2c->CMD = I2C_CMD_ABORT;
bogdanm 0:9b334a45a8ff 153 }
bogdanm 0:9b334a45a8ff 154
bogdanm 0:9b334a45a8ff 155 }
bogdanm 0:9b334a45a8ff 156 }
bogdanm 0:9b334a45a8ff 157
bogdanm 0:9b334a45a8ff 158 void i2c_enable_pins(i2c_t *obj, uint8_t enable)
bogdanm 0:9b334a45a8ff 159 {
bogdanm 0:9b334a45a8ff 160 if (enable) {
bogdanm 0:9b334a45a8ff 161 pin_mode(obj->i2c.scl, WiredAndPullUp);
bogdanm 0:9b334a45a8ff 162 pin_mode(obj->i2c.sda, WiredAndPullUp);
bogdanm 0:9b334a45a8ff 163 } else {
bogdanm 0:9b334a45a8ff 164 // TODO_LP return PinMode to the previous state
bogdanm 0:9b334a45a8ff 165 pin_mode(obj->i2c.sda, Disabled);
bogdanm 0:9b334a45a8ff 166 pin_mode(obj->i2c.scl, Disabled);
bogdanm 0:9b334a45a8ff 167 }
bogdanm 0:9b334a45a8ff 168 }
bogdanm 0:9b334a45a8ff 169
bogdanm 0:9b334a45a8ff 170 void i2c_enable_interrupt(i2c_t *obj, uint32_t address, uint8_t enable)
bogdanm 0:9b334a45a8ff 171 {
bogdanm 0:9b334a45a8ff 172 IRQn_Type irq_number;
bogdanm 0:9b334a45a8ff 173
bogdanm 0:9b334a45a8ff 174 switch (i2c_get_index(obj)) {
bogdanm 0:9b334a45a8ff 175 #ifdef I2C0
bogdanm 0:9b334a45a8ff 176 case 0:
bogdanm 0:9b334a45a8ff 177 irq_number = I2C0_IRQn;
bogdanm 0:9b334a45a8ff 178 break;
bogdanm 0:9b334a45a8ff 179 #endif
bogdanm 0:9b334a45a8ff 180 #ifdef I2C1
bogdanm 0:9b334a45a8ff 181 case 1:
bogdanm 0:9b334a45a8ff 182 irq_number = I2C1_IRQn;
bogdanm 0:9b334a45a8ff 183 break;
bogdanm 0:9b334a45a8ff 184 #endif
bogdanm 0:9b334a45a8ff 185 }
bogdanm 0:9b334a45a8ff 186
bogdanm 0:9b334a45a8ff 187 NVIC_SetVector(irq_number, address);
bogdanm 0:9b334a45a8ff 188 /* Lower IRQ priority to avoid messing with asynch RX on UART */
bogdanm 0:9b334a45a8ff 189 NVIC_SetPriority(irq_number, 1);
bogdanm 0:9b334a45a8ff 190 if (enable) {
bogdanm 0:9b334a45a8ff 191 NVIC_EnableIRQ(irq_number);
bogdanm 0:9b334a45a8ff 192 } else {
bogdanm 0:9b334a45a8ff 193 NVIC_DisableIRQ(irq_number);
bogdanm 0:9b334a45a8ff 194 }
bogdanm 0:9b334a45a8ff 195 }
bogdanm 0:9b334a45a8ff 196
bogdanm 0:9b334a45a8ff 197 /* Set the frequency of the I2C interface */
bogdanm 0:9b334a45a8ff 198 void i2c_frequency(i2c_t *obj, int hz)
bogdanm 0:9b334a45a8ff 199 {
bogdanm 0:9b334a45a8ff 200 /* Set frequency. As the second argument is 0,
bogdanm 0:9b334a45a8ff 201 * HFPER clock frequency is used as reference freq */
bogdanm 0:9b334a45a8ff 202 I2C_BusFreqSet(obj->i2c.i2c, REFERENCE_FREQUENCY, hz, i2cClockHLRStandard);
bogdanm 0:9b334a45a8ff 203 }
bogdanm 0:9b334a45a8ff 204
bogdanm 0:9b334a45a8ff 205 /* Creates a start condition on the I2C bus */
bogdanm 0:9b334a45a8ff 206 int i2c_start(i2c_t *obj)
bogdanm 0:9b334a45a8ff 207 {
bogdanm 0:9b334a45a8ff 208 I2C_TypeDef *i2c = obj->i2c.i2c;
bogdanm 0:9b334a45a8ff 209
bogdanm 0:9b334a45a8ff 210 /* Ensure buffers are empty */
bogdanm 0:9b334a45a8ff 211 i2c->CMD = I2C_CMD_CLEARPC | I2C_CMD_CLEARTX;
bogdanm 0:9b334a45a8ff 212 if (i2c->IF & I2C_IF_RXDATAV) {
bogdanm 0:9b334a45a8ff 213 (void) i2c->RXDATA;
bogdanm 0:9b334a45a8ff 214 }
bogdanm 0:9b334a45a8ff 215
bogdanm 0:9b334a45a8ff 216 /* Clear all pending interrupts prior to starting transfer. */
bogdanm 0:9b334a45a8ff 217 i2c->IFC = _I2C_IFC_MASK;
bogdanm 0:9b334a45a8ff 218
bogdanm 0:9b334a45a8ff 219 /* Send start */
bogdanm 0:9b334a45a8ff 220 obj->i2c.i2c->CMD = I2C_CMD_START;
bogdanm 0:9b334a45a8ff 221 return 0;
bogdanm 0:9b334a45a8ff 222 }
bogdanm 0:9b334a45a8ff 223
bogdanm 0:9b334a45a8ff 224 /* Creates a stop condition on the I2C bus */
bogdanm 0:9b334a45a8ff 225 int i2c_stop(i2c_t *obj)
bogdanm 0:9b334a45a8ff 226 {
bogdanm 0:9b334a45a8ff 227 obj->i2c.i2c->CMD = I2C_CMD_STOP;
bogdanm 0:9b334a45a8ff 228
bogdanm 0:9b334a45a8ff 229 /* Wait for the stop to be sent */
bogdanm 0:9b334a45a8ff 230 int timeout = I2C_TIMEOUT;
bogdanm 0:9b334a45a8ff 231 while (!(obj->i2c.i2c->IF & I2C_IF_MSTOP) && !timeout--);
bogdanm 0:9b334a45a8ff 232
bogdanm 0:9b334a45a8ff 233 return 0;
bogdanm 0:9b334a45a8ff 234 }
bogdanm 0:9b334a45a8ff 235
bogdanm 0:9b334a45a8ff 236 /* Returns number of bytes read */
bogdanm 0:9b334a45a8ff 237 int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
bogdanm 0:9b334a45a8ff 238 {
bogdanm 0:9b334a45a8ff 239 int retval;
bogdanm 0:9b334a45a8ff 240
bogdanm 0:9b334a45a8ff 241 i2c_start(obj);
bogdanm 0:9b334a45a8ff 242
bogdanm 0:9b334a45a8ff 243 retval = i2c_byte_write(obj, (address | 1));
bogdanm 0:9b334a45a8ff 244 if ((!retval) || (length == 0)) { //Write address with W flag (last bit 1)
bogdanm 0:9b334a45a8ff 245 obj->i2c.i2c->CMD = I2C_CMD_STOP | I2C_CMD_ABORT;
bogdanm 0:9b334a45a8ff 246 while(obj->i2c.i2c->STATE & I2C_STATE_BUSY); // Wait until the bus is done
bogdanm 0:9b334a45a8ff 247 return (retval == 0 ? I2C_ERROR_NO_SLAVE : 0); //NACK or error when writing adress. Return 0 as 0 bytes were read
bogdanm 0:9b334a45a8ff 248 }
bogdanm 0:9b334a45a8ff 249 int i = 0;
bogdanm 0:9b334a45a8ff 250 while (i < length) {
bogdanm 0:9b334a45a8ff 251 uint8_t last = (i == length - 1);
bogdanm 0:9b334a45a8ff 252 data[i++] = i2c_byte_read(obj, last);
bogdanm 0:9b334a45a8ff 253 }
bogdanm 0:9b334a45a8ff 254
bogdanm 0:9b334a45a8ff 255 if (stop) {
bogdanm 0:9b334a45a8ff 256 i2c_stop(obj);
bogdanm 0:9b334a45a8ff 257 }
bogdanm 0:9b334a45a8ff 258
bogdanm 0:9b334a45a8ff 259 return length;
bogdanm 0:9b334a45a8ff 260 }
bogdanm 0:9b334a45a8ff 261
bogdanm 0:9b334a45a8ff 262 int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
bogdanm 0:9b334a45a8ff 263 {
bogdanm 0:9b334a45a8ff 264 i2c_start(obj);
bogdanm 0:9b334a45a8ff 265
bogdanm 0:9b334a45a8ff 266 if (!i2c_byte_write(obj, (address & 0xFE))) {
bogdanm 0:9b334a45a8ff 267 i2c_stop(obj);
bogdanm 0:9b334a45a8ff 268 return I2C_ERROR_NO_SLAVE; //NACK or error when writing adress. Return 0 as 0 bytes were written
bogdanm 0:9b334a45a8ff 269 }
bogdanm 0:9b334a45a8ff 270 int i;
bogdanm 0:9b334a45a8ff 271 for (i = 0; i < length; i++) {
bogdanm 0:9b334a45a8ff 272 if (!i2c_byte_write(obj, data[i])) {
bogdanm 0:9b334a45a8ff 273 i2c_stop(obj);
bogdanm 0:9b334a45a8ff 274 return i;
bogdanm 0:9b334a45a8ff 275 }
bogdanm 0:9b334a45a8ff 276 }
bogdanm 0:9b334a45a8ff 277
bogdanm 0:9b334a45a8ff 278 if (stop) {
bogdanm 0:9b334a45a8ff 279 i2c_stop(obj);
bogdanm 0:9b334a45a8ff 280 }
bogdanm 0:9b334a45a8ff 281
bogdanm 0:9b334a45a8ff 282 return length;
bogdanm 0:9b334a45a8ff 283 }
bogdanm 0:9b334a45a8ff 284
bogdanm 0:9b334a45a8ff 285 void i2c_reset(i2c_t *obj)
bogdanm 0:9b334a45a8ff 286 {
bogdanm 0:9b334a45a8ff 287 /* EMLib function */
bogdanm 0:9b334a45a8ff 288 I2C_Reset(obj->i2c.i2c);
bogdanm 0:9b334a45a8ff 289 }
bogdanm 0:9b334a45a8ff 290
bogdanm 0:9b334a45a8ff 291 int i2c_byte_read(i2c_t *obj, int last)
bogdanm 0:9b334a45a8ff 292 {
bogdanm 0:9b334a45a8ff 293 int timeout = I2C_TIMEOUT;
bogdanm 0:9b334a45a8ff 294 /* Wait for data */
bogdanm 0:9b334a45a8ff 295 while (!(obj->i2c.i2c->STATUS & I2C_STATUS_RXDATAV) && timeout--);
bogdanm 0:9b334a45a8ff 296
bogdanm 0:9b334a45a8ff 297 if (timeout <= 0) {
bogdanm 0:9b334a45a8ff 298 return 0; //TODO Is this the correct way to handle this?
bogdanm 0:9b334a45a8ff 299 }
bogdanm 0:9b334a45a8ff 300 char data = obj->i2c.i2c->RXDATA;
bogdanm 0:9b334a45a8ff 301
bogdanm 0:9b334a45a8ff 302 if (last) {
bogdanm 0:9b334a45a8ff 303 obj->i2c.i2c->CMD = I2C_CMD_NACK;
bogdanm 0:9b334a45a8ff 304 } else {
bogdanm 0:9b334a45a8ff 305 obj->i2c.i2c->CMD = I2C_CMD_ACK;
bogdanm 0:9b334a45a8ff 306 }
bogdanm 0:9b334a45a8ff 307 return data;
bogdanm 0:9b334a45a8ff 308 }
bogdanm 0:9b334a45a8ff 309
bogdanm 0:9b334a45a8ff 310 int i2c_byte_write(i2c_t *obj, int data)
bogdanm 0:9b334a45a8ff 311 {
bogdanm 0:9b334a45a8ff 312 obj->i2c.i2c->TXDATA = data;
bogdanm 0:9b334a45a8ff 313 return block_and_wait_for_ack(obj->i2c.i2c);
bogdanm 0:9b334a45a8ff 314 }
bogdanm 0:9b334a45a8ff 315
bogdanm 0:9b334a45a8ff 316 /*
bogdanm 0:9b334a45a8ff 317 * Returns 1 for ACK. 0 for NACK, timeout or error.
bogdanm 0:9b334a45a8ff 318 */
bogdanm 0:9b334a45a8ff 319 int block_and_wait_for_ack(I2C_TypeDef *i2c)
bogdanm 0:9b334a45a8ff 320 {
bogdanm 0:9b334a45a8ff 321 uint32_t pending;
bogdanm 0:9b334a45a8ff 322 uint32_t timeout = I2C_TIMEOUT;
bogdanm 0:9b334a45a8ff 323 while (timeout > 0) {
bogdanm 0:9b334a45a8ff 324 timeout -= 1;
bogdanm 0:9b334a45a8ff 325 pending = i2c->IF;
bogdanm 0:9b334a45a8ff 326 /* If some sort of fault, abort transfer. */
bogdanm 0:9b334a45a8ff 327 if (pending & I2C_IF_ERRORS) {
bogdanm 0:9b334a45a8ff 328 if (pending & I2C_IF_ARBLOST) {
bogdanm 0:9b334a45a8ff 329 /* If arbitration fault, it indicates either a slave device */
bogdanm 0:9b334a45a8ff 330 /* not responding as expected, or other master which is not */
bogdanm 0:9b334a45a8ff 331 /* supported by this SW. */
bogdanm 0:9b334a45a8ff 332 return 0;
bogdanm 0:9b334a45a8ff 333 } else if (pending & I2C_IF_BUSERR) {
bogdanm 0:9b334a45a8ff 334 /* A bus error indicates a misplaced start or stop, which should */
bogdanm 0:9b334a45a8ff 335 /* not occur in master mode controlled by this SW. */
bogdanm 0:9b334a45a8ff 336 return 0;
bogdanm 0:9b334a45a8ff 337 }
bogdanm 0:9b334a45a8ff 338 }
bogdanm 0:9b334a45a8ff 339
bogdanm 0:9b334a45a8ff 340 if (pending & I2C_IF_NACK) {
bogdanm 0:9b334a45a8ff 341 i2c->IFC = I2C_IFC_NACK;
bogdanm 0:9b334a45a8ff 342 return 0; //Received NACK
bogdanm 0:9b334a45a8ff 343 } else if (pending & I2C_IF_ACK) {
bogdanm 0:9b334a45a8ff 344 i2c->IFC = I2C_IFC_ACK;
bogdanm 0:9b334a45a8ff 345 return 1; //Got ACK
bogdanm 0:9b334a45a8ff 346 }
bogdanm 0:9b334a45a8ff 347 }
bogdanm 0:9b334a45a8ff 348 return 0; //Timeout
bogdanm 0:9b334a45a8ff 349 }
bogdanm 0:9b334a45a8ff 350
bogdanm 0:9b334a45a8ff 351 #if DEVICE_I2CSLAVE
bogdanm 0:9b334a45a8ff 352
bogdanm 0:9b334a45a8ff 353 #define NoData 0
bogdanm 0:9b334a45a8ff 354 #define ReadAddressed 1
bogdanm 0:9b334a45a8ff 355 #define WriteGeneral 2
bogdanm 0:9b334a45a8ff 356 #define WriteAddressed 3
bogdanm 0:9b334a45a8ff 357
bogdanm 0:9b334a45a8ff 358
bogdanm 0:9b334a45a8ff 359 void i2c_slave_mode(i2c_t *obj, int enable_slave)
bogdanm 0:9b334a45a8ff 360 {
bogdanm 0:9b334a45a8ff 361 if(enable_slave) {
bogdanm 0:9b334a45a8ff 362 obj->i2c.i2c->CTRL |= _I2C_CTRL_SLAVE_MASK;
bogdanm 0:9b334a45a8ff 363 obj->i2c.i2c->CTRL |= _I2C_CTRL_AUTOACK_MASK; //Slave implementation assumes auto acking
bogdanm 0:9b334a45a8ff 364 } else {
bogdanm 0:9b334a45a8ff 365 obj->i2c.i2c->CTRL &= ~_I2C_CTRL_SLAVE_MASK;
bogdanm 0:9b334a45a8ff 366 obj->i2c.i2c->CTRL &= ~_I2C_CTRL_AUTOACK_MASK; //Master implementation ACKs manually
bogdanm 0:9b334a45a8ff 367 }
bogdanm 0:9b334a45a8ff 368 }
bogdanm 0:9b334a45a8ff 369
bogdanm 0:9b334a45a8ff 370 int i2c_slave_receive(i2c_t *obj)
bogdanm 0:9b334a45a8ff 371 {
bogdanm 0:9b334a45a8ff 372
bogdanm 0:9b334a45a8ff 373 if(obj->i2c.i2c->IF & I2C_IF_ADDR) {
bogdanm 0:9b334a45a8ff 374 obj->i2c.i2c->IFC = I2C_IF_ADDR; //Clear interrupt
bogdanm 0:9b334a45a8ff 375 /*0x00 is the address for general write.
bogdanm 0:9b334a45a8ff 376 The address the master wrote is in RXDATA now
bogdanm 0:9b334a45a8ff 377 and reading it also frees the buffer for the next
bogdanm 0:9b334a45a8ff 378 write which can then be acked. */
bogdanm 0:9b334a45a8ff 379 if(obj->i2c.i2c->RXDATA == 0x00) {
bogdanm 0:9b334a45a8ff 380 return WriteGeneral; //Read the address;
bogdanm 0:9b334a45a8ff 381 }
bogdanm 0:9b334a45a8ff 382
bogdanm 0:9b334a45a8ff 383 if(obj->i2c.i2c->STATE & I2C_STATE_TRANSMITTER) {
bogdanm 0:9b334a45a8ff 384 return ReadAddressed;
bogdanm 0:9b334a45a8ff 385 } else {
bogdanm 0:9b334a45a8ff 386 return WriteAddressed;
bogdanm 0:9b334a45a8ff 387 }
bogdanm 0:9b334a45a8ff 388 }
bogdanm 0:9b334a45a8ff 389
bogdanm 0:9b334a45a8ff 390 return NoData;
bogdanm 0:9b334a45a8ff 391
bogdanm 0:9b334a45a8ff 392 }
bogdanm 0:9b334a45a8ff 393
bogdanm 0:9b334a45a8ff 394 int i2c_slave_read(i2c_t *obj, char *data, int length)
bogdanm 0:9b334a45a8ff 395 {
bogdanm 0:9b334a45a8ff 396 int count;
bogdanm 0:9b334a45a8ff 397 for (count = 0; count < length; count++) {
bogdanm 0:9b334a45a8ff 398 data[count] = i2c_byte_read(obj, 0);
bogdanm 0:9b334a45a8ff 399 }
bogdanm 0:9b334a45a8ff 400
bogdanm 0:9b334a45a8ff 401
bogdanm 0:9b334a45a8ff 402 return count;
bogdanm 0:9b334a45a8ff 403
bogdanm 0:9b334a45a8ff 404 }
bogdanm 0:9b334a45a8ff 405
bogdanm 0:9b334a45a8ff 406 int i2c_slave_write(i2c_t *obj, const char *data, int length)
bogdanm 0:9b334a45a8ff 407 {
bogdanm 0:9b334a45a8ff 408 int count;
bogdanm 0:9b334a45a8ff 409 for (count = 0; count < length; count++) {
bogdanm 0:9b334a45a8ff 410 i2c_byte_write(obj, data[count]);
bogdanm 0:9b334a45a8ff 411 }
bogdanm 0:9b334a45a8ff 412
bogdanm 0:9b334a45a8ff 413 return count;
bogdanm 0:9b334a45a8ff 414 }
bogdanm 0:9b334a45a8ff 415
bogdanm 0:9b334a45a8ff 416 void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask)
bogdanm 0:9b334a45a8ff 417 {
bogdanm 0:9b334a45a8ff 418 obj->i2c.i2c->SADDR = address;
bogdanm 0:9b334a45a8ff 419 obj->i2c.i2c->SADDRMASK = 0xFE;//mask;
bogdanm 0:9b334a45a8ff 420 }
bogdanm 0:9b334a45a8ff 421
bogdanm 0:9b334a45a8ff 422 #endif //DEVICE_I2CSLAVE
bogdanm 0:9b334a45a8ff 423
bogdanm 0:9b334a45a8ff 424 #ifdef DEVICE_I2C_ASYNCH
bogdanm 0:9b334a45a8ff 425
bogdanm 0:9b334a45a8ff 426 #include "em_dma.h"
bogdanm 0:9b334a45a8ff 427 #include "dma_api_HAL.h"
bogdanm 0:9b334a45a8ff 428 #include "dma_api.h"
bogdanm 0:9b334a45a8ff 429 #include "sleep_api.h"
bogdanm 0:9b334a45a8ff 430 #include "buffer.h"
bogdanm 0:9b334a45a8ff 431
bogdanm 0:9b334a45a8ff 432 /** Start i2c asynchronous transfer.
bogdanm 0:9b334a45a8ff 433 * @param obj The I2C object
bogdanm 0:9b334a45a8ff 434 * @param tx The buffer to send
bogdanm 0:9b334a45a8ff 435 * @param tx_length The number of words to transmit
bogdanm 0:9b334a45a8ff 436 * @param rx The buffer to receive
bogdanm 0:9b334a45a8ff 437 * @param rx_length The number of words to receive
bogdanm 0:9b334a45a8ff 438 * @param address The address to be set - 7bit or 9 bit
bogdanm 0:9b334a45a8ff 439 * @param stop If true, stop will be generated after the transfer is done
bogdanm 0:9b334a45a8ff 440 * @param handler The I2C IRQ handler to be set
bogdanm 0:9b334a45a8ff 441 * @param hint DMA hint usage
bogdanm 0:9b334a45a8ff 442 */
bogdanm 0:9b334a45a8ff 443 void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint)
bogdanm 0:9b334a45a8ff 444 {
bogdanm 0:9b334a45a8ff 445 I2C_TransferReturn_TypeDef retval;
bogdanm 0:9b334a45a8ff 446 if(i2c_active(obj)) return;
bogdanm 0:9b334a45a8ff 447 if((tx_length == 0) && (rx_length == 0)) return;
bogdanm 0:9b334a45a8ff 448 // For now, we are assuming a solely interrupt-driven implementation.
bogdanm 0:9b334a45a8ff 449
bogdanm 0:9b334a45a8ff 450 // Store transfer config
bogdanm 0:9b334a45a8ff 451 obj->i2c.xfer.addr = address;
bogdanm 0:9b334a45a8ff 452
bogdanm 0:9b334a45a8ff 453 // Some combination of tx_length and rx_length will tell us what to do
bogdanm 0:9b334a45a8ff 454 if((tx_length > 0) && (rx_length == 0)) {
bogdanm 0:9b334a45a8ff 455 obj->i2c.xfer.flags = I2C_FLAG_WRITE;
bogdanm 0:9b334a45a8ff 456 //Store buffer info
bogdanm 0:9b334a45a8ff 457 obj->i2c.xfer.buf[0].data = (void *)tx;
bogdanm 0:9b334a45a8ff 458 obj->i2c.xfer.buf[0].len = (uint16_t) tx_length;
bogdanm 0:9b334a45a8ff 459 } else if ((tx_length == 0) && (rx_length > 0)) {
bogdanm 0:9b334a45a8ff 460 obj->i2c.xfer.flags = I2C_FLAG_READ;
bogdanm 0:9b334a45a8ff 461 //Store buffer info
bogdanm 0:9b334a45a8ff 462 obj->i2c.xfer.buf[0].data = rx;
bogdanm 0:9b334a45a8ff 463 obj->i2c.xfer.buf[0].len = (uint16_t) rx_length;
bogdanm 0:9b334a45a8ff 464 } else if ((tx_length > 0) && (rx_length > 0)) {
bogdanm 0:9b334a45a8ff 465 obj->i2c.xfer.flags = I2C_FLAG_WRITE_READ;
bogdanm 0:9b334a45a8ff 466 //Store buffer info
bogdanm 0:9b334a45a8ff 467 obj->i2c.xfer.buf[0].data = (void *)tx;
bogdanm 0:9b334a45a8ff 468 obj->i2c.xfer.buf[0].len = (uint16_t) tx_length;
bogdanm 0:9b334a45a8ff 469 obj->i2c.xfer.buf[1].data = rx;
bogdanm 0:9b334a45a8ff 470 obj->i2c.xfer.buf[1].len = (uint16_t) rx_length;
bogdanm 0:9b334a45a8ff 471 }
bogdanm 0:9b334a45a8ff 472
bogdanm 0:9b334a45a8ff 473 if(address > 255) obj->i2c.xfer.flags |= I2C_FLAG_10BIT_ADDR;
bogdanm 0:9b334a45a8ff 474
bogdanm 0:9b334a45a8ff 475 // Store event flags
bogdanm 0:9b334a45a8ff 476 obj->i2c.events = event;
bogdanm 0:9b334a45a8ff 477
bogdanm 0:9b334a45a8ff 478 // Enable interrupt
bogdanm 0:9b334a45a8ff 479 i2c_enable_interrupt(obj, handler, true);
bogdanm 0:9b334a45a8ff 480
bogdanm 0:9b334a45a8ff 481 // Kick off the transfer
bogdanm 0:9b334a45a8ff 482 retval = I2C_TransferInit(obj->i2c.i2c, &(obj->i2c.xfer));
bogdanm 0:9b334a45a8ff 483
bogdanm 0:9b334a45a8ff 484 if(retval == i2cTransferInProgress) {
bogdanm 0:9b334a45a8ff 485 blockSleepMode(EM1);
bogdanm 0:9b334a45a8ff 486 } else {
bogdanm 0:9b334a45a8ff 487 // something happened, and the transfer did not go through
bogdanm 0:9b334a45a8ff 488 // So, we need to clean up
bogdanm 0:9b334a45a8ff 489
bogdanm 0:9b334a45a8ff 490 // Disable interrupt
bogdanm 0:9b334a45a8ff 491 i2c_enable_interrupt(obj, 0, false);
bogdanm 0:9b334a45a8ff 492
bogdanm 0:9b334a45a8ff 493 // Block until free
bogdanm 0:9b334a45a8ff 494 while(i2c_active(obj));
bogdanm 0:9b334a45a8ff 495 }
bogdanm 0:9b334a45a8ff 496 }
bogdanm 0:9b334a45a8ff 497
bogdanm 0:9b334a45a8ff 498 /** The asynchronous IRQ handler
bogdanm 0:9b334a45a8ff 499 * @param obj The I2C object which holds the transfer information
bogdanm 0:9b334a45a8ff 500 * @return Returns event flags if a transfer termination condition was met or 0 otherwise.
bogdanm 0:9b334a45a8ff 501 */
bogdanm 0:9b334a45a8ff 502 uint32_t i2c_irq_handler_asynch(i2c_t *obj)
bogdanm 0:9b334a45a8ff 503 {
bogdanm 0:9b334a45a8ff 504
bogdanm 0:9b334a45a8ff 505 // For now, we are assuming a solely interrupt-driven implementation.
bogdanm 0:9b334a45a8ff 506
bogdanm 0:9b334a45a8ff 507 I2C_TransferReturn_TypeDef status = I2C_Transfer(obj->i2c.i2c);
bogdanm 0:9b334a45a8ff 508 switch(status) {
bogdanm 0:9b334a45a8ff 509 case i2cTransferInProgress:
bogdanm 0:9b334a45a8ff 510 // Still busy transferring, so let it.
bogdanm 0:9b334a45a8ff 511 return 0;
bogdanm 0:9b334a45a8ff 512 case i2cTransferDone:
bogdanm 0:9b334a45a8ff 513 // Transfer has completed
bogdanm 0:9b334a45a8ff 514
bogdanm 0:9b334a45a8ff 515 // Disable interrupt
bogdanm 0:9b334a45a8ff 516 i2c_enable_interrupt(obj, 0, false);
bogdanm 0:9b334a45a8ff 517
bogdanm 0:9b334a45a8ff 518 unblockSleepMode(EM1);
bogdanm 0:9b334a45a8ff 519
bogdanm 0:9b334a45a8ff 520 return I2C_EVENT_TRANSFER_COMPLETE & obj->i2c.events;
bogdanm 0:9b334a45a8ff 521 case i2cTransferNack:
bogdanm 0:9b334a45a8ff 522 // A NACK has been received while an ACK was expected. This is usually because the slave did not respond to the address.
bogdanm 0:9b334a45a8ff 523 // Disable interrupt
bogdanm 0:9b334a45a8ff 524 i2c_enable_interrupt(obj, 0, false);
bogdanm 0:9b334a45a8ff 525
bogdanm 0:9b334a45a8ff 526 unblockSleepMode(EM1);
bogdanm 0:9b334a45a8ff 527
bogdanm 0:9b334a45a8ff 528 return I2C_EVENT_ERROR_NO_SLAVE & obj->i2c.events;
bogdanm 0:9b334a45a8ff 529 default:
bogdanm 0:9b334a45a8ff 530 // An error situation has arisen.
bogdanm 0:9b334a45a8ff 531 // Disable interrupt
bogdanm 0:9b334a45a8ff 532 i2c_enable_interrupt(obj, 0, false);
bogdanm 0:9b334a45a8ff 533
bogdanm 0:9b334a45a8ff 534 unblockSleepMode(EM1);
bogdanm 0:9b334a45a8ff 535
bogdanm 0:9b334a45a8ff 536 // return error
bogdanm 0:9b334a45a8ff 537 return I2C_EVENT_ERROR & obj->i2c.events;
bogdanm 0:9b334a45a8ff 538 }
bogdanm 0:9b334a45a8ff 539 }
bogdanm 0:9b334a45a8ff 540
bogdanm 0:9b334a45a8ff 541 /** Attempts to determine if I2C peripheral is already in use.
bogdanm 0:9b334a45a8ff 542 * @param obj The I2C object
bogdanm 0:9b334a45a8ff 543 * @return non-zero if the I2C module is active or zero if it is not
bogdanm 0:9b334a45a8ff 544 */
bogdanm 0:9b334a45a8ff 545 uint8_t i2c_active(i2c_t *obj)
bogdanm 0:9b334a45a8ff 546 {
bogdanm 0:9b334a45a8ff 547 return (obj->i2c.i2c->STATE & I2C_STATE_BUSY);
bogdanm 0:9b334a45a8ff 548 }
bogdanm 0:9b334a45a8ff 549
bogdanm 0:9b334a45a8ff 550 /** Abort ongoing asynchronous transaction.
bogdanm 0:9b334a45a8ff 551 * @param obj The I2C object
bogdanm 0:9b334a45a8ff 552 */
bogdanm 0:9b334a45a8ff 553 void i2c_abort_asynch(i2c_t *obj)
bogdanm 0:9b334a45a8ff 554 {
bogdanm 0:9b334a45a8ff 555 // Do not deactivate I2C twice
bogdanm 0:9b334a45a8ff 556 if (!i2c_active(obj)) return;
bogdanm 0:9b334a45a8ff 557
bogdanm 0:9b334a45a8ff 558 // Disable interrupt
bogdanm 0:9b334a45a8ff 559 i2c_enable_interrupt(obj, 0, false);
bogdanm 0:9b334a45a8ff 560
bogdanm 0:9b334a45a8ff 561 // Abort
bogdanm 0:9b334a45a8ff 562 obj->i2c.i2c->CMD = I2C_CMD_STOP | I2C_CMD_ABORT;
bogdanm 0:9b334a45a8ff 563
bogdanm 0:9b334a45a8ff 564 // Block until free
bogdanm 0:9b334a45a8ff 565 while(i2c_active(obj));
bogdanm 0:9b334a45a8ff 566
bogdanm 0:9b334a45a8ff 567 unblockSleepMode(EM1);
bogdanm 0:9b334a45a8ff 568 }
bogdanm 0:9b334a45a8ff 569
bogdanm 0:9b334a45a8ff 570 #endif //DEVICE_I2C ASYNCH
bogdanm 0:9b334a45a8ff 571 #endif //DEVICE_I2C