Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Freescale/TARGET_KLXX/clk_freqs.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /* mbed Microcontroller Library
bogdanm 0:9b334a45a8ff 2 * Copyright (c) 2006-2013 ARM Limited
bogdanm 0:9b334a45a8ff 3 *
bogdanm 0:9b334a45a8ff 4 * Licensed under the Apache License, Version 2.0 (the "License");
bogdanm 0:9b334a45a8ff 5 * you may not use this file except in compliance with the License.
bogdanm 0:9b334a45a8ff 6 * You may obtain a copy of the License at
bogdanm 0:9b334a45a8ff 7 *
bogdanm 0:9b334a45a8ff 8 * http://www.apache.org/licenses/LICENSE-2.0
bogdanm 0:9b334a45a8ff 9 *
bogdanm 0:9b334a45a8ff 10 * Unless required by applicable law or agreed to in writing, software
bogdanm 0:9b334a45a8ff 11 * distributed under the License is distributed on an "AS IS" BASIS,
bogdanm 0:9b334a45a8ff 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
bogdanm 0:9b334a45a8ff 13 * See the License for the specific language governing permissions and
bogdanm 0:9b334a45a8ff 14 * limitations under the License.
bogdanm 0:9b334a45a8ff 15 */
bogdanm 0:9b334a45a8ff 16 #ifndef MBED_CLK_FREQS_H
bogdanm 0:9b334a45a8ff 17 #define MBED_CLK_FREQS_H
bogdanm 0:9b334a45a8ff 18
bogdanm 0:9b334a45a8ff 19 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 20 extern "C" {
bogdanm 0:9b334a45a8ff 21 #endif
bogdanm 0:9b334a45a8ff 22
bogdanm 0:9b334a45a8ff 23 #include "PeripheralPins.h"
bogdanm 0:9b334a45a8ff 24
bogdanm 0:9b334a45a8ff 25 //Get the peripheral bus clock frequency
bogdanm 0:9b334a45a8ff 26 static inline uint32_t bus_frequency(void) {
bogdanm 0:9b334a45a8ff 27 return (SystemCoreClock / (((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT) + 1));
bogdanm 0:9b334a45a8ff 28 }
bogdanm 0:9b334a45a8ff 29
bogdanm 0:9b334a45a8ff 30 #if defined(TARGET_KL43Z)
bogdanm 0:9b334a45a8ff 31
bogdanm 0:9b334a45a8ff 32 static inline uint32_t extosc_frequency(void) {
bogdanm 0:9b334a45a8ff 33 return CPU_XTAL_CLK_HZ;
bogdanm 0:9b334a45a8ff 34 }
bogdanm 0:9b334a45a8ff 35
bogdanm 0:9b334a45a8ff 36 static inline uint32_t fastirc_frequency(void) {
bogdanm 0:9b334a45a8ff 37 return CPU_INT_FAST_CLK_HZ;
bogdanm 0:9b334a45a8ff 38 }
bogdanm 0:9b334a45a8ff 39
bogdanm 0:9b334a45a8ff 40 static inline uint32_t mcgirc_frequency(void) {
bogdanm 0:9b334a45a8ff 41 uint32_t mcgirc_clock = 0;
bogdanm 0:9b334a45a8ff 42
bogdanm 0:9b334a45a8ff 43 if (MCG->C1 & MCG_C1_IREFSTEN_MASK) {
bogdanm 0:9b334a45a8ff 44 mcgirc_clock = (MCG->C2 & MCG_C2_IRCS_MASK) ? 8000000u : 2000000u;
bogdanm 0:9b334a45a8ff 45 mcgirc_clock /= 1u + ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT);
bogdanm 0:9b334a45a8ff 46 mcgirc_clock /= 1u + (MCG->MC & MCG_MC_LIRC_DIV2_MASK);
bogdanm 0:9b334a45a8ff 47 }
bogdanm 0:9b334a45a8ff 48
bogdanm 0:9b334a45a8ff 49 return mcgirc_clock;
bogdanm 0:9b334a45a8ff 50 }
bogdanm 0:9b334a45a8ff 51
bogdanm 0:9b334a45a8ff 52 #else
bogdanm 0:9b334a45a8ff 53
bogdanm 0:9b334a45a8ff 54 //Get external oscillator (crystal) frequency
bogdanm 0:9b334a45a8ff 55 static uint32_t extosc_frequency(void) {
bogdanm 0:9b334a45a8ff 56 uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT));
bogdanm 0:9b334a45a8ff 57
bogdanm 0:9b334a45a8ff 58 if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(2)) //MCG clock = external reference clock
bogdanm 0:9b334a45a8ff 59 return MCGClock;
bogdanm 0:9b334a45a8ff 60
bogdanm 0:9b334a45a8ff 61 uint32_t divider, multiplier;
bogdanm 0:9b334a45a8ff 62 #ifdef MCG_C5_PLLCLKEN0_MASK //PLL available
bogdanm 0:9b334a45a8ff 63 if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0)) { //PLL/FLL is selected
bogdanm 0:9b334a45a8ff 64 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { //FLL is selected
bogdanm 0:9b334a45a8ff 65 #endif
bogdanm 0:9b334a45a8ff 66 if ((MCG->S & MCG_S_IREFST_MASK) == 0x0u) { //FLL uses external reference
bogdanm 0:9b334a45a8ff 67 divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
bogdanm 0:9b334a45a8ff 68 if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u)
bogdanm 0:9b334a45a8ff 69 divider <<= 5u;
bogdanm 0:9b334a45a8ff 70 /* Select correct multiplier to calculate the MCG output clock */
bogdanm 0:9b334a45a8ff 71 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
bogdanm 0:9b334a45a8ff 72 case 0x0u:
bogdanm 0:9b334a45a8ff 73 multiplier = 640u;
bogdanm 0:9b334a45a8ff 74 break;
bogdanm 0:9b334a45a8ff 75 case 0x20u:
bogdanm 0:9b334a45a8ff 76 multiplier = 1280u;
bogdanm 0:9b334a45a8ff 77 break;
bogdanm 0:9b334a45a8ff 78 case 0x40u:
bogdanm 0:9b334a45a8ff 79 multiplier = 1920u;
bogdanm 0:9b334a45a8ff 80 break;
bogdanm 0:9b334a45a8ff 81 case 0x60u:
bogdanm 0:9b334a45a8ff 82 multiplier = 2560u;
bogdanm 0:9b334a45a8ff 83 break;
bogdanm 0:9b334a45a8ff 84 case 0x80u:
bogdanm 0:9b334a45a8ff 85 multiplier = 732u;
bogdanm 0:9b334a45a8ff 86 break;
bogdanm 0:9b334a45a8ff 87 case 0xA0u:
bogdanm 0:9b334a45a8ff 88 multiplier = 1464u;
bogdanm 0:9b334a45a8ff 89 break;
bogdanm 0:9b334a45a8ff 90 case 0xC0u:
bogdanm 0:9b334a45a8ff 91 multiplier = 2197u;
bogdanm 0:9b334a45a8ff 92 break;
bogdanm 0:9b334a45a8ff 93 case 0xE0u:
bogdanm 0:9b334a45a8ff 94 default:
bogdanm 0:9b334a45a8ff 95 multiplier = 2929u;
bogdanm 0:9b334a45a8ff 96 break;
bogdanm 0:9b334a45a8ff 97 }
bogdanm 0:9b334a45a8ff 98
bogdanm 0:9b334a45a8ff 99 return MCGClock * divider / multiplier;
bogdanm 0:9b334a45a8ff 100 }
bogdanm 0:9b334a45a8ff 101 #ifdef MCG_C5_PLLCLKEN0_MASK
bogdanm 0:9b334a45a8ff 102 } else { //PLL is selected
bogdanm 0:9b334a45a8ff 103 divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
bogdanm 0:9b334a45a8ff 104 multiplier = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
bogdanm 0:9b334a45a8ff 105 return MCGClock * divider / multiplier;
bogdanm 0:9b334a45a8ff 106 }
bogdanm 0:9b334a45a8ff 107 }
bogdanm 0:9b334a45a8ff 108 #endif
bogdanm 0:9b334a45a8ff 109
bogdanm 0:9b334a45a8ff 110 //In all other cases either there is no crystal or we cannot determine it
bogdanm 0:9b334a45a8ff 111 //For example when the FLL is running on the internal reference, and there is also an
bogdanm 0:9b334a45a8ff 112 //external crystal. However these are unlikely situations
bogdanm 0:9b334a45a8ff 113 return 0;
bogdanm 0:9b334a45a8ff 114 }
bogdanm 0:9b334a45a8ff 115
bogdanm 0:9b334a45a8ff 116 //Get MCG PLL/2 or FLL frequency, depending on which one is active, sets PLLFLLSEL bit
bogdanm 0:9b334a45a8ff 117 static uint32_t mcgpllfll_frequency(void) {
bogdanm 0:9b334a45a8ff 118 if ((MCG->C1 & MCG_C1_CLKS_MASK) != MCG_C1_CLKS(0)) //PLL/FLL is not selected
bogdanm 0:9b334a45a8ff 119 return 0;
bogdanm 0:9b334a45a8ff 120
bogdanm 0:9b334a45a8ff 121 uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT));
bogdanm 0:9b334a45a8ff 122 #ifdef MCG_C5_PLLCLKEN0_MASK
bogdanm 0:9b334a45a8ff 123 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { //FLL is selected
bogdanm 0:9b334a45a8ff 124 SIM->SOPT2 &= ~SIM_SOPT2_PLLFLLSEL_MASK; //MCG peripheral clock is FLL output
bogdanm 0:9b334a45a8ff 125 #endif
bogdanm 0:9b334a45a8ff 126 return MCGClock;
bogdanm 0:9b334a45a8ff 127 #ifdef MCG_C5_PLLCLKEN0_MASK
bogdanm 0:9b334a45a8ff 128 } else { //PLL is selected
bogdanm 0:9b334a45a8ff 129 SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; //MCG peripheral clock is PLL output
bogdanm 0:9b334a45a8ff 130 return (MCGClock >> 1);
bogdanm 0:9b334a45a8ff 131 }
bogdanm 0:9b334a45a8ff 132 #endif
bogdanm 0:9b334a45a8ff 133
bogdanm 0:9b334a45a8ff 134 //It is possible the SystemCoreClock isn't running on the PLL, and the PLL is still active
bogdanm 0:9b334a45a8ff 135 //for the peripherals, this is however an unlikely setup
bogdanm 0:9b334a45a8ff 136 }
bogdanm 0:9b334a45a8ff 137
bogdanm 0:9b334a45a8ff 138 #endif
bogdanm 0:9b334a45a8ff 139
bogdanm 0:9b334a45a8ff 140 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 141 }
bogdanm 0:9b334a45a8ff 142 #endif
bogdanm 0:9b334a45a8ff 143
bogdanm 0:9b334a45a8ff 144 #endif