added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Initial commit on mbed-dev

Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /*
bogdanm 0:9b334a45a8ff 2 ** ###################################################################
bogdanm 0:9b334a45a8ff 3 ** Processors: MKL46Z256VLH4
bogdanm 0:9b334a45a8ff 4 ** MKL46Z128VLH4
bogdanm 0:9b334a45a8ff 5 ** MKL46Z256VLL4
bogdanm 0:9b334a45a8ff 6 ** MKL46Z128VLL4
bogdanm 0:9b334a45a8ff 7 ** MKL46Z256VMC4
bogdanm 0:9b334a45a8ff 8 ** MKL46Z128VMC4
bogdanm 0:9b334a45a8ff 9 **
bogdanm 0:9b334a45a8ff 10 ** Compilers: ARM Compiler
bogdanm 0:9b334a45a8ff 11 ** Freescale C/C++ for Embedded ARM
bogdanm 0:9b334a45a8ff 12 ** GNU C Compiler
bogdanm 0:9b334a45a8ff 13 ** IAR ANSI C/C++ Compiler for ARM
bogdanm 0:9b334a45a8ff 14 **
bogdanm 0:9b334a45a8ff 15 ** Reference manual: KL46P121M48SF4RM, Rev.2, Dec 2012
bogdanm 0:9b334a45a8ff 16 ** Version: rev. 2.2, 2013-04-12
bogdanm 0:9b334a45a8ff 17 **
bogdanm 0:9b334a45a8ff 18 ** Abstract:
bogdanm 0:9b334a45a8ff 19 ** CMSIS Peripheral Access Layer for MKL46Z4
bogdanm 0:9b334a45a8ff 20 **
bogdanm 0:9b334a45a8ff 21 ** Copyright: 1997 - 2013 Freescale, Inc. All Rights Reserved.
bogdanm 0:9b334a45a8ff 22 **
bogdanm 0:9b334a45a8ff 23 ** http: www.freescale.com
bogdanm 0:9b334a45a8ff 24 ** mail: support@freescale.com
bogdanm 0:9b334a45a8ff 25 **
bogdanm 0:9b334a45a8ff 26 ** Revisions:
bogdanm 0:9b334a45a8ff 27 ** - rev. 1.0 (2012-10-16)
bogdanm 0:9b334a45a8ff 28 ** Initial version.
bogdanm 0:9b334a45a8ff 29 ** - rev. 2.0 (2012-12-12)
bogdanm 0:9b334a45a8ff 30 ** Update to reference manual rev. 1.
bogdanm 0:9b334a45a8ff 31 ** - rev. 2.1 (2013-04-05)
bogdanm 0:9b334a45a8ff 32 ** Changed start of doxygen comment.
bogdanm 0:9b334a45a8ff 33 ** - rev. 2.2 (2013-04-12)
bogdanm 0:9b334a45a8ff 34 ** SystemInit function fixed for clock configuration 1.
bogdanm 0:9b334a45a8ff 35 ** Name of the interrupt num. 31 updated to reflect proper function.
bogdanm 0:9b334a45a8ff 36 **
bogdanm 0:9b334a45a8ff 37 ** ###################################################################
bogdanm 0:9b334a45a8ff 38 */
bogdanm 0:9b334a45a8ff 39
bogdanm 0:9b334a45a8ff 40 /*!
bogdanm 0:9b334a45a8ff 41 * @file MKL46Z4.h
bogdanm 0:9b334a45a8ff 42 * @version 2.2
bogdanm 0:9b334a45a8ff 43 * @date 2013-04-12
bogdanm 0:9b334a45a8ff 44 * @brief CMSIS Peripheral Access Layer for MKL46Z4
bogdanm 0:9b334a45a8ff 45 *
bogdanm 0:9b334a45a8ff 46 * CMSIS Peripheral Access Layer for MKL46Z4
bogdanm 0:9b334a45a8ff 47 */
bogdanm 0:9b334a45a8ff 48
bogdanm 0:9b334a45a8ff 49 #if !defined(MKL46Z4_H_)
bogdanm 0:9b334a45a8ff 50 #define MKL46Z4_H_ /**< Symbol preventing repeated inclusion */
bogdanm 0:9b334a45a8ff 51
bogdanm 0:9b334a45a8ff 52 /** Memory map major version (memory maps with equal major version number are
bogdanm 0:9b334a45a8ff 53 * compatible) */
bogdanm 0:9b334a45a8ff 54 #define MCU_MEM_MAP_VERSION 0x0200u
bogdanm 0:9b334a45a8ff 55 /** Memory map minor version */
bogdanm 0:9b334a45a8ff 56 #define MCU_MEM_MAP_VERSION_MINOR 0x0002u
bogdanm 0:9b334a45a8ff 57
bogdanm 0:9b334a45a8ff 58
bogdanm 0:9b334a45a8ff 59 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 60 -- Interrupt vector numbers
bogdanm 0:9b334a45a8ff 61 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 62
bogdanm 0:9b334a45a8ff 63 /*!
bogdanm 0:9b334a45a8ff 64 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
bogdanm 0:9b334a45a8ff 65 * @{
bogdanm 0:9b334a45a8ff 66 */
bogdanm 0:9b334a45a8ff 67
bogdanm 0:9b334a45a8ff 68 /** Interrupt Number Definitions */
bogdanm 0:9b334a45a8ff 69 typedef enum IRQn {
bogdanm 0:9b334a45a8ff 70 /* Core interrupts */
bogdanm 0:9b334a45a8ff 71 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
bogdanm 0:9b334a45a8ff 72 HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
bogdanm 0:9b334a45a8ff 73 SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
bogdanm 0:9b334a45a8ff 74 PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
bogdanm 0:9b334a45a8ff 75 SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
bogdanm 0:9b334a45a8ff 76
bogdanm 0:9b334a45a8ff 77 /* Device specific interrupts */
bogdanm 0:9b334a45a8ff 78 DMA0_IRQn = 0, /**< DMA channel 0 transfer complete/error interrupt */
bogdanm 0:9b334a45a8ff 79 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete/error interrupt */
bogdanm 0:9b334a45a8ff 80 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete/error interrupt */
bogdanm 0:9b334a45a8ff 81 DMA3_IRQn = 3, /**< DMA channel 3 transfer complete/error interrupt */
bogdanm 0:9b334a45a8ff 82 Reserved20_IRQn = 4, /**< Reserved interrupt 20 */
bogdanm 0:9b334a45a8ff 83 FTFA_IRQn = 5, /**< FTFA command complete/read collision interrupt */
bogdanm 0:9b334a45a8ff 84 LVD_LVW_IRQn = 6, /**< Low Voltage Detect, Low Voltage Warning */
bogdanm 0:9b334a45a8ff 85 LLW_IRQn = 7, /**< Low Leakage Wakeup */
bogdanm 0:9b334a45a8ff 86 I2C0_IRQn = 8, /**< I2C0 interrupt */
bogdanm 0:9b334a45a8ff 87 I2C1_IRQn = 9, /**< I2C0 interrupt 25 */
bogdanm 0:9b334a45a8ff 88 SPI0_IRQn = 10, /**< SPI0 interrupt */
bogdanm 0:9b334a45a8ff 89 SPI1_IRQn = 11, /**< SPI1 interrupt */
bogdanm 0:9b334a45a8ff 90 UART0_IRQn = 12, /**< UART0 status/error interrupt */
bogdanm 0:9b334a45a8ff 91 UART1_IRQn = 13, /**< UART1 status/error interrupt */
bogdanm 0:9b334a45a8ff 92 UART2_IRQn = 14, /**< UART2 status/error interrupt */
bogdanm 0:9b334a45a8ff 93 ADC0_IRQn = 15, /**< ADC0 interrupt */
bogdanm 0:9b334a45a8ff 94 CMP0_IRQn = 16, /**< CMP0 interrupt */
bogdanm 0:9b334a45a8ff 95 TPM0_IRQn = 17, /**< TPM0 fault, overflow and channels interrupt */
bogdanm 0:9b334a45a8ff 96 TPM1_IRQn = 18, /**< TPM1 fault, overflow and channels interrupt */
bogdanm 0:9b334a45a8ff 97 TPM2_IRQn = 19, /**< TPM2 fault, overflow and channels interrupt */
bogdanm 0:9b334a45a8ff 98 RTC_IRQn = 20, /**< RTC interrupt */
bogdanm 0:9b334a45a8ff 99 RTC_Seconds_IRQn = 21, /**< RTC seconds interrupt */
bogdanm 0:9b334a45a8ff 100 PIT_IRQn = 22, /**< PIT timer interrupt */
bogdanm 0:9b334a45a8ff 101 I2S0_IRQn = 23, /**< I2S0 transmit interrupt */
bogdanm 0:9b334a45a8ff 102 USB0_IRQn = 24, /**< USB0 interrupt */
bogdanm 0:9b334a45a8ff 103 DAC0_IRQn = 25, /**< DAC0 interrupt */
bogdanm 0:9b334a45a8ff 104 TSI0_IRQn = 26, /**< TSI0 interrupt */
bogdanm 0:9b334a45a8ff 105 MCG_IRQn = 27, /**< MCG interrupt */
bogdanm 0:9b334a45a8ff 106 LPTimer_IRQn = 28, /**< LPTimer interrupt */
bogdanm 0:9b334a45a8ff 107 LCD_IRQn = 29, /**< Segment LCD Interrupt */
bogdanm 0:9b334a45a8ff 108 PORTA_IRQn = 30, /**< Port A interrupt */
bogdanm 0:9b334a45a8ff 109 PORTC_PORTD_IRQn = 31 /**< Port C and port D interrupt */
bogdanm 0:9b334a45a8ff 110 } IRQn_Type;
bogdanm 0:9b334a45a8ff 111
bogdanm 0:9b334a45a8ff 112 /*!
bogdanm 0:9b334a45a8ff 113 * @}
bogdanm 0:9b334a45a8ff 114 */ /* end of group Interrupt_vector_numbers */
bogdanm 0:9b334a45a8ff 115
bogdanm 0:9b334a45a8ff 116
bogdanm 0:9b334a45a8ff 117 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 118 -- Cortex M0 Core Configuration
bogdanm 0:9b334a45a8ff 119 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 120
bogdanm 0:9b334a45a8ff 121 /*!
bogdanm 0:9b334a45a8ff 122 * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
bogdanm 0:9b334a45a8ff 123 * @{
bogdanm 0:9b334a45a8ff 124 */
bogdanm 0:9b334a45a8ff 125
bogdanm 0:9b334a45a8ff 126 #define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */
bogdanm 0:9b334a45a8ff 127 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
bogdanm 0:9b334a45a8ff 128 #define __VTOR_PRESENT 1 /**< Defines if an MPU is present or not */
bogdanm 0:9b334a45a8ff 129 #define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
bogdanm 0:9b334a45a8ff 130 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
bogdanm 0:9b334a45a8ff 131
bogdanm 0:9b334a45a8ff 132 #include "core_cm0plus.h" /* Core Peripheral Access Layer */
bogdanm 0:9b334a45a8ff 133 #include "system_MKL46Z4.h" /* Device specific configuration file */
bogdanm 0:9b334a45a8ff 134
bogdanm 0:9b334a45a8ff 135 /*!
bogdanm 0:9b334a45a8ff 136 * @}
bogdanm 0:9b334a45a8ff 137 */ /* end of group Cortex_Core_Configuration */
bogdanm 0:9b334a45a8ff 138
bogdanm 0:9b334a45a8ff 139
bogdanm 0:9b334a45a8ff 140 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 141 -- Device Peripheral Access Layer
bogdanm 0:9b334a45a8ff 142 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 143
bogdanm 0:9b334a45a8ff 144 /*!
bogdanm 0:9b334a45a8ff 145 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
bogdanm 0:9b334a45a8ff 146 * @{
bogdanm 0:9b334a45a8ff 147 */
bogdanm 0:9b334a45a8ff 148
bogdanm 0:9b334a45a8ff 149
bogdanm 0:9b334a45a8ff 150 /*
bogdanm 0:9b334a45a8ff 151 ** Start of section using anonymous unions
bogdanm 0:9b334a45a8ff 152 */
bogdanm 0:9b334a45a8ff 153
bogdanm 0:9b334a45a8ff 154 #if defined(__ARMCC_VERSION)
bogdanm 0:9b334a45a8ff 155 #pragma push
bogdanm 0:9b334a45a8ff 156 #pragma anon_unions
bogdanm 0:9b334a45a8ff 157 #elif defined(__CWCC__)
bogdanm 0:9b334a45a8ff 158 #pragma push
bogdanm 0:9b334a45a8ff 159 #pragma cpp_extensions on
bogdanm 0:9b334a45a8ff 160 #elif defined(__GNUC__)
bogdanm 0:9b334a45a8ff 161 /* anonymous unions are enabled by default */
bogdanm 0:9b334a45a8ff 162 #elif defined(__IAR_SYSTEMS_ICC__)
bogdanm 0:9b334a45a8ff 163 #pragma language=extended
bogdanm 0:9b334a45a8ff 164 #else
bogdanm 0:9b334a45a8ff 165 #error Not supported compiler type
bogdanm 0:9b334a45a8ff 166 #endif
bogdanm 0:9b334a45a8ff 167
bogdanm 0:9b334a45a8ff 168 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 169 -- ADC Peripheral Access Layer
bogdanm 0:9b334a45a8ff 170 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 171
bogdanm 0:9b334a45a8ff 172 /*!
bogdanm 0:9b334a45a8ff 173 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
bogdanm 0:9b334a45a8ff 174 * @{
bogdanm 0:9b334a45a8ff 175 */
bogdanm 0:9b334a45a8ff 176
bogdanm 0:9b334a45a8ff 177 /** ADC - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 178 typedef struct {
bogdanm 0:9b334a45a8ff 179 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
bogdanm 0:9b334a45a8ff 180 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
bogdanm 0:9b334a45a8ff 181 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
bogdanm 0:9b334a45a8ff 182 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
bogdanm 0:9b334a45a8ff 183 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
bogdanm 0:9b334a45a8ff 184 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
bogdanm 0:9b334a45a8ff 185 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
bogdanm 0:9b334a45a8ff 186 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
bogdanm 0:9b334a45a8ff 187 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
bogdanm 0:9b334a45a8ff 188 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
bogdanm 0:9b334a45a8ff 189 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
bogdanm 0:9b334a45a8ff 190 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
bogdanm 0:9b334a45a8ff 191 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
bogdanm 0:9b334a45a8ff 192 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
bogdanm 0:9b334a45a8ff 193 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
bogdanm 0:9b334a45a8ff 194 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
bogdanm 0:9b334a45a8ff 195 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
bogdanm 0:9b334a45a8ff 196 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
bogdanm 0:9b334a45a8ff 197 uint8_t RESERVED_0[4];
bogdanm 0:9b334a45a8ff 198 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
bogdanm 0:9b334a45a8ff 199 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
bogdanm 0:9b334a45a8ff 200 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
bogdanm 0:9b334a45a8ff 201 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
bogdanm 0:9b334a45a8ff 202 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
bogdanm 0:9b334a45a8ff 203 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
bogdanm 0:9b334a45a8ff 204 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
bogdanm 0:9b334a45a8ff 205 } ADC_Type;
bogdanm 0:9b334a45a8ff 206
bogdanm 0:9b334a45a8ff 207 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 208 -- ADC Register Masks
bogdanm 0:9b334a45a8ff 209 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 210
bogdanm 0:9b334a45a8ff 211 /*!
bogdanm 0:9b334a45a8ff 212 * @addtogroup ADC_Register_Masks ADC Register Masks
bogdanm 0:9b334a45a8ff 213 * @{
bogdanm 0:9b334a45a8ff 214 */
bogdanm 0:9b334a45a8ff 215
bogdanm 0:9b334a45a8ff 216 /* SC1 Bit Fields */
bogdanm 0:9b334a45a8ff 217 #define ADC_SC1_ADCH_MASK 0x1Fu
bogdanm 0:9b334a45a8ff 218 #define ADC_SC1_ADCH_SHIFT 0
bogdanm 0:9b334a45a8ff 219 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
bogdanm 0:9b334a45a8ff 220 #define ADC_SC1_DIFF_MASK 0x20u
bogdanm 0:9b334a45a8ff 221 #define ADC_SC1_DIFF_SHIFT 5
bogdanm 0:9b334a45a8ff 222 #define ADC_SC1_AIEN_MASK 0x40u
bogdanm 0:9b334a45a8ff 223 #define ADC_SC1_AIEN_SHIFT 6
bogdanm 0:9b334a45a8ff 224 #define ADC_SC1_COCO_MASK 0x80u
bogdanm 0:9b334a45a8ff 225 #define ADC_SC1_COCO_SHIFT 7
bogdanm 0:9b334a45a8ff 226 /* CFG1 Bit Fields */
bogdanm 0:9b334a45a8ff 227 #define ADC_CFG1_ADICLK_MASK 0x3u
bogdanm 0:9b334a45a8ff 228 #define ADC_CFG1_ADICLK_SHIFT 0
bogdanm 0:9b334a45a8ff 229 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
bogdanm 0:9b334a45a8ff 230 #define ADC_CFG1_MODE_MASK 0xCu
bogdanm 0:9b334a45a8ff 231 #define ADC_CFG1_MODE_SHIFT 2
bogdanm 0:9b334a45a8ff 232 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
bogdanm 0:9b334a45a8ff 233 #define ADC_CFG1_ADLSMP_MASK 0x10u
bogdanm 0:9b334a45a8ff 234 #define ADC_CFG1_ADLSMP_SHIFT 4
bogdanm 0:9b334a45a8ff 235 #define ADC_CFG1_ADIV_MASK 0x60u
bogdanm 0:9b334a45a8ff 236 #define ADC_CFG1_ADIV_SHIFT 5
bogdanm 0:9b334a45a8ff 237 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
bogdanm 0:9b334a45a8ff 238 #define ADC_CFG1_ADLPC_MASK 0x80u
bogdanm 0:9b334a45a8ff 239 #define ADC_CFG1_ADLPC_SHIFT 7
bogdanm 0:9b334a45a8ff 240 /* CFG2 Bit Fields */
bogdanm 0:9b334a45a8ff 241 #define ADC_CFG2_ADLSTS_MASK 0x3u
bogdanm 0:9b334a45a8ff 242 #define ADC_CFG2_ADLSTS_SHIFT 0
bogdanm 0:9b334a45a8ff 243 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
bogdanm 0:9b334a45a8ff 244 #define ADC_CFG2_ADHSC_MASK 0x4u
bogdanm 0:9b334a45a8ff 245 #define ADC_CFG2_ADHSC_SHIFT 2
bogdanm 0:9b334a45a8ff 246 #define ADC_CFG2_ADACKEN_MASK 0x8u
bogdanm 0:9b334a45a8ff 247 #define ADC_CFG2_ADACKEN_SHIFT 3
bogdanm 0:9b334a45a8ff 248 #define ADC_CFG2_MUXSEL_MASK 0x10u
bogdanm 0:9b334a45a8ff 249 #define ADC_CFG2_MUXSEL_SHIFT 4
bogdanm 0:9b334a45a8ff 250 /* R Bit Fields */
bogdanm 0:9b334a45a8ff 251 #define ADC_R_D_MASK 0xFFFFu
bogdanm 0:9b334a45a8ff 252 #define ADC_R_D_SHIFT 0
bogdanm 0:9b334a45a8ff 253 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
bogdanm 0:9b334a45a8ff 254 /* CV1 Bit Fields */
bogdanm 0:9b334a45a8ff 255 #define ADC_CV1_CV_MASK 0xFFFFu
bogdanm 0:9b334a45a8ff 256 #define ADC_CV1_CV_SHIFT 0
bogdanm 0:9b334a45a8ff 257 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
bogdanm 0:9b334a45a8ff 258 /* CV2 Bit Fields */
bogdanm 0:9b334a45a8ff 259 #define ADC_CV2_CV_MASK 0xFFFFu
bogdanm 0:9b334a45a8ff 260 #define ADC_CV2_CV_SHIFT 0
bogdanm 0:9b334a45a8ff 261 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
bogdanm 0:9b334a45a8ff 262 /* SC2 Bit Fields */
bogdanm 0:9b334a45a8ff 263 #define ADC_SC2_REFSEL_MASK 0x3u
bogdanm 0:9b334a45a8ff 264 #define ADC_SC2_REFSEL_SHIFT 0
bogdanm 0:9b334a45a8ff 265 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
bogdanm 0:9b334a45a8ff 266 #define ADC_SC2_DMAEN_MASK 0x4u
bogdanm 0:9b334a45a8ff 267 #define ADC_SC2_DMAEN_SHIFT 2
bogdanm 0:9b334a45a8ff 268 #define ADC_SC2_ACREN_MASK 0x8u
bogdanm 0:9b334a45a8ff 269 #define ADC_SC2_ACREN_SHIFT 3
bogdanm 0:9b334a45a8ff 270 #define ADC_SC2_ACFGT_MASK 0x10u
bogdanm 0:9b334a45a8ff 271 #define ADC_SC2_ACFGT_SHIFT 4
bogdanm 0:9b334a45a8ff 272 #define ADC_SC2_ACFE_MASK 0x20u
bogdanm 0:9b334a45a8ff 273 #define ADC_SC2_ACFE_SHIFT 5
bogdanm 0:9b334a45a8ff 274 #define ADC_SC2_ADTRG_MASK 0x40u
bogdanm 0:9b334a45a8ff 275 #define ADC_SC2_ADTRG_SHIFT 6
bogdanm 0:9b334a45a8ff 276 #define ADC_SC2_ADACT_MASK 0x80u
bogdanm 0:9b334a45a8ff 277 #define ADC_SC2_ADACT_SHIFT 7
bogdanm 0:9b334a45a8ff 278 /* SC3 Bit Fields */
bogdanm 0:9b334a45a8ff 279 #define ADC_SC3_AVGS_MASK 0x3u
bogdanm 0:9b334a45a8ff 280 #define ADC_SC3_AVGS_SHIFT 0
bogdanm 0:9b334a45a8ff 281 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
bogdanm 0:9b334a45a8ff 282 #define ADC_SC3_AVGE_MASK 0x4u
bogdanm 0:9b334a45a8ff 283 #define ADC_SC3_AVGE_SHIFT 2
bogdanm 0:9b334a45a8ff 284 #define ADC_SC3_ADCO_MASK 0x8u
bogdanm 0:9b334a45a8ff 285 #define ADC_SC3_ADCO_SHIFT 3
bogdanm 0:9b334a45a8ff 286 #define ADC_SC3_CALF_MASK 0x40u
bogdanm 0:9b334a45a8ff 287 #define ADC_SC3_CALF_SHIFT 6
bogdanm 0:9b334a45a8ff 288 #define ADC_SC3_CAL_MASK 0x80u
bogdanm 0:9b334a45a8ff 289 #define ADC_SC3_CAL_SHIFT 7
bogdanm 0:9b334a45a8ff 290 /* OFS Bit Fields */
bogdanm 0:9b334a45a8ff 291 #define ADC_OFS_OFS_MASK 0xFFFFu
bogdanm 0:9b334a45a8ff 292 #define ADC_OFS_OFS_SHIFT 0
bogdanm 0:9b334a45a8ff 293 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
bogdanm 0:9b334a45a8ff 294 /* PG Bit Fields */
bogdanm 0:9b334a45a8ff 295 #define ADC_PG_PG_MASK 0xFFFFu
bogdanm 0:9b334a45a8ff 296 #define ADC_PG_PG_SHIFT 0
bogdanm 0:9b334a45a8ff 297 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
bogdanm 0:9b334a45a8ff 298 /* MG Bit Fields */
bogdanm 0:9b334a45a8ff 299 #define ADC_MG_MG_MASK 0xFFFFu
bogdanm 0:9b334a45a8ff 300 #define ADC_MG_MG_SHIFT 0
bogdanm 0:9b334a45a8ff 301 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
bogdanm 0:9b334a45a8ff 302 /* CLPD Bit Fields */
bogdanm 0:9b334a45a8ff 303 #define ADC_CLPD_CLPD_MASK 0x3Fu
bogdanm 0:9b334a45a8ff 304 #define ADC_CLPD_CLPD_SHIFT 0
bogdanm 0:9b334a45a8ff 305 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
bogdanm 0:9b334a45a8ff 306 /* CLPS Bit Fields */
bogdanm 0:9b334a45a8ff 307 #define ADC_CLPS_CLPS_MASK 0x3Fu
bogdanm 0:9b334a45a8ff 308 #define ADC_CLPS_CLPS_SHIFT 0
bogdanm 0:9b334a45a8ff 309 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
bogdanm 0:9b334a45a8ff 310 /* CLP4 Bit Fields */
bogdanm 0:9b334a45a8ff 311 #define ADC_CLP4_CLP4_MASK 0x3FFu
bogdanm 0:9b334a45a8ff 312 #define ADC_CLP4_CLP4_SHIFT 0
bogdanm 0:9b334a45a8ff 313 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
bogdanm 0:9b334a45a8ff 314 /* CLP3 Bit Fields */
bogdanm 0:9b334a45a8ff 315 #define ADC_CLP3_CLP3_MASK 0x1FFu
bogdanm 0:9b334a45a8ff 316 #define ADC_CLP3_CLP3_SHIFT 0
bogdanm 0:9b334a45a8ff 317 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
bogdanm 0:9b334a45a8ff 318 /* CLP2 Bit Fields */
bogdanm 0:9b334a45a8ff 319 #define ADC_CLP2_CLP2_MASK 0xFFu
bogdanm 0:9b334a45a8ff 320 #define ADC_CLP2_CLP2_SHIFT 0
bogdanm 0:9b334a45a8ff 321 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
bogdanm 0:9b334a45a8ff 322 /* CLP1 Bit Fields */
bogdanm 0:9b334a45a8ff 323 #define ADC_CLP1_CLP1_MASK 0x7Fu
bogdanm 0:9b334a45a8ff 324 #define ADC_CLP1_CLP1_SHIFT 0
bogdanm 0:9b334a45a8ff 325 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
bogdanm 0:9b334a45a8ff 326 /* CLP0 Bit Fields */
bogdanm 0:9b334a45a8ff 327 #define ADC_CLP0_CLP0_MASK 0x3Fu
bogdanm 0:9b334a45a8ff 328 #define ADC_CLP0_CLP0_SHIFT 0
bogdanm 0:9b334a45a8ff 329 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
bogdanm 0:9b334a45a8ff 330 /* CLMD Bit Fields */
bogdanm 0:9b334a45a8ff 331 #define ADC_CLMD_CLMD_MASK 0x3Fu
bogdanm 0:9b334a45a8ff 332 #define ADC_CLMD_CLMD_SHIFT 0
bogdanm 0:9b334a45a8ff 333 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
bogdanm 0:9b334a45a8ff 334 /* CLMS Bit Fields */
bogdanm 0:9b334a45a8ff 335 #define ADC_CLMS_CLMS_MASK 0x3Fu
bogdanm 0:9b334a45a8ff 336 #define ADC_CLMS_CLMS_SHIFT 0
bogdanm 0:9b334a45a8ff 337 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
bogdanm 0:9b334a45a8ff 338 /* CLM4 Bit Fields */
bogdanm 0:9b334a45a8ff 339 #define ADC_CLM4_CLM4_MASK 0x3FFu
bogdanm 0:9b334a45a8ff 340 #define ADC_CLM4_CLM4_SHIFT 0
bogdanm 0:9b334a45a8ff 341 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
bogdanm 0:9b334a45a8ff 342 /* CLM3 Bit Fields */
bogdanm 0:9b334a45a8ff 343 #define ADC_CLM3_CLM3_MASK 0x1FFu
bogdanm 0:9b334a45a8ff 344 #define ADC_CLM3_CLM3_SHIFT 0
bogdanm 0:9b334a45a8ff 345 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
bogdanm 0:9b334a45a8ff 346 /* CLM2 Bit Fields */
bogdanm 0:9b334a45a8ff 347 #define ADC_CLM2_CLM2_MASK 0xFFu
bogdanm 0:9b334a45a8ff 348 #define ADC_CLM2_CLM2_SHIFT 0
bogdanm 0:9b334a45a8ff 349 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
bogdanm 0:9b334a45a8ff 350 /* CLM1 Bit Fields */
bogdanm 0:9b334a45a8ff 351 #define ADC_CLM1_CLM1_MASK 0x7Fu
bogdanm 0:9b334a45a8ff 352 #define ADC_CLM1_CLM1_SHIFT 0
bogdanm 0:9b334a45a8ff 353 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
bogdanm 0:9b334a45a8ff 354 /* CLM0 Bit Fields */
bogdanm 0:9b334a45a8ff 355 #define ADC_CLM0_CLM0_MASK 0x3Fu
bogdanm 0:9b334a45a8ff 356 #define ADC_CLM0_CLM0_SHIFT 0
bogdanm 0:9b334a45a8ff 357 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
bogdanm 0:9b334a45a8ff 358
bogdanm 0:9b334a45a8ff 359 /*!
bogdanm 0:9b334a45a8ff 360 * @}
bogdanm 0:9b334a45a8ff 361 */ /* end of group ADC_Register_Masks */
bogdanm 0:9b334a45a8ff 362
bogdanm 0:9b334a45a8ff 363
bogdanm 0:9b334a45a8ff 364 /* ADC - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 365 /** Peripheral ADC0 base address */
bogdanm 0:9b334a45a8ff 366 #define ADC0_BASE (0x4003B000u)
bogdanm 0:9b334a45a8ff 367 /** Peripheral ADC0 base pointer */
bogdanm 0:9b334a45a8ff 368 #define ADC0 ((ADC_Type *)ADC0_BASE)
bogdanm 0:9b334a45a8ff 369 /** Array initializer of ADC peripheral base pointers */
bogdanm 0:9b334a45a8ff 370 #define ADC_BASES { ADC0 }
bogdanm 0:9b334a45a8ff 371
bogdanm 0:9b334a45a8ff 372 /*!
bogdanm 0:9b334a45a8ff 373 * @}
bogdanm 0:9b334a45a8ff 374 */ /* end of group ADC_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 375
bogdanm 0:9b334a45a8ff 376
bogdanm 0:9b334a45a8ff 377 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 378 -- CMP Peripheral Access Layer
bogdanm 0:9b334a45a8ff 379 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 380
bogdanm 0:9b334a45a8ff 381 /*!
bogdanm 0:9b334a45a8ff 382 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
bogdanm 0:9b334a45a8ff 383 * @{
bogdanm 0:9b334a45a8ff 384 */
bogdanm 0:9b334a45a8ff 385
bogdanm 0:9b334a45a8ff 386 /** CMP - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 387 typedef struct {
bogdanm 0:9b334a45a8ff 388 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
bogdanm 0:9b334a45a8ff 389 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
bogdanm 0:9b334a45a8ff 390 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
bogdanm 0:9b334a45a8ff 391 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
bogdanm 0:9b334a45a8ff 392 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
bogdanm 0:9b334a45a8ff 393 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
bogdanm 0:9b334a45a8ff 394 } CMP_Type;
bogdanm 0:9b334a45a8ff 395
bogdanm 0:9b334a45a8ff 396 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 397 -- CMP Register Masks
bogdanm 0:9b334a45a8ff 398 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 399
bogdanm 0:9b334a45a8ff 400 /*!
bogdanm 0:9b334a45a8ff 401 * @addtogroup CMP_Register_Masks CMP Register Masks
bogdanm 0:9b334a45a8ff 402 * @{
bogdanm 0:9b334a45a8ff 403 */
bogdanm 0:9b334a45a8ff 404
bogdanm 0:9b334a45a8ff 405 /* CR0 Bit Fields */
bogdanm 0:9b334a45a8ff 406 #define CMP_CR0_HYSTCTR_MASK 0x3u
bogdanm 0:9b334a45a8ff 407 #define CMP_CR0_HYSTCTR_SHIFT 0
bogdanm 0:9b334a45a8ff 408 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
bogdanm 0:9b334a45a8ff 409 #define CMP_CR0_FILTER_CNT_MASK 0x70u
bogdanm 0:9b334a45a8ff 410 #define CMP_CR0_FILTER_CNT_SHIFT 4
bogdanm 0:9b334a45a8ff 411 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
bogdanm 0:9b334a45a8ff 412 /* CR1 Bit Fields */
bogdanm 0:9b334a45a8ff 413 #define CMP_CR1_EN_MASK 0x1u
bogdanm 0:9b334a45a8ff 414 #define CMP_CR1_EN_SHIFT 0
bogdanm 0:9b334a45a8ff 415 #define CMP_CR1_OPE_MASK 0x2u
bogdanm 0:9b334a45a8ff 416 #define CMP_CR1_OPE_SHIFT 1
bogdanm 0:9b334a45a8ff 417 #define CMP_CR1_COS_MASK 0x4u
bogdanm 0:9b334a45a8ff 418 #define CMP_CR1_COS_SHIFT 2
bogdanm 0:9b334a45a8ff 419 #define CMP_CR1_INV_MASK 0x8u
bogdanm 0:9b334a45a8ff 420 #define CMP_CR1_INV_SHIFT 3
bogdanm 0:9b334a45a8ff 421 #define CMP_CR1_PMODE_MASK 0x10u
bogdanm 0:9b334a45a8ff 422 #define CMP_CR1_PMODE_SHIFT 4
bogdanm 0:9b334a45a8ff 423 #define CMP_CR1_TRIGM_MASK 0x20u
bogdanm 0:9b334a45a8ff 424 #define CMP_CR1_TRIGM_SHIFT 5
bogdanm 0:9b334a45a8ff 425 #define CMP_CR1_WE_MASK 0x40u
bogdanm 0:9b334a45a8ff 426 #define CMP_CR1_WE_SHIFT 6
bogdanm 0:9b334a45a8ff 427 #define CMP_CR1_SE_MASK 0x80u
bogdanm 0:9b334a45a8ff 428 #define CMP_CR1_SE_SHIFT 7
bogdanm 0:9b334a45a8ff 429 /* FPR Bit Fields */
bogdanm 0:9b334a45a8ff 430 #define CMP_FPR_FILT_PER_MASK 0xFFu
bogdanm 0:9b334a45a8ff 431 #define CMP_FPR_FILT_PER_SHIFT 0
bogdanm 0:9b334a45a8ff 432 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
bogdanm 0:9b334a45a8ff 433 /* SCR Bit Fields */
bogdanm 0:9b334a45a8ff 434 #define CMP_SCR_COUT_MASK 0x1u
bogdanm 0:9b334a45a8ff 435 #define CMP_SCR_COUT_SHIFT 0
bogdanm 0:9b334a45a8ff 436 #define CMP_SCR_CFF_MASK 0x2u
bogdanm 0:9b334a45a8ff 437 #define CMP_SCR_CFF_SHIFT 1
bogdanm 0:9b334a45a8ff 438 #define CMP_SCR_CFR_MASK 0x4u
bogdanm 0:9b334a45a8ff 439 #define CMP_SCR_CFR_SHIFT 2
bogdanm 0:9b334a45a8ff 440 #define CMP_SCR_IEF_MASK 0x8u
bogdanm 0:9b334a45a8ff 441 #define CMP_SCR_IEF_SHIFT 3
bogdanm 0:9b334a45a8ff 442 #define CMP_SCR_IER_MASK 0x10u
bogdanm 0:9b334a45a8ff 443 #define CMP_SCR_IER_SHIFT 4
bogdanm 0:9b334a45a8ff 444 #define CMP_SCR_DMAEN_MASK 0x40u
bogdanm 0:9b334a45a8ff 445 #define CMP_SCR_DMAEN_SHIFT 6
bogdanm 0:9b334a45a8ff 446 /* DACCR Bit Fields */
bogdanm 0:9b334a45a8ff 447 #define CMP_DACCR_VOSEL_MASK 0x3Fu
bogdanm 0:9b334a45a8ff 448 #define CMP_DACCR_VOSEL_SHIFT 0
bogdanm 0:9b334a45a8ff 449 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
bogdanm 0:9b334a45a8ff 450 #define CMP_DACCR_VRSEL_MASK 0x40u
bogdanm 0:9b334a45a8ff 451 #define CMP_DACCR_VRSEL_SHIFT 6
bogdanm 0:9b334a45a8ff 452 #define CMP_DACCR_DACEN_MASK 0x80u
bogdanm 0:9b334a45a8ff 453 #define CMP_DACCR_DACEN_SHIFT 7
bogdanm 0:9b334a45a8ff 454 /* MUXCR Bit Fields */
bogdanm 0:9b334a45a8ff 455 #define CMP_MUXCR_MSEL_MASK 0x7u
bogdanm 0:9b334a45a8ff 456 #define CMP_MUXCR_MSEL_SHIFT 0
bogdanm 0:9b334a45a8ff 457 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
bogdanm 0:9b334a45a8ff 458 #define CMP_MUXCR_PSEL_MASK 0x38u
bogdanm 0:9b334a45a8ff 459 #define CMP_MUXCR_PSEL_SHIFT 3
bogdanm 0:9b334a45a8ff 460 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
bogdanm 0:9b334a45a8ff 461 #define CMP_MUXCR_PSTM_MASK 0x80u
bogdanm 0:9b334a45a8ff 462 #define CMP_MUXCR_PSTM_SHIFT 7
bogdanm 0:9b334a45a8ff 463
bogdanm 0:9b334a45a8ff 464 /*!
bogdanm 0:9b334a45a8ff 465 * @}
bogdanm 0:9b334a45a8ff 466 */ /* end of group CMP_Register_Masks */
bogdanm 0:9b334a45a8ff 467
bogdanm 0:9b334a45a8ff 468
bogdanm 0:9b334a45a8ff 469 /* CMP - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 470 /** Peripheral CMP0 base address */
bogdanm 0:9b334a45a8ff 471 #define CMP0_BASE (0x40073000u)
bogdanm 0:9b334a45a8ff 472 /** Peripheral CMP0 base pointer */
bogdanm 0:9b334a45a8ff 473 #define CMP0 ((CMP_Type *)CMP0_BASE)
bogdanm 0:9b334a45a8ff 474 /** Array initializer of CMP peripheral base pointers */
bogdanm 0:9b334a45a8ff 475 #define CMP_BASES { CMP0 }
bogdanm 0:9b334a45a8ff 476
bogdanm 0:9b334a45a8ff 477 /*!
bogdanm 0:9b334a45a8ff 478 * @}
bogdanm 0:9b334a45a8ff 479 */ /* end of group CMP_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 480
bogdanm 0:9b334a45a8ff 481
bogdanm 0:9b334a45a8ff 482 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 483 -- DAC Peripheral Access Layer
bogdanm 0:9b334a45a8ff 484 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 485
bogdanm 0:9b334a45a8ff 486 /*!
bogdanm 0:9b334a45a8ff 487 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
bogdanm 0:9b334a45a8ff 488 * @{
bogdanm 0:9b334a45a8ff 489 */
bogdanm 0:9b334a45a8ff 490
bogdanm 0:9b334a45a8ff 491 /** DAC - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 492 typedef struct {
bogdanm 0:9b334a45a8ff 493 struct { /* offset: 0x0, array step: 0x2 */
bogdanm 0:9b334a45a8ff 494 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
bogdanm 0:9b334a45a8ff 495 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
bogdanm 0:9b334a45a8ff 496 } DAT[2];
bogdanm 0:9b334a45a8ff 497 uint8_t RESERVED_0[28];
bogdanm 0:9b334a45a8ff 498 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
bogdanm 0:9b334a45a8ff 499 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
bogdanm 0:9b334a45a8ff 500 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
bogdanm 0:9b334a45a8ff 501 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
bogdanm 0:9b334a45a8ff 502 } DAC_Type;
bogdanm 0:9b334a45a8ff 503
bogdanm 0:9b334a45a8ff 504 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 505 -- DAC Register Masks
bogdanm 0:9b334a45a8ff 506 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 507
bogdanm 0:9b334a45a8ff 508 /*!
bogdanm 0:9b334a45a8ff 509 * @addtogroup DAC_Register_Masks DAC Register Masks
bogdanm 0:9b334a45a8ff 510 * @{
bogdanm 0:9b334a45a8ff 511 */
bogdanm 0:9b334a45a8ff 512
bogdanm 0:9b334a45a8ff 513 /* DATL Bit Fields */
bogdanm 0:9b334a45a8ff 514 #define DAC_DATL_DATA0_MASK 0xFFu
bogdanm 0:9b334a45a8ff 515 #define DAC_DATL_DATA0_SHIFT 0
bogdanm 0:9b334a45a8ff 516 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
bogdanm 0:9b334a45a8ff 517 /* DATH Bit Fields */
bogdanm 0:9b334a45a8ff 518 #define DAC_DATH_DATA1_MASK 0xFu
bogdanm 0:9b334a45a8ff 519 #define DAC_DATH_DATA1_SHIFT 0
bogdanm 0:9b334a45a8ff 520 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
bogdanm 0:9b334a45a8ff 521 /* SR Bit Fields */
bogdanm 0:9b334a45a8ff 522 #define DAC_SR_DACBFRPBF_MASK 0x1u
bogdanm 0:9b334a45a8ff 523 #define DAC_SR_DACBFRPBF_SHIFT 0
bogdanm 0:9b334a45a8ff 524 #define DAC_SR_DACBFRPTF_MASK 0x2u
bogdanm 0:9b334a45a8ff 525 #define DAC_SR_DACBFRPTF_SHIFT 1
bogdanm 0:9b334a45a8ff 526 /* C0 Bit Fields */
bogdanm 0:9b334a45a8ff 527 #define DAC_C0_DACBBIEN_MASK 0x1u
bogdanm 0:9b334a45a8ff 528 #define DAC_C0_DACBBIEN_SHIFT 0
bogdanm 0:9b334a45a8ff 529 #define DAC_C0_DACBTIEN_MASK 0x2u
bogdanm 0:9b334a45a8ff 530 #define DAC_C0_DACBTIEN_SHIFT 1
bogdanm 0:9b334a45a8ff 531 #define DAC_C0_LPEN_MASK 0x8u
bogdanm 0:9b334a45a8ff 532 #define DAC_C0_LPEN_SHIFT 3
bogdanm 0:9b334a45a8ff 533 #define DAC_C0_DACSWTRG_MASK 0x10u
bogdanm 0:9b334a45a8ff 534 #define DAC_C0_DACSWTRG_SHIFT 4
bogdanm 0:9b334a45a8ff 535 #define DAC_C0_DACTRGSEL_MASK 0x20u
bogdanm 0:9b334a45a8ff 536 #define DAC_C0_DACTRGSEL_SHIFT 5
bogdanm 0:9b334a45a8ff 537 #define DAC_C0_DACRFS_MASK 0x40u
bogdanm 0:9b334a45a8ff 538 #define DAC_C0_DACRFS_SHIFT 6
bogdanm 0:9b334a45a8ff 539 #define DAC_C0_DACEN_MASK 0x80u
bogdanm 0:9b334a45a8ff 540 #define DAC_C0_DACEN_SHIFT 7
bogdanm 0:9b334a45a8ff 541 /* C1 Bit Fields */
bogdanm 0:9b334a45a8ff 542 #define DAC_C1_DACBFEN_MASK 0x1u
bogdanm 0:9b334a45a8ff 543 #define DAC_C1_DACBFEN_SHIFT 0
bogdanm 0:9b334a45a8ff 544 #define DAC_C1_DACBFMD_MASK 0x4u
bogdanm 0:9b334a45a8ff 545 #define DAC_C1_DACBFMD_SHIFT 2
bogdanm 0:9b334a45a8ff 546 #define DAC_C1_DMAEN_MASK 0x80u
bogdanm 0:9b334a45a8ff 547 #define DAC_C1_DMAEN_SHIFT 7
bogdanm 0:9b334a45a8ff 548 /* C2 Bit Fields */
bogdanm 0:9b334a45a8ff 549 #define DAC_C2_DACBFUP_MASK 0x1u
bogdanm 0:9b334a45a8ff 550 #define DAC_C2_DACBFUP_SHIFT 0
bogdanm 0:9b334a45a8ff 551 #define DAC_C2_DACBFRP_MASK 0x10u
bogdanm 0:9b334a45a8ff 552 #define DAC_C2_DACBFRP_SHIFT 4
bogdanm 0:9b334a45a8ff 553
bogdanm 0:9b334a45a8ff 554 /*!
bogdanm 0:9b334a45a8ff 555 * @}
bogdanm 0:9b334a45a8ff 556 */ /* end of group DAC_Register_Masks */
bogdanm 0:9b334a45a8ff 557
bogdanm 0:9b334a45a8ff 558
bogdanm 0:9b334a45a8ff 559 /* DAC - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 560 /** Peripheral DAC0 base address */
bogdanm 0:9b334a45a8ff 561 #define DAC0_BASE (0x4003F000u)
bogdanm 0:9b334a45a8ff 562 /** Peripheral DAC0 base pointer */
bogdanm 0:9b334a45a8ff 563 #define DAC0 ((DAC_Type *)DAC0_BASE)
bogdanm 0:9b334a45a8ff 564 /** Array initializer of DAC peripheral base pointers */
bogdanm 0:9b334a45a8ff 565 #define DAC_BASES { DAC0 }
bogdanm 0:9b334a45a8ff 566
bogdanm 0:9b334a45a8ff 567 /*!
bogdanm 0:9b334a45a8ff 568 * @}
bogdanm 0:9b334a45a8ff 569 */ /* end of group DAC_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 570
bogdanm 0:9b334a45a8ff 571
bogdanm 0:9b334a45a8ff 572 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 573 -- DMA Peripheral Access Layer
bogdanm 0:9b334a45a8ff 574 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 575
bogdanm 0:9b334a45a8ff 576 /*!
bogdanm 0:9b334a45a8ff 577 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
bogdanm 0:9b334a45a8ff 578 * @{
bogdanm 0:9b334a45a8ff 579 */
bogdanm 0:9b334a45a8ff 580
bogdanm 0:9b334a45a8ff 581 /** DMA - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 582 typedef struct {
bogdanm 0:9b334a45a8ff 583 uint8_t RESERVED_0[256];
bogdanm 0:9b334a45a8ff 584 struct { /* offset: 0x100, array step: 0x10 */
bogdanm 0:9b334a45a8ff 585 __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */
bogdanm 0:9b334a45a8ff 586 __IO uint32_t DAR; /**< Destination Address Register, array offset: 0x104, array step: 0x10 */
bogdanm 0:9b334a45a8ff 587 union { /* offset: 0x108, array step: 0x10 */
bogdanm 0:9b334a45a8ff 588 __IO uint32_t DSR_BCR; /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */
bogdanm 0:9b334a45a8ff 589 struct { /* offset: 0x108, array step: 0x10 */
bogdanm 0:9b334a45a8ff 590 uint8_t RESERVED_0[3];
bogdanm 0:9b334a45a8ff 591 __IO uint8_t DSR; /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */
bogdanm 0:9b334a45a8ff 592 } DMA_DSR_ACCESS8BIT;
bogdanm 0:9b334a45a8ff 593 };
bogdanm 0:9b334a45a8ff 594 __IO uint32_t DCR; /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */
bogdanm 0:9b334a45a8ff 595 } DMA[4];
bogdanm 0:9b334a45a8ff 596 } DMA_Type;
bogdanm 0:9b334a45a8ff 597
bogdanm 0:9b334a45a8ff 598 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 599 -- DMA Register Masks
bogdanm 0:9b334a45a8ff 600 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 601
bogdanm 0:9b334a45a8ff 602 /*!
bogdanm 0:9b334a45a8ff 603 * @addtogroup DMA_Register_Masks DMA Register Masks
bogdanm 0:9b334a45a8ff 604 * @{
bogdanm 0:9b334a45a8ff 605 */
bogdanm 0:9b334a45a8ff 606
bogdanm 0:9b334a45a8ff 607 /* SAR Bit Fields */
bogdanm 0:9b334a45a8ff 608 #define DMA_SAR_SAR_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 609 #define DMA_SAR_SAR_SHIFT 0
bogdanm 0:9b334a45a8ff 610 #define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SAR_SAR_SHIFT))&DMA_SAR_SAR_MASK)
bogdanm 0:9b334a45a8ff 611 /* DAR Bit Fields */
bogdanm 0:9b334a45a8ff 612 #define DMA_DAR_DAR_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 613 #define DMA_DAR_DAR_SHIFT 0
bogdanm 0:9b334a45a8ff 614 #define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DAR_DAR_SHIFT))&DMA_DAR_DAR_MASK)
bogdanm 0:9b334a45a8ff 615 /* DSR_BCR Bit Fields */
bogdanm 0:9b334a45a8ff 616 #define DMA_DSR_BCR_BCR_MASK 0xFFFFFFu
bogdanm 0:9b334a45a8ff 617 #define DMA_DSR_BCR_BCR_SHIFT 0
bogdanm 0:9b334a45a8ff 618 #define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BCR_SHIFT))&DMA_DSR_BCR_BCR_MASK)
bogdanm 0:9b334a45a8ff 619 #define DMA_DSR_BCR_DONE_MASK 0x1000000u
bogdanm 0:9b334a45a8ff 620 #define DMA_DSR_BCR_DONE_SHIFT 24
bogdanm 0:9b334a45a8ff 621 #define DMA_DSR_BCR_BSY_MASK 0x2000000u
bogdanm 0:9b334a45a8ff 622 #define DMA_DSR_BCR_BSY_SHIFT 25
bogdanm 0:9b334a45a8ff 623 #define DMA_DSR_BCR_REQ_MASK 0x4000000u
bogdanm 0:9b334a45a8ff 624 #define DMA_DSR_BCR_REQ_SHIFT 26
bogdanm 0:9b334a45a8ff 625 #define DMA_DSR_BCR_BED_MASK 0x10000000u
bogdanm 0:9b334a45a8ff 626 #define DMA_DSR_BCR_BED_SHIFT 28
bogdanm 0:9b334a45a8ff 627 #define DMA_DSR_BCR_BES_MASK 0x20000000u
bogdanm 0:9b334a45a8ff 628 #define DMA_DSR_BCR_BES_SHIFT 29
bogdanm 0:9b334a45a8ff 629 #define DMA_DSR_BCR_CE_MASK 0x40000000u
bogdanm 0:9b334a45a8ff 630 #define DMA_DSR_BCR_CE_SHIFT 30
bogdanm 0:9b334a45a8ff 631 /* DCR Bit Fields */
bogdanm 0:9b334a45a8ff 632 #define DMA_DCR_LCH2_MASK 0x3u
bogdanm 0:9b334a45a8ff 633 #define DMA_DCR_LCH2_SHIFT 0
bogdanm 0:9b334a45a8ff 634 #define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH2_SHIFT))&DMA_DCR_LCH2_MASK)
bogdanm 0:9b334a45a8ff 635 #define DMA_DCR_LCH1_MASK 0xCu
bogdanm 0:9b334a45a8ff 636 #define DMA_DCR_LCH1_SHIFT 2
bogdanm 0:9b334a45a8ff 637 #define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH1_SHIFT))&DMA_DCR_LCH1_MASK)
bogdanm 0:9b334a45a8ff 638 #define DMA_DCR_LINKCC_MASK 0x30u
bogdanm 0:9b334a45a8ff 639 #define DMA_DCR_LINKCC_SHIFT 4
bogdanm 0:9b334a45a8ff 640 #define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LINKCC_SHIFT))&DMA_DCR_LINKCC_MASK)
bogdanm 0:9b334a45a8ff 641 #define DMA_DCR_D_REQ_MASK 0x80u
bogdanm 0:9b334a45a8ff 642 #define DMA_DCR_D_REQ_SHIFT 7
bogdanm 0:9b334a45a8ff 643 #define DMA_DCR_DMOD_MASK 0xF00u
bogdanm 0:9b334a45a8ff 644 #define DMA_DCR_DMOD_SHIFT 8
bogdanm 0:9b334a45a8ff 645 #define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DMOD_SHIFT))&DMA_DCR_DMOD_MASK)
bogdanm 0:9b334a45a8ff 646 #define DMA_DCR_SMOD_MASK 0xF000u
bogdanm 0:9b334a45a8ff 647 #define DMA_DCR_SMOD_SHIFT 12
bogdanm 0:9b334a45a8ff 648 #define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SMOD_SHIFT))&DMA_DCR_SMOD_MASK)
bogdanm 0:9b334a45a8ff 649 #define DMA_DCR_START_MASK 0x10000u
bogdanm 0:9b334a45a8ff 650 #define DMA_DCR_START_SHIFT 16
bogdanm 0:9b334a45a8ff 651 #define DMA_DCR_DSIZE_MASK 0x60000u
bogdanm 0:9b334a45a8ff 652 #define DMA_DCR_DSIZE_SHIFT 17
bogdanm 0:9b334a45a8ff 653 #define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DSIZE_SHIFT))&DMA_DCR_DSIZE_MASK)
bogdanm 0:9b334a45a8ff 654 #define DMA_DCR_DINC_MASK 0x80000u
bogdanm 0:9b334a45a8ff 655 #define DMA_DCR_DINC_SHIFT 19
bogdanm 0:9b334a45a8ff 656 #define DMA_DCR_SSIZE_MASK 0x300000u
bogdanm 0:9b334a45a8ff 657 #define DMA_DCR_SSIZE_SHIFT 20
bogdanm 0:9b334a45a8ff 658 #define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SSIZE_SHIFT))&DMA_DCR_SSIZE_MASK)
bogdanm 0:9b334a45a8ff 659 #define DMA_DCR_SINC_MASK 0x400000u
bogdanm 0:9b334a45a8ff 660 #define DMA_DCR_SINC_SHIFT 22
bogdanm 0:9b334a45a8ff 661 #define DMA_DCR_EADREQ_MASK 0x800000u
bogdanm 0:9b334a45a8ff 662 #define DMA_DCR_EADREQ_SHIFT 23
bogdanm 0:9b334a45a8ff 663 #define DMA_DCR_AA_MASK 0x10000000u
bogdanm 0:9b334a45a8ff 664 #define DMA_DCR_AA_SHIFT 28
bogdanm 0:9b334a45a8ff 665 #define DMA_DCR_CS_MASK 0x20000000u
bogdanm 0:9b334a45a8ff 666 #define DMA_DCR_CS_SHIFT 29
bogdanm 0:9b334a45a8ff 667 #define DMA_DCR_ERQ_MASK 0x40000000u
bogdanm 0:9b334a45a8ff 668 #define DMA_DCR_ERQ_SHIFT 30
bogdanm 0:9b334a45a8ff 669 #define DMA_DCR_EINT_MASK 0x80000000u
bogdanm 0:9b334a45a8ff 670 #define DMA_DCR_EINT_SHIFT 31
bogdanm 0:9b334a45a8ff 671
bogdanm 0:9b334a45a8ff 672 /*!
bogdanm 0:9b334a45a8ff 673 * @}
bogdanm 0:9b334a45a8ff 674 */ /* end of group DMA_Register_Masks */
bogdanm 0:9b334a45a8ff 675
bogdanm 0:9b334a45a8ff 676
bogdanm 0:9b334a45a8ff 677 /* DMA - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 678 /** Peripheral DMA base address */
bogdanm 0:9b334a45a8ff 679 #define DMA_BASE (0x40008000u)
bogdanm 0:9b334a45a8ff 680 /** Peripheral DMA base pointer */
bogdanm 0:9b334a45a8ff 681 #define DMA0 ((DMA_Type *)DMA_BASE)
bogdanm 0:9b334a45a8ff 682 /** Array initializer of DMA peripheral base pointers */
bogdanm 0:9b334a45a8ff 683 #define DMA_BASES { DMA0 }
bogdanm 0:9b334a45a8ff 684
bogdanm 0:9b334a45a8ff 685 /*!
bogdanm 0:9b334a45a8ff 686 * @}
bogdanm 0:9b334a45a8ff 687 */ /* end of group DMA_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 688
bogdanm 0:9b334a45a8ff 689
bogdanm 0:9b334a45a8ff 690 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 691 -- DMAMUX Peripheral Access Layer
bogdanm 0:9b334a45a8ff 692 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 693
bogdanm 0:9b334a45a8ff 694 /*!
bogdanm 0:9b334a45a8ff 695 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
bogdanm 0:9b334a45a8ff 696 * @{
bogdanm 0:9b334a45a8ff 697 */
bogdanm 0:9b334a45a8ff 698
bogdanm 0:9b334a45a8ff 699 /** DMAMUX - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 700 typedef struct {
bogdanm 0:9b334a45a8ff 701 __IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
bogdanm 0:9b334a45a8ff 702 } DMAMUX_Type;
bogdanm 0:9b334a45a8ff 703
bogdanm 0:9b334a45a8ff 704 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 705 -- DMAMUX Register Masks
bogdanm 0:9b334a45a8ff 706 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 707
bogdanm 0:9b334a45a8ff 708 /*!
bogdanm 0:9b334a45a8ff 709 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
bogdanm 0:9b334a45a8ff 710 * @{
bogdanm 0:9b334a45a8ff 711 */
bogdanm 0:9b334a45a8ff 712
bogdanm 0:9b334a45a8ff 713 /* CHCFG Bit Fields */
bogdanm 0:9b334a45a8ff 714 #define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
bogdanm 0:9b334a45a8ff 715 #define DMAMUX_CHCFG_SOURCE_SHIFT 0
bogdanm 0:9b334a45a8ff 716 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
bogdanm 0:9b334a45a8ff 717 #define DMAMUX_CHCFG_TRIG_MASK 0x40u
bogdanm 0:9b334a45a8ff 718 #define DMAMUX_CHCFG_TRIG_SHIFT 6
bogdanm 0:9b334a45a8ff 719 #define DMAMUX_CHCFG_ENBL_MASK 0x80u
bogdanm 0:9b334a45a8ff 720 #define DMAMUX_CHCFG_ENBL_SHIFT 7
bogdanm 0:9b334a45a8ff 721
bogdanm 0:9b334a45a8ff 722 /*!
bogdanm 0:9b334a45a8ff 723 * @}
bogdanm 0:9b334a45a8ff 724 */ /* end of group DMAMUX_Register_Masks */
bogdanm 0:9b334a45a8ff 725
bogdanm 0:9b334a45a8ff 726
bogdanm 0:9b334a45a8ff 727 /* DMAMUX - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 728 /** Peripheral DMAMUX0 base address */
bogdanm 0:9b334a45a8ff 729 #define DMAMUX0_BASE (0x40021000u)
bogdanm 0:9b334a45a8ff 730 /** Peripheral DMAMUX0 base pointer */
bogdanm 0:9b334a45a8ff 731 #define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
bogdanm 0:9b334a45a8ff 732 /** Array initializer of DMAMUX peripheral base pointers */
bogdanm 0:9b334a45a8ff 733 #define DMAMUX_BASES { DMAMUX0 }
bogdanm 0:9b334a45a8ff 734
bogdanm 0:9b334a45a8ff 735 /*!
bogdanm 0:9b334a45a8ff 736 * @}
bogdanm 0:9b334a45a8ff 737 */ /* end of group DMAMUX_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 738
bogdanm 0:9b334a45a8ff 739
bogdanm 0:9b334a45a8ff 740 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 741 -- FGPIO Peripheral Access Layer
bogdanm 0:9b334a45a8ff 742 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 743
bogdanm 0:9b334a45a8ff 744 /*!
bogdanm 0:9b334a45a8ff 745 * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
bogdanm 0:9b334a45a8ff 746 * @{
bogdanm 0:9b334a45a8ff 747 */
bogdanm 0:9b334a45a8ff 748
bogdanm 0:9b334a45a8ff 749 /** FGPIO - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 750 typedef struct {
bogdanm 0:9b334a45a8ff 751 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
bogdanm 0:9b334a45a8ff 752 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
bogdanm 0:9b334a45a8ff 753 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
bogdanm 0:9b334a45a8ff 754 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
bogdanm 0:9b334a45a8ff 755 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
bogdanm 0:9b334a45a8ff 756 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
bogdanm 0:9b334a45a8ff 757 } FGPIO_Type;
bogdanm 0:9b334a45a8ff 758
bogdanm 0:9b334a45a8ff 759 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 760 -- FGPIO Register Masks
bogdanm 0:9b334a45a8ff 761 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 762
bogdanm 0:9b334a45a8ff 763 /*!
bogdanm 0:9b334a45a8ff 764 * @addtogroup FGPIO_Register_Masks FGPIO Register Masks
bogdanm 0:9b334a45a8ff 765 * @{
bogdanm 0:9b334a45a8ff 766 */
bogdanm 0:9b334a45a8ff 767
bogdanm 0:9b334a45a8ff 768 /* PDOR Bit Fields */
bogdanm 0:9b334a45a8ff 769 #define FGPIO_PDOR_PDO_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 770 #define FGPIO_PDOR_PDO_SHIFT 0
bogdanm 0:9b334a45a8ff 771 #define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDOR_PDO_SHIFT))&FGPIO_PDOR_PDO_MASK)
bogdanm 0:9b334a45a8ff 772 /* PSOR Bit Fields */
bogdanm 0:9b334a45a8ff 773 #define FGPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 774 #define FGPIO_PSOR_PTSO_SHIFT 0
bogdanm 0:9b334a45a8ff 775 #define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PSOR_PTSO_SHIFT))&FGPIO_PSOR_PTSO_MASK)
bogdanm 0:9b334a45a8ff 776 /* PCOR Bit Fields */
bogdanm 0:9b334a45a8ff 777 #define FGPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 778 #define FGPIO_PCOR_PTCO_SHIFT 0
bogdanm 0:9b334a45a8ff 779 #define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PCOR_PTCO_SHIFT))&FGPIO_PCOR_PTCO_MASK)
bogdanm 0:9b334a45a8ff 780 /* PTOR Bit Fields */
bogdanm 0:9b334a45a8ff 781 #define FGPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 782 #define FGPIO_PTOR_PTTO_SHIFT 0
bogdanm 0:9b334a45a8ff 783 #define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PTOR_PTTO_SHIFT))&FGPIO_PTOR_PTTO_MASK)
bogdanm 0:9b334a45a8ff 784 /* PDIR Bit Fields */
bogdanm 0:9b334a45a8ff 785 #define FGPIO_PDIR_PDI_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 786 #define FGPIO_PDIR_PDI_SHIFT 0
bogdanm 0:9b334a45a8ff 787 #define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDIR_PDI_SHIFT))&FGPIO_PDIR_PDI_MASK)
bogdanm 0:9b334a45a8ff 788 /* PDDR Bit Fields */
bogdanm 0:9b334a45a8ff 789 #define FGPIO_PDDR_PDD_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 790 #define FGPIO_PDDR_PDD_SHIFT 0
bogdanm 0:9b334a45a8ff 791 #define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDDR_PDD_SHIFT))&FGPIO_PDDR_PDD_MASK)
bogdanm 0:9b334a45a8ff 792
bogdanm 0:9b334a45a8ff 793 /*!
bogdanm 0:9b334a45a8ff 794 * @}
bogdanm 0:9b334a45a8ff 795 */ /* end of group FGPIO_Register_Masks */
bogdanm 0:9b334a45a8ff 796
bogdanm 0:9b334a45a8ff 797
bogdanm 0:9b334a45a8ff 798 /* FGPIO - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 799 /** Peripheral FPTA base address */
bogdanm 0:9b334a45a8ff 800 #define FPTA_BASE (0xF80FF000u)
bogdanm 0:9b334a45a8ff 801 /** Peripheral FPTA base pointer */
bogdanm 0:9b334a45a8ff 802 #define FPTA ((FGPIO_Type *)FPTA_BASE)
bogdanm 0:9b334a45a8ff 803 /** Peripheral FPTB base address */
bogdanm 0:9b334a45a8ff 804 #define FPTB_BASE (0xF80FF040u)
bogdanm 0:9b334a45a8ff 805 /** Peripheral FPTB base pointer */
bogdanm 0:9b334a45a8ff 806 #define FPTB ((FGPIO_Type *)FPTB_BASE)
bogdanm 0:9b334a45a8ff 807 /** Peripheral FPTC base address */
bogdanm 0:9b334a45a8ff 808 #define FPTC_BASE (0xF80FF080u)
bogdanm 0:9b334a45a8ff 809 /** Peripheral FPTC base pointer */
bogdanm 0:9b334a45a8ff 810 #define FPTC ((FGPIO_Type *)FPTC_BASE)
bogdanm 0:9b334a45a8ff 811 /** Peripheral FPTD base address */
bogdanm 0:9b334a45a8ff 812 #define FPTD_BASE (0xF80FF0C0u)
bogdanm 0:9b334a45a8ff 813 /** Peripheral FPTD base pointer */
bogdanm 0:9b334a45a8ff 814 #define FPTD ((FGPIO_Type *)FPTD_BASE)
bogdanm 0:9b334a45a8ff 815 /** Peripheral FPTE base address */
bogdanm 0:9b334a45a8ff 816 #define FPTE_BASE (0xF80FF100u)
bogdanm 0:9b334a45a8ff 817 /** Peripheral FPTE base pointer */
bogdanm 0:9b334a45a8ff 818 #define FPTE ((FGPIO_Type *)FPTE_BASE)
bogdanm 0:9b334a45a8ff 819 /** Array initializer of FGPIO peripheral base pointers */
bogdanm 0:9b334a45a8ff 820 #define FGPIO_BASES { FPTA, FPTB, FPTC, FPTD, FPTE }
bogdanm 0:9b334a45a8ff 821
bogdanm 0:9b334a45a8ff 822 /*!
bogdanm 0:9b334a45a8ff 823 * @}
bogdanm 0:9b334a45a8ff 824 */ /* end of group FGPIO_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 825
bogdanm 0:9b334a45a8ff 826
bogdanm 0:9b334a45a8ff 827 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 828 -- FTFA Peripheral Access Layer
bogdanm 0:9b334a45a8ff 829 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 830
bogdanm 0:9b334a45a8ff 831 /*!
bogdanm 0:9b334a45a8ff 832 * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
bogdanm 0:9b334a45a8ff 833 * @{
bogdanm 0:9b334a45a8ff 834 */
bogdanm 0:9b334a45a8ff 835
bogdanm 0:9b334a45a8ff 836 /** FTFA - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 837 typedef struct {
bogdanm 0:9b334a45a8ff 838 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
bogdanm 0:9b334a45a8ff 839 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
bogdanm 0:9b334a45a8ff 840 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
bogdanm 0:9b334a45a8ff 841 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
bogdanm 0:9b334a45a8ff 842 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
bogdanm 0:9b334a45a8ff 843 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
bogdanm 0:9b334a45a8ff 844 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
bogdanm 0:9b334a45a8ff 845 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
bogdanm 0:9b334a45a8ff 846 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
bogdanm 0:9b334a45a8ff 847 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
bogdanm 0:9b334a45a8ff 848 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
bogdanm 0:9b334a45a8ff 849 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
bogdanm 0:9b334a45a8ff 850 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
bogdanm 0:9b334a45a8ff 851 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
bogdanm 0:9b334a45a8ff 852 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
bogdanm 0:9b334a45a8ff 853 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
bogdanm 0:9b334a45a8ff 854 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
bogdanm 0:9b334a45a8ff 855 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
bogdanm 0:9b334a45a8ff 856 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
bogdanm 0:9b334a45a8ff 857 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
bogdanm 0:9b334a45a8ff 858 } FTFA_Type;
bogdanm 0:9b334a45a8ff 859
bogdanm 0:9b334a45a8ff 860 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 861 -- FTFA Register Masks
bogdanm 0:9b334a45a8ff 862 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 863
bogdanm 0:9b334a45a8ff 864 /*!
bogdanm 0:9b334a45a8ff 865 * @addtogroup FTFA_Register_Masks FTFA Register Masks
bogdanm 0:9b334a45a8ff 866 * @{
bogdanm 0:9b334a45a8ff 867 */
bogdanm 0:9b334a45a8ff 868
bogdanm 0:9b334a45a8ff 869 /* FSTAT Bit Fields */
bogdanm 0:9b334a45a8ff 870 #define FTFA_FSTAT_MGSTAT0_MASK 0x1u
bogdanm 0:9b334a45a8ff 871 #define FTFA_FSTAT_MGSTAT0_SHIFT 0
bogdanm 0:9b334a45a8ff 872 #define FTFA_FSTAT_FPVIOL_MASK 0x10u
bogdanm 0:9b334a45a8ff 873 #define FTFA_FSTAT_FPVIOL_SHIFT 4
bogdanm 0:9b334a45a8ff 874 #define FTFA_FSTAT_ACCERR_MASK 0x20u
bogdanm 0:9b334a45a8ff 875 #define FTFA_FSTAT_ACCERR_SHIFT 5
bogdanm 0:9b334a45a8ff 876 #define FTFA_FSTAT_RDCOLERR_MASK 0x40u
bogdanm 0:9b334a45a8ff 877 #define FTFA_FSTAT_RDCOLERR_SHIFT 6
bogdanm 0:9b334a45a8ff 878 #define FTFA_FSTAT_CCIF_MASK 0x80u
bogdanm 0:9b334a45a8ff 879 #define FTFA_FSTAT_CCIF_SHIFT 7
bogdanm 0:9b334a45a8ff 880 /* FCNFG Bit Fields */
bogdanm 0:9b334a45a8ff 881 #define FTFA_FCNFG_ERSSUSP_MASK 0x10u
bogdanm 0:9b334a45a8ff 882 #define FTFA_FCNFG_ERSSUSP_SHIFT 4
bogdanm 0:9b334a45a8ff 883 #define FTFA_FCNFG_ERSAREQ_MASK 0x20u
bogdanm 0:9b334a45a8ff 884 #define FTFA_FCNFG_ERSAREQ_SHIFT 5
bogdanm 0:9b334a45a8ff 885 #define FTFA_FCNFG_RDCOLLIE_MASK 0x40u
bogdanm 0:9b334a45a8ff 886 #define FTFA_FCNFG_RDCOLLIE_SHIFT 6
bogdanm 0:9b334a45a8ff 887 #define FTFA_FCNFG_CCIE_MASK 0x80u
bogdanm 0:9b334a45a8ff 888 #define FTFA_FCNFG_CCIE_SHIFT 7
bogdanm 0:9b334a45a8ff 889 /* FSEC Bit Fields */
bogdanm 0:9b334a45a8ff 890 #define FTFA_FSEC_SEC_MASK 0x3u
bogdanm 0:9b334a45a8ff 891 #define FTFA_FSEC_SEC_SHIFT 0
bogdanm 0:9b334a45a8ff 892 #define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
bogdanm 0:9b334a45a8ff 893 #define FTFA_FSEC_FSLACC_MASK 0xCu
bogdanm 0:9b334a45a8ff 894 #define FTFA_FSEC_FSLACC_SHIFT 2
bogdanm 0:9b334a45a8ff 895 #define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
bogdanm 0:9b334a45a8ff 896 #define FTFA_FSEC_MEEN_MASK 0x30u
bogdanm 0:9b334a45a8ff 897 #define FTFA_FSEC_MEEN_SHIFT 4
bogdanm 0:9b334a45a8ff 898 #define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
bogdanm 0:9b334a45a8ff 899 #define FTFA_FSEC_KEYEN_MASK 0xC0u
bogdanm 0:9b334a45a8ff 900 #define FTFA_FSEC_KEYEN_SHIFT 6
bogdanm 0:9b334a45a8ff 901 #define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
bogdanm 0:9b334a45a8ff 902 /* FOPT Bit Fields */
bogdanm 0:9b334a45a8ff 903 #define FTFA_FOPT_OPT_MASK 0xFFu
bogdanm 0:9b334a45a8ff 904 #define FTFA_FOPT_OPT_SHIFT 0
bogdanm 0:9b334a45a8ff 905 #define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
bogdanm 0:9b334a45a8ff 906 /* FCCOB3 Bit Fields */
bogdanm 0:9b334a45a8ff 907 #define FTFA_FCCOB3_CCOBn_MASK 0xFFu
bogdanm 0:9b334a45a8ff 908 #define FTFA_FCCOB3_CCOBn_SHIFT 0
bogdanm 0:9b334a45a8ff 909 #define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
bogdanm 0:9b334a45a8ff 910 /* FCCOB2 Bit Fields */
bogdanm 0:9b334a45a8ff 911 #define FTFA_FCCOB2_CCOBn_MASK 0xFFu
bogdanm 0:9b334a45a8ff 912 #define FTFA_FCCOB2_CCOBn_SHIFT 0
bogdanm 0:9b334a45a8ff 913 #define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
bogdanm 0:9b334a45a8ff 914 /* FCCOB1 Bit Fields */
bogdanm 0:9b334a45a8ff 915 #define FTFA_FCCOB1_CCOBn_MASK 0xFFu
bogdanm 0:9b334a45a8ff 916 #define FTFA_FCCOB1_CCOBn_SHIFT 0
bogdanm 0:9b334a45a8ff 917 #define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
bogdanm 0:9b334a45a8ff 918 /* FCCOB0 Bit Fields */
bogdanm 0:9b334a45a8ff 919 #define FTFA_FCCOB0_CCOBn_MASK 0xFFu
bogdanm 0:9b334a45a8ff 920 #define FTFA_FCCOB0_CCOBn_SHIFT 0
bogdanm 0:9b334a45a8ff 921 #define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
bogdanm 0:9b334a45a8ff 922 /* FCCOB7 Bit Fields */
bogdanm 0:9b334a45a8ff 923 #define FTFA_FCCOB7_CCOBn_MASK 0xFFu
bogdanm 0:9b334a45a8ff 924 #define FTFA_FCCOB7_CCOBn_SHIFT 0
bogdanm 0:9b334a45a8ff 925 #define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
bogdanm 0:9b334a45a8ff 926 /* FCCOB6 Bit Fields */
bogdanm 0:9b334a45a8ff 927 #define FTFA_FCCOB6_CCOBn_MASK 0xFFu
bogdanm 0:9b334a45a8ff 928 #define FTFA_FCCOB6_CCOBn_SHIFT 0
bogdanm 0:9b334a45a8ff 929 #define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
bogdanm 0:9b334a45a8ff 930 /* FCCOB5 Bit Fields */
bogdanm 0:9b334a45a8ff 931 #define FTFA_FCCOB5_CCOBn_MASK 0xFFu
bogdanm 0:9b334a45a8ff 932 #define FTFA_FCCOB5_CCOBn_SHIFT 0
bogdanm 0:9b334a45a8ff 933 #define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
bogdanm 0:9b334a45a8ff 934 /* FCCOB4 Bit Fields */
bogdanm 0:9b334a45a8ff 935 #define FTFA_FCCOB4_CCOBn_MASK 0xFFu
bogdanm 0:9b334a45a8ff 936 #define FTFA_FCCOB4_CCOBn_SHIFT 0
bogdanm 0:9b334a45a8ff 937 #define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
bogdanm 0:9b334a45a8ff 938 /* FCCOBB Bit Fields */
bogdanm 0:9b334a45a8ff 939 #define FTFA_FCCOBB_CCOBn_MASK 0xFFu
bogdanm 0:9b334a45a8ff 940 #define FTFA_FCCOBB_CCOBn_SHIFT 0
bogdanm 0:9b334a45a8ff 941 #define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
bogdanm 0:9b334a45a8ff 942 /* FCCOBA Bit Fields */
bogdanm 0:9b334a45a8ff 943 #define FTFA_FCCOBA_CCOBn_MASK 0xFFu
bogdanm 0:9b334a45a8ff 944 #define FTFA_FCCOBA_CCOBn_SHIFT 0
bogdanm 0:9b334a45a8ff 945 #define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
bogdanm 0:9b334a45a8ff 946 /* FCCOB9 Bit Fields */
bogdanm 0:9b334a45a8ff 947 #define FTFA_FCCOB9_CCOBn_MASK 0xFFu
bogdanm 0:9b334a45a8ff 948 #define FTFA_FCCOB9_CCOBn_SHIFT 0
bogdanm 0:9b334a45a8ff 949 #define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
bogdanm 0:9b334a45a8ff 950 /* FCCOB8 Bit Fields */
bogdanm 0:9b334a45a8ff 951 #define FTFA_FCCOB8_CCOBn_MASK 0xFFu
bogdanm 0:9b334a45a8ff 952 #define FTFA_FCCOB8_CCOBn_SHIFT 0
bogdanm 0:9b334a45a8ff 953 #define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
bogdanm 0:9b334a45a8ff 954 /* FPROT3 Bit Fields */
bogdanm 0:9b334a45a8ff 955 #define FTFA_FPROT3_PROT_MASK 0xFFu
bogdanm 0:9b334a45a8ff 956 #define FTFA_FPROT3_PROT_SHIFT 0
bogdanm 0:9b334a45a8ff 957 #define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
bogdanm 0:9b334a45a8ff 958 /* FPROT2 Bit Fields */
bogdanm 0:9b334a45a8ff 959 #define FTFA_FPROT2_PROT_MASK 0xFFu
bogdanm 0:9b334a45a8ff 960 #define FTFA_FPROT2_PROT_SHIFT 0
bogdanm 0:9b334a45a8ff 961 #define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
bogdanm 0:9b334a45a8ff 962 /* FPROT1 Bit Fields */
bogdanm 0:9b334a45a8ff 963 #define FTFA_FPROT1_PROT_MASK 0xFFu
bogdanm 0:9b334a45a8ff 964 #define FTFA_FPROT1_PROT_SHIFT 0
bogdanm 0:9b334a45a8ff 965 #define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
bogdanm 0:9b334a45a8ff 966 /* FPROT0 Bit Fields */
bogdanm 0:9b334a45a8ff 967 #define FTFA_FPROT0_PROT_MASK 0xFFu
bogdanm 0:9b334a45a8ff 968 #define FTFA_FPROT0_PROT_SHIFT 0
bogdanm 0:9b334a45a8ff 969 #define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
bogdanm 0:9b334a45a8ff 970
bogdanm 0:9b334a45a8ff 971 /*!
bogdanm 0:9b334a45a8ff 972 * @}
bogdanm 0:9b334a45a8ff 973 */ /* end of group FTFA_Register_Masks */
bogdanm 0:9b334a45a8ff 974
bogdanm 0:9b334a45a8ff 975
bogdanm 0:9b334a45a8ff 976 /* FTFA - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 977 /** Peripheral FTFA base address */
bogdanm 0:9b334a45a8ff 978 #define FTFA_BASE (0x40020000u)
bogdanm 0:9b334a45a8ff 979 /** Peripheral FTFA base pointer */
bogdanm 0:9b334a45a8ff 980 #define FTFA ((FTFA_Type *)FTFA_BASE)
bogdanm 0:9b334a45a8ff 981 /** Array initializer of FTFA peripheral base pointers */
bogdanm 0:9b334a45a8ff 982 #define FTFA_BASES { FTFA }
bogdanm 0:9b334a45a8ff 983
bogdanm 0:9b334a45a8ff 984 /*!
bogdanm 0:9b334a45a8ff 985 * @}
bogdanm 0:9b334a45a8ff 986 */ /* end of group FTFA_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 987
bogdanm 0:9b334a45a8ff 988
bogdanm 0:9b334a45a8ff 989 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 990 -- GPIO Peripheral Access Layer
bogdanm 0:9b334a45a8ff 991 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 992
bogdanm 0:9b334a45a8ff 993 /*!
bogdanm 0:9b334a45a8ff 994 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
bogdanm 0:9b334a45a8ff 995 * @{
bogdanm 0:9b334a45a8ff 996 */
bogdanm 0:9b334a45a8ff 997
bogdanm 0:9b334a45a8ff 998 /** GPIO - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 999 typedef struct {
bogdanm 0:9b334a45a8ff 1000 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
bogdanm 0:9b334a45a8ff 1001 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
bogdanm 0:9b334a45a8ff 1002 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
bogdanm 0:9b334a45a8ff 1003 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
bogdanm 0:9b334a45a8ff 1004 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
bogdanm 0:9b334a45a8ff 1005 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
bogdanm 0:9b334a45a8ff 1006 } GPIO_Type;
bogdanm 0:9b334a45a8ff 1007
bogdanm 0:9b334a45a8ff 1008 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 1009 -- GPIO Register Masks
bogdanm 0:9b334a45a8ff 1010 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 1011
bogdanm 0:9b334a45a8ff 1012 /*!
bogdanm 0:9b334a45a8ff 1013 * @addtogroup GPIO_Register_Masks GPIO Register Masks
bogdanm 0:9b334a45a8ff 1014 * @{
bogdanm 0:9b334a45a8ff 1015 */
bogdanm 0:9b334a45a8ff 1016
bogdanm 0:9b334a45a8ff 1017 /* PDOR Bit Fields */
bogdanm 0:9b334a45a8ff 1018 #define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 1019 #define GPIO_PDOR_PDO_SHIFT 0
bogdanm 0:9b334a45a8ff 1020 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
bogdanm 0:9b334a45a8ff 1021 /* PSOR Bit Fields */
bogdanm 0:9b334a45a8ff 1022 #define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 1023 #define GPIO_PSOR_PTSO_SHIFT 0
bogdanm 0:9b334a45a8ff 1024 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
bogdanm 0:9b334a45a8ff 1025 /* PCOR Bit Fields */
bogdanm 0:9b334a45a8ff 1026 #define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 1027 #define GPIO_PCOR_PTCO_SHIFT 0
bogdanm 0:9b334a45a8ff 1028 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
bogdanm 0:9b334a45a8ff 1029 /* PTOR Bit Fields */
bogdanm 0:9b334a45a8ff 1030 #define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 1031 #define GPIO_PTOR_PTTO_SHIFT 0
bogdanm 0:9b334a45a8ff 1032 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
bogdanm 0:9b334a45a8ff 1033 /* PDIR Bit Fields */
bogdanm 0:9b334a45a8ff 1034 #define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 1035 #define GPIO_PDIR_PDI_SHIFT 0
bogdanm 0:9b334a45a8ff 1036 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
bogdanm 0:9b334a45a8ff 1037 /* PDDR Bit Fields */
bogdanm 0:9b334a45a8ff 1038 #define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 1039 #define GPIO_PDDR_PDD_SHIFT 0
bogdanm 0:9b334a45a8ff 1040 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
bogdanm 0:9b334a45a8ff 1041
bogdanm 0:9b334a45a8ff 1042 /*!
bogdanm 0:9b334a45a8ff 1043 * @}
bogdanm 0:9b334a45a8ff 1044 */ /* end of group GPIO_Register_Masks */
bogdanm 0:9b334a45a8ff 1045
bogdanm 0:9b334a45a8ff 1046
bogdanm 0:9b334a45a8ff 1047 /* GPIO - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 1048 /** Peripheral PTA base address */
bogdanm 0:9b334a45a8ff 1049 #define PTA_BASE (0x400FF000u)
bogdanm 0:9b334a45a8ff 1050 /** Peripheral PTA base pointer */
bogdanm 0:9b334a45a8ff 1051 #define PTA ((GPIO_Type *)PTA_BASE)
bogdanm 0:9b334a45a8ff 1052 /** Peripheral PTB base address */
bogdanm 0:9b334a45a8ff 1053 #define PTB_BASE (0x400FF040u)
bogdanm 0:9b334a45a8ff 1054 /** Peripheral PTB base pointer */
bogdanm 0:9b334a45a8ff 1055 #define PTB ((GPIO_Type *)PTB_BASE)
bogdanm 0:9b334a45a8ff 1056 /** Peripheral PTC base address */
bogdanm 0:9b334a45a8ff 1057 #define PTC_BASE (0x400FF080u)
bogdanm 0:9b334a45a8ff 1058 /** Peripheral PTC base pointer */
bogdanm 0:9b334a45a8ff 1059 #define PTC ((GPIO_Type *)PTC_BASE)
bogdanm 0:9b334a45a8ff 1060 /** Peripheral PTD base address */
bogdanm 0:9b334a45a8ff 1061 #define PTD_BASE (0x400FF0C0u)
bogdanm 0:9b334a45a8ff 1062 /** Peripheral PTD base pointer */
bogdanm 0:9b334a45a8ff 1063 #define PTD ((GPIO_Type *)PTD_BASE)
bogdanm 0:9b334a45a8ff 1064 /** Peripheral PTE base address */
bogdanm 0:9b334a45a8ff 1065 #define PTE_BASE (0x400FF100u)
bogdanm 0:9b334a45a8ff 1066 /** Peripheral PTE base pointer */
bogdanm 0:9b334a45a8ff 1067 #define PTE ((GPIO_Type *)PTE_BASE)
bogdanm 0:9b334a45a8ff 1068 /** Array initializer of GPIO peripheral base pointers */
bogdanm 0:9b334a45a8ff 1069 #define GPIO_BASES { PTA, PTB, PTC, PTD, PTE }
bogdanm 0:9b334a45a8ff 1070
bogdanm 0:9b334a45a8ff 1071 /*!
bogdanm 0:9b334a45a8ff 1072 * @}
bogdanm 0:9b334a45a8ff 1073 */ /* end of group GPIO_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 1074
bogdanm 0:9b334a45a8ff 1075
bogdanm 0:9b334a45a8ff 1076 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 1077 -- I2C Peripheral Access Layer
bogdanm 0:9b334a45a8ff 1078 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 1079
bogdanm 0:9b334a45a8ff 1080 /*!
bogdanm 0:9b334a45a8ff 1081 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
bogdanm 0:9b334a45a8ff 1082 * @{
bogdanm 0:9b334a45a8ff 1083 */
bogdanm 0:9b334a45a8ff 1084
bogdanm 0:9b334a45a8ff 1085 /** I2C - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 1086 typedef struct {
bogdanm 0:9b334a45a8ff 1087 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
bogdanm 0:9b334a45a8ff 1088 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
bogdanm 0:9b334a45a8ff 1089 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
bogdanm 0:9b334a45a8ff 1090 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
bogdanm 0:9b334a45a8ff 1091 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
bogdanm 0:9b334a45a8ff 1092 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
bogdanm 0:9b334a45a8ff 1093 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
bogdanm 0:9b334a45a8ff 1094 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
bogdanm 0:9b334a45a8ff 1095 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
bogdanm 0:9b334a45a8ff 1096 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
bogdanm 0:9b334a45a8ff 1097 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
bogdanm 0:9b334a45a8ff 1098 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
bogdanm 0:9b334a45a8ff 1099 } I2C_Type;
bogdanm 0:9b334a45a8ff 1100
bogdanm 0:9b334a45a8ff 1101 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 1102 -- I2C Register Masks
bogdanm 0:9b334a45a8ff 1103 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 1104
bogdanm 0:9b334a45a8ff 1105 /*!
bogdanm 0:9b334a45a8ff 1106 * @addtogroup I2C_Register_Masks I2C Register Masks
bogdanm 0:9b334a45a8ff 1107 * @{
bogdanm 0:9b334a45a8ff 1108 */
bogdanm 0:9b334a45a8ff 1109
bogdanm 0:9b334a45a8ff 1110 /* A1 Bit Fields */
bogdanm 0:9b334a45a8ff 1111 #define I2C_A1_AD_MASK 0xFEu
bogdanm 0:9b334a45a8ff 1112 #define I2C_A1_AD_SHIFT 1
bogdanm 0:9b334a45a8ff 1113 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
bogdanm 0:9b334a45a8ff 1114 /* F Bit Fields */
bogdanm 0:9b334a45a8ff 1115 #define I2C_F_ICR_MASK 0x3Fu
bogdanm 0:9b334a45a8ff 1116 #define I2C_F_ICR_SHIFT 0
bogdanm 0:9b334a45a8ff 1117 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
bogdanm 0:9b334a45a8ff 1118 #define I2C_F_MULT_MASK 0xC0u
bogdanm 0:9b334a45a8ff 1119 #define I2C_F_MULT_SHIFT 6
bogdanm 0:9b334a45a8ff 1120 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
bogdanm 0:9b334a45a8ff 1121 /* C1 Bit Fields */
bogdanm 0:9b334a45a8ff 1122 #define I2C_C1_DMAEN_MASK 0x1u
bogdanm 0:9b334a45a8ff 1123 #define I2C_C1_DMAEN_SHIFT 0
bogdanm 0:9b334a45a8ff 1124 #define I2C_C1_WUEN_MASK 0x2u
bogdanm 0:9b334a45a8ff 1125 #define I2C_C1_WUEN_SHIFT 1
bogdanm 0:9b334a45a8ff 1126 #define I2C_C1_RSTA_MASK 0x4u
bogdanm 0:9b334a45a8ff 1127 #define I2C_C1_RSTA_SHIFT 2
bogdanm 0:9b334a45a8ff 1128 #define I2C_C1_TXAK_MASK 0x8u
bogdanm 0:9b334a45a8ff 1129 #define I2C_C1_TXAK_SHIFT 3
bogdanm 0:9b334a45a8ff 1130 #define I2C_C1_TX_MASK 0x10u
bogdanm 0:9b334a45a8ff 1131 #define I2C_C1_TX_SHIFT 4
bogdanm 0:9b334a45a8ff 1132 #define I2C_C1_MST_MASK 0x20u
bogdanm 0:9b334a45a8ff 1133 #define I2C_C1_MST_SHIFT 5
bogdanm 0:9b334a45a8ff 1134 #define I2C_C1_IICIE_MASK 0x40u
bogdanm 0:9b334a45a8ff 1135 #define I2C_C1_IICIE_SHIFT 6
bogdanm 0:9b334a45a8ff 1136 #define I2C_C1_IICEN_MASK 0x80u
bogdanm 0:9b334a45a8ff 1137 #define I2C_C1_IICEN_SHIFT 7
bogdanm 0:9b334a45a8ff 1138 /* S Bit Fields */
bogdanm 0:9b334a45a8ff 1139 #define I2C_S_RXAK_MASK 0x1u
bogdanm 0:9b334a45a8ff 1140 #define I2C_S_RXAK_SHIFT 0
bogdanm 0:9b334a45a8ff 1141 #define I2C_S_IICIF_MASK 0x2u
bogdanm 0:9b334a45a8ff 1142 #define I2C_S_IICIF_SHIFT 1
bogdanm 0:9b334a45a8ff 1143 #define I2C_S_SRW_MASK 0x4u
bogdanm 0:9b334a45a8ff 1144 #define I2C_S_SRW_SHIFT 2
bogdanm 0:9b334a45a8ff 1145 #define I2C_S_RAM_MASK 0x8u
bogdanm 0:9b334a45a8ff 1146 #define I2C_S_RAM_SHIFT 3
bogdanm 0:9b334a45a8ff 1147 #define I2C_S_ARBL_MASK 0x10u
bogdanm 0:9b334a45a8ff 1148 #define I2C_S_ARBL_SHIFT 4
bogdanm 0:9b334a45a8ff 1149 #define I2C_S_BUSY_MASK 0x20u
bogdanm 0:9b334a45a8ff 1150 #define I2C_S_BUSY_SHIFT 5
bogdanm 0:9b334a45a8ff 1151 #define I2C_S_IAAS_MASK 0x40u
bogdanm 0:9b334a45a8ff 1152 #define I2C_S_IAAS_SHIFT 6
bogdanm 0:9b334a45a8ff 1153 #define I2C_S_TCF_MASK 0x80u
bogdanm 0:9b334a45a8ff 1154 #define I2C_S_TCF_SHIFT 7
bogdanm 0:9b334a45a8ff 1155 /* D Bit Fields */
bogdanm 0:9b334a45a8ff 1156 #define I2C_D_DATA_MASK 0xFFu
bogdanm 0:9b334a45a8ff 1157 #define I2C_D_DATA_SHIFT 0
bogdanm 0:9b334a45a8ff 1158 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
bogdanm 0:9b334a45a8ff 1159 /* C2 Bit Fields */
bogdanm 0:9b334a45a8ff 1160 #define I2C_C2_AD_MASK 0x7u
bogdanm 0:9b334a45a8ff 1161 #define I2C_C2_AD_SHIFT 0
bogdanm 0:9b334a45a8ff 1162 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
bogdanm 0:9b334a45a8ff 1163 #define I2C_C2_RMEN_MASK 0x8u
bogdanm 0:9b334a45a8ff 1164 #define I2C_C2_RMEN_SHIFT 3
bogdanm 0:9b334a45a8ff 1165 #define I2C_C2_SBRC_MASK 0x10u
bogdanm 0:9b334a45a8ff 1166 #define I2C_C2_SBRC_SHIFT 4
bogdanm 0:9b334a45a8ff 1167 #define I2C_C2_HDRS_MASK 0x20u
bogdanm 0:9b334a45a8ff 1168 #define I2C_C2_HDRS_SHIFT 5
bogdanm 0:9b334a45a8ff 1169 #define I2C_C2_ADEXT_MASK 0x40u
bogdanm 0:9b334a45a8ff 1170 #define I2C_C2_ADEXT_SHIFT 6
bogdanm 0:9b334a45a8ff 1171 #define I2C_C2_GCAEN_MASK 0x80u
bogdanm 0:9b334a45a8ff 1172 #define I2C_C2_GCAEN_SHIFT 7
bogdanm 0:9b334a45a8ff 1173 /* FLT Bit Fields */
bogdanm 0:9b334a45a8ff 1174 #define I2C_FLT_FLT_MASK 0x1Fu
bogdanm 0:9b334a45a8ff 1175 #define I2C_FLT_FLT_SHIFT 0
bogdanm 0:9b334a45a8ff 1176 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
bogdanm 0:9b334a45a8ff 1177 #define I2C_FLT_STOPIE_MASK 0x20u
bogdanm 0:9b334a45a8ff 1178 #define I2C_FLT_STOPIE_SHIFT 5
bogdanm 0:9b334a45a8ff 1179 #define I2C_FLT_STOPF_MASK 0x40u
bogdanm 0:9b334a45a8ff 1180 #define I2C_FLT_STOPF_SHIFT 6
bogdanm 0:9b334a45a8ff 1181 #define I2C_FLT_SHEN_MASK 0x80u
bogdanm 0:9b334a45a8ff 1182 #define I2C_FLT_SHEN_SHIFT 7
bogdanm 0:9b334a45a8ff 1183 /* RA Bit Fields */
bogdanm 0:9b334a45a8ff 1184 #define I2C_RA_RAD_MASK 0xFEu
bogdanm 0:9b334a45a8ff 1185 #define I2C_RA_RAD_SHIFT 1
bogdanm 0:9b334a45a8ff 1186 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
bogdanm 0:9b334a45a8ff 1187 /* SMB Bit Fields */
bogdanm 0:9b334a45a8ff 1188 #define I2C_SMB_SHTF2IE_MASK 0x1u
bogdanm 0:9b334a45a8ff 1189 #define I2C_SMB_SHTF2IE_SHIFT 0
bogdanm 0:9b334a45a8ff 1190 #define I2C_SMB_SHTF2_MASK 0x2u
bogdanm 0:9b334a45a8ff 1191 #define I2C_SMB_SHTF2_SHIFT 1
bogdanm 0:9b334a45a8ff 1192 #define I2C_SMB_SHTF1_MASK 0x4u
bogdanm 0:9b334a45a8ff 1193 #define I2C_SMB_SHTF1_SHIFT 2
bogdanm 0:9b334a45a8ff 1194 #define I2C_SMB_SLTF_MASK 0x8u
bogdanm 0:9b334a45a8ff 1195 #define I2C_SMB_SLTF_SHIFT 3
bogdanm 0:9b334a45a8ff 1196 #define I2C_SMB_TCKSEL_MASK 0x10u
bogdanm 0:9b334a45a8ff 1197 #define I2C_SMB_TCKSEL_SHIFT 4
bogdanm 0:9b334a45a8ff 1198 #define I2C_SMB_SIICAEN_MASK 0x20u
bogdanm 0:9b334a45a8ff 1199 #define I2C_SMB_SIICAEN_SHIFT 5
bogdanm 0:9b334a45a8ff 1200 #define I2C_SMB_ALERTEN_MASK 0x40u
bogdanm 0:9b334a45a8ff 1201 #define I2C_SMB_ALERTEN_SHIFT 6
bogdanm 0:9b334a45a8ff 1202 #define I2C_SMB_FACK_MASK 0x80u
bogdanm 0:9b334a45a8ff 1203 #define I2C_SMB_FACK_SHIFT 7
bogdanm 0:9b334a45a8ff 1204 /* A2 Bit Fields */
bogdanm 0:9b334a45a8ff 1205 #define I2C_A2_SAD_MASK 0xFEu
bogdanm 0:9b334a45a8ff 1206 #define I2C_A2_SAD_SHIFT 1
bogdanm 0:9b334a45a8ff 1207 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
bogdanm 0:9b334a45a8ff 1208 /* SLTH Bit Fields */
bogdanm 0:9b334a45a8ff 1209 #define I2C_SLTH_SSLT_MASK 0xFFu
bogdanm 0:9b334a45a8ff 1210 #define I2C_SLTH_SSLT_SHIFT 0
bogdanm 0:9b334a45a8ff 1211 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
bogdanm 0:9b334a45a8ff 1212 /* SLTL Bit Fields */
bogdanm 0:9b334a45a8ff 1213 #define I2C_SLTL_SSLT_MASK 0xFFu
bogdanm 0:9b334a45a8ff 1214 #define I2C_SLTL_SSLT_SHIFT 0
bogdanm 0:9b334a45a8ff 1215 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
bogdanm 0:9b334a45a8ff 1216
bogdanm 0:9b334a45a8ff 1217 /*!
bogdanm 0:9b334a45a8ff 1218 * @}
bogdanm 0:9b334a45a8ff 1219 */ /* end of group I2C_Register_Masks */
bogdanm 0:9b334a45a8ff 1220
bogdanm 0:9b334a45a8ff 1221
bogdanm 0:9b334a45a8ff 1222 /* I2C - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 1223 /** Peripheral I2C0 base address */
bogdanm 0:9b334a45a8ff 1224 #define I2C0_BASE (0x40066000u)
bogdanm 0:9b334a45a8ff 1225 /** Peripheral I2C0 base pointer */
bogdanm 0:9b334a45a8ff 1226 #define I2C0 ((I2C_Type *)I2C0_BASE)
bogdanm 0:9b334a45a8ff 1227 /** Peripheral I2C1 base address */
bogdanm 0:9b334a45a8ff 1228 #define I2C1_BASE (0x40067000u)
bogdanm 0:9b334a45a8ff 1229 /** Peripheral I2C1 base pointer */
bogdanm 0:9b334a45a8ff 1230 #define I2C1 ((I2C_Type *)I2C1_BASE)
bogdanm 0:9b334a45a8ff 1231 /** Array initializer of I2C peripheral base pointers */
bogdanm 0:9b334a45a8ff 1232 #define I2C_BASES { I2C0, I2C1 }
bogdanm 0:9b334a45a8ff 1233
bogdanm 0:9b334a45a8ff 1234 /*!
bogdanm 0:9b334a45a8ff 1235 * @}
bogdanm 0:9b334a45a8ff 1236 */ /* end of group I2C_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 1237
bogdanm 0:9b334a45a8ff 1238
bogdanm 0:9b334a45a8ff 1239 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 1240 -- I2S Peripheral Access Layer
bogdanm 0:9b334a45a8ff 1241 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 1242
bogdanm 0:9b334a45a8ff 1243 /*!
bogdanm 0:9b334a45a8ff 1244 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
bogdanm 0:9b334a45a8ff 1245 * @{
bogdanm 0:9b334a45a8ff 1246 */
bogdanm 0:9b334a45a8ff 1247
bogdanm 0:9b334a45a8ff 1248 /** I2S - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 1249 typedef struct {
bogdanm 0:9b334a45a8ff 1250 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
bogdanm 0:9b334a45a8ff 1251 uint8_t RESERVED_0[4];
bogdanm 0:9b334a45a8ff 1252 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
bogdanm 0:9b334a45a8ff 1253 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
bogdanm 0:9b334a45a8ff 1254 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
bogdanm 0:9b334a45a8ff 1255 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
bogdanm 0:9b334a45a8ff 1256 uint8_t RESERVED_1[8];
bogdanm 0:9b334a45a8ff 1257 __O uint32_t TDR[1]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
bogdanm 0:9b334a45a8ff 1258 uint8_t RESERVED_2[60];
bogdanm 0:9b334a45a8ff 1259 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
bogdanm 0:9b334a45a8ff 1260 uint8_t RESERVED_3[28];
bogdanm 0:9b334a45a8ff 1261 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
bogdanm 0:9b334a45a8ff 1262 uint8_t RESERVED_4[4];
bogdanm 0:9b334a45a8ff 1263 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
bogdanm 0:9b334a45a8ff 1264 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
bogdanm 0:9b334a45a8ff 1265 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
bogdanm 0:9b334a45a8ff 1266 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
bogdanm 0:9b334a45a8ff 1267 uint8_t RESERVED_5[8];
bogdanm 0:9b334a45a8ff 1268 __I uint32_t RDR[1]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
bogdanm 0:9b334a45a8ff 1269 uint8_t RESERVED_6[60];
bogdanm 0:9b334a45a8ff 1270 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
bogdanm 0:9b334a45a8ff 1271 uint8_t RESERVED_7[28];
bogdanm 0:9b334a45a8ff 1272 __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
bogdanm 0:9b334a45a8ff 1273 __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */
bogdanm 0:9b334a45a8ff 1274 } I2S_Type;
bogdanm 0:9b334a45a8ff 1275
bogdanm 0:9b334a45a8ff 1276 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 1277 -- I2S Register Masks
bogdanm 0:9b334a45a8ff 1278 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 1279
bogdanm 0:9b334a45a8ff 1280 /*!
bogdanm 0:9b334a45a8ff 1281 * @addtogroup I2S_Register_Masks I2S Register Masks
bogdanm 0:9b334a45a8ff 1282 * @{
bogdanm 0:9b334a45a8ff 1283 */
bogdanm 0:9b334a45a8ff 1284
bogdanm 0:9b334a45a8ff 1285 /* TCSR Bit Fields */
bogdanm 0:9b334a45a8ff 1286 #define I2S_TCSR_FWDE_MASK 0x2u
bogdanm 0:9b334a45a8ff 1287 #define I2S_TCSR_FWDE_SHIFT 1
bogdanm 0:9b334a45a8ff 1288 #define I2S_TCSR_FWIE_MASK 0x200u
bogdanm 0:9b334a45a8ff 1289 #define I2S_TCSR_FWIE_SHIFT 9
bogdanm 0:9b334a45a8ff 1290 #define I2S_TCSR_FEIE_MASK 0x400u
bogdanm 0:9b334a45a8ff 1291 #define I2S_TCSR_FEIE_SHIFT 10
bogdanm 0:9b334a45a8ff 1292 #define I2S_TCSR_SEIE_MASK 0x800u
bogdanm 0:9b334a45a8ff 1293 #define I2S_TCSR_SEIE_SHIFT 11
bogdanm 0:9b334a45a8ff 1294 #define I2S_TCSR_WSIE_MASK 0x1000u
bogdanm 0:9b334a45a8ff 1295 #define I2S_TCSR_WSIE_SHIFT 12
bogdanm 0:9b334a45a8ff 1296 #define I2S_TCSR_FWF_MASK 0x20000u
bogdanm 0:9b334a45a8ff 1297 #define I2S_TCSR_FWF_SHIFT 17
bogdanm 0:9b334a45a8ff 1298 #define I2S_TCSR_FEF_MASK 0x40000u
bogdanm 0:9b334a45a8ff 1299 #define I2S_TCSR_FEF_SHIFT 18
bogdanm 0:9b334a45a8ff 1300 #define I2S_TCSR_SEF_MASK 0x80000u
bogdanm 0:9b334a45a8ff 1301 #define I2S_TCSR_SEF_SHIFT 19
bogdanm 0:9b334a45a8ff 1302 #define I2S_TCSR_WSF_MASK 0x100000u
bogdanm 0:9b334a45a8ff 1303 #define I2S_TCSR_WSF_SHIFT 20
bogdanm 0:9b334a45a8ff 1304 #define I2S_TCSR_SR_MASK 0x1000000u
bogdanm 0:9b334a45a8ff 1305 #define I2S_TCSR_SR_SHIFT 24
bogdanm 0:9b334a45a8ff 1306 #define I2S_TCSR_FR_MASK 0x2000000u
bogdanm 0:9b334a45a8ff 1307 #define I2S_TCSR_FR_SHIFT 25
bogdanm 0:9b334a45a8ff 1308 #define I2S_TCSR_BCE_MASK 0x10000000u
bogdanm 0:9b334a45a8ff 1309 #define I2S_TCSR_BCE_SHIFT 28
bogdanm 0:9b334a45a8ff 1310 #define I2S_TCSR_DBGE_MASK 0x20000000u
bogdanm 0:9b334a45a8ff 1311 #define I2S_TCSR_DBGE_SHIFT 29
bogdanm 0:9b334a45a8ff 1312 #define I2S_TCSR_STOPE_MASK 0x40000000u
bogdanm 0:9b334a45a8ff 1313 #define I2S_TCSR_STOPE_SHIFT 30
bogdanm 0:9b334a45a8ff 1314 #define I2S_TCSR_TE_MASK 0x80000000u
bogdanm 0:9b334a45a8ff 1315 #define I2S_TCSR_TE_SHIFT 31
bogdanm 0:9b334a45a8ff 1316 /* TCR2 Bit Fields */
bogdanm 0:9b334a45a8ff 1317 #define I2S_TCR2_DIV_MASK 0xFFu
bogdanm 0:9b334a45a8ff 1318 #define I2S_TCR2_DIV_SHIFT 0
bogdanm 0:9b334a45a8ff 1319 #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
bogdanm 0:9b334a45a8ff 1320 #define I2S_TCR2_BCD_MASK 0x1000000u
bogdanm 0:9b334a45a8ff 1321 #define I2S_TCR2_BCD_SHIFT 24
bogdanm 0:9b334a45a8ff 1322 #define I2S_TCR2_BCP_MASK 0x2000000u
bogdanm 0:9b334a45a8ff 1323 #define I2S_TCR2_BCP_SHIFT 25
bogdanm 0:9b334a45a8ff 1324 #define I2S_TCR2_CLKMODE_MASK 0xC000000u
bogdanm 0:9b334a45a8ff 1325 #define I2S_TCR2_CLKMODE_SHIFT 26
bogdanm 0:9b334a45a8ff 1326 #define I2S_TCR2_CLKMODE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_CLKMODE_SHIFT))&I2S_TCR2_CLKMODE_MASK)
bogdanm 0:9b334a45a8ff 1327 /* TCR3 Bit Fields */
bogdanm 0:9b334a45a8ff 1328 #define I2S_TCR3_WDFL_MASK 0x1u
bogdanm 0:9b334a45a8ff 1329 #define I2S_TCR3_WDFL_SHIFT 0
bogdanm 0:9b334a45a8ff 1330 #define I2S_TCR3_TCE_MASK 0x10000u
bogdanm 0:9b334a45a8ff 1331 #define I2S_TCR3_TCE_SHIFT 16
bogdanm 0:9b334a45a8ff 1332 /* TCR4 Bit Fields */
bogdanm 0:9b334a45a8ff 1333 #define I2S_TCR4_FSD_MASK 0x1u
bogdanm 0:9b334a45a8ff 1334 #define I2S_TCR4_FSD_SHIFT 0
bogdanm 0:9b334a45a8ff 1335 #define I2S_TCR4_FSP_MASK 0x2u
bogdanm 0:9b334a45a8ff 1336 #define I2S_TCR4_FSP_SHIFT 1
bogdanm 0:9b334a45a8ff 1337 #define I2S_TCR4_FSE_MASK 0x8u
bogdanm 0:9b334a45a8ff 1338 #define I2S_TCR4_FSE_SHIFT 3
bogdanm 0:9b334a45a8ff 1339 #define I2S_TCR4_MF_MASK 0x10u
bogdanm 0:9b334a45a8ff 1340 #define I2S_TCR4_MF_SHIFT 4
bogdanm 0:9b334a45a8ff 1341 #define I2S_TCR4_SYWD_MASK 0x1F00u
bogdanm 0:9b334a45a8ff 1342 #define I2S_TCR4_SYWD_SHIFT 8
bogdanm 0:9b334a45a8ff 1343 #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
bogdanm 0:9b334a45a8ff 1344 #define I2S_TCR4_FRSZ_MASK 0x10000u
bogdanm 0:9b334a45a8ff 1345 #define I2S_TCR4_FRSZ_SHIFT 16
bogdanm 0:9b334a45a8ff 1346 /* TCR5 Bit Fields */
bogdanm 0:9b334a45a8ff 1347 #define I2S_TCR5_FBT_MASK 0x1F00u
bogdanm 0:9b334a45a8ff 1348 #define I2S_TCR5_FBT_SHIFT 8
bogdanm 0:9b334a45a8ff 1349 #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
bogdanm 0:9b334a45a8ff 1350 #define I2S_TCR5_W0W_MASK 0x1F0000u
bogdanm 0:9b334a45a8ff 1351 #define I2S_TCR5_W0W_SHIFT 16
bogdanm 0:9b334a45a8ff 1352 #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
bogdanm 0:9b334a45a8ff 1353 #define I2S_TCR5_WNW_MASK 0x1F000000u
bogdanm 0:9b334a45a8ff 1354 #define I2S_TCR5_WNW_SHIFT 24
bogdanm 0:9b334a45a8ff 1355 #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
bogdanm 0:9b334a45a8ff 1356 /* TDR Bit Fields */
bogdanm 0:9b334a45a8ff 1357 #define I2S_TDR_TDR_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 1358 #define I2S_TDR_TDR_SHIFT 0
bogdanm 0:9b334a45a8ff 1359 #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
bogdanm 0:9b334a45a8ff 1360 /* TMR Bit Fields */
bogdanm 0:9b334a45a8ff 1361 #define I2S_TMR_TWM_MASK 0x3u
bogdanm 0:9b334a45a8ff 1362 #define I2S_TMR_TWM_SHIFT 0
bogdanm 0:9b334a45a8ff 1363 #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
bogdanm 0:9b334a45a8ff 1364 /* RCSR Bit Fields */
bogdanm 0:9b334a45a8ff 1365 #define I2S_RCSR_FWDE_MASK 0x2u
bogdanm 0:9b334a45a8ff 1366 #define I2S_RCSR_FWDE_SHIFT 1
bogdanm 0:9b334a45a8ff 1367 #define I2S_RCSR_FWIE_MASK 0x200u
bogdanm 0:9b334a45a8ff 1368 #define I2S_RCSR_FWIE_SHIFT 9
bogdanm 0:9b334a45a8ff 1369 #define I2S_RCSR_FEIE_MASK 0x400u
bogdanm 0:9b334a45a8ff 1370 #define I2S_RCSR_FEIE_SHIFT 10
bogdanm 0:9b334a45a8ff 1371 #define I2S_RCSR_SEIE_MASK 0x800u
bogdanm 0:9b334a45a8ff 1372 #define I2S_RCSR_SEIE_SHIFT 11
bogdanm 0:9b334a45a8ff 1373 #define I2S_RCSR_WSIE_MASK 0x1000u
bogdanm 0:9b334a45a8ff 1374 #define I2S_RCSR_WSIE_SHIFT 12
bogdanm 0:9b334a45a8ff 1375 #define I2S_RCSR_FWF_MASK 0x20000u
bogdanm 0:9b334a45a8ff 1376 #define I2S_RCSR_FWF_SHIFT 17
bogdanm 0:9b334a45a8ff 1377 #define I2S_RCSR_FEF_MASK 0x40000u
bogdanm 0:9b334a45a8ff 1378 #define I2S_RCSR_FEF_SHIFT 18
bogdanm 0:9b334a45a8ff 1379 #define I2S_RCSR_SEF_MASK 0x80000u
bogdanm 0:9b334a45a8ff 1380 #define I2S_RCSR_SEF_SHIFT 19
bogdanm 0:9b334a45a8ff 1381 #define I2S_RCSR_WSF_MASK 0x100000u
bogdanm 0:9b334a45a8ff 1382 #define I2S_RCSR_WSF_SHIFT 20
bogdanm 0:9b334a45a8ff 1383 #define I2S_RCSR_SR_MASK 0x1000000u
bogdanm 0:9b334a45a8ff 1384 #define I2S_RCSR_SR_SHIFT 24
bogdanm 0:9b334a45a8ff 1385 #define I2S_RCSR_FR_MASK 0x2000000u
bogdanm 0:9b334a45a8ff 1386 #define I2S_RCSR_FR_SHIFT 25
bogdanm 0:9b334a45a8ff 1387 #define I2S_RCSR_BCE_MASK 0x10000000u
bogdanm 0:9b334a45a8ff 1388 #define I2S_RCSR_BCE_SHIFT 28
bogdanm 0:9b334a45a8ff 1389 #define I2S_RCSR_DBGE_MASK 0x20000000u
bogdanm 0:9b334a45a8ff 1390 #define I2S_RCSR_DBGE_SHIFT 29
bogdanm 0:9b334a45a8ff 1391 #define I2S_RCSR_STOPE_MASK 0x40000000u
bogdanm 0:9b334a45a8ff 1392 #define I2S_RCSR_STOPE_SHIFT 30
bogdanm 0:9b334a45a8ff 1393 #define I2S_RCSR_RE_MASK 0x80000000u
bogdanm 0:9b334a45a8ff 1394 #define I2S_RCSR_RE_SHIFT 31
bogdanm 0:9b334a45a8ff 1395 /* RCR2 Bit Fields */
bogdanm 0:9b334a45a8ff 1396 #define I2S_RCR2_DIV_MASK 0xFFu
bogdanm 0:9b334a45a8ff 1397 #define I2S_RCR2_DIV_SHIFT 0
bogdanm 0:9b334a45a8ff 1398 #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
bogdanm 0:9b334a45a8ff 1399 #define I2S_RCR2_BCD_MASK 0x1000000u
bogdanm 0:9b334a45a8ff 1400 #define I2S_RCR2_BCD_SHIFT 24
bogdanm 0:9b334a45a8ff 1401 #define I2S_RCR2_BCP_MASK 0x2000000u
bogdanm 0:9b334a45a8ff 1402 #define I2S_RCR2_BCP_SHIFT 25
bogdanm 0:9b334a45a8ff 1403 #define I2S_RCR2_CLKMODE_MASK 0xC000000u
bogdanm 0:9b334a45a8ff 1404 #define I2S_RCR2_CLKMODE_SHIFT 26
bogdanm 0:9b334a45a8ff 1405 #define I2S_RCR2_CLKMODE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_CLKMODE_SHIFT))&I2S_RCR2_CLKMODE_MASK)
bogdanm 0:9b334a45a8ff 1406 /* RCR3 Bit Fields */
bogdanm 0:9b334a45a8ff 1407 #define I2S_RCR3_WDFL_MASK 0x1u
bogdanm 0:9b334a45a8ff 1408 #define I2S_RCR3_WDFL_SHIFT 0
bogdanm 0:9b334a45a8ff 1409 #define I2S_RCR3_RCE_MASK 0x10000u
bogdanm 0:9b334a45a8ff 1410 #define I2S_RCR3_RCE_SHIFT 16
bogdanm 0:9b334a45a8ff 1411 /* RCR4 Bit Fields */
bogdanm 0:9b334a45a8ff 1412 #define I2S_RCR4_FSD_MASK 0x1u
bogdanm 0:9b334a45a8ff 1413 #define I2S_RCR4_FSD_SHIFT 0
bogdanm 0:9b334a45a8ff 1414 #define I2S_RCR4_FSP_MASK 0x2u
bogdanm 0:9b334a45a8ff 1415 #define I2S_RCR4_FSP_SHIFT 1
bogdanm 0:9b334a45a8ff 1416 #define I2S_RCR4_FSE_MASK 0x8u
bogdanm 0:9b334a45a8ff 1417 #define I2S_RCR4_FSE_SHIFT 3
bogdanm 0:9b334a45a8ff 1418 #define I2S_RCR4_MF_MASK 0x10u
bogdanm 0:9b334a45a8ff 1419 #define I2S_RCR4_MF_SHIFT 4
bogdanm 0:9b334a45a8ff 1420 #define I2S_RCR4_SYWD_MASK 0x1F00u
bogdanm 0:9b334a45a8ff 1421 #define I2S_RCR4_SYWD_SHIFT 8
bogdanm 0:9b334a45a8ff 1422 #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
bogdanm 0:9b334a45a8ff 1423 #define I2S_RCR4_FRSZ_MASK 0x10000u
bogdanm 0:9b334a45a8ff 1424 #define I2S_RCR4_FRSZ_SHIFT 16
bogdanm 0:9b334a45a8ff 1425 /* RCR5 Bit Fields */
bogdanm 0:9b334a45a8ff 1426 #define I2S_RCR5_FBT_MASK 0x1F00u
bogdanm 0:9b334a45a8ff 1427 #define I2S_RCR5_FBT_SHIFT 8
bogdanm 0:9b334a45a8ff 1428 #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
bogdanm 0:9b334a45a8ff 1429 #define I2S_RCR5_W0W_MASK 0x1F0000u
bogdanm 0:9b334a45a8ff 1430 #define I2S_RCR5_W0W_SHIFT 16
bogdanm 0:9b334a45a8ff 1431 #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
bogdanm 0:9b334a45a8ff 1432 #define I2S_RCR5_WNW_MASK 0x1F000000u
bogdanm 0:9b334a45a8ff 1433 #define I2S_RCR5_WNW_SHIFT 24
bogdanm 0:9b334a45a8ff 1434 #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
bogdanm 0:9b334a45a8ff 1435 /* RDR Bit Fields */
bogdanm 0:9b334a45a8ff 1436 #define I2S_RDR_RDR_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 1437 #define I2S_RDR_RDR_SHIFT 0
bogdanm 0:9b334a45a8ff 1438 #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
bogdanm 0:9b334a45a8ff 1439 /* RMR Bit Fields */
bogdanm 0:9b334a45a8ff 1440 #define I2S_RMR_RWM_MASK 0x3u
bogdanm 0:9b334a45a8ff 1441 #define I2S_RMR_RWM_SHIFT 0
bogdanm 0:9b334a45a8ff 1442 #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
bogdanm 0:9b334a45a8ff 1443 /* MCR Bit Fields */
bogdanm 0:9b334a45a8ff 1444 #define I2S_MCR_MICS_MASK 0x3000000u
bogdanm 0:9b334a45a8ff 1445 #define I2S_MCR_MICS_SHIFT 24
bogdanm 0:9b334a45a8ff 1446 #define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
bogdanm 0:9b334a45a8ff 1447 #define I2S_MCR_MOE_MASK 0x40000000u
bogdanm 0:9b334a45a8ff 1448 #define I2S_MCR_MOE_SHIFT 30
bogdanm 0:9b334a45a8ff 1449 #define I2S_MCR_DUF_MASK 0x80000000u
bogdanm 0:9b334a45a8ff 1450 #define I2S_MCR_DUF_SHIFT 31
bogdanm 0:9b334a45a8ff 1451 /* MDR Bit Fields */
bogdanm 0:9b334a45a8ff 1452 #define I2S_MDR_DIVIDE_MASK 0xFFFu
bogdanm 0:9b334a45a8ff 1453 #define I2S_MDR_DIVIDE_SHIFT 0
bogdanm 0:9b334a45a8ff 1454 #define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
bogdanm 0:9b334a45a8ff 1455 #define I2S_MDR_FRACT_MASK 0xFF000u
bogdanm 0:9b334a45a8ff 1456 #define I2S_MDR_FRACT_SHIFT 12
bogdanm 0:9b334a45a8ff 1457 #define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
bogdanm 0:9b334a45a8ff 1458
bogdanm 0:9b334a45a8ff 1459 /*!
bogdanm 0:9b334a45a8ff 1460 * @}
bogdanm 0:9b334a45a8ff 1461 */ /* end of group I2S_Register_Masks */
bogdanm 0:9b334a45a8ff 1462
bogdanm 0:9b334a45a8ff 1463
bogdanm 0:9b334a45a8ff 1464 /* I2S - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 1465 /** Peripheral I2S0 base address */
bogdanm 0:9b334a45a8ff 1466 #define I2S0_BASE (0x4002F000u)
bogdanm 0:9b334a45a8ff 1467 /** Peripheral I2S0 base pointer */
bogdanm 0:9b334a45a8ff 1468 #define I2S0 ((I2S_Type *)I2S0_BASE)
bogdanm 0:9b334a45a8ff 1469 /** Array initializer of I2S peripheral base pointers */
bogdanm 0:9b334a45a8ff 1470 #define I2S_BASES { I2S0 }
bogdanm 0:9b334a45a8ff 1471
bogdanm 0:9b334a45a8ff 1472 /*!
bogdanm 0:9b334a45a8ff 1473 * @}
bogdanm 0:9b334a45a8ff 1474 */ /* end of group I2S_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 1475
bogdanm 0:9b334a45a8ff 1476
bogdanm 0:9b334a45a8ff 1477 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 1478 -- LCD Peripheral Access Layer
bogdanm 0:9b334a45a8ff 1479 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 1480
bogdanm 0:9b334a45a8ff 1481 /*!
bogdanm 0:9b334a45a8ff 1482 * @addtogroup LCD_Peripheral_Access_Layer LCD Peripheral Access Layer
bogdanm 0:9b334a45a8ff 1483 * @{
bogdanm 0:9b334a45a8ff 1484 */
bogdanm 0:9b334a45a8ff 1485
bogdanm 0:9b334a45a8ff 1486 /** LCD - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 1487 typedef struct {
bogdanm 0:9b334a45a8ff 1488 __IO uint32_t GCR; /**< LCD General Control Register, offset: 0x0 */
bogdanm 0:9b334a45a8ff 1489 __IO uint32_t AR; /**< LCD Auxiliary Register, offset: 0x4 */
bogdanm 0:9b334a45a8ff 1490 __IO uint32_t FDCR; /**< LCD Fault Detect Control Register, offset: 0x8 */
bogdanm 0:9b334a45a8ff 1491 __IO uint32_t FDSR; /**< LCD Fault Detect Status Register, offset: 0xC */
bogdanm 0:9b334a45a8ff 1492 __IO uint32_t PEN[2]; /**< LCD Pin Enable register, array offset: 0x10, array step: 0x4 */
bogdanm 0:9b334a45a8ff 1493 __IO uint32_t BPEN[2]; /**< LCD Back Plane Enable register, array offset: 0x18, array step: 0x4 */
bogdanm 0:9b334a45a8ff 1494 union { /* offset: 0x20 */
bogdanm 0:9b334a45a8ff 1495 __IO uint32_t WF[16]; /**< LCD Waveform register, array offset: 0x20, array step: 0x4 */
bogdanm 0:9b334a45a8ff 1496 __IO uint8_t WF8B[64]; /**< LCD Waveform Register 0...LCD Waveform Register 63., array offset: 0x20, array step: 0x1 */
bogdanm 0:9b334a45a8ff 1497 };
bogdanm 0:9b334a45a8ff 1498 } LCD_Type;
bogdanm 0:9b334a45a8ff 1499
bogdanm 0:9b334a45a8ff 1500 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 1501 -- LCD Register Masks
bogdanm 0:9b334a45a8ff 1502 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 1503
bogdanm 0:9b334a45a8ff 1504 /*!
bogdanm 0:9b334a45a8ff 1505 * @addtogroup LCD_Register_Masks LCD Register Masks
bogdanm 0:9b334a45a8ff 1506 * @{
bogdanm 0:9b334a45a8ff 1507 */
bogdanm 0:9b334a45a8ff 1508
bogdanm 0:9b334a45a8ff 1509 /* GCR Bit Fields */
bogdanm 0:9b334a45a8ff 1510 #define LCD_GCR_DUTY_MASK 0x7u
bogdanm 0:9b334a45a8ff 1511 #define LCD_GCR_DUTY_SHIFT 0
bogdanm 0:9b334a45a8ff 1512 #define LCD_GCR_DUTY(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_DUTY_SHIFT))&LCD_GCR_DUTY_MASK)
bogdanm 0:9b334a45a8ff 1513 #define LCD_GCR_LCLK_MASK 0x38u
bogdanm 0:9b334a45a8ff 1514 #define LCD_GCR_LCLK_SHIFT 3
bogdanm 0:9b334a45a8ff 1515 #define LCD_GCR_LCLK(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_LCLK_SHIFT))&LCD_GCR_LCLK_MASK)
bogdanm 0:9b334a45a8ff 1516 #define LCD_GCR_SOURCE_MASK 0x40u
bogdanm 0:9b334a45a8ff 1517 #define LCD_GCR_SOURCE_SHIFT 6
bogdanm 0:9b334a45a8ff 1518 #define LCD_GCR_LCDEN_MASK 0x80u
bogdanm 0:9b334a45a8ff 1519 #define LCD_GCR_LCDEN_SHIFT 7
bogdanm 0:9b334a45a8ff 1520 #define LCD_GCR_LCDSTP_MASK 0x100u
bogdanm 0:9b334a45a8ff 1521 #define LCD_GCR_LCDSTP_SHIFT 8
bogdanm 0:9b334a45a8ff 1522 #define LCD_GCR_LCDDOZE_MASK 0x200u
bogdanm 0:9b334a45a8ff 1523 #define LCD_GCR_LCDDOZE_SHIFT 9
bogdanm 0:9b334a45a8ff 1524 #define LCD_GCR_FFR_MASK 0x400u
bogdanm 0:9b334a45a8ff 1525 #define LCD_GCR_FFR_SHIFT 10
bogdanm 0:9b334a45a8ff 1526 #define LCD_GCR_ALTSOURCE_MASK 0x800u
bogdanm 0:9b334a45a8ff 1527 #define LCD_GCR_ALTSOURCE_SHIFT 11
bogdanm 0:9b334a45a8ff 1528 #define LCD_GCR_ALTDIV_MASK 0x3000u
bogdanm 0:9b334a45a8ff 1529 #define LCD_GCR_ALTDIV_SHIFT 12
bogdanm 0:9b334a45a8ff 1530 #define LCD_GCR_ALTDIV(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_ALTDIV_SHIFT))&LCD_GCR_ALTDIV_MASK)
bogdanm 0:9b334a45a8ff 1531 #define LCD_GCR_FDCIEN_MASK 0x4000u
bogdanm 0:9b334a45a8ff 1532 #define LCD_GCR_FDCIEN_SHIFT 14
bogdanm 0:9b334a45a8ff 1533 #define LCD_GCR_PADSAFE_MASK 0x8000u
bogdanm 0:9b334a45a8ff 1534 #define LCD_GCR_PADSAFE_SHIFT 15
bogdanm 0:9b334a45a8ff 1535 #define LCD_GCR_VSUPPLY_MASK 0x20000u
bogdanm 0:9b334a45a8ff 1536 #define LCD_GCR_VSUPPLY_SHIFT 17
bogdanm 0:9b334a45a8ff 1537 #define LCD_GCR_LADJ_MASK 0x300000u
bogdanm 0:9b334a45a8ff 1538 #define LCD_GCR_LADJ_SHIFT 20
bogdanm 0:9b334a45a8ff 1539 #define LCD_GCR_LADJ(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_LADJ_SHIFT))&LCD_GCR_LADJ_MASK)
bogdanm 0:9b334a45a8ff 1540 #define LCD_GCR_CPSEL_MASK 0x800000u
bogdanm 0:9b334a45a8ff 1541 #define LCD_GCR_CPSEL_SHIFT 23
bogdanm 0:9b334a45a8ff 1542 #define LCD_GCR_RVTRIM_MASK 0xF000000u
bogdanm 0:9b334a45a8ff 1543 #define LCD_GCR_RVTRIM_SHIFT 24
bogdanm 0:9b334a45a8ff 1544 #define LCD_GCR_RVTRIM(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_RVTRIM_SHIFT))&LCD_GCR_RVTRIM_MASK)
bogdanm 0:9b334a45a8ff 1545 #define LCD_GCR_RVEN_MASK 0x80000000u
bogdanm 0:9b334a45a8ff 1546 #define LCD_GCR_RVEN_SHIFT 31
bogdanm 0:9b334a45a8ff 1547 /* AR Bit Fields */
bogdanm 0:9b334a45a8ff 1548 #define LCD_AR_BRATE_MASK 0x7u
bogdanm 0:9b334a45a8ff 1549 #define LCD_AR_BRATE_SHIFT 0
bogdanm 0:9b334a45a8ff 1550 #define LCD_AR_BRATE(x) (((uint32_t)(((uint32_t)(x))<<LCD_AR_BRATE_SHIFT))&LCD_AR_BRATE_MASK)
bogdanm 0:9b334a45a8ff 1551 #define LCD_AR_BMODE_MASK 0x8u
bogdanm 0:9b334a45a8ff 1552 #define LCD_AR_BMODE_SHIFT 3
bogdanm 0:9b334a45a8ff 1553 #define LCD_AR_BLANK_MASK 0x20u
bogdanm 0:9b334a45a8ff 1554 #define LCD_AR_BLANK_SHIFT 5
bogdanm 0:9b334a45a8ff 1555 #define LCD_AR_ALT_MASK 0x40u
bogdanm 0:9b334a45a8ff 1556 #define LCD_AR_ALT_SHIFT 6
bogdanm 0:9b334a45a8ff 1557 #define LCD_AR_BLINK_MASK 0x80u
bogdanm 0:9b334a45a8ff 1558 #define LCD_AR_BLINK_SHIFT 7
bogdanm 0:9b334a45a8ff 1559 /* FDCR Bit Fields */
bogdanm 0:9b334a45a8ff 1560 #define LCD_FDCR_FDPINID_MASK 0x3Fu
bogdanm 0:9b334a45a8ff 1561 #define LCD_FDCR_FDPINID_SHIFT 0
bogdanm 0:9b334a45a8ff 1562 #define LCD_FDCR_FDPINID(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDPINID_SHIFT))&LCD_FDCR_FDPINID_MASK)
bogdanm 0:9b334a45a8ff 1563 #define LCD_FDCR_FDBPEN_MASK 0x40u
bogdanm 0:9b334a45a8ff 1564 #define LCD_FDCR_FDBPEN_SHIFT 6
bogdanm 0:9b334a45a8ff 1565 #define LCD_FDCR_FDEN_MASK 0x80u
bogdanm 0:9b334a45a8ff 1566 #define LCD_FDCR_FDEN_SHIFT 7
bogdanm 0:9b334a45a8ff 1567 #define LCD_FDCR_FDSWW_MASK 0xE00u
bogdanm 0:9b334a45a8ff 1568 #define LCD_FDCR_FDSWW_SHIFT 9
bogdanm 0:9b334a45a8ff 1569 #define LCD_FDCR_FDSWW(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDSWW_SHIFT))&LCD_FDCR_FDSWW_MASK)
bogdanm 0:9b334a45a8ff 1570 #define LCD_FDCR_FDPRS_MASK 0x7000u
bogdanm 0:9b334a45a8ff 1571 #define LCD_FDCR_FDPRS_SHIFT 12
bogdanm 0:9b334a45a8ff 1572 #define LCD_FDCR_FDPRS(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDPRS_SHIFT))&LCD_FDCR_FDPRS_MASK)
bogdanm 0:9b334a45a8ff 1573 /* FDSR Bit Fields */
bogdanm 0:9b334a45a8ff 1574 #define LCD_FDSR_FDCNT_MASK 0xFFu
bogdanm 0:9b334a45a8ff 1575 #define LCD_FDSR_FDCNT_SHIFT 0
bogdanm 0:9b334a45a8ff 1576 #define LCD_FDSR_FDCNT(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDSR_FDCNT_SHIFT))&LCD_FDSR_FDCNT_MASK)
bogdanm 0:9b334a45a8ff 1577 #define LCD_FDSR_FDCF_MASK 0x8000u
bogdanm 0:9b334a45a8ff 1578 #define LCD_FDSR_FDCF_SHIFT 15
bogdanm 0:9b334a45a8ff 1579 /* PEN Bit Fields */
bogdanm 0:9b334a45a8ff 1580 #define LCD_PEN_PEN_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 1581 #define LCD_PEN_PEN_SHIFT 0
bogdanm 0:9b334a45a8ff 1582 #define LCD_PEN_PEN(x) (((uint32_t)(((uint32_t)(x))<<LCD_PEN_PEN_SHIFT))&LCD_PEN_PEN_MASK)
bogdanm 0:9b334a45a8ff 1583 /* BPEN Bit Fields */
bogdanm 0:9b334a45a8ff 1584 #define LCD_BPEN_BPEN_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 1585 #define LCD_BPEN_BPEN_SHIFT 0
bogdanm 0:9b334a45a8ff 1586 #define LCD_BPEN_BPEN(x) (((uint32_t)(((uint32_t)(x))<<LCD_BPEN_BPEN_SHIFT))&LCD_BPEN_BPEN_MASK)
bogdanm 0:9b334a45a8ff 1587 /* WF Bit Fields */
bogdanm 0:9b334a45a8ff 1588 #define LCD_WF_WF0_MASK 0xFFu
bogdanm 0:9b334a45a8ff 1589 #define LCD_WF_WF0_SHIFT 0
bogdanm 0:9b334a45a8ff 1590 #define LCD_WF_WF0(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF0_SHIFT))&LCD_WF_WF0_MASK)
bogdanm 0:9b334a45a8ff 1591 #define LCD_WF_WF60_MASK 0xFFu
bogdanm 0:9b334a45a8ff 1592 #define LCD_WF_WF60_SHIFT 0
bogdanm 0:9b334a45a8ff 1593 #define LCD_WF_WF60(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF60_SHIFT))&LCD_WF_WF60_MASK)
bogdanm 0:9b334a45a8ff 1594 #define LCD_WF_WF56_MASK 0xFFu
bogdanm 0:9b334a45a8ff 1595 #define LCD_WF_WF56_SHIFT 0
bogdanm 0:9b334a45a8ff 1596 #define LCD_WF_WF56(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF56_SHIFT))&LCD_WF_WF56_MASK)
bogdanm 0:9b334a45a8ff 1597 #define LCD_WF_WF52_MASK 0xFFu
bogdanm 0:9b334a45a8ff 1598 #define LCD_WF_WF52_SHIFT 0
bogdanm 0:9b334a45a8ff 1599 #define LCD_WF_WF52(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF52_SHIFT))&LCD_WF_WF52_MASK)
bogdanm 0:9b334a45a8ff 1600 #define LCD_WF_WF4_MASK 0xFFu
bogdanm 0:9b334a45a8ff 1601 #define LCD_WF_WF4_SHIFT 0
bogdanm 0:9b334a45a8ff 1602 #define LCD_WF_WF4(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF4_SHIFT))&LCD_WF_WF4_MASK)
bogdanm 0:9b334a45a8ff 1603 #define LCD_WF_WF48_MASK 0xFFu
bogdanm 0:9b334a45a8ff 1604 #define LCD_WF_WF48_SHIFT 0
bogdanm 0:9b334a45a8ff 1605 #define LCD_WF_WF48(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF48_SHIFT))&LCD_WF_WF48_MASK)
bogdanm 0:9b334a45a8ff 1606 #define LCD_WF_WF44_MASK 0xFFu
bogdanm 0:9b334a45a8ff 1607 #define LCD_WF_WF44_SHIFT 0
bogdanm 0:9b334a45a8ff 1608 #define LCD_WF_WF44(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF44_SHIFT))&LCD_WF_WF44_MASK)
bogdanm 0:9b334a45a8ff 1609 #define LCD_WF_WF40_MASK 0xFFu
bogdanm 0:9b334a45a8ff 1610 #define LCD_WF_WF40_SHIFT 0
bogdanm 0:9b334a45a8ff 1611 #define LCD_WF_WF40(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF40_SHIFT))&LCD_WF_WF40_MASK)
bogdanm 0:9b334a45a8ff 1612 #define LCD_WF_WF8_MASK 0xFFu
bogdanm 0:9b334a45a8ff 1613 #define LCD_WF_WF8_SHIFT 0
bogdanm 0:9b334a45a8ff 1614 #define LCD_WF_WF8(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF8_SHIFT))&LCD_WF_WF8_MASK)
bogdanm 0:9b334a45a8ff 1615 #define LCD_WF_WF36_MASK 0xFFu
bogdanm 0:9b334a45a8ff 1616 #define LCD_WF_WF36_SHIFT 0
bogdanm 0:9b334a45a8ff 1617 #define LCD_WF_WF36(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF36_SHIFT))&LCD_WF_WF36_MASK)
bogdanm 0:9b334a45a8ff 1618 #define LCD_WF_WF32_MASK 0xFFu
bogdanm 0:9b334a45a8ff 1619 #define LCD_WF_WF32_SHIFT 0
bogdanm 0:9b334a45a8ff 1620 #define LCD_WF_WF32(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF32_SHIFT))&LCD_WF_WF32_MASK)
bogdanm 0:9b334a45a8ff 1621 #define LCD_WF_WF28_MASK 0xFFu
bogdanm 0:9b334a45a8ff 1622 #define LCD_WF_WF28_SHIFT 0
bogdanm 0:9b334a45a8ff 1623 #define LCD_WF_WF28(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF28_SHIFT))&LCD_WF_WF28_MASK)
bogdanm 0:9b334a45a8ff 1624 #define LCD_WF_WF12_MASK 0xFFu
bogdanm 0:9b334a45a8ff 1625 #define LCD_WF_WF12_SHIFT 0
bogdanm 0:9b334a45a8ff 1626 #define LCD_WF_WF12(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF12_SHIFT))&LCD_WF_WF12_MASK)
bogdanm 0:9b334a45a8ff 1627 #define LCD_WF_WF24_MASK 0xFFu
bogdanm 0:9b334a45a8ff 1628 #define LCD_WF_WF24_SHIFT 0
bogdanm 0:9b334a45a8ff 1629 #define LCD_WF_WF24(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF24_SHIFT))&LCD_WF_WF24_MASK)
bogdanm 0:9b334a45a8ff 1630 #define LCD_WF_WF20_MASK 0xFFu
bogdanm 0:9b334a45a8ff 1631 #define LCD_WF_WF20_SHIFT 0
bogdanm 0:9b334a45a8ff 1632 #define LCD_WF_WF20(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF20_SHIFT))&LCD_WF_WF20_MASK)
bogdanm 0:9b334a45a8ff 1633 #define LCD_WF_WF16_MASK 0xFFu
bogdanm 0:9b334a45a8ff 1634 #define LCD_WF_WF16_SHIFT 0
bogdanm 0:9b334a45a8ff 1635 #define LCD_WF_WF16(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF16_SHIFT))&LCD_WF_WF16_MASK)
bogdanm 0:9b334a45a8ff 1636 #define LCD_WF_WF5_MASK 0xFF00u
bogdanm 0:9b334a45a8ff 1637 #define LCD_WF_WF5_SHIFT 8
bogdanm 0:9b334a45a8ff 1638 #define LCD_WF_WF5(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF5_SHIFT))&LCD_WF_WF5_MASK)
bogdanm 0:9b334a45a8ff 1639 #define LCD_WF_WF49_MASK 0xFF00u
bogdanm 0:9b334a45a8ff 1640 #define LCD_WF_WF49_SHIFT 8
bogdanm 0:9b334a45a8ff 1641 #define LCD_WF_WF49(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF49_SHIFT))&LCD_WF_WF49_MASK)
bogdanm 0:9b334a45a8ff 1642 #define LCD_WF_WF45_MASK 0xFF00u
bogdanm 0:9b334a45a8ff 1643 #define LCD_WF_WF45_SHIFT 8
bogdanm 0:9b334a45a8ff 1644 #define LCD_WF_WF45(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF45_SHIFT))&LCD_WF_WF45_MASK)
bogdanm 0:9b334a45a8ff 1645 #define LCD_WF_WF61_MASK 0xFF00u
bogdanm 0:9b334a45a8ff 1646 #define LCD_WF_WF61_SHIFT 8
bogdanm 0:9b334a45a8ff 1647 #define LCD_WF_WF61(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF61_SHIFT))&LCD_WF_WF61_MASK)
bogdanm 0:9b334a45a8ff 1648 #define LCD_WF_WF25_MASK 0xFF00u
bogdanm 0:9b334a45a8ff 1649 #define LCD_WF_WF25_SHIFT 8
bogdanm 0:9b334a45a8ff 1650 #define LCD_WF_WF25(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF25_SHIFT))&LCD_WF_WF25_MASK)
bogdanm 0:9b334a45a8ff 1651 #define LCD_WF_WF17_MASK 0xFF00u
bogdanm 0:9b334a45a8ff 1652 #define LCD_WF_WF17_SHIFT 8
bogdanm 0:9b334a45a8ff 1653 #define LCD_WF_WF17(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF17_SHIFT))&LCD_WF_WF17_MASK)
bogdanm 0:9b334a45a8ff 1654 #define LCD_WF_WF41_MASK 0xFF00u
bogdanm 0:9b334a45a8ff 1655 #define LCD_WF_WF41_SHIFT 8
bogdanm 0:9b334a45a8ff 1656 #define LCD_WF_WF41(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF41_SHIFT))&LCD_WF_WF41_MASK)
bogdanm 0:9b334a45a8ff 1657 #define LCD_WF_WF13_MASK 0xFF00u
bogdanm 0:9b334a45a8ff 1658 #define LCD_WF_WF13_SHIFT 8
bogdanm 0:9b334a45a8ff 1659 #define LCD_WF_WF13(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF13_SHIFT))&LCD_WF_WF13_MASK)
bogdanm 0:9b334a45a8ff 1660 #define LCD_WF_WF57_MASK 0xFF00u
bogdanm 0:9b334a45a8ff 1661 #define LCD_WF_WF57_SHIFT 8
bogdanm 0:9b334a45a8ff 1662 #define LCD_WF_WF57(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF57_SHIFT))&LCD_WF_WF57_MASK)
bogdanm 0:9b334a45a8ff 1663 #define LCD_WF_WF53_MASK 0xFF00u
bogdanm 0:9b334a45a8ff 1664 #define LCD_WF_WF53_SHIFT 8
bogdanm 0:9b334a45a8ff 1665 #define LCD_WF_WF53(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF53_SHIFT))&LCD_WF_WF53_MASK)
bogdanm 0:9b334a45a8ff 1666 #define LCD_WF_WF37_MASK 0xFF00u
bogdanm 0:9b334a45a8ff 1667 #define LCD_WF_WF37_SHIFT 8
bogdanm 0:9b334a45a8ff 1668 #define LCD_WF_WF37(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF37_SHIFT))&LCD_WF_WF37_MASK)
bogdanm 0:9b334a45a8ff 1669 #define LCD_WF_WF9_MASK 0xFF00u
bogdanm 0:9b334a45a8ff 1670 #define LCD_WF_WF9_SHIFT 8
bogdanm 0:9b334a45a8ff 1671 #define LCD_WF_WF9(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF9_SHIFT))&LCD_WF_WF9_MASK)
bogdanm 0:9b334a45a8ff 1672 #define LCD_WF_WF1_MASK 0xFF00u
bogdanm 0:9b334a45a8ff 1673 #define LCD_WF_WF1_SHIFT 8
bogdanm 0:9b334a45a8ff 1674 #define LCD_WF_WF1(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF1_SHIFT))&LCD_WF_WF1_MASK)
bogdanm 0:9b334a45a8ff 1675 #define LCD_WF_WF29_MASK 0xFF00u
bogdanm 0:9b334a45a8ff 1676 #define LCD_WF_WF29_SHIFT 8
bogdanm 0:9b334a45a8ff 1677 #define LCD_WF_WF29(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF29_SHIFT))&LCD_WF_WF29_MASK)
bogdanm 0:9b334a45a8ff 1678 #define LCD_WF_WF33_MASK 0xFF00u
bogdanm 0:9b334a45a8ff 1679 #define LCD_WF_WF33_SHIFT 8
bogdanm 0:9b334a45a8ff 1680 #define LCD_WF_WF33(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF33_SHIFT))&LCD_WF_WF33_MASK)
bogdanm 0:9b334a45a8ff 1681 #define LCD_WF_WF21_MASK 0xFF00u
bogdanm 0:9b334a45a8ff 1682 #define LCD_WF_WF21_SHIFT 8
bogdanm 0:9b334a45a8ff 1683 #define LCD_WF_WF21(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF21_SHIFT))&LCD_WF_WF21_MASK)
bogdanm 0:9b334a45a8ff 1684 #define LCD_WF_WF26_MASK 0xFF0000u
bogdanm 0:9b334a45a8ff 1685 #define LCD_WF_WF26_SHIFT 16
bogdanm 0:9b334a45a8ff 1686 #define LCD_WF_WF26(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF26_SHIFT))&LCD_WF_WF26_MASK)
bogdanm 0:9b334a45a8ff 1687 #define LCD_WF_WF46_MASK 0xFF0000u
bogdanm 0:9b334a45a8ff 1688 #define LCD_WF_WF46_SHIFT 16
bogdanm 0:9b334a45a8ff 1689 #define LCD_WF_WF46(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF46_SHIFT))&LCD_WF_WF46_MASK)
bogdanm 0:9b334a45a8ff 1690 #define LCD_WF_WF6_MASK 0xFF0000u
bogdanm 0:9b334a45a8ff 1691 #define LCD_WF_WF6_SHIFT 16
bogdanm 0:9b334a45a8ff 1692 #define LCD_WF_WF6(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF6_SHIFT))&LCD_WF_WF6_MASK)
bogdanm 0:9b334a45a8ff 1693 #define LCD_WF_WF42_MASK 0xFF0000u
bogdanm 0:9b334a45a8ff 1694 #define LCD_WF_WF42_SHIFT 16
bogdanm 0:9b334a45a8ff 1695 #define LCD_WF_WF42(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF42_SHIFT))&LCD_WF_WF42_MASK)
bogdanm 0:9b334a45a8ff 1696 #define LCD_WF_WF18_MASK 0xFF0000u
bogdanm 0:9b334a45a8ff 1697 #define LCD_WF_WF18_SHIFT 16
bogdanm 0:9b334a45a8ff 1698 #define LCD_WF_WF18(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF18_SHIFT))&LCD_WF_WF18_MASK)
bogdanm 0:9b334a45a8ff 1699 #define LCD_WF_WF38_MASK 0xFF0000u
bogdanm 0:9b334a45a8ff 1700 #define LCD_WF_WF38_SHIFT 16
bogdanm 0:9b334a45a8ff 1701 #define LCD_WF_WF38(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF38_SHIFT))&LCD_WF_WF38_MASK)
bogdanm 0:9b334a45a8ff 1702 #define LCD_WF_WF22_MASK 0xFF0000u
bogdanm 0:9b334a45a8ff 1703 #define LCD_WF_WF22_SHIFT 16
bogdanm 0:9b334a45a8ff 1704 #define LCD_WF_WF22(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF22_SHIFT))&LCD_WF_WF22_MASK)
bogdanm 0:9b334a45a8ff 1705 #define LCD_WF_WF34_MASK 0xFF0000u
bogdanm 0:9b334a45a8ff 1706 #define LCD_WF_WF34_SHIFT 16
bogdanm 0:9b334a45a8ff 1707 #define LCD_WF_WF34(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF34_SHIFT))&LCD_WF_WF34_MASK)
bogdanm 0:9b334a45a8ff 1708 #define LCD_WF_WF50_MASK 0xFF0000u
bogdanm 0:9b334a45a8ff 1709 #define LCD_WF_WF50_SHIFT 16
bogdanm 0:9b334a45a8ff 1710 #define LCD_WF_WF50(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF50_SHIFT))&LCD_WF_WF50_MASK)
bogdanm 0:9b334a45a8ff 1711 #define LCD_WF_WF14_MASK 0xFF0000u
bogdanm 0:9b334a45a8ff 1712 #define LCD_WF_WF14_SHIFT 16
bogdanm 0:9b334a45a8ff 1713 #define LCD_WF_WF14(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF14_SHIFT))&LCD_WF_WF14_MASK)
bogdanm 0:9b334a45a8ff 1714 #define LCD_WF_WF54_MASK 0xFF0000u
bogdanm 0:9b334a45a8ff 1715 #define LCD_WF_WF54_SHIFT 16
bogdanm 0:9b334a45a8ff 1716 #define LCD_WF_WF54(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF54_SHIFT))&LCD_WF_WF54_MASK)
bogdanm 0:9b334a45a8ff 1717 #define LCD_WF_WF2_MASK 0xFF0000u
bogdanm 0:9b334a45a8ff 1718 #define LCD_WF_WF2_SHIFT 16
bogdanm 0:9b334a45a8ff 1719 #define LCD_WF_WF2(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF2_SHIFT))&LCD_WF_WF2_MASK)
bogdanm 0:9b334a45a8ff 1720 #define LCD_WF_WF58_MASK 0xFF0000u
bogdanm 0:9b334a45a8ff 1721 #define LCD_WF_WF58_SHIFT 16
bogdanm 0:9b334a45a8ff 1722 #define LCD_WF_WF58(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF58_SHIFT))&LCD_WF_WF58_MASK)
bogdanm 0:9b334a45a8ff 1723 #define LCD_WF_WF30_MASK 0xFF0000u
bogdanm 0:9b334a45a8ff 1724 #define LCD_WF_WF30_SHIFT 16
bogdanm 0:9b334a45a8ff 1725 #define LCD_WF_WF30(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF30_SHIFT))&LCD_WF_WF30_MASK)
bogdanm 0:9b334a45a8ff 1726 #define LCD_WF_WF62_MASK 0xFF0000u
bogdanm 0:9b334a45a8ff 1727 #define LCD_WF_WF62_SHIFT 16
bogdanm 0:9b334a45a8ff 1728 #define LCD_WF_WF62(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF62_SHIFT))&LCD_WF_WF62_MASK)
bogdanm 0:9b334a45a8ff 1729 #define LCD_WF_WF10_MASK 0xFF0000u
bogdanm 0:9b334a45a8ff 1730 #define LCD_WF_WF10_SHIFT 16
bogdanm 0:9b334a45a8ff 1731 #define LCD_WF_WF10(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF10_SHIFT))&LCD_WF_WF10_MASK)
bogdanm 0:9b334a45a8ff 1732 #define LCD_WF_WF63_MASK 0xFF000000u
bogdanm 0:9b334a45a8ff 1733 #define LCD_WF_WF63_SHIFT 24
bogdanm 0:9b334a45a8ff 1734 #define LCD_WF_WF63(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF63_SHIFT))&LCD_WF_WF63_MASK)
bogdanm 0:9b334a45a8ff 1735 #define LCD_WF_WF59_MASK 0xFF000000u
bogdanm 0:9b334a45a8ff 1736 #define LCD_WF_WF59_SHIFT 24
bogdanm 0:9b334a45a8ff 1737 #define LCD_WF_WF59(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF59_SHIFT))&LCD_WF_WF59_MASK)
bogdanm 0:9b334a45a8ff 1738 #define LCD_WF_WF55_MASK 0xFF000000u
bogdanm 0:9b334a45a8ff 1739 #define LCD_WF_WF55_SHIFT 24
bogdanm 0:9b334a45a8ff 1740 #define LCD_WF_WF55(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF55_SHIFT))&LCD_WF_WF55_MASK)
bogdanm 0:9b334a45a8ff 1741 #define LCD_WF_WF3_MASK 0xFF000000u
bogdanm 0:9b334a45a8ff 1742 #define LCD_WF_WF3_SHIFT 24
bogdanm 0:9b334a45a8ff 1743 #define LCD_WF_WF3(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF3_SHIFT))&LCD_WF_WF3_MASK)
bogdanm 0:9b334a45a8ff 1744 #define LCD_WF_WF51_MASK 0xFF000000u
bogdanm 0:9b334a45a8ff 1745 #define LCD_WF_WF51_SHIFT 24
bogdanm 0:9b334a45a8ff 1746 #define LCD_WF_WF51(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF51_SHIFT))&LCD_WF_WF51_MASK)
bogdanm 0:9b334a45a8ff 1747 #define LCD_WF_WF47_MASK 0xFF000000u
bogdanm 0:9b334a45a8ff 1748 #define LCD_WF_WF47_SHIFT 24
bogdanm 0:9b334a45a8ff 1749 #define LCD_WF_WF47(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF47_SHIFT))&LCD_WF_WF47_MASK)
bogdanm 0:9b334a45a8ff 1750 #define LCD_WF_WF43_MASK 0xFF000000u
bogdanm 0:9b334a45a8ff 1751 #define LCD_WF_WF43_SHIFT 24
bogdanm 0:9b334a45a8ff 1752 #define LCD_WF_WF43(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF43_SHIFT))&LCD_WF_WF43_MASK)
bogdanm 0:9b334a45a8ff 1753 #define LCD_WF_WF7_MASK 0xFF000000u
bogdanm 0:9b334a45a8ff 1754 #define LCD_WF_WF7_SHIFT 24
bogdanm 0:9b334a45a8ff 1755 #define LCD_WF_WF7(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF7_SHIFT))&LCD_WF_WF7_MASK)
bogdanm 0:9b334a45a8ff 1756 #define LCD_WF_WF39_MASK 0xFF000000u
bogdanm 0:9b334a45a8ff 1757 #define LCD_WF_WF39_SHIFT 24
bogdanm 0:9b334a45a8ff 1758 #define LCD_WF_WF39(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF39_SHIFT))&LCD_WF_WF39_MASK)
bogdanm 0:9b334a45a8ff 1759 #define LCD_WF_WF35_MASK 0xFF000000u
bogdanm 0:9b334a45a8ff 1760 #define LCD_WF_WF35_SHIFT 24
bogdanm 0:9b334a45a8ff 1761 #define LCD_WF_WF35(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF35_SHIFT))&LCD_WF_WF35_MASK)
bogdanm 0:9b334a45a8ff 1762 #define LCD_WF_WF31_MASK 0xFF000000u
bogdanm 0:9b334a45a8ff 1763 #define LCD_WF_WF31_SHIFT 24
bogdanm 0:9b334a45a8ff 1764 #define LCD_WF_WF31(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF31_SHIFT))&LCD_WF_WF31_MASK)
bogdanm 0:9b334a45a8ff 1765 #define LCD_WF_WF11_MASK 0xFF000000u
bogdanm 0:9b334a45a8ff 1766 #define LCD_WF_WF11_SHIFT 24
bogdanm 0:9b334a45a8ff 1767 #define LCD_WF_WF11(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF11_SHIFT))&LCD_WF_WF11_MASK)
bogdanm 0:9b334a45a8ff 1768 #define LCD_WF_WF27_MASK 0xFF000000u
bogdanm 0:9b334a45a8ff 1769 #define LCD_WF_WF27_SHIFT 24
bogdanm 0:9b334a45a8ff 1770 #define LCD_WF_WF27(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF27_SHIFT))&LCD_WF_WF27_MASK)
bogdanm 0:9b334a45a8ff 1771 #define LCD_WF_WF23_MASK 0xFF000000u
bogdanm 0:9b334a45a8ff 1772 #define LCD_WF_WF23_SHIFT 24
bogdanm 0:9b334a45a8ff 1773 #define LCD_WF_WF23(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF23_SHIFT))&LCD_WF_WF23_MASK)
bogdanm 0:9b334a45a8ff 1774 #define LCD_WF_WF19_MASK 0xFF000000u
bogdanm 0:9b334a45a8ff 1775 #define LCD_WF_WF19_SHIFT 24
bogdanm 0:9b334a45a8ff 1776 #define LCD_WF_WF19(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF19_SHIFT))&LCD_WF_WF19_MASK)
bogdanm 0:9b334a45a8ff 1777 #define LCD_WF_WF15_MASK 0xFF000000u
bogdanm 0:9b334a45a8ff 1778 #define LCD_WF_WF15_SHIFT 24
bogdanm 0:9b334a45a8ff 1779 #define LCD_WF_WF15(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF15_SHIFT))&LCD_WF_WF15_MASK)
bogdanm 0:9b334a45a8ff 1780 /* WF8B Bit Fields */
bogdanm 0:9b334a45a8ff 1781 #define LCD_WF8B_BPALCD0_MASK 0x1u
bogdanm 0:9b334a45a8ff 1782 #define LCD_WF8B_BPALCD0_SHIFT 0
bogdanm 0:9b334a45a8ff 1783 #define LCD_WF8B_BPALCD63_MASK 0x1u
bogdanm 0:9b334a45a8ff 1784 #define LCD_WF8B_BPALCD63_SHIFT 0
bogdanm 0:9b334a45a8ff 1785 #define LCD_WF8B_BPALCD62_MASK 0x1u
bogdanm 0:9b334a45a8ff 1786 #define LCD_WF8B_BPALCD62_SHIFT 0
bogdanm 0:9b334a45a8ff 1787 #define LCD_WF8B_BPALCD61_MASK 0x1u
bogdanm 0:9b334a45a8ff 1788 #define LCD_WF8B_BPALCD61_SHIFT 0
bogdanm 0:9b334a45a8ff 1789 #define LCD_WF8B_BPALCD60_MASK 0x1u
bogdanm 0:9b334a45a8ff 1790 #define LCD_WF8B_BPALCD60_SHIFT 0
bogdanm 0:9b334a45a8ff 1791 #define LCD_WF8B_BPALCD59_MASK 0x1u
bogdanm 0:9b334a45a8ff 1792 #define LCD_WF8B_BPALCD59_SHIFT 0
bogdanm 0:9b334a45a8ff 1793 #define LCD_WF8B_BPALCD58_MASK 0x1u
bogdanm 0:9b334a45a8ff 1794 #define LCD_WF8B_BPALCD58_SHIFT 0
bogdanm 0:9b334a45a8ff 1795 #define LCD_WF8B_BPALCD57_MASK 0x1u
bogdanm 0:9b334a45a8ff 1796 #define LCD_WF8B_BPALCD57_SHIFT 0
bogdanm 0:9b334a45a8ff 1797 #define LCD_WF8B_BPALCD1_MASK 0x1u
bogdanm 0:9b334a45a8ff 1798 #define LCD_WF8B_BPALCD1_SHIFT 0
bogdanm 0:9b334a45a8ff 1799 #define LCD_WF8B_BPALCD56_MASK 0x1u
bogdanm 0:9b334a45a8ff 1800 #define LCD_WF8B_BPALCD56_SHIFT 0
bogdanm 0:9b334a45a8ff 1801 #define LCD_WF8B_BPALCD55_MASK 0x1u
bogdanm 0:9b334a45a8ff 1802 #define LCD_WF8B_BPALCD55_SHIFT 0
bogdanm 0:9b334a45a8ff 1803 #define LCD_WF8B_BPALCD54_MASK 0x1u
bogdanm 0:9b334a45a8ff 1804 #define LCD_WF8B_BPALCD54_SHIFT 0
bogdanm 0:9b334a45a8ff 1805 #define LCD_WF8B_BPALCD53_MASK 0x1u
bogdanm 0:9b334a45a8ff 1806 #define LCD_WF8B_BPALCD53_SHIFT 0
bogdanm 0:9b334a45a8ff 1807 #define LCD_WF8B_BPALCD52_MASK 0x1u
bogdanm 0:9b334a45a8ff 1808 #define LCD_WF8B_BPALCD52_SHIFT 0
bogdanm 0:9b334a45a8ff 1809 #define LCD_WF8B_BPALCD51_MASK 0x1u
bogdanm 0:9b334a45a8ff 1810 #define LCD_WF8B_BPALCD51_SHIFT 0
bogdanm 0:9b334a45a8ff 1811 #define LCD_WF8B_BPALCD50_MASK 0x1u
bogdanm 0:9b334a45a8ff 1812 #define LCD_WF8B_BPALCD50_SHIFT 0
bogdanm 0:9b334a45a8ff 1813 #define LCD_WF8B_BPALCD2_MASK 0x1u
bogdanm 0:9b334a45a8ff 1814 #define LCD_WF8B_BPALCD2_SHIFT 0
bogdanm 0:9b334a45a8ff 1815 #define LCD_WF8B_BPALCD49_MASK 0x1u
bogdanm 0:9b334a45a8ff 1816 #define LCD_WF8B_BPALCD49_SHIFT 0
bogdanm 0:9b334a45a8ff 1817 #define LCD_WF8B_BPALCD48_MASK 0x1u
bogdanm 0:9b334a45a8ff 1818 #define LCD_WF8B_BPALCD48_SHIFT 0
bogdanm 0:9b334a45a8ff 1819 #define LCD_WF8B_BPALCD47_MASK 0x1u
bogdanm 0:9b334a45a8ff 1820 #define LCD_WF8B_BPALCD47_SHIFT 0
bogdanm 0:9b334a45a8ff 1821 #define LCD_WF8B_BPALCD46_MASK 0x1u
bogdanm 0:9b334a45a8ff 1822 #define LCD_WF8B_BPALCD46_SHIFT 0
bogdanm 0:9b334a45a8ff 1823 #define LCD_WF8B_BPALCD45_MASK 0x1u
bogdanm 0:9b334a45a8ff 1824 #define LCD_WF8B_BPALCD45_SHIFT 0
bogdanm 0:9b334a45a8ff 1825 #define LCD_WF8B_BPALCD44_MASK 0x1u
bogdanm 0:9b334a45a8ff 1826 #define LCD_WF8B_BPALCD44_SHIFT 0
bogdanm 0:9b334a45a8ff 1827 #define LCD_WF8B_BPALCD43_MASK 0x1u
bogdanm 0:9b334a45a8ff 1828 #define LCD_WF8B_BPALCD43_SHIFT 0
bogdanm 0:9b334a45a8ff 1829 #define LCD_WF8B_BPALCD3_MASK 0x1u
bogdanm 0:9b334a45a8ff 1830 #define LCD_WF8B_BPALCD3_SHIFT 0
bogdanm 0:9b334a45a8ff 1831 #define LCD_WF8B_BPALCD42_MASK 0x1u
bogdanm 0:9b334a45a8ff 1832 #define LCD_WF8B_BPALCD42_SHIFT 0
bogdanm 0:9b334a45a8ff 1833 #define LCD_WF8B_BPALCD41_MASK 0x1u
bogdanm 0:9b334a45a8ff 1834 #define LCD_WF8B_BPALCD41_SHIFT 0
bogdanm 0:9b334a45a8ff 1835 #define LCD_WF8B_BPALCD40_MASK 0x1u
bogdanm 0:9b334a45a8ff 1836 #define LCD_WF8B_BPALCD40_SHIFT 0
bogdanm 0:9b334a45a8ff 1837 #define LCD_WF8B_BPALCD39_MASK 0x1u
bogdanm 0:9b334a45a8ff 1838 #define LCD_WF8B_BPALCD39_SHIFT 0
bogdanm 0:9b334a45a8ff 1839 #define LCD_WF8B_BPALCD38_MASK 0x1u
bogdanm 0:9b334a45a8ff 1840 #define LCD_WF8B_BPALCD38_SHIFT 0
bogdanm 0:9b334a45a8ff 1841 #define LCD_WF8B_BPALCD37_MASK 0x1u
bogdanm 0:9b334a45a8ff 1842 #define LCD_WF8B_BPALCD37_SHIFT 0
bogdanm 0:9b334a45a8ff 1843 #define LCD_WF8B_BPALCD36_MASK 0x1u
bogdanm 0:9b334a45a8ff 1844 #define LCD_WF8B_BPALCD36_SHIFT 0
bogdanm 0:9b334a45a8ff 1845 #define LCD_WF8B_BPALCD4_MASK 0x1u
bogdanm 0:9b334a45a8ff 1846 #define LCD_WF8B_BPALCD4_SHIFT 0
bogdanm 0:9b334a45a8ff 1847 #define LCD_WF8B_BPALCD35_MASK 0x1u
bogdanm 0:9b334a45a8ff 1848 #define LCD_WF8B_BPALCD35_SHIFT 0
bogdanm 0:9b334a45a8ff 1849 #define LCD_WF8B_BPALCD34_MASK 0x1u
bogdanm 0:9b334a45a8ff 1850 #define LCD_WF8B_BPALCD34_SHIFT 0
bogdanm 0:9b334a45a8ff 1851 #define LCD_WF8B_BPALCD33_MASK 0x1u
bogdanm 0:9b334a45a8ff 1852 #define LCD_WF8B_BPALCD33_SHIFT 0
bogdanm 0:9b334a45a8ff 1853 #define LCD_WF8B_BPALCD32_MASK 0x1u
bogdanm 0:9b334a45a8ff 1854 #define LCD_WF8B_BPALCD32_SHIFT 0
bogdanm 0:9b334a45a8ff 1855 #define LCD_WF8B_BPALCD31_MASK 0x1u
bogdanm 0:9b334a45a8ff 1856 #define LCD_WF8B_BPALCD31_SHIFT 0
bogdanm 0:9b334a45a8ff 1857 #define LCD_WF8B_BPALCD30_MASK 0x1u
bogdanm 0:9b334a45a8ff 1858 #define LCD_WF8B_BPALCD30_SHIFT 0
bogdanm 0:9b334a45a8ff 1859 #define LCD_WF8B_BPALCD29_MASK 0x1u
bogdanm 0:9b334a45a8ff 1860 #define LCD_WF8B_BPALCD29_SHIFT 0
bogdanm 0:9b334a45a8ff 1861 #define LCD_WF8B_BPALCD5_MASK 0x1u
bogdanm 0:9b334a45a8ff 1862 #define LCD_WF8B_BPALCD5_SHIFT 0
bogdanm 0:9b334a45a8ff 1863 #define LCD_WF8B_BPALCD28_MASK 0x1u
bogdanm 0:9b334a45a8ff 1864 #define LCD_WF8B_BPALCD28_SHIFT 0
bogdanm 0:9b334a45a8ff 1865 #define LCD_WF8B_BPALCD27_MASK 0x1u
bogdanm 0:9b334a45a8ff 1866 #define LCD_WF8B_BPALCD27_SHIFT 0
bogdanm 0:9b334a45a8ff 1867 #define LCD_WF8B_BPALCD26_MASK 0x1u
bogdanm 0:9b334a45a8ff 1868 #define LCD_WF8B_BPALCD26_SHIFT 0
bogdanm 0:9b334a45a8ff 1869 #define LCD_WF8B_BPALCD25_MASK 0x1u
bogdanm 0:9b334a45a8ff 1870 #define LCD_WF8B_BPALCD25_SHIFT 0
bogdanm 0:9b334a45a8ff 1871 #define LCD_WF8B_BPALCD24_MASK 0x1u
bogdanm 0:9b334a45a8ff 1872 #define LCD_WF8B_BPALCD24_SHIFT 0
bogdanm 0:9b334a45a8ff 1873 #define LCD_WF8B_BPALCD23_MASK 0x1u
bogdanm 0:9b334a45a8ff 1874 #define LCD_WF8B_BPALCD23_SHIFT 0
bogdanm 0:9b334a45a8ff 1875 #define LCD_WF8B_BPALCD22_MASK 0x1u
bogdanm 0:9b334a45a8ff 1876 #define LCD_WF8B_BPALCD22_SHIFT 0
bogdanm 0:9b334a45a8ff 1877 #define LCD_WF8B_BPALCD6_MASK 0x1u
bogdanm 0:9b334a45a8ff 1878 #define LCD_WF8B_BPALCD6_SHIFT 0
bogdanm 0:9b334a45a8ff 1879 #define LCD_WF8B_BPALCD21_MASK 0x1u
bogdanm 0:9b334a45a8ff 1880 #define LCD_WF8B_BPALCD21_SHIFT 0
bogdanm 0:9b334a45a8ff 1881 #define LCD_WF8B_BPALCD20_MASK 0x1u
bogdanm 0:9b334a45a8ff 1882 #define LCD_WF8B_BPALCD20_SHIFT 0
bogdanm 0:9b334a45a8ff 1883 #define LCD_WF8B_BPALCD19_MASK 0x1u
bogdanm 0:9b334a45a8ff 1884 #define LCD_WF8B_BPALCD19_SHIFT 0
bogdanm 0:9b334a45a8ff 1885 #define LCD_WF8B_BPALCD18_MASK 0x1u
bogdanm 0:9b334a45a8ff 1886 #define LCD_WF8B_BPALCD18_SHIFT 0
bogdanm 0:9b334a45a8ff 1887 #define LCD_WF8B_BPALCD17_MASK 0x1u
bogdanm 0:9b334a45a8ff 1888 #define LCD_WF8B_BPALCD17_SHIFT 0
bogdanm 0:9b334a45a8ff 1889 #define LCD_WF8B_BPALCD16_MASK 0x1u
bogdanm 0:9b334a45a8ff 1890 #define LCD_WF8B_BPALCD16_SHIFT 0
bogdanm 0:9b334a45a8ff 1891 #define LCD_WF8B_BPALCD15_MASK 0x1u
bogdanm 0:9b334a45a8ff 1892 #define LCD_WF8B_BPALCD15_SHIFT 0
bogdanm 0:9b334a45a8ff 1893 #define LCD_WF8B_BPALCD7_MASK 0x1u
bogdanm 0:9b334a45a8ff 1894 #define LCD_WF8B_BPALCD7_SHIFT 0
bogdanm 0:9b334a45a8ff 1895 #define LCD_WF8B_BPALCD14_MASK 0x1u
bogdanm 0:9b334a45a8ff 1896 #define LCD_WF8B_BPALCD14_SHIFT 0
bogdanm 0:9b334a45a8ff 1897 #define LCD_WF8B_BPALCD13_MASK 0x1u
bogdanm 0:9b334a45a8ff 1898 #define LCD_WF8B_BPALCD13_SHIFT 0
bogdanm 0:9b334a45a8ff 1899 #define LCD_WF8B_BPALCD12_MASK 0x1u
bogdanm 0:9b334a45a8ff 1900 #define LCD_WF8B_BPALCD12_SHIFT 0
bogdanm 0:9b334a45a8ff 1901 #define LCD_WF8B_BPALCD11_MASK 0x1u
bogdanm 0:9b334a45a8ff 1902 #define LCD_WF8B_BPALCD11_SHIFT 0
bogdanm 0:9b334a45a8ff 1903 #define LCD_WF8B_BPALCD10_MASK 0x1u
bogdanm 0:9b334a45a8ff 1904 #define LCD_WF8B_BPALCD10_SHIFT 0
bogdanm 0:9b334a45a8ff 1905 #define LCD_WF8B_BPALCD9_MASK 0x1u
bogdanm 0:9b334a45a8ff 1906 #define LCD_WF8B_BPALCD9_SHIFT 0
bogdanm 0:9b334a45a8ff 1907 #define LCD_WF8B_BPALCD8_MASK 0x1u
bogdanm 0:9b334a45a8ff 1908 #define LCD_WF8B_BPALCD8_SHIFT 0
bogdanm 0:9b334a45a8ff 1909 #define LCD_WF8B_BPBLCD1_MASK 0x2u
bogdanm 0:9b334a45a8ff 1910 #define LCD_WF8B_BPBLCD1_SHIFT 1
bogdanm 0:9b334a45a8ff 1911 #define LCD_WF8B_BPBLCD32_MASK 0x2u
bogdanm 0:9b334a45a8ff 1912 #define LCD_WF8B_BPBLCD32_SHIFT 1
bogdanm 0:9b334a45a8ff 1913 #define LCD_WF8B_BPBLCD30_MASK 0x2u
bogdanm 0:9b334a45a8ff 1914 #define LCD_WF8B_BPBLCD30_SHIFT 1
bogdanm 0:9b334a45a8ff 1915 #define LCD_WF8B_BPBLCD60_MASK 0x2u
bogdanm 0:9b334a45a8ff 1916 #define LCD_WF8B_BPBLCD60_SHIFT 1
bogdanm 0:9b334a45a8ff 1917 #define LCD_WF8B_BPBLCD24_MASK 0x2u
bogdanm 0:9b334a45a8ff 1918 #define LCD_WF8B_BPBLCD24_SHIFT 1
bogdanm 0:9b334a45a8ff 1919 #define LCD_WF8B_BPBLCD28_MASK 0x2u
bogdanm 0:9b334a45a8ff 1920 #define LCD_WF8B_BPBLCD28_SHIFT 1
bogdanm 0:9b334a45a8ff 1921 #define LCD_WF8B_BPBLCD23_MASK 0x2u
bogdanm 0:9b334a45a8ff 1922 #define LCD_WF8B_BPBLCD23_SHIFT 1
bogdanm 0:9b334a45a8ff 1923 #define LCD_WF8B_BPBLCD48_MASK 0x2u
bogdanm 0:9b334a45a8ff 1924 #define LCD_WF8B_BPBLCD48_SHIFT 1
bogdanm 0:9b334a45a8ff 1925 #define LCD_WF8B_BPBLCD10_MASK 0x2u
bogdanm 0:9b334a45a8ff 1926 #define LCD_WF8B_BPBLCD10_SHIFT 1
bogdanm 0:9b334a45a8ff 1927 #define LCD_WF8B_BPBLCD15_MASK 0x2u
bogdanm 0:9b334a45a8ff 1928 #define LCD_WF8B_BPBLCD15_SHIFT 1
bogdanm 0:9b334a45a8ff 1929 #define LCD_WF8B_BPBLCD36_MASK 0x2u
bogdanm 0:9b334a45a8ff 1930 #define LCD_WF8B_BPBLCD36_SHIFT 1
bogdanm 0:9b334a45a8ff 1931 #define LCD_WF8B_BPBLCD44_MASK 0x2u
bogdanm 0:9b334a45a8ff 1932 #define LCD_WF8B_BPBLCD44_SHIFT 1
bogdanm 0:9b334a45a8ff 1933 #define LCD_WF8B_BPBLCD62_MASK 0x2u
bogdanm 0:9b334a45a8ff 1934 #define LCD_WF8B_BPBLCD62_SHIFT 1
bogdanm 0:9b334a45a8ff 1935 #define LCD_WF8B_BPBLCD53_MASK 0x2u
bogdanm 0:9b334a45a8ff 1936 #define LCD_WF8B_BPBLCD53_SHIFT 1
bogdanm 0:9b334a45a8ff 1937 #define LCD_WF8B_BPBLCD22_MASK 0x2u
bogdanm 0:9b334a45a8ff 1938 #define LCD_WF8B_BPBLCD22_SHIFT 1
bogdanm 0:9b334a45a8ff 1939 #define LCD_WF8B_BPBLCD47_MASK 0x2u
bogdanm 0:9b334a45a8ff 1940 #define LCD_WF8B_BPBLCD47_SHIFT 1
bogdanm 0:9b334a45a8ff 1941 #define LCD_WF8B_BPBLCD33_MASK 0x2u
bogdanm 0:9b334a45a8ff 1942 #define LCD_WF8B_BPBLCD33_SHIFT 1
bogdanm 0:9b334a45a8ff 1943 #define LCD_WF8B_BPBLCD2_MASK 0x2u
bogdanm 0:9b334a45a8ff 1944 #define LCD_WF8B_BPBLCD2_SHIFT 1
bogdanm 0:9b334a45a8ff 1945 #define LCD_WF8B_BPBLCD49_MASK 0x2u
bogdanm 0:9b334a45a8ff 1946 #define LCD_WF8B_BPBLCD49_SHIFT 1
bogdanm 0:9b334a45a8ff 1947 #define LCD_WF8B_BPBLCD0_MASK 0x2u
bogdanm 0:9b334a45a8ff 1948 #define LCD_WF8B_BPBLCD0_SHIFT 1
bogdanm 0:9b334a45a8ff 1949 #define LCD_WF8B_BPBLCD55_MASK 0x2u
bogdanm 0:9b334a45a8ff 1950 #define LCD_WF8B_BPBLCD55_SHIFT 1
bogdanm 0:9b334a45a8ff 1951 #define LCD_WF8B_BPBLCD56_MASK 0x2u
bogdanm 0:9b334a45a8ff 1952 #define LCD_WF8B_BPBLCD56_SHIFT 1
bogdanm 0:9b334a45a8ff 1953 #define LCD_WF8B_BPBLCD21_MASK 0x2u
bogdanm 0:9b334a45a8ff 1954 #define LCD_WF8B_BPBLCD21_SHIFT 1
bogdanm 0:9b334a45a8ff 1955 #define LCD_WF8B_BPBLCD6_MASK 0x2u
bogdanm 0:9b334a45a8ff 1956 #define LCD_WF8B_BPBLCD6_SHIFT 1
bogdanm 0:9b334a45a8ff 1957 #define LCD_WF8B_BPBLCD29_MASK 0x2u
bogdanm 0:9b334a45a8ff 1958 #define LCD_WF8B_BPBLCD29_SHIFT 1
bogdanm 0:9b334a45a8ff 1959 #define LCD_WF8B_BPBLCD25_MASK 0x2u
bogdanm 0:9b334a45a8ff 1960 #define LCD_WF8B_BPBLCD25_SHIFT 1
bogdanm 0:9b334a45a8ff 1961 #define LCD_WF8B_BPBLCD8_MASK 0x2u
bogdanm 0:9b334a45a8ff 1962 #define LCD_WF8B_BPBLCD8_SHIFT 1
bogdanm 0:9b334a45a8ff 1963 #define LCD_WF8B_BPBLCD54_MASK 0x2u
bogdanm 0:9b334a45a8ff 1964 #define LCD_WF8B_BPBLCD54_SHIFT 1
bogdanm 0:9b334a45a8ff 1965 #define LCD_WF8B_BPBLCD38_MASK 0x2u
bogdanm 0:9b334a45a8ff 1966 #define LCD_WF8B_BPBLCD38_SHIFT 1
bogdanm 0:9b334a45a8ff 1967 #define LCD_WF8B_BPBLCD43_MASK 0x2u
bogdanm 0:9b334a45a8ff 1968 #define LCD_WF8B_BPBLCD43_SHIFT 1
bogdanm 0:9b334a45a8ff 1969 #define LCD_WF8B_BPBLCD20_MASK 0x2u
bogdanm 0:9b334a45a8ff 1970 #define LCD_WF8B_BPBLCD20_SHIFT 1
bogdanm 0:9b334a45a8ff 1971 #define LCD_WF8B_BPBLCD9_MASK 0x2u
bogdanm 0:9b334a45a8ff 1972 #define LCD_WF8B_BPBLCD9_SHIFT 1
bogdanm 0:9b334a45a8ff 1973 #define LCD_WF8B_BPBLCD7_MASK 0x2u
bogdanm 0:9b334a45a8ff 1974 #define LCD_WF8B_BPBLCD7_SHIFT 1
bogdanm 0:9b334a45a8ff 1975 #define LCD_WF8B_BPBLCD50_MASK 0x2u
bogdanm 0:9b334a45a8ff 1976 #define LCD_WF8B_BPBLCD50_SHIFT 1
bogdanm 0:9b334a45a8ff 1977 #define LCD_WF8B_BPBLCD40_MASK 0x2u
bogdanm 0:9b334a45a8ff 1978 #define LCD_WF8B_BPBLCD40_SHIFT 1
bogdanm 0:9b334a45a8ff 1979 #define LCD_WF8B_BPBLCD63_MASK 0x2u
bogdanm 0:9b334a45a8ff 1980 #define LCD_WF8B_BPBLCD63_SHIFT 1
bogdanm 0:9b334a45a8ff 1981 #define LCD_WF8B_BPBLCD26_MASK 0x2u
bogdanm 0:9b334a45a8ff 1982 #define LCD_WF8B_BPBLCD26_SHIFT 1
bogdanm 0:9b334a45a8ff 1983 #define LCD_WF8B_BPBLCD12_MASK 0x2u
bogdanm 0:9b334a45a8ff 1984 #define LCD_WF8B_BPBLCD12_SHIFT 1
bogdanm 0:9b334a45a8ff 1985 #define LCD_WF8B_BPBLCD19_MASK 0x2u
bogdanm 0:9b334a45a8ff 1986 #define LCD_WF8B_BPBLCD19_SHIFT 1
bogdanm 0:9b334a45a8ff 1987 #define LCD_WF8B_BPBLCD34_MASK 0x2u
bogdanm 0:9b334a45a8ff 1988 #define LCD_WF8B_BPBLCD34_SHIFT 1
bogdanm 0:9b334a45a8ff 1989 #define LCD_WF8B_BPBLCD39_MASK 0x2u
bogdanm 0:9b334a45a8ff 1990 #define LCD_WF8B_BPBLCD39_SHIFT 1
bogdanm 0:9b334a45a8ff 1991 #define LCD_WF8B_BPBLCD59_MASK 0x2u
bogdanm 0:9b334a45a8ff 1992 #define LCD_WF8B_BPBLCD59_SHIFT 1
bogdanm 0:9b334a45a8ff 1993 #define LCD_WF8B_BPBLCD61_MASK 0x2u
bogdanm 0:9b334a45a8ff 1994 #define LCD_WF8B_BPBLCD61_SHIFT 1
bogdanm 0:9b334a45a8ff 1995 #define LCD_WF8B_BPBLCD37_MASK 0x2u
bogdanm 0:9b334a45a8ff 1996 #define LCD_WF8B_BPBLCD37_SHIFT 1
bogdanm 0:9b334a45a8ff 1997 #define LCD_WF8B_BPBLCD31_MASK 0x2u
bogdanm 0:9b334a45a8ff 1998 #define LCD_WF8B_BPBLCD31_SHIFT 1
bogdanm 0:9b334a45a8ff 1999 #define LCD_WF8B_BPBLCD58_MASK 0x2u
bogdanm 0:9b334a45a8ff 2000 #define LCD_WF8B_BPBLCD58_SHIFT 1
bogdanm 0:9b334a45a8ff 2001 #define LCD_WF8B_BPBLCD18_MASK 0x2u
bogdanm 0:9b334a45a8ff 2002 #define LCD_WF8B_BPBLCD18_SHIFT 1
bogdanm 0:9b334a45a8ff 2003 #define LCD_WF8B_BPBLCD45_MASK 0x2u
bogdanm 0:9b334a45a8ff 2004 #define LCD_WF8B_BPBLCD45_SHIFT 1
bogdanm 0:9b334a45a8ff 2005 #define LCD_WF8B_BPBLCD27_MASK 0x2u
bogdanm 0:9b334a45a8ff 2006 #define LCD_WF8B_BPBLCD27_SHIFT 1
bogdanm 0:9b334a45a8ff 2007 #define LCD_WF8B_BPBLCD14_MASK 0x2u
bogdanm 0:9b334a45a8ff 2008 #define LCD_WF8B_BPBLCD14_SHIFT 1
bogdanm 0:9b334a45a8ff 2009 #define LCD_WF8B_BPBLCD51_MASK 0x2u
bogdanm 0:9b334a45a8ff 2010 #define LCD_WF8B_BPBLCD51_SHIFT 1
bogdanm 0:9b334a45a8ff 2011 #define LCD_WF8B_BPBLCD52_MASK 0x2u
bogdanm 0:9b334a45a8ff 2012 #define LCD_WF8B_BPBLCD52_SHIFT 1
bogdanm 0:9b334a45a8ff 2013 #define LCD_WF8B_BPBLCD4_MASK 0x2u
bogdanm 0:9b334a45a8ff 2014 #define LCD_WF8B_BPBLCD4_SHIFT 1
bogdanm 0:9b334a45a8ff 2015 #define LCD_WF8B_BPBLCD35_MASK 0x2u
bogdanm 0:9b334a45a8ff 2016 #define LCD_WF8B_BPBLCD35_SHIFT 1
bogdanm 0:9b334a45a8ff 2017 #define LCD_WF8B_BPBLCD17_MASK 0x2u
bogdanm 0:9b334a45a8ff 2018 #define LCD_WF8B_BPBLCD17_SHIFT 1
bogdanm 0:9b334a45a8ff 2019 #define LCD_WF8B_BPBLCD41_MASK 0x2u
bogdanm 0:9b334a45a8ff 2020 #define LCD_WF8B_BPBLCD41_SHIFT 1
bogdanm 0:9b334a45a8ff 2021 #define LCD_WF8B_BPBLCD11_MASK 0x2u
bogdanm 0:9b334a45a8ff 2022 #define LCD_WF8B_BPBLCD11_SHIFT 1
bogdanm 0:9b334a45a8ff 2023 #define LCD_WF8B_BPBLCD46_MASK 0x2u
bogdanm 0:9b334a45a8ff 2024 #define LCD_WF8B_BPBLCD46_SHIFT 1
bogdanm 0:9b334a45a8ff 2025 #define LCD_WF8B_BPBLCD57_MASK 0x2u
bogdanm 0:9b334a45a8ff 2026 #define LCD_WF8B_BPBLCD57_SHIFT 1
bogdanm 0:9b334a45a8ff 2027 #define LCD_WF8B_BPBLCD42_MASK 0x2u
bogdanm 0:9b334a45a8ff 2028 #define LCD_WF8B_BPBLCD42_SHIFT 1
bogdanm 0:9b334a45a8ff 2029 #define LCD_WF8B_BPBLCD5_MASK 0x2u
bogdanm 0:9b334a45a8ff 2030 #define LCD_WF8B_BPBLCD5_SHIFT 1
bogdanm 0:9b334a45a8ff 2031 #define LCD_WF8B_BPBLCD3_MASK 0x2u
bogdanm 0:9b334a45a8ff 2032 #define LCD_WF8B_BPBLCD3_SHIFT 1
bogdanm 0:9b334a45a8ff 2033 #define LCD_WF8B_BPBLCD16_MASK 0x2u
bogdanm 0:9b334a45a8ff 2034 #define LCD_WF8B_BPBLCD16_SHIFT 1
bogdanm 0:9b334a45a8ff 2035 #define LCD_WF8B_BPBLCD13_MASK 0x2u
bogdanm 0:9b334a45a8ff 2036 #define LCD_WF8B_BPBLCD13_SHIFT 1
bogdanm 0:9b334a45a8ff 2037 #define LCD_WF8B_BPCLCD10_MASK 0x4u
bogdanm 0:9b334a45a8ff 2038 #define LCD_WF8B_BPCLCD10_SHIFT 2
bogdanm 0:9b334a45a8ff 2039 #define LCD_WF8B_BPCLCD55_MASK 0x4u
bogdanm 0:9b334a45a8ff 2040 #define LCD_WF8B_BPCLCD55_SHIFT 2
bogdanm 0:9b334a45a8ff 2041 #define LCD_WF8B_BPCLCD2_MASK 0x4u
bogdanm 0:9b334a45a8ff 2042 #define LCD_WF8B_BPCLCD2_SHIFT 2
bogdanm 0:9b334a45a8ff 2043 #define LCD_WF8B_BPCLCD23_MASK 0x4u
bogdanm 0:9b334a45a8ff 2044 #define LCD_WF8B_BPCLCD23_SHIFT 2
bogdanm 0:9b334a45a8ff 2045 #define LCD_WF8B_BPCLCD48_MASK 0x4u
bogdanm 0:9b334a45a8ff 2046 #define LCD_WF8B_BPCLCD48_SHIFT 2
bogdanm 0:9b334a45a8ff 2047 #define LCD_WF8B_BPCLCD24_MASK 0x4u
bogdanm 0:9b334a45a8ff 2048 #define LCD_WF8B_BPCLCD24_SHIFT 2
bogdanm 0:9b334a45a8ff 2049 #define LCD_WF8B_BPCLCD60_MASK 0x4u
bogdanm 0:9b334a45a8ff 2050 #define LCD_WF8B_BPCLCD60_SHIFT 2
bogdanm 0:9b334a45a8ff 2051 #define LCD_WF8B_BPCLCD47_MASK 0x4u
bogdanm 0:9b334a45a8ff 2052 #define LCD_WF8B_BPCLCD47_SHIFT 2
bogdanm 0:9b334a45a8ff 2053 #define LCD_WF8B_BPCLCD22_MASK 0x4u
bogdanm 0:9b334a45a8ff 2054 #define LCD_WF8B_BPCLCD22_SHIFT 2
bogdanm 0:9b334a45a8ff 2055 #define LCD_WF8B_BPCLCD8_MASK 0x4u
bogdanm 0:9b334a45a8ff 2056 #define LCD_WF8B_BPCLCD8_SHIFT 2
bogdanm 0:9b334a45a8ff 2057 #define LCD_WF8B_BPCLCD21_MASK 0x4u
bogdanm 0:9b334a45a8ff 2058 #define LCD_WF8B_BPCLCD21_SHIFT 2
bogdanm 0:9b334a45a8ff 2059 #define LCD_WF8B_BPCLCD49_MASK 0x4u
bogdanm 0:9b334a45a8ff 2060 #define LCD_WF8B_BPCLCD49_SHIFT 2
bogdanm 0:9b334a45a8ff 2061 #define LCD_WF8B_BPCLCD25_MASK 0x4u
bogdanm 0:9b334a45a8ff 2062 #define LCD_WF8B_BPCLCD25_SHIFT 2
bogdanm 0:9b334a45a8ff 2063 #define LCD_WF8B_BPCLCD1_MASK 0x4u
bogdanm 0:9b334a45a8ff 2064 #define LCD_WF8B_BPCLCD1_SHIFT 2
bogdanm 0:9b334a45a8ff 2065 #define LCD_WF8B_BPCLCD20_MASK 0x4u
bogdanm 0:9b334a45a8ff 2066 #define LCD_WF8B_BPCLCD20_SHIFT 2
bogdanm 0:9b334a45a8ff 2067 #define LCD_WF8B_BPCLCD50_MASK 0x4u
bogdanm 0:9b334a45a8ff 2068 #define LCD_WF8B_BPCLCD50_SHIFT 2
bogdanm 0:9b334a45a8ff 2069 #define LCD_WF8B_BPCLCD19_MASK 0x4u
bogdanm 0:9b334a45a8ff 2070 #define LCD_WF8B_BPCLCD19_SHIFT 2
bogdanm 0:9b334a45a8ff 2071 #define LCD_WF8B_BPCLCD26_MASK 0x4u
bogdanm 0:9b334a45a8ff 2072 #define LCD_WF8B_BPCLCD26_SHIFT 2
bogdanm 0:9b334a45a8ff 2073 #define LCD_WF8B_BPCLCD59_MASK 0x4u
bogdanm 0:9b334a45a8ff 2074 #define LCD_WF8B_BPCLCD59_SHIFT 2
bogdanm 0:9b334a45a8ff 2075 #define LCD_WF8B_BPCLCD61_MASK 0x4u
bogdanm 0:9b334a45a8ff 2076 #define LCD_WF8B_BPCLCD61_SHIFT 2
bogdanm 0:9b334a45a8ff 2077 #define LCD_WF8B_BPCLCD46_MASK 0x4u
bogdanm 0:9b334a45a8ff 2078 #define LCD_WF8B_BPCLCD46_SHIFT 2
bogdanm 0:9b334a45a8ff 2079 #define LCD_WF8B_BPCLCD18_MASK 0x4u
bogdanm 0:9b334a45a8ff 2080 #define LCD_WF8B_BPCLCD18_SHIFT 2
bogdanm 0:9b334a45a8ff 2081 #define LCD_WF8B_BPCLCD5_MASK 0x4u
bogdanm 0:9b334a45a8ff 2082 #define LCD_WF8B_BPCLCD5_SHIFT 2
bogdanm 0:9b334a45a8ff 2083 #define LCD_WF8B_BPCLCD63_MASK 0x4u
bogdanm 0:9b334a45a8ff 2084 #define LCD_WF8B_BPCLCD63_SHIFT 2
bogdanm 0:9b334a45a8ff 2085 #define LCD_WF8B_BPCLCD27_MASK 0x4u
bogdanm 0:9b334a45a8ff 2086 #define LCD_WF8B_BPCLCD27_SHIFT 2
bogdanm 0:9b334a45a8ff 2087 #define LCD_WF8B_BPCLCD17_MASK 0x4u
bogdanm 0:9b334a45a8ff 2088 #define LCD_WF8B_BPCLCD17_SHIFT 2
bogdanm 0:9b334a45a8ff 2089 #define LCD_WF8B_BPCLCD51_MASK 0x4u
bogdanm 0:9b334a45a8ff 2090 #define LCD_WF8B_BPCLCD51_SHIFT 2
bogdanm 0:9b334a45a8ff 2091 #define LCD_WF8B_BPCLCD9_MASK 0x4u
bogdanm 0:9b334a45a8ff 2092 #define LCD_WF8B_BPCLCD9_SHIFT 2
bogdanm 0:9b334a45a8ff 2093 #define LCD_WF8B_BPCLCD54_MASK 0x4u
bogdanm 0:9b334a45a8ff 2094 #define LCD_WF8B_BPCLCD54_SHIFT 2
bogdanm 0:9b334a45a8ff 2095 #define LCD_WF8B_BPCLCD15_MASK 0x4u
bogdanm 0:9b334a45a8ff 2096 #define LCD_WF8B_BPCLCD15_SHIFT 2
bogdanm 0:9b334a45a8ff 2097 #define LCD_WF8B_BPCLCD16_MASK 0x4u
bogdanm 0:9b334a45a8ff 2098 #define LCD_WF8B_BPCLCD16_SHIFT 2
bogdanm 0:9b334a45a8ff 2099 #define LCD_WF8B_BPCLCD14_MASK 0x4u
bogdanm 0:9b334a45a8ff 2100 #define LCD_WF8B_BPCLCD14_SHIFT 2
bogdanm 0:9b334a45a8ff 2101 #define LCD_WF8B_BPCLCD32_MASK 0x4u
bogdanm 0:9b334a45a8ff 2102 #define LCD_WF8B_BPCLCD32_SHIFT 2
bogdanm 0:9b334a45a8ff 2103 #define LCD_WF8B_BPCLCD28_MASK 0x4u
bogdanm 0:9b334a45a8ff 2104 #define LCD_WF8B_BPCLCD28_SHIFT 2
bogdanm 0:9b334a45a8ff 2105 #define LCD_WF8B_BPCLCD53_MASK 0x4u
bogdanm 0:9b334a45a8ff 2106 #define LCD_WF8B_BPCLCD53_SHIFT 2
bogdanm 0:9b334a45a8ff 2107 #define LCD_WF8B_BPCLCD33_MASK 0x4u
bogdanm 0:9b334a45a8ff 2108 #define LCD_WF8B_BPCLCD33_SHIFT 2
bogdanm 0:9b334a45a8ff 2109 #define LCD_WF8B_BPCLCD0_MASK 0x4u
bogdanm 0:9b334a45a8ff 2110 #define LCD_WF8B_BPCLCD0_SHIFT 2
bogdanm 0:9b334a45a8ff 2111 #define LCD_WF8B_BPCLCD43_MASK 0x4u
bogdanm 0:9b334a45a8ff 2112 #define LCD_WF8B_BPCLCD43_SHIFT 2
bogdanm 0:9b334a45a8ff 2113 #define LCD_WF8B_BPCLCD7_MASK 0x4u
bogdanm 0:9b334a45a8ff 2114 #define LCD_WF8B_BPCLCD7_SHIFT 2
bogdanm 0:9b334a45a8ff 2115 #define LCD_WF8B_BPCLCD4_MASK 0x4u
bogdanm 0:9b334a45a8ff 2116 #define LCD_WF8B_BPCLCD4_SHIFT 2
bogdanm 0:9b334a45a8ff 2117 #define LCD_WF8B_BPCLCD34_MASK 0x4u
bogdanm 0:9b334a45a8ff 2118 #define LCD_WF8B_BPCLCD34_SHIFT 2
bogdanm 0:9b334a45a8ff 2119 #define LCD_WF8B_BPCLCD29_MASK 0x4u
bogdanm 0:9b334a45a8ff 2120 #define LCD_WF8B_BPCLCD29_SHIFT 2
bogdanm 0:9b334a45a8ff 2121 #define LCD_WF8B_BPCLCD45_MASK 0x4u
bogdanm 0:9b334a45a8ff 2122 #define LCD_WF8B_BPCLCD45_SHIFT 2
bogdanm 0:9b334a45a8ff 2123 #define LCD_WF8B_BPCLCD57_MASK 0x4u
bogdanm 0:9b334a45a8ff 2124 #define LCD_WF8B_BPCLCD57_SHIFT 2
bogdanm 0:9b334a45a8ff 2125 #define LCD_WF8B_BPCLCD42_MASK 0x4u
bogdanm 0:9b334a45a8ff 2126 #define LCD_WF8B_BPCLCD42_SHIFT 2
bogdanm 0:9b334a45a8ff 2127 #define LCD_WF8B_BPCLCD35_MASK 0x4u
bogdanm 0:9b334a45a8ff 2128 #define LCD_WF8B_BPCLCD35_SHIFT 2
bogdanm 0:9b334a45a8ff 2129 #define LCD_WF8B_BPCLCD13_MASK 0x4u
bogdanm 0:9b334a45a8ff 2130 #define LCD_WF8B_BPCLCD13_SHIFT 2
bogdanm 0:9b334a45a8ff 2131 #define LCD_WF8B_BPCLCD36_MASK 0x4u
bogdanm 0:9b334a45a8ff 2132 #define LCD_WF8B_BPCLCD36_SHIFT 2
bogdanm 0:9b334a45a8ff 2133 #define LCD_WF8B_BPCLCD30_MASK 0x4u
bogdanm 0:9b334a45a8ff 2134 #define LCD_WF8B_BPCLCD30_SHIFT 2
bogdanm 0:9b334a45a8ff 2135 #define LCD_WF8B_BPCLCD52_MASK 0x4u
bogdanm 0:9b334a45a8ff 2136 #define LCD_WF8B_BPCLCD52_SHIFT 2
bogdanm 0:9b334a45a8ff 2137 #define LCD_WF8B_BPCLCD58_MASK 0x4u
bogdanm 0:9b334a45a8ff 2138 #define LCD_WF8B_BPCLCD58_SHIFT 2
bogdanm 0:9b334a45a8ff 2139 #define LCD_WF8B_BPCLCD41_MASK 0x4u
bogdanm 0:9b334a45a8ff 2140 #define LCD_WF8B_BPCLCD41_SHIFT 2
bogdanm 0:9b334a45a8ff 2141 #define LCD_WF8B_BPCLCD37_MASK 0x4u
bogdanm 0:9b334a45a8ff 2142 #define LCD_WF8B_BPCLCD37_SHIFT 2
bogdanm 0:9b334a45a8ff 2143 #define LCD_WF8B_BPCLCD3_MASK 0x4u
bogdanm 0:9b334a45a8ff 2144 #define LCD_WF8B_BPCLCD3_SHIFT 2
bogdanm 0:9b334a45a8ff 2145 #define LCD_WF8B_BPCLCD12_MASK 0x4u
bogdanm 0:9b334a45a8ff 2146 #define LCD_WF8B_BPCLCD12_SHIFT 2
bogdanm 0:9b334a45a8ff 2147 #define LCD_WF8B_BPCLCD11_MASK 0x4u
bogdanm 0:9b334a45a8ff 2148 #define LCD_WF8B_BPCLCD11_SHIFT 2
bogdanm 0:9b334a45a8ff 2149 #define LCD_WF8B_BPCLCD38_MASK 0x4u
bogdanm 0:9b334a45a8ff 2150 #define LCD_WF8B_BPCLCD38_SHIFT 2
bogdanm 0:9b334a45a8ff 2151 #define LCD_WF8B_BPCLCD44_MASK 0x4u
bogdanm 0:9b334a45a8ff 2152 #define LCD_WF8B_BPCLCD44_SHIFT 2
bogdanm 0:9b334a45a8ff 2153 #define LCD_WF8B_BPCLCD31_MASK 0x4u
bogdanm 0:9b334a45a8ff 2154 #define LCD_WF8B_BPCLCD31_SHIFT 2
bogdanm 0:9b334a45a8ff 2155 #define LCD_WF8B_BPCLCD40_MASK 0x4u
bogdanm 0:9b334a45a8ff 2156 #define LCD_WF8B_BPCLCD40_SHIFT 2
bogdanm 0:9b334a45a8ff 2157 #define LCD_WF8B_BPCLCD62_MASK 0x4u
bogdanm 0:9b334a45a8ff 2158 #define LCD_WF8B_BPCLCD62_SHIFT 2
bogdanm 0:9b334a45a8ff 2159 #define LCD_WF8B_BPCLCD56_MASK 0x4u
bogdanm 0:9b334a45a8ff 2160 #define LCD_WF8B_BPCLCD56_SHIFT 2
bogdanm 0:9b334a45a8ff 2161 #define LCD_WF8B_BPCLCD39_MASK 0x4u
bogdanm 0:9b334a45a8ff 2162 #define LCD_WF8B_BPCLCD39_SHIFT 2
bogdanm 0:9b334a45a8ff 2163 #define LCD_WF8B_BPCLCD6_MASK 0x4u
bogdanm 0:9b334a45a8ff 2164 #define LCD_WF8B_BPCLCD6_SHIFT 2
bogdanm 0:9b334a45a8ff 2165 #define LCD_WF8B_BPDLCD47_MASK 0x8u
bogdanm 0:9b334a45a8ff 2166 #define LCD_WF8B_BPDLCD47_SHIFT 3
bogdanm 0:9b334a45a8ff 2167 #define LCD_WF8B_BPDLCD23_MASK 0x8u
bogdanm 0:9b334a45a8ff 2168 #define LCD_WF8B_BPDLCD23_SHIFT 3
bogdanm 0:9b334a45a8ff 2169 #define LCD_WF8B_BPDLCD48_MASK 0x8u
bogdanm 0:9b334a45a8ff 2170 #define LCD_WF8B_BPDLCD48_SHIFT 3
bogdanm 0:9b334a45a8ff 2171 #define LCD_WF8B_BPDLCD24_MASK 0x8u
bogdanm 0:9b334a45a8ff 2172 #define LCD_WF8B_BPDLCD24_SHIFT 3
bogdanm 0:9b334a45a8ff 2173 #define LCD_WF8B_BPDLCD15_MASK 0x8u
bogdanm 0:9b334a45a8ff 2174 #define LCD_WF8B_BPDLCD15_SHIFT 3
bogdanm 0:9b334a45a8ff 2175 #define LCD_WF8B_BPDLCD22_MASK 0x8u
bogdanm 0:9b334a45a8ff 2176 #define LCD_WF8B_BPDLCD22_SHIFT 3
bogdanm 0:9b334a45a8ff 2177 #define LCD_WF8B_BPDLCD60_MASK 0x8u
bogdanm 0:9b334a45a8ff 2178 #define LCD_WF8B_BPDLCD60_SHIFT 3
bogdanm 0:9b334a45a8ff 2179 #define LCD_WF8B_BPDLCD10_MASK 0x8u
bogdanm 0:9b334a45a8ff 2180 #define LCD_WF8B_BPDLCD10_SHIFT 3
bogdanm 0:9b334a45a8ff 2181 #define LCD_WF8B_BPDLCD21_MASK 0x8u
bogdanm 0:9b334a45a8ff 2182 #define LCD_WF8B_BPDLCD21_SHIFT 3
bogdanm 0:9b334a45a8ff 2183 #define LCD_WF8B_BPDLCD49_MASK 0x8u
bogdanm 0:9b334a45a8ff 2184 #define LCD_WF8B_BPDLCD49_SHIFT 3
bogdanm 0:9b334a45a8ff 2185 #define LCD_WF8B_BPDLCD1_MASK 0x8u
bogdanm 0:9b334a45a8ff 2186 #define LCD_WF8B_BPDLCD1_SHIFT 3
bogdanm 0:9b334a45a8ff 2187 #define LCD_WF8B_BPDLCD25_MASK 0x8u
bogdanm 0:9b334a45a8ff 2188 #define LCD_WF8B_BPDLCD25_SHIFT 3
bogdanm 0:9b334a45a8ff 2189 #define LCD_WF8B_BPDLCD20_MASK 0x8u
bogdanm 0:9b334a45a8ff 2190 #define LCD_WF8B_BPDLCD20_SHIFT 3
bogdanm 0:9b334a45a8ff 2191 #define LCD_WF8B_BPDLCD2_MASK 0x8u
bogdanm 0:9b334a45a8ff 2192 #define LCD_WF8B_BPDLCD2_SHIFT 3
bogdanm 0:9b334a45a8ff 2193 #define LCD_WF8B_BPDLCD55_MASK 0x8u
bogdanm 0:9b334a45a8ff 2194 #define LCD_WF8B_BPDLCD55_SHIFT 3
bogdanm 0:9b334a45a8ff 2195 #define LCD_WF8B_BPDLCD59_MASK 0x8u
bogdanm 0:9b334a45a8ff 2196 #define LCD_WF8B_BPDLCD59_SHIFT 3
bogdanm 0:9b334a45a8ff 2197 #define LCD_WF8B_BPDLCD5_MASK 0x8u
bogdanm 0:9b334a45a8ff 2198 #define LCD_WF8B_BPDLCD5_SHIFT 3
bogdanm 0:9b334a45a8ff 2199 #define LCD_WF8B_BPDLCD19_MASK 0x8u
bogdanm 0:9b334a45a8ff 2200 #define LCD_WF8B_BPDLCD19_SHIFT 3
bogdanm 0:9b334a45a8ff 2201 #define LCD_WF8B_BPDLCD6_MASK 0x8u
bogdanm 0:9b334a45a8ff 2202 #define LCD_WF8B_BPDLCD6_SHIFT 3
bogdanm 0:9b334a45a8ff 2203 #define LCD_WF8B_BPDLCD26_MASK 0x8u
bogdanm 0:9b334a45a8ff 2204 #define LCD_WF8B_BPDLCD26_SHIFT 3
bogdanm 0:9b334a45a8ff 2205 #define LCD_WF8B_BPDLCD0_MASK 0x8u
bogdanm 0:9b334a45a8ff 2206 #define LCD_WF8B_BPDLCD0_SHIFT 3
bogdanm 0:9b334a45a8ff 2207 #define LCD_WF8B_BPDLCD50_MASK 0x8u
bogdanm 0:9b334a45a8ff 2208 #define LCD_WF8B_BPDLCD50_SHIFT 3
bogdanm 0:9b334a45a8ff 2209 #define LCD_WF8B_BPDLCD46_MASK 0x8u
bogdanm 0:9b334a45a8ff 2210 #define LCD_WF8B_BPDLCD46_SHIFT 3
bogdanm 0:9b334a45a8ff 2211 #define LCD_WF8B_BPDLCD18_MASK 0x8u
bogdanm 0:9b334a45a8ff 2212 #define LCD_WF8B_BPDLCD18_SHIFT 3
bogdanm 0:9b334a45a8ff 2213 #define LCD_WF8B_BPDLCD61_MASK 0x8u
bogdanm 0:9b334a45a8ff 2214 #define LCD_WF8B_BPDLCD61_SHIFT 3
bogdanm 0:9b334a45a8ff 2215 #define LCD_WF8B_BPDLCD9_MASK 0x8u
bogdanm 0:9b334a45a8ff 2216 #define LCD_WF8B_BPDLCD9_SHIFT 3
bogdanm 0:9b334a45a8ff 2217 #define LCD_WF8B_BPDLCD17_MASK 0x8u
bogdanm 0:9b334a45a8ff 2218 #define LCD_WF8B_BPDLCD17_SHIFT 3
bogdanm 0:9b334a45a8ff 2219 #define LCD_WF8B_BPDLCD27_MASK 0x8u
bogdanm 0:9b334a45a8ff 2220 #define LCD_WF8B_BPDLCD27_SHIFT 3
bogdanm 0:9b334a45a8ff 2221 #define LCD_WF8B_BPDLCD53_MASK 0x8u
bogdanm 0:9b334a45a8ff 2222 #define LCD_WF8B_BPDLCD53_SHIFT 3
bogdanm 0:9b334a45a8ff 2223 #define LCD_WF8B_BPDLCD51_MASK 0x8u
bogdanm 0:9b334a45a8ff 2224 #define LCD_WF8B_BPDLCD51_SHIFT 3
bogdanm 0:9b334a45a8ff 2225 #define LCD_WF8B_BPDLCD54_MASK 0x8u
bogdanm 0:9b334a45a8ff 2226 #define LCD_WF8B_BPDLCD54_SHIFT 3
bogdanm 0:9b334a45a8ff 2227 #define LCD_WF8B_BPDLCD13_MASK 0x8u
bogdanm 0:9b334a45a8ff 2228 #define LCD_WF8B_BPDLCD13_SHIFT 3
bogdanm 0:9b334a45a8ff 2229 #define LCD_WF8B_BPDLCD16_MASK 0x8u
bogdanm 0:9b334a45a8ff 2230 #define LCD_WF8B_BPDLCD16_SHIFT 3
bogdanm 0:9b334a45a8ff 2231 #define LCD_WF8B_BPDLCD32_MASK 0x8u
bogdanm 0:9b334a45a8ff 2232 #define LCD_WF8B_BPDLCD32_SHIFT 3
bogdanm 0:9b334a45a8ff 2233 #define LCD_WF8B_BPDLCD14_MASK 0x8u
bogdanm 0:9b334a45a8ff 2234 #define LCD_WF8B_BPDLCD14_SHIFT 3
bogdanm 0:9b334a45a8ff 2235 #define LCD_WF8B_BPDLCD28_MASK 0x8u
bogdanm 0:9b334a45a8ff 2236 #define LCD_WF8B_BPDLCD28_SHIFT 3
bogdanm 0:9b334a45a8ff 2237 #define LCD_WF8B_BPDLCD43_MASK 0x8u
bogdanm 0:9b334a45a8ff 2238 #define LCD_WF8B_BPDLCD43_SHIFT 3
bogdanm 0:9b334a45a8ff 2239 #define LCD_WF8B_BPDLCD4_MASK 0x8u
bogdanm 0:9b334a45a8ff 2240 #define LCD_WF8B_BPDLCD4_SHIFT 3
bogdanm 0:9b334a45a8ff 2241 #define LCD_WF8B_BPDLCD45_MASK 0x8u
bogdanm 0:9b334a45a8ff 2242 #define LCD_WF8B_BPDLCD45_SHIFT 3
bogdanm 0:9b334a45a8ff 2243 #define LCD_WF8B_BPDLCD8_MASK 0x8u
bogdanm 0:9b334a45a8ff 2244 #define LCD_WF8B_BPDLCD8_SHIFT 3
bogdanm 0:9b334a45a8ff 2245 #define LCD_WF8B_BPDLCD62_MASK 0x8u
bogdanm 0:9b334a45a8ff 2246 #define LCD_WF8B_BPDLCD62_SHIFT 3
bogdanm 0:9b334a45a8ff 2247 #define LCD_WF8B_BPDLCD33_MASK 0x8u
bogdanm 0:9b334a45a8ff 2248 #define LCD_WF8B_BPDLCD33_SHIFT 3
bogdanm 0:9b334a45a8ff 2249 #define LCD_WF8B_BPDLCD34_MASK 0x8u
bogdanm 0:9b334a45a8ff 2250 #define LCD_WF8B_BPDLCD34_SHIFT 3
bogdanm 0:9b334a45a8ff 2251 #define LCD_WF8B_BPDLCD29_MASK 0x8u
bogdanm 0:9b334a45a8ff 2252 #define LCD_WF8B_BPDLCD29_SHIFT 3
bogdanm 0:9b334a45a8ff 2253 #define LCD_WF8B_BPDLCD58_MASK 0x8u
bogdanm 0:9b334a45a8ff 2254 #define LCD_WF8B_BPDLCD58_SHIFT 3
bogdanm 0:9b334a45a8ff 2255 #define LCD_WF8B_BPDLCD57_MASK 0x8u
bogdanm 0:9b334a45a8ff 2256 #define LCD_WF8B_BPDLCD57_SHIFT 3
bogdanm 0:9b334a45a8ff 2257 #define LCD_WF8B_BPDLCD42_MASK 0x8u
bogdanm 0:9b334a45a8ff 2258 #define LCD_WF8B_BPDLCD42_SHIFT 3
bogdanm 0:9b334a45a8ff 2259 #define LCD_WF8B_BPDLCD35_MASK 0x8u
bogdanm 0:9b334a45a8ff 2260 #define LCD_WF8B_BPDLCD35_SHIFT 3
bogdanm 0:9b334a45a8ff 2261 #define LCD_WF8B_BPDLCD52_MASK 0x8u
bogdanm 0:9b334a45a8ff 2262 #define LCD_WF8B_BPDLCD52_SHIFT 3
bogdanm 0:9b334a45a8ff 2263 #define LCD_WF8B_BPDLCD7_MASK 0x8u
bogdanm 0:9b334a45a8ff 2264 #define LCD_WF8B_BPDLCD7_SHIFT 3
bogdanm 0:9b334a45a8ff 2265 #define LCD_WF8B_BPDLCD36_MASK 0x8u
bogdanm 0:9b334a45a8ff 2266 #define LCD_WF8B_BPDLCD36_SHIFT 3
bogdanm 0:9b334a45a8ff 2267 #define LCD_WF8B_BPDLCD30_MASK 0x8u
bogdanm 0:9b334a45a8ff 2268 #define LCD_WF8B_BPDLCD30_SHIFT 3
bogdanm 0:9b334a45a8ff 2269 #define LCD_WF8B_BPDLCD41_MASK 0x8u
bogdanm 0:9b334a45a8ff 2270 #define LCD_WF8B_BPDLCD41_SHIFT 3
bogdanm 0:9b334a45a8ff 2271 #define LCD_WF8B_BPDLCD37_MASK 0x8u
bogdanm 0:9b334a45a8ff 2272 #define LCD_WF8B_BPDLCD37_SHIFT 3
bogdanm 0:9b334a45a8ff 2273 #define LCD_WF8B_BPDLCD44_MASK 0x8u
bogdanm 0:9b334a45a8ff 2274 #define LCD_WF8B_BPDLCD44_SHIFT 3
bogdanm 0:9b334a45a8ff 2275 #define LCD_WF8B_BPDLCD63_MASK 0x8u
bogdanm 0:9b334a45a8ff 2276 #define LCD_WF8B_BPDLCD63_SHIFT 3
bogdanm 0:9b334a45a8ff 2277 #define LCD_WF8B_BPDLCD38_MASK 0x8u
bogdanm 0:9b334a45a8ff 2278 #define LCD_WF8B_BPDLCD38_SHIFT 3
bogdanm 0:9b334a45a8ff 2279 #define LCD_WF8B_BPDLCD56_MASK 0x8u
bogdanm 0:9b334a45a8ff 2280 #define LCD_WF8B_BPDLCD56_SHIFT 3
bogdanm 0:9b334a45a8ff 2281 #define LCD_WF8B_BPDLCD40_MASK 0x8u
bogdanm 0:9b334a45a8ff 2282 #define LCD_WF8B_BPDLCD40_SHIFT 3
bogdanm 0:9b334a45a8ff 2283 #define LCD_WF8B_BPDLCD31_MASK 0x8u
bogdanm 0:9b334a45a8ff 2284 #define LCD_WF8B_BPDLCD31_SHIFT 3
bogdanm 0:9b334a45a8ff 2285 #define LCD_WF8B_BPDLCD12_MASK 0x8u
bogdanm 0:9b334a45a8ff 2286 #define LCD_WF8B_BPDLCD12_SHIFT 3
bogdanm 0:9b334a45a8ff 2287 #define LCD_WF8B_BPDLCD39_MASK 0x8u
bogdanm 0:9b334a45a8ff 2288 #define LCD_WF8B_BPDLCD39_SHIFT 3
bogdanm 0:9b334a45a8ff 2289 #define LCD_WF8B_BPDLCD3_MASK 0x8u
bogdanm 0:9b334a45a8ff 2290 #define LCD_WF8B_BPDLCD3_SHIFT 3
bogdanm 0:9b334a45a8ff 2291 #define LCD_WF8B_BPDLCD11_MASK 0x8u
bogdanm 0:9b334a45a8ff 2292 #define LCD_WF8B_BPDLCD11_SHIFT 3
bogdanm 0:9b334a45a8ff 2293 #define LCD_WF8B_BPELCD12_MASK 0x10u
bogdanm 0:9b334a45a8ff 2294 #define LCD_WF8B_BPELCD12_SHIFT 4
bogdanm 0:9b334a45a8ff 2295 #define LCD_WF8B_BPELCD39_MASK 0x10u
bogdanm 0:9b334a45a8ff 2296 #define LCD_WF8B_BPELCD39_SHIFT 4
bogdanm 0:9b334a45a8ff 2297 #define LCD_WF8B_BPELCD3_MASK 0x10u
bogdanm 0:9b334a45a8ff 2298 #define LCD_WF8B_BPELCD3_SHIFT 4
bogdanm 0:9b334a45a8ff 2299 #define LCD_WF8B_BPELCD38_MASK 0x10u
bogdanm 0:9b334a45a8ff 2300 #define LCD_WF8B_BPELCD38_SHIFT 4
bogdanm 0:9b334a45a8ff 2301 #define LCD_WF8B_BPELCD40_MASK 0x10u
bogdanm 0:9b334a45a8ff 2302 #define LCD_WF8B_BPELCD40_SHIFT 4
bogdanm 0:9b334a45a8ff 2303 #define LCD_WF8B_BPELCD37_MASK 0x10u
bogdanm 0:9b334a45a8ff 2304 #define LCD_WF8B_BPELCD37_SHIFT 4
bogdanm 0:9b334a45a8ff 2305 #define LCD_WF8B_BPELCD41_MASK 0x10u
bogdanm 0:9b334a45a8ff 2306 #define LCD_WF8B_BPELCD41_SHIFT 4
bogdanm 0:9b334a45a8ff 2307 #define LCD_WF8B_BPELCD36_MASK 0x10u
bogdanm 0:9b334a45a8ff 2308 #define LCD_WF8B_BPELCD36_SHIFT 4
bogdanm 0:9b334a45a8ff 2309 #define LCD_WF8B_BPELCD8_MASK 0x10u
bogdanm 0:9b334a45a8ff 2310 #define LCD_WF8B_BPELCD8_SHIFT 4
bogdanm 0:9b334a45a8ff 2311 #define LCD_WF8B_BPELCD35_MASK 0x10u
bogdanm 0:9b334a45a8ff 2312 #define LCD_WF8B_BPELCD35_SHIFT 4
bogdanm 0:9b334a45a8ff 2313 #define LCD_WF8B_BPELCD42_MASK 0x10u
bogdanm 0:9b334a45a8ff 2314 #define LCD_WF8B_BPELCD42_SHIFT 4
bogdanm 0:9b334a45a8ff 2315 #define LCD_WF8B_BPELCD34_MASK 0x10u
bogdanm 0:9b334a45a8ff 2316 #define LCD_WF8B_BPELCD34_SHIFT 4
bogdanm 0:9b334a45a8ff 2317 #define LCD_WF8B_BPELCD33_MASK 0x10u
bogdanm 0:9b334a45a8ff 2318 #define LCD_WF8B_BPELCD33_SHIFT 4
bogdanm 0:9b334a45a8ff 2319 #define LCD_WF8B_BPELCD11_MASK 0x10u
bogdanm 0:9b334a45a8ff 2320 #define LCD_WF8B_BPELCD11_SHIFT 4
bogdanm 0:9b334a45a8ff 2321 #define LCD_WF8B_BPELCD43_MASK 0x10u
bogdanm 0:9b334a45a8ff 2322 #define LCD_WF8B_BPELCD43_SHIFT 4
bogdanm 0:9b334a45a8ff 2323 #define LCD_WF8B_BPELCD32_MASK 0x10u
bogdanm 0:9b334a45a8ff 2324 #define LCD_WF8B_BPELCD32_SHIFT 4
bogdanm 0:9b334a45a8ff 2325 #define LCD_WF8B_BPELCD31_MASK 0x10u
bogdanm 0:9b334a45a8ff 2326 #define LCD_WF8B_BPELCD31_SHIFT 4
bogdanm 0:9b334a45a8ff 2327 #define LCD_WF8B_BPELCD44_MASK 0x10u
bogdanm 0:9b334a45a8ff 2328 #define LCD_WF8B_BPELCD44_SHIFT 4
bogdanm 0:9b334a45a8ff 2329 #define LCD_WF8B_BPELCD30_MASK 0x10u
bogdanm 0:9b334a45a8ff 2330 #define LCD_WF8B_BPELCD30_SHIFT 4
bogdanm 0:9b334a45a8ff 2331 #define LCD_WF8B_BPELCD29_MASK 0x10u
bogdanm 0:9b334a45a8ff 2332 #define LCD_WF8B_BPELCD29_SHIFT 4
bogdanm 0:9b334a45a8ff 2333 #define LCD_WF8B_BPELCD7_MASK 0x10u
bogdanm 0:9b334a45a8ff 2334 #define LCD_WF8B_BPELCD7_SHIFT 4
bogdanm 0:9b334a45a8ff 2335 #define LCD_WF8B_BPELCD45_MASK 0x10u
bogdanm 0:9b334a45a8ff 2336 #define LCD_WF8B_BPELCD45_SHIFT 4
bogdanm 0:9b334a45a8ff 2337 #define LCD_WF8B_BPELCD28_MASK 0x10u
bogdanm 0:9b334a45a8ff 2338 #define LCD_WF8B_BPELCD28_SHIFT 4
bogdanm 0:9b334a45a8ff 2339 #define LCD_WF8B_BPELCD2_MASK 0x10u
bogdanm 0:9b334a45a8ff 2340 #define LCD_WF8B_BPELCD2_SHIFT 4
bogdanm 0:9b334a45a8ff 2341 #define LCD_WF8B_BPELCD27_MASK 0x10u
bogdanm 0:9b334a45a8ff 2342 #define LCD_WF8B_BPELCD27_SHIFT 4
bogdanm 0:9b334a45a8ff 2343 #define LCD_WF8B_BPELCD46_MASK 0x10u
bogdanm 0:9b334a45a8ff 2344 #define LCD_WF8B_BPELCD46_SHIFT 4
bogdanm 0:9b334a45a8ff 2345 #define LCD_WF8B_BPELCD26_MASK 0x10u
bogdanm 0:9b334a45a8ff 2346 #define LCD_WF8B_BPELCD26_SHIFT 4
bogdanm 0:9b334a45a8ff 2347 #define LCD_WF8B_BPELCD10_MASK 0x10u
bogdanm 0:9b334a45a8ff 2348 #define LCD_WF8B_BPELCD10_SHIFT 4
bogdanm 0:9b334a45a8ff 2349 #define LCD_WF8B_BPELCD13_MASK 0x10u
bogdanm 0:9b334a45a8ff 2350 #define LCD_WF8B_BPELCD13_SHIFT 4
bogdanm 0:9b334a45a8ff 2351 #define LCD_WF8B_BPELCD25_MASK 0x10u
bogdanm 0:9b334a45a8ff 2352 #define LCD_WF8B_BPELCD25_SHIFT 4
bogdanm 0:9b334a45a8ff 2353 #define LCD_WF8B_BPELCD5_MASK 0x10u
bogdanm 0:9b334a45a8ff 2354 #define LCD_WF8B_BPELCD5_SHIFT 4
bogdanm 0:9b334a45a8ff 2355 #define LCD_WF8B_BPELCD24_MASK 0x10u
bogdanm 0:9b334a45a8ff 2356 #define LCD_WF8B_BPELCD24_SHIFT 4
bogdanm 0:9b334a45a8ff 2357 #define LCD_WF8B_BPELCD47_MASK 0x10u
bogdanm 0:9b334a45a8ff 2358 #define LCD_WF8B_BPELCD47_SHIFT 4
bogdanm 0:9b334a45a8ff 2359 #define LCD_WF8B_BPELCD23_MASK 0x10u
bogdanm 0:9b334a45a8ff 2360 #define LCD_WF8B_BPELCD23_SHIFT 4
bogdanm 0:9b334a45a8ff 2361 #define LCD_WF8B_BPELCD22_MASK 0x10u
bogdanm 0:9b334a45a8ff 2362 #define LCD_WF8B_BPELCD22_SHIFT 4
bogdanm 0:9b334a45a8ff 2363 #define LCD_WF8B_BPELCD48_MASK 0x10u
bogdanm 0:9b334a45a8ff 2364 #define LCD_WF8B_BPELCD48_SHIFT 4
bogdanm 0:9b334a45a8ff 2365 #define LCD_WF8B_BPELCD21_MASK 0x10u
bogdanm 0:9b334a45a8ff 2366 #define LCD_WF8B_BPELCD21_SHIFT 4
bogdanm 0:9b334a45a8ff 2367 #define LCD_WF8B_BPELCD49_MASK 0x10u
bogdanm 0:9b334a45a8ff 2368 #define LCD_WF8B_BPELCD49_SHIFT 4
bogdanm 0:9b334a45a8ff 2369 #define LCD_WF8B_BPELCD20_MASK 0x10u
bogdanm 0:9b334a45a8ff 2370 #define LCD_WF8B_BPELCD20_SHIFT 4
bogdanm 0:9b334a45a8ff 2371 #define LCD_WF8B_BPELCD19_MASK 0x10u
bogdanm 0:9b334a45a8ff 2372 #define LCD_WF8B_BPELCD19_SHIFT 4
bogdanm 0:9b334a45a8ff 2373 #define LCD_WF8B_BPELCD9_MASK 0x10u
bogdanm 0:9b334a45a8ff 2374 #define LCD_WF8B_BPELCD9_SHIFT 4
bogdanm 0:9b334a45a8ff 2375 #define LCD_WF8B_BPELCD50_MASK 0x10u
bogdanm 0:9b334a45a8ff 2376 #define LCD_WF8B_BPELCD50_SHIFT 4
bogdanm 0:9b334a45a8ff 2377 #define LCD_WF8B_BPELCD18_MASK 0x10u
bogdanm 0:9b334a45a8ff 2378 #define LCD_WF8B_BPELCD18_SHIFT 4
bogdanm 0:9b334a45a8ff 2379 #define LCD_WF8B_BPELCD6_MASK 0x10u
bogdanm 0:9b334a45a8ff 2380 #define LCD_WF8B_BPELCD6_SHIFT 4
bogdanm 0:9b334a45a8ff 2381 #define LCD_WF8B_BPELCD17_MASK 0x10u
bogdanm 0:9b334a45a8ff 2382 #define LCD_WF8B_BPELCD17_SHIFT 4
bogdanm 0:9b334a45a8ff 2383 #define LCD_WF8B_BPELCD51_MASK 0x10u
bogdanm 0:9b334a45a8ff 2384 #define LCD_WF8B_BPELCD51_SHIFT 4
bogdanm 0:9b334a45a8ff 2385 #define LCD_WF8B_BPELCD16_MASK 0x10u
bogdanm 0:9b334a45a8ff 2386 #define LCD_WF8B_BPELCD16_SHIFT 4
bogdanm 0:9b334a45a8ff 2387 #define LCD_WF8B_BPELCD56_MASK 0x10u
bogdanm 0:9b334a45a8ff 2388 #define LCD_WF8B_BPELCD56_SHIFT 4
bogdanm 0:9b334a45a8ff 2389 #define LCD_WF8B_BPELCD57_MASK 0x10u
bogdanm 0:9b334a45a8ff 2390 #define LCD_WF8B_BPELCD57_SHIFT 4
bogdanm 0:9b334a45a8ff 2391 #define LCD_WF8B_BPELCD52_MASK 0x10u
bogdanm 0:9b334a45a8ff 2392 #define LCD_WF8B_BPELCD52_SHIFT 4
bogdanm 0:9b334a45a8ff 2393 #define LCD_WF8B_BPELCD1_MASK 0x10u
bogdanm 0:9b334a45a8ff 2394 #define LCD_WF8B_BPELCD1_SHIFT 4
bogdanm 0:9b334a45a8ff 2395 #define LCD_WF8B_BPELCD58_MASK 0x10u
bogdanm 0:9b334a45a8ff 2396 #define LCD_WF8B_BPELCD58_SHIFT 4
bogdanm 0:9b334a45a8ff 2397 #define LCD_WF8B_BPELCD59_MASK 0x10u
bogdanm 0:9b334a45a8ff 2398 #define LCD_WF8B_BPELCD59_SHIFT 4
bogdanm 0:9b334a45a8ff 2399 #define LCD_WF8B_BPELCD53_MASK 0x10u
bogdanm 0:9b334a45a8ff 2400 #define LCD_WF8B_BPELCD53_SHIFT 4
bogdanm 0:9b334a45a8ff 2401 #define LCD_WF8B_BPELCD14_MASK 0x10u
bogdanm 0:9b334a45a8ff 2402 #define LCD_WF8B_BPELCD14_SHIFT 4
bogdanm 0:9b334a45a8ff 2403 #define LCD_WF8B_BPELCD0_MASK 0x10u
bogdanm 0:9b334a45a8ff 2404 #define LCD_WF8B_BPELCD0_SHIFT 4
bogdanm 0:9b334a45a8ff 2405 #define LCD_WF8B_BPELCD60_MASK 0x10u
bogdanm 0:9b334a45a8ff 2406 #define LCD_WF8B_BPELCD60_SHIFT 4
bogdanm 0:9b334a45a8ff 2407 #define LCD_WF8B_BPELCD15_MASK 0x10u
bogdanm 0:9b334a45a8ff 2408 #define LCD_WF8B_BPELCD15_SHIFT 4
bogdanm 0:9b334a45a8ff 2409 #define LCD_WF8B_BPELCD61_MASK 0x10u
bogdanm 0:9b334a45a8ff 2410 #define LCD_WF8B_BPELCD61_SHIFT 4
bogdanm 0:9b334a45a8ff 2411 #define LCD_WF8B_BPELCD54_MASK 0x10u
bogdanm 0:9b334a45a8ff 2412 #define LCD_WF8B_BPELCD54_SHIFT 4
bogdanm 0:9b334a45a8ff 2413 #define LCD_WF8B_BPELCD62_MASK 0x10u
bogdanm 0:9b334a45a8ff 2414 #define LCD_WF8B_BPELCD62_SHIFT 4
bogdanm 0:9b334a45a8ff 2415 #define LCD_WF8B_BPELCD63_MASK 0x10u
bogdanm 0:9b334a45a8ff 2416 #define LCD_WF8B_BPELCD63_SHIFT 4
bogdanm 0:9b334a45a8ff 2417 #define LCD_WF8B_BPELCD55_MASK 0x10u
bogdanm 0:9b334a45a8ff 2418 #define LCD_WF8B_BPELCD55_SHIFT 4
bogdanm 0:9b334a45a8ff 2419 #define LCD_WF8B_BPELCD4_MASK 0x10u
bogdanm 0:9b334a45a8ff 2420 #define LCD_WF8B_BPELCD4_SHIFT 4
bogdanm 0:9b334a45a8ff 2421 #define LCD_WF8B_BPFLCD13_MASK 0x20u
bogdanm 0:9b334a45a8ff 2422 #define LCD_WF8B_BPFLCD13_SHIFT 5
bogdanm 0:9b334a45a8ff 2423 #define LCD_WF8B_BPFLCD39_MASK 0x20u
bogdanm 0:9b334a45a8ff 2424 #define LCD_WF8B_BPFLCD39_SHIFT 5
bogdanm 0:9b334a45a8ff 2425 #define LCD_WF8B_BPFLCD55_MASK 0x20u
bogdanm 0:9b334a45a8ff 2426 #define LCD_WF8B_BPFLCD55_SHIFT 5
bogdanm 0:9b334a45a8ff 2427 #define LCD_WF8B_BPFLCD47_MASK 0x20u
bogdanm 0:9b334a45a8ff 2428 #define LCD_WF8B_BPFLCD47_SHIFT 5
bogdanm 0:9b334a45a8ff 2429 #define LCD_WF8B_BPFLCD63_MASK 0x20u
bogdanm 0:9b334a45a8ff 2430 #define LCD_WF8B_BPFLCD63_SHIFT 5
bogdanm 0:9b334a45a8ff 2431 #define LCD_WF8B_BPFLCD43_MASK 0x20u
bogdanm 0:9b334a45a8ff 2432 #define LCD_WF8B_BPFLCD43_SHIFT 5
bogdanm 0:9b334a45a8ff 2433 #define LCD_WF8B_BPFLCD5_MASK 0x20u
bogdanm 0:9b334a45a8ff 2434 #define LCD_WF8B_BPFLCD5_SHIFT 5
bogdanm 0:9b334a45a8ff 2435 #define LCD_WF8B_BPFLCD62_MASK 0x20u
bogdanm 0:9b334a45a8ff 2436 #define LCD_WF8B_BPFLCD62_SHIFT 5
bogdanm 0:9b334a45a8ff 2437 #define LCD_WF8B_BPFLCD14_MASK 0x20u
bogdanm 0:9b334a45a8ff 2438 #define LCD_WF8B_BPFLCD14_SHIFT 5
bogdanm 0:9b334a45a8ff 2439 #define LCD_WF8B_BPFLCD24_MASK 0x20u
bogdanm 0:9b334a45a8ff 2440 #define LCD_WF8B_BPFLCD24_SHIFT 5
bogdanm 0:9b334a45a8ff 2441 #define LCD_WF8B_BPFLCD54_MASK 0x20u
bogdanm 0:9b334a45a8ff 2442 #define LCD_WF8B_BPFLCD54_SHIFT 5
bogdanm 0:9b334a45a8ff 2443 #define LCD_WF8B_BPFLCD15_MASK 0x20u
bogdanm 0:9b334a45a8ff 2444 #define LCD_WF8B_BPFLCD15_SHIFT 5
bogdanm 0:9b334a45a8ff 2445 #define LCD_WF8B_BPFLCD32_MASK 0x20u
bogdanm 0:9b334a45a8ff 2446 #define LCD_WF8B_BPFLCD32_SHIFT 5
bogdanm 0:9b334a45a8ff 2447 #define LCD_WF8B_BPFLCD61_MASK 0x20u
bogdanm 0:9b334a45a8ff 2448 #define LCD_WF8B_BPFLCD61_SHIFT 5
bogdanm 0:9b334a45a8ff 2449 #define LCD_WF8B_BPFLCD25_MASK 0x20u
bogdanm 0:9b334a45a8ff 2450 #define LCD_WF8B_BPFLCD25_SHIFT 5
bogdanm 0:9b334a45a8ff 2451 #define LCD_WF8B_BPFLCD60_MASK 0x20u
bogdanm 0:9b334a45a8ff 2452 #define LCD_WF8B_BPFLCD60_SHIFT 5
bogdanm 0:9b334a45a8ff 2453 #define LCD_WF8B_BPFLCD41_MASK 0x20u
bogdanm 0:9b334a45a8ff 2454 #define LCD_WF8B_BPFLCD41_SHIFT 5
bogdanm 0:9b334a45a8ff 2455 #define LCD_WF8B_BPFLCD33_MASK 0x20u
bogdanm 0:9b334a45a8ff 2456 #define LCD_WF8B_BPFLCD33_SHIFT 5
bogdanm 0:9b334a45a8ff 2457 #define LCD_WF8B_BPFLCD53_MASK 0x20u
bogdanm 0:9b334a45a8ff 2458 #define LCD_WF8B_BPFLCD53_SHIFT 5
bogdanm 0:9b334a45a8ff 2459 #define LCD_WF8B_BPFLCD59_MASK 0x20u
bogdanm 0:9b334a45a8ff 2460 #define LCD_WF8B_BPFLCD59_SHIFT 5
bogdanm 0:9b334a45a8ff 2461 #define LCD_WF8B_BPFLCD0_MASK 0x20u
bogdanm 0:9b334a45a8ff 2462 #define LCD_WF8B_BPFLCD0_SHIFT 5
bogdanm 0:9b334a45a8ff 2463 #define LCD_WF8B_BPFLCD46_MASK 0x20u
bogdanm 0:9b334a45a8ff 2464 #define LCD_WF8B_BPFLCD46_SHIFT 5
bogdanm 0:9b334a45a8ff 2465 #define LCD_WF8B_BPFLCD58_MASK 0x20u
bogdanm 0:9b334a45a8ff 2466 #define LCD_WF8B_BPFLCD58_SHIFT 5
bogdanm 0:9b334a45a8ff 2467 #define LCD_WF8B_BPFLCD26_MASK 0x20u
bogdanm 0:9b334a45a8ff 2468 #define LCD_WF8B_BPFLCD26_SHIFT 5
bogdanm 0:9b334a45a8ff 2469 #define LCD_WF8B_BPFLCD36_MASK 0x20u
bogdanm 0:9b334a45a8ff 2470 #define LCD_WF8B_BPFLCD36_SHIFT 5
bogdanm 0:9b334a45a8ff 2471 #define LCD_WF8B_BPFLCD10_MASK 0x20u
bogdanm 0:9b334a45a8ff 2472 #define LCD_WF8B_BPFLCD10_SHIFT 5
bogdanm 0:9b334a45a8ff 2473 #define LCD_WF8B_BPFLCD52_MASK 0x20u
bogdanm 0:9b334a45a8ff 2474 #define LCD_WF8B_BPFLCD52_SHIFT 5
bogdanm 0:9b334a45a8ff 2475 #define LCD_WF8B_BPFLCD57_MASK 0x20u
bogdanm 0:9b334a45a8ff 2476 #define LCD_WF8B_BPFLCD57_SHIFT 5
bogdanm 0:9b334a45a8ff 2477 #define LCD_WF8B_BPFLCD27_MASK 0x20u
bogdanm 0:9b334a45a8ff 2478 #define LCD_WF8B_BPFLCD27_SHIFT 5
bogdanm 0:9b334a45a8ff 2479 #define LCD_WF8B_BPFLCD11_MASK 0x20u
bogdanm 0:9b334a45a8ff 2480 #define LCD_WF8B_BPFLCD11_SHIFT 5
bogdanm 0:9b334a45a8ff 2481 #define LCD_WF8B_BPFLCD56_MASK 0x20u
bogdanm 0:9b334a45a8ff 2482 #define LCD_WF8B_BPFLCD56_SHIFT 5
bogdanm 0:9b334a45a8ff 2483 #define LCD_WF8B_BPFLCD1_MASK 0x20u
bogdanm 0:9b334a45a8ff 2484 #define LCD_WF8B_BPFLCD1_SHIFT 5
bogdanm 0:9b334a45a8ff 2485 #define LCD_WF8B_BPFLCD8_MASK 0x20u
bogdanm 0:9b334a45a8ff 2486 #define LCD_WF8B_BPFLCD8_SHIFT 5
bogdanm 0:9b334a45a8ff 2487 #define LCD_WF8B_BPFLCD40_MASK 0x20u
bogdanm 0:9b334a45a8ff 2488 #define LCD_WF8B_BPFLCD40_SHIFT 5
bogdanm 0:9b334a45a8ff 2489 #define LCD_WF8B_BPFLCD51_MASK 0x20u
bogdanm 0:9b334a45a8ff 2490 #define LCD_WF8B_BPFLCD51_SHIFT 5
bogdanm 0:9b334a45a8ff 2491 #define LCD_WF8B_BPFLCD16_MASK 0x20u
bogdanm 0:9b334a45a8ff 2492 #define LCD_WF8B_BPFLCD16_SHIFT 5
bogdanm 0:9b334a45a8ff 2493 #define LCD_WF8B_BPFLCD45_MASK 0x20u
bogdanm 0:9b334a45a8ff 2494 #define LCD_WF8B_BPFLCD45_SHIFT 5
bogdanm 0:9b334a45a8ff 2495 #define LCD_WF8B_BPFLCD6_MASK 0x20u
bogdanm 0:9b334a45a8ff 2496 #define LCD_WF8B_BPFLCD6_SHIFT 5
bogdanm 0:9b334a45a8ff 2497 #define LCD_WF8B_BPFLCD17_MASK 0x20u
bogdanm 0:9b334a45a8ff 2498 #define LCD_WF8B_BPFLCD17_SHIFT 5
bogdanm 0:9b334a45a8ff 2499 #define LCD_WF8B_BPFLCD28_MASK 0x20u
bogdanm 0:9b334a45a8ff 2500 #define LCD_WF8B_BPFLCD28_SHIFT 5
bogdanm 0:9b334a45a8ff 2501 #define LCD_WF8B_BPFLCD42_MASK 0x20u
bogdanm 0:9b334a45a8ff 2502 #define LCD_WF8B_BPFLCD42_SHIFT 5
bogdanm 0:9b334a45a8ff 2503 #define LCD_WF8B_BPFLCD29_MASK 0x20u
bogdanm 0:9b334a45a8ff 2504 #define LCD_WF8B_BPFLCD29_SHIFT 5
bogdanm 0:9b334a45a8ff 2505 #define LCD_WF8B_BPFLCD50_MASK 0x20u
bogdanm 0:9b334a45a8ff 2506 #define LCD_WF8B_BPFLCD50_SHIFT 5
bogdanm 0:9b334a45a8ff 2507 #define LCD_WF8B_BPFLCD18_MASK 0x20u
bogdanm 0:9b334a45a8ff 2508 #define LCD_WF8B_BPFLCD18_SHIFT 5
bogdanm 0:9b334a45a8ff 2509 #define LCD_WF8B_BPFLCD34_MASK 0x20u
bogdanm 0:9b334a45a8ff 2510 #define LCD_WF8B_BPFLCD34_SHIFT 5
bogdanm 0:9b334a45a8ff 2511 #define LCD_WF8B_BPFLCD19_MASK 0x20u
bogdanm 0:9b334a45a8ff 2512 #define LCD_WF8B_BPFLCD19_SHIFT 5
bogdanm 0:9b334a45a8ff 2513 #define LCD_WF8B_BPFLCD2_MASK 0x20u
bogdanm 0:9b334a45a8ff 2514 #define LCD_WF8B_BPFLCD2_SHIFT 5
bogdanm 0:9b334a45a8ff 2515 #define LCD_WF8B_BPFLCD9_MASK 0x20u
bogdanm 0:9b334a45a8ff 2516 #define LCD_WF8B_BPFLCD9_SHIFT 5
bogdanm 0:9b334a45a8ff 2517 #define LCD_WF8B_BPFLCD3_MASK 0x20u
bogdanm 0:9b334a45a8ff 2518 #define LCD_WF8B_BPFLCD3_SHIFT 5
bogdanm 0:9b334a45a8ff 2519 #define LCD_WF8B_BPFLCD37_MASK 0x20u
bogdanm 0:9b334a45a8ff 2520 #define LCD_WF8B_BPFLCD37_SHIFT 5
bogdanm 0:9b334a45a8ff 2521 #define LCD_WF8B_BPFLCD49_MASK 0x20u
bogdanm 0:9b334a45a8ff 2522 #define LCD_WF8B_BPFLCD49_SHIFT 5
bogdanm 0:9b334a45a8ff 2523 #define LCD_WF8B_BPFLCD20_MASK 0x20u
bogdanm 0:9b334a45a8ff 2524 #define LCD_WF8B_BPFLCD20_SHIFT 5
bogdanm 0:9b334a45a8ff 2525 #define LCD_WF8B_BPFLCD44_MASK 0x20u
bogdanm 0:9b334a45a8ff 2526 #define LCD_WF8B_BPFLCD44_SHIFT 5
bogdanm 0:9b334a45a8ff 2527 #define LCD_WF8B_BPFLCD30_MASK 0x20u
bogdanm 0:9b334a45a8ff 2528 #define LCD_WF8B_BPFLCD30_SHIFT 5
bogdanm 0:9b334a45a8ff 2529 #define LCD_WF8B_BPFLCD21_MASK 0x20u
bogdanm 0:9b334a45a8ff 2530 #define LCD_WF8B_BPFLCD21_SHIFT 5
bogdanm 0:9b334a45a8ff 2531 #define LCD_WF8B_BPFLCD35_MASK 0x20u
bogdanm 0:9b334a45a8ff 2532 #define LCD_WF8B_BPFLCD35_SHIFT 5
bogdanm 0:9b334a45a8ff 2533 #define LCD_WF8B_BPFLCD4_MASK 0x20u
bogdanm 0:9b334a45a8ff 2534 #define LCD_WF8B_BPFLCD4_SHIFT 5
bogdanm 0:9b334a45a8ff 2535 #define LCD_WF8B_BPFLCD31_MASK 0x20u
bogdanm 0:9b334a45a8ff 2536 #define LCD_WF8B_BPFLCD31_SHIFT 5
bogdanm 0:9b334a45a8ff 2537 #define LCD_WF8B_BPFLCD48_MASK 0x20u
bogdanm 0:9b334a45a8ff 2538 #define LCD_WF8B_BPFLCD48_SHIFT 5
bogdanm 0:9b334a45a8ff 2539 #define LCD_WF8B_BPFLCD7_MASK 0x20u
bogdanm 0:9b334a45a8ff 2540 #define LCD_WF8B_BPFLCD7_SHIFT 5
bogdanm 0:9b334a45a8ff 2541 #define LCD_WF8B_BPFLCD22_MASK 0x20u
bogdanm 0:9b334a45a8ff 2542 #define LCD_WF8B_BPFLCD22_SHIFT 5
bogdanm 0:9b334a45a8ff 2543 #define LCD_WF8B_BPFLCD38_MASK 0x20u
bogdanm 0:9b334a45a8ff 2544 #define LCD_WF8B_BPFLCD38_SHIFT 5
bogdanm 0:9b334a45a8ff 2545 #define LCD_WF8B_BPFLCD12_MASK 0x20u
bogdanm 0:9b334a45a8ff 2546 #define LCD_WF8B_BPFLCD12_SHIFT 5
bogdanm 0:9b334a45a8ff 2547 #define LCD_WF8B_BPFLCD23_MASK 0x20u
bogdanm 0:9b334a45a8ff 2548 #define LCD_WF8B_BPFLCD23_SHIFT 5
bogdanm 0:9b334a45a8ff 2549 #define LCD_WF8B_BPGLCD14_MASK 0x40u
bogdanm 0:9b334a45a8ff 2550 #define LCD_WF8B_BPGLCD14_SHIFT 6
bogdanm 0:9b334a45a8ff 2551 #define LCD_WF8B_BPGLCD55_MASK 0x40u
bogdanm 0:9b334a45a8ff 2552 #define LCD_WF8B_BPGLCD55_SHIFT 6
bogdanm 0:9b334a45a8ff 2553 #define LCD_WF8B_BPGLCD63_MASK 0x40u
bogdanm 0:9b334a45a8ff 2554 #define LCD_WF8B_BPGLCD63_SHIFT 6
bogdanm 0:9b334a45a8ff 2555 #define LCD_WF8B_BPGLCD15_MASK 0x40u
bogdanm 0:9b334a45a8ff 2556 #define LCD_WF8B_BPGLCD15_SHIFT 6
bogdanm 0:9b334a45a8ff 2557 #define LCD_WF8B_BPGLCD62_MASK 0x40u
bogdanm 0:9b334a45a8ff 2558 #define LCD_WF8B_BPGLCD62_SHIFT 6
bogdanm 0:9b334a45a8ff 2559 #define LCD_WF8B_BPGLCD54_MASK 0x40u
bogdanm 0:9b334a45a8ff 2560 #define LCD_WF8B_BPGLCD54_SHIFT 6
bogdanm 0:9b334a45a8ff 2561 #define LCD_WF8B_BPGLCD61_MASK 0x40u
bogdanm 0:9b334a45a8ff 2562 #define LCD_WF8B_BPGLCD61_SHIFT 6
bogdanm 0:9b334a45a8ff 2563 #define LCD_WF8B_BPGLCD60_MASK 0x40u
bogdanm 0:9b334a45a8ff 2564 #define LCD_WF8B_BPGLCD60_SHIFT 6
bogdanm 0:9b334a45a8ff 2565 #define LCD_WF8B_BPGLCD59_MASK 0x40u
bogdanm 0:9b334a45a8ff 2566 #define LCD_WF8B_BPGLCD59_SHIFT 6
bogdanm 0:9b334a45a8ff 2567 #define LCD_WF8B_BPGLCD53_MASK 0x40u
bogdanm 0:9b334a45a8ff 2568 #define LCD_WF8B_BPGLCD53_SHIFT 6
bogdanm 0:9b334a45a8ff 2569 #define LCD_WF8B_BPGLCD58_MASK 0x40u
bogdanm 0:9b334a45a8ff 2570 #define LCD_WF8B_BPGLCD58_SHIFT 6
bogdanm 0:9b334a45a8ff 2571 #define LCD_WF8B_BPGLCD0_MASK 0x40u
bogdanm 0:9b334a45a8ff 2572 #define LCD_WF8B_BPGLCD0_SHIFT 6
bogdanm 0:9b334a45a8ff 2573 #define LCD_WF8B_BPGLCD57_MASK 0x40u
bogdanm 0:9b334a45a8ff 2574 #define LCD_WF8B_BPGLCD57_SHIFT 6
bogdanm 0:9b334a45a8ff 2575 #define LCD_WF8B_BPGLCD52_MASK 0x40u
bogdanm 0:9b334a45a8ff 2576 #define LCD_WF8B_BPGLCD52_SHIFT 6
bogdanm 0:9b334a45a8ff 2577 #define LCD_WF8B_BPGLCD7_MASK 0x40u
bogdanm 0:9b334a45a8ff 2578 #define LCD_WF8B_BPGLCD7_SHIFT 6
bogdanm 0:9b334a45a8ff 2579 #define LCD_WF8B_BPGLCD56_MASK 0x40u
bogdanm 0:9b334a45a8ff 2580 #define LCD_WF8B_BPGLCD56_SHIFT 6
bogdanm 0:9b334a45a8ff 2581 #define LCD_WF8B_BPGLCD6_MASK 0x40u
bogdanm 0:9b334a45a8ff 2582 #define LCD_WF8B_BPGLCD6_SHIFT 6
bogdanm 0:9b334a45a8ff 2583 #define LCD_WF8B_BPGLCD51_MASK 0x40u
bogdanm 0:9b334a45a8ff 2584 #define LCD_WF8B_BPGLCD51_SHIFT 6
bogdanm 0:9b334a45a8ff 2585 #define LCD_WF8B_BPGLCD16_MASK 0x40u
bogdanm 0:9b334a45a8ff 2586 #define LCD_WF8B_BPGLCD16_SHIFT 6
bogdanm 0:9b334a45a8ff 2587 #define LCD_WF8B_BPGLCD1_MASK 0x40u
bogdanm 0:9b334a45a8ff 2588 #define LCD_WF8B_BPGLCD1_SHIFT 6
bogdanm 0:9b334a45a8ff 2589 #define LCD_WF8B_BPGLCD17_MASK 0x40u
bogdanm 0:9b334a45a8ff 2590 #define LCD_WF8B_BPGLCD17_SHIFT 6
bogdanm 0:9b334a45a8ff 2591 #define LCD_WF8B_BPGLCD50_MASK 0x40u
bogdanm 0:9b334a45a8ff 2592 #define LCD_WF8B_BPGLCD50_SHIFT 6
bogdanm 0:9b334a45a8ff 2593 #define LCD_WF8B_BPGLCD18_MASK 0x40u
bogdanm 0:9b334a45a8ff 2594 #define LCD_WF8B_BPGLCD18_SHIFT 6
bogdanm 0:9b334a45a8ff 2595 #define LCD_WF8B_BPGLCD19_MASK 0x40u
bogdanm 0:9b334a45a8ff 2596 #define LCD_WF8B_BPGLCD19_SHIFT 6
bogdanm 0:9b334a45a8ff 2597 #define LCD_WF8B_BPGLCD8_MASK 0x40u
bogdanm 0:9b334a45a8ff 2598 #define LCD_WF8B_BPGLCD8_SHIFT 6
bogdanm 0:9b334a45a8ff 2599 #define LCD_WF8B_BPGLCD49_MASK 0x40u
bogdanm 0:9b334a45a8ff 2600 #define LCD_WF8B_BPGLCD49_SHIFT 6
bogdanm 0:9b334a45a8ff 2601 #define LCD_WF8B_BPGLCD20_MASK 0x40u
bogdanm 0:9b334a45a8ff 2602 #define LCD_WF8B_BPGLCD20_SHIFT 6
bogdanm 0:9b334a45a8ff 2603 #define LCD_WF8B_BPGLCD9_MASK 0x40u
bogdanm 0:9b334a45a8ff 2604 #define LCD_WF8B_BPGLCD9_SHIFT 6
bogdanm 0:9b334a45a8ff 2605 #define LCD_WF8B_BPGLCD21_MASK 0x40u
bogdanm 0:9b334a45a8ff 2606 #define LCD_WF8B_BPGLCD21_SHIFT 6
bogdanm 0:9b334a45a8ff 2607 #define LCD_WF8B_BPGLCD13_MASK 0x40u
bogdanm 0:9b334a45a8ff 2608 #define LCD_WF8B_BPGLCD13_SHIFT 6
bogdanm 0:9b334a45a8ff 2609 #define LCD_WF8B_BPGLCD48_MASK 0x40u
bogdanm 0:9b334a45a8ff 2610 #define LCD_WF8B_BPGLCD48_SHIFT 6
bogdanm 0:9b334a45a8ff 2611 #define LCD_WF8B_BPGLCD22_MASK 0x40u
bogdanm 0:9b334a45a8ff 2612 #define LCD_WF8B_BPGLCD22_SHIFT 6
bogdanm 0:9b334a45a8ff 2613 #define LCD_WF8B_BPGLCD5_MASK 0x40u
bogdanm 0:9b334a45a8ff 2614 #define LCD_WF8B_BPGLCD5_SHIFT 6
bogdanm 0:9b334a45a8ff 2615 #define LCD_WF8B_BPGLCD47_MASK 0x40u
bogdanm 0:9b334a45a8ff 2616 #define LCD_WF8B_BPGLCD47_SHIFT 6
bogdanm 0:9b334a45a8ff 2617 #define LCD_WF8B_BPGLCD23_MASK 0x40u
bogdanm 0:9b334a45a8ff 2618 #define LCD_WF8B_BPGLCD23_SHIFT 6
bogdanm 0:9b334a45a8ff 2619 #define LCD_WF8B_BPGLCD24_MASK 0x40u
bogdanm 0:9b334a45a8ff 2620 #define LCD_WF8B_BPGLCD24_SHIFT 6
bogdanm 0:9b334a45a8ff 2621 #define LCD_WF8B_BPGLCD25_MASK 0x40u
bogdanm 0:9b334a45a8ff 2622 #define LCD_WF8B_BPGLCD25_SHIFT 6
bogdanm 0:9b334a45a8ff 2623 #define LCD_WF8B_BPGLCD46_MASK 0x40u
bogdanm 0:9b334a45a8ff 2624 #define LCD_WF8B_BPGLCD46_SHIFT 6
bogdanm 0:9b334a45a8ff 2625 #define LCD_WF8B_BPGLCD26_MASK 0x40u
bogdanm 0:9b334a45a8ff 2626 #define LCD_WF8B_BPGLCD26_SHIFT 6
bogdanm 0:9b334a45a8ff 2627 #define LCD_WF8B_BPGLCD27_MASK 0x40u
bogdanm 0:9b334a45a8ff 2628 #define LCD_WF8B_BPGLCD27_SHIFT 6
bogdanm 0:9b334a45a8ff 2629 #define LCD_WF8B_BPGLCD10_MASK 0x40u
bogdanm 0:9b334a45a8ff 2630 #define LCD_WF8B_BPGLCD10_SHIFT 6
bogdanm 0:9b334a45a8ff 2631 #define LCD_WF8B_BPGLCD45_MASK 0x40u
bogdanm 0:9b334a45a8ff 2632 #define LCD_WF8B_BPGLCD45_SHIFT 6
bogdanm 0:9b334a45a8ff 2633 #define LCD_WF8B_BPGLCD28_MASK 0x40u
bogdanm 0:9b334a45a8ff 2634 #define LCD_WF8B_BPGLCD28_SHIFT 6
bogdanm 0:9b334a45a8ff 2635 #define LCD_WF8B_BPGLCD29_MASK 0x40u
bogdanm 0:9b334a45a8ff 2636 #define LCD_WF8B_BPGLCD29_SHIFT 6
bogdanm 0:9b334a45a8ff 2637 #define LCD_WF8B_BPGLCD4_MASK 0x40u
bogdanm 0:9b334a45a8ff 2638 #define LCD_WF8B_BPGLCD4_SHIFT 6
bogdanm 0:9b334a45a8ff 2639 #define LCD_WF8B_BPGLCD44_MASK 0x40u
bogdanm 0:9b334a45a8ff 2640 #define LCD_WF8B_BPGLCD44_SHIFT 6
bogdanm 0:9b334a45a8ff 2641 #define LCD_WF8B_BPGLCD30_MASK 0x40u
bogdanm 0:9b334a45a8ff 2642 #define LCD_WF8B_BPGLCD30_SHIFT 6
bogdanm 0:9b334a45a8ff 2643 #define LCD_WF8B_BPGLCD2_MASK 0x40u
bogdanm 0:9b334a45a8ff 2644 #define LCD_WF8B_BPGLCD2_SHIFT 6
bogdanm 0:9b334a45a8ff 2645 #define LCD_WF8B_BPGLCD31_MASK 0x40u
bogdanm 0:9b334a45a8ff 2646 #define LCD_WF8B_BPGLCD31_SHIFT 6
bogdanm 0:9b334a45a8ff 2647 #define LCD_WF8B_BPGLCD43_MASK 0x40u
bogdanm 0:9b334a45a8ff 2648 #define LCD_WF8B_BPGLCD43_SHIFT 6
bogdanm 0:9b334a45a8ff 2649 #define LCD_WF8B_BPGLCD32_MASK 0x40u
bogdanm 0:9b334a45a8ff 2650 #define LCD_WF8B_BPGLCD32_SHIFT 6
bogdanm 0:9b334a45a8ff 2651 #define LCD_WF8B_BPGLCD33_MASK 0x40u
bogdanm 0:9b334a45a8ff 2652 #define LCD_WF8B_BPGLCD33_SHIFT 6
bogdanm 0:9b334a45a8ff 2653 #define LCD_WF8B_BPGLCD42_MASK 0x40u
bogdanm 0:9b334a45a8ff 2654 #define LCD_WF8B_BPGLCD42_SHIFT 6
bogdanm 0:9b334a45a8ff 2655 #define LCD_WF8B_BPGLCD34_MASK 0x40u
bogdanm 0:9b334a45a8ff 2656 #define LCD_WF8B_BPGLCD34_SHIFT 6
bogdanm 0:9b334a45a8ff 2657 #define LCD_WF8B_BPGLCD11_MASK 0x40u
bogdanm 0:9b334a45a8ff 2658 #define LCD_WF8B_BPGLCD11_SHIFT 6
bogdanm 0:9b334a45a8ff 2659 #define LCD_WF8B_BPGLCD35_MASK 0x40u
bogdanm 0:9b334a45a8ff 2660 #define LCD_WF8B_BPGLCD35_SHIFT 6
bogdanm 0:9b334a45a8ff 2661 #define LCD_WF8B_BPGLCD12_MASK 0x40u
bogdanm 0:9b334a45a8ff 2662 #define LCD_WF8B_BPGLCD12_SHIFT 6
bogdanm 0:9b334a45a8ff 2663 #define LCD_WF8B_BPGLCD41_MASK 0x40u
bogdanm 0:9b334a45a8ff 2664 #define LCD_WF8B_BPGLCD41_SHIFT 6
bogdanm 0:9b334a45a8ff 2665 #define LCD_WF8B_BPGLCD36_MASK 0x40u
bogdanm 0:9b334a45a8ff 2666 #define LCD_WF8B_BPGLCD36_SHIFT 6
bogdanm 0:9b334a45a8ff 2667 #define LCD_WF8B_BPGLCD3_MASK 0x40u
bogdanm 0:9b334a45a8ff 2668 #define LCD_WF8B_BPGLCD3_SHIFT 6
bogdanm 0:9b334a45a8ff 2669 #define LCD_WF8B_BPGLCD37_MASK 0x40u
bogdanm 0:9b334a45a8ff 2670 #define LCD_WF8B_BPGLCD37_SHIFT 6
bogdanm 0:9b334a45a8ff 2671 #define LCD_WF8B_BPGLCD40_MASK 0x40u
bogdanm 0:9b334a45a8ff 2672 #define LCD_WF8B_BPGLCD40_SHIFT 6
bogdanm 0:9b334a45a8ff 2673 #define LCD_WF8B_BPGLCD38_MASK 0x40u
bogdanm 0:9b334a45a8ff 2674 #define LCD_WF8B_BPGLCD38_SHIFT 6
bogdanm 0:9b334a45a8ff 2675 #define LCD_WF8B_BPGLCD39_MASK 0x40u
bogdanm 0:9b334a45a8ff 2676 #define LCD_WF8B_BPGLCD39_SHIFT 6
bogdanm 0:9b334a45a8ff 2677 #define LCD_WF8B_BPHLCD63_MASK 0x80u
bogdanm 0:9b334a45a8ff 2678 #define LCD_WF8B_BPHLCD63_SHIFT 7
bogdanm 0:9b334a45a8ff 2679 #define LCD_WF8B_BPHLCD62_MASK 0x80u
bogdanm 0:9b334a45a8ff 2680 #define LCD_WF8B_BPHLCD62_SHIFT 7
bogdanm 0:9b334a45a8ff 2681 #define LCD_WF8B_BPHLCD61_MASK 0x80u
bogdanm 0:9b334a45a8ff 2682 #define LCD_WF8B_BPHLCD61_SHIFT 7
bogdanm 0:9b334a45a8ff 2683 #define LCD_WF8B_BPHLCD60_MASK 0x80u
bogdanm 0:9b334a45a8ff 2684 #define LCD_WF8B_BPHLCD60_SHIFT 7
bogdanm 0:9b334a45a8ff 2685 #define LCD_WF8B_BPHLCD59_MASK 0x80u
bogdanm 0:9b334a45a8ff 2686 #define LCD_WF8B_BPHLCD59_SHIFT 7
bogdanm 0:9b334a45a8ff 2687 #define LCD_WF8B_BPHLCD58_MASK 0x80u
bogdanm 0:9b334a45a8ff 2688 #define LCD_WF8B_BPHLCD58_SHIFT 7
bogdanm 0:9b334a45a8ff 2689 #define LCD_WF8B_BPHLCD57_MASK 0x80u
bogdanm 0:9b334a45a8ff 2690 #define LCD_WF8B_BPHLCD57_SHIFT 7
bogdanm 0:9b334a45a8ff 2691 #define LCD_WF8B_BPHLCD0_MASK 0x80u
bogdanm 0:9b334a45a8ff 2692 #define LCD_WF8B_BPHLCD0_SHIFT 7
bogdanm 0:9b334a45a8ff 2693 #define LCD_WF8B_BPHLCD56_MASK 0x80u
bogdanm 0:9b334a45a8ff 2694 #define LCD_WF8B_BPHLCD56_SHIFT 7
bogdanm 0:9b334a45a8ff 2695 #define LCD_WF8B_BPHLCD55_MASK 0x80u
bogdanm 0:9b334a45a8ff 2696 #define LCD_WF8B_BPHLCD55_SHIFT 7
bogdanm 0:9b334a45a8ff 2697 #define LCD_WF8B_BPHLCD54_MASK 0x80u
bogdanm 0:9b334a45a8ff 2698 #define LCD_WF8B_BPHLCD54_SHIFT 7
bogdanm 0:9b334a45a8ff 2699 #define LCD_WF8B_BPHLCD53_MASK 0x80u
bogdanm 0:9b334a45a8ff 2700 #define LCD_WF8B_BPHLCD53_SHIFT 7
bogdanm 0:9b334a45a8ff 2701 #define LCD_WF8B_BPHLCD52_MASK 0x80u
bogdanm 0:9b334a45a8ff 2702 #define LCD_WF8B_BPHLCD52_SHIFT 7
bogdanm 0:9b334a45a8ff 2703 #define LCD_WF8B_BPHLCD51_MASK 0x80u
bogdanm 0:9b334a45a8ff 2704 #define LCD_WF8B_BPHLCD51_SHIFT 7
bogdanm 0:9b334a45a8ff 2705 #define LCD_WF8B_BPHLCD50_MASK 0x80u
bogdanm 0:9b334a45a8ff 2706 #define LCD_WF8B_BPHLCD50_SHIFT 7
bogdanm 0:9b334a45a8ff 2707 #define LCD_WF8B_BPHLCD1_MASK 0x80u
bogdanm 0:9b334a45a8ff 2708 #define LCD_WF8B_BPHLCD1_SHIFT 7
bogdanm 0:9b334a45a8ff 2709 #define LCD_WF8B_BPHLCD49_MASK 0x80u
bogdanm 0:9b334a45a8ff 2710 #define LCD_WF8B_BPHLCD49_SHIFT 7
bogdanm 0:9b334a45a8ff 2711 #define LCD_WF8B_BPHLCD48_MASK 0x80u
bogdanm 0:9b334a45a8ff 2712 #define LCD_WF8B_BPHLCD48_SHIFT 7
bogdanm 0:9b334a45a8ff 2713 #define LCD_WF8B_BPHLCD47_MASK 0x80u
bogdanm 0:9b334a45a8ff 2714 #define LCD_WF8B_BPHLCD47_SHIFT 7
bogdanm 0:9b334a45a8ff 2715 #define LCD_WF8B_BPHLCD46_MASK 0x80u
bogdanm 0:9b334a45a8ff 2716 #define LCD_WF8B_BPHLCD46_SHIFT 7
bogdanm 0:9b334a45a8ff 2717 #define LCD_WF8B_BPHLCD45_MASK 0x80u
bogdanm 0:9b334a45a8ff 2718 #define LCD_WF8B_BPHLCD45_SHIFT 7
bogdanm 0:9b334a45a8ff 2719 #define LCD_WF8B_BPHLCD44_MASK 0x80u
bogdanm 0:9b334a45a8ff 2720 #define LCD_WF8B_BPHLCD44_SHIFT 7
bogdanm 0:9b334a45a8ff 2721 #define LCD_WF8B_BPHLCD43_MASK 0x80u
bogdanm 0:9b334a45a8ff 2722 #define LCD_WF8B_BPHLCD43_SHIFT 7
bogdanm 0:9b334a45a8ff 2723 #define LCD_WF8B_BPHLCD2_MASK 0x80u
bogdanm 0:9b334a45a8ff 2724 #define LCD_WF8B_BPHLCD2_SHIFT 7
bogdanm 0:9b334a45a8ff 2725 #define LCD_WF8B_BPHLCD42_MASK 0x80u
bogdanm 0:9b334a45a8ff 2726 #define LCD_WF8B_BPHLCD42_SHIFT 7
bogdanm 0:9b334a45a8ff 2727 #define LCD_WF8B_BPHLCD41_MASK 0x80u
bogdanm 0:9b334a45a8ff 2728 #define LCD_WF8B_BPHLCD41_SHIFT 7
bogdanm 0:9b334a45a8ff 2729 #define LCD_WF8B_BPHLCD40_MASK 0x80u
bogdanm 0:9b334a45a8ff 2730 #define LCD_WF8B_BPHLCD40_SHIFT 7
bogdanm 0:9b334a45a8ff 2731 #define LCD_WF8B_BPHLCD39_MASK 0x80u
bogdanm 0:9b334a45a8ff 2732 #define LCD_WF8B_BPHLCD39_SHIFT 7
bogdanm 0:9b334a45a8ff 2733 #define LCD_WF8B_BPHLCD38_MASK 0x80u
bogdanm 0:9b334a45a8ff 2734 #define LCD_WF8B_BPHLCD38_SHIFT 7
bogdanm 0:9b334a45a8ff 2735 #define LCD_WF8B_BPHLCD37_MASK 0x80u
bogdanm 0:9b334a45a8ff 2736 #define LCD_WF8B_BPHLCD37_SHIFT 7
bogdanm 0:9b334a45a8ff 2737 #define LCD_WF8B_BPHLCD36_MASK 0x80u
bogdanm 0:9b334a45a8ff 2738 #define LCD_WF8B_BPHLCD36_SHIFT 7
bogdanm 0:9b334a45a8ff 2739 #define LCD_WF8B_BPHLCD3_MASK 0x80u
bogdanm 0:9b334a45a8ff 2740 #define LCD_WF8B_BPHLCD3_SHIFT 7
bogdanm 0:9b334a45a8ff 2741 #define LCD_WF8B_BPHLCD35_MASK 0x80u
bogdanm 0:9b334a45a8ff 2742 #define LCD_WF8B_BPHLCD35_SHIFT 7
bogdanm 0:9b334a45a8ff 2743 #define LCD_WF8B_BPHLCD34_MASK 0x80u
bogdanm 0:9b334a45a8ff 2744 #define LCD_WF8B_BPHLCD34_SHIFT 7
bogdanm 0:9b334a45a8ff 2745 #define LCD_WF8B_BPHLCD33_MASK 0x80u
bogdanm 0:9b334a45a8ff 2746 #define LCD_WF8B_BPHLCD33_SHIFT 7
bogdanm 0:9b334a45a8ff 2747 #define LCD_WF8B_BPHLCD32_MASK 0x80u
bogdanm 0:9b334a45a8ff 2748 #define LCD_WF8B_BPHLCD32_SHIFT 7
bogdanm 0:9b334a45a8ff 2749 #define LCD_WF8B_BPHLCD31_MASK 0x80u
bogdanm 0:9b334a45a8ff 2750 #define LCD_WF8B_BPHLCD31_SHIFT 7
bogdanm 0:9b334a45a8ff 2751 #define LCD_WF8B_BPHLCD30_MASK 0x80u
bogdanm 0:9b334a45a8ff 2752 #define LCD_WF8B_BPHLCD30_SHIFT 7
bogdanm 0:9b334a45a8ff 2753 #define LCD_WF8B_BPHLCD29_MASK 0x80u
bogdanm 0:9b334a45a8ff 2754 #define LCD_WF8B_BPHLCD29_SHIFT 7
bogdanm 0:9b334a45a8ff 2755 #define LCD_WF8B_BPHLCD4_MASK 0x80u
bogdanm 0:9b334a45a8ff 2756 #define LCD_WF8B_BPHLCD4_SHIFT 7
bogdanm 0:9b334a45a8ff 2757 #define LCD_WF8B_BPHLCD28_MASK 0x80u
bogdanm 0:9b334a45a8ff 2758 #define LCD_WF8B_BPHLCD28_SHIFT 7
bogdanm 0:9b334a45a8ff 2759 #define LCD_WF8B_BPHLCD27_MASK 0x80u
bogdanm 0:9b334a45a8ff 2760 #define LCD_WF8B_BPHLCD27_SHIFT 7
bogdanm 0:9b334a45a8ff 2761 #define LCD_WF8B_BPHLCD26_MASK 0x80u
bogdanm 0:9b334a45a8ff 2762 #define LCD_WF8B_BPHLCD26_SHIFT 7
bogdanm 0:9b334a45a8ff 2763 #define LCD_WF8B_BPHLCD25_MASK 0x80u
bogdanm 0:9b334a45a8ff 2764 #define LCD_WF8B_BPHLCD25_SHIFT 7
bogdanm 0:9b334a45a8ff 2765 #define LCD_WF8B_BPHLCD24_MASK 0x80u
bogdanm 0:9b334a45a8ff 2766 #define LCD_WF8B_BPHLCD24_SHIFT 7
bogdanm 0:9b334a45a8ff 2767 #define LCD_WF8B_BPHLCD23_MASK 0x80u
bogdanm 0:9b334a45a8ff 2768 #define LCD_WF8B_BPHLCD23_SHIFT 7
bogdanm 0:9b334a45a8ff 2769 #define LCD_WF8B_BPHLCD22_MASK 0x80u
bogdanm 0:9b334a45a8ff 2770 #define LCD_WF8B_BPHLCD22_SHIFT 7
bogdanm 0:9b334a45a8ff 2771 #define LCD_WF8B_BPHLCD5_MASK 0x80u
bogdanm 0:9b334a45a8ff 2772 #define LCD_WF8B_BPHLCD5_SHIFT 7
bogdanm 0:9b334a45a8ff 2773 #define LCD_WF8B_BPHLCD21_MASK 0x80u
bogdanm 0:9b334a45a8ff 2774 #define LCD_WF8B_BPHLCD21_SHIFT 7
bogdanm 0:9b334a45a8ff 2775 #define LCD_WF8B_BPHLCD20_MASK 0x80u
bogdanm 0:9b334a45a8ff 2776 #define LCD_WF8B_BPHLCD20_SHIFT 7
bogdanm 0:9b334a45a8ff 2777 #define LCD_WF8B_BPHLCD19_MASK 0x80u
bogdanm 0:9b334a45a8ff 2778 #define LCD_WF8B_BPHLCD19_SHIFT 7
bogdanm 0:9b334a45a8ff 2779 #define LCD_WF8B_BPHLCD18_MASK 0x80u
bogdanm 0:9b334a45a8ff 2780 #define LCD_WF8B_BPHLCD18_SHIFT 7
bogdanm 0:9b334a45a8ff 2781 #define LCD_WF8B_BPHLCD17_MASK 0x80u
bogdanm 0:9b334a45a8ff 2782 #define LCD_WF8B_BPHLCD17_SHIFT 7
bogdanm 0:9b334a45a8ff 2783 #define LCD_WF8B_BPHLCD16_MASK 0x80u
bogdanm 0:9b334a45a8ff 2784 #define LCD_WF8B_BPHLCD16_SHIFT 7
bogdanm 0:9b334a45a8ff 2785 #define LCD_WF8B_BPHLCD15_MASK 0x80u
bogdanm 0:9b334a45a8ff 2786 #define LCD_WF8B_BPHLCD15_SHIFT 7
bogdanm 0:9b334a45a8ff 2787 #define LCD_WF8B_BPHLCD6_MASK 0x80u
bogdanm 0:9b334a45a8ff 2788 #define LCD_WF8B_BPHLCD6_SHIFT 7
bogdanm 0:9b334a45a8ff 2789 #define LCD_WF8B_BPHLCD14_MASK 0x80u
bogdanm 0:9b334a45a8ff 2790 #define LCD_WF8B_BPHLCD14_SHIFT 7
bogdanm 0:9b334a45a8ff 2791 #define LCD_WF8B_BPHLCD13_MASK 0x80u
bogdanm 0:9b334a45a8ff 2792 #define LCD_WF8B_BPHLCD13_SHIFT 7
bogdanm 0:9b334a45a8ff 2793 #define LCD_WF8B_BPHLCD12_MASK 0x80u
bogdanm 0:9b334a45a8ff 2794 #define LCD_WF8B_BPHLCD12_SHIFT 7
bogdanm 0:9b334a45a8ff 2795 #define LCD_WF8B_BPHLCD11_MASK 0x80u
bogdanm 0:9b334a45a8ff 2796 #define LCD_WF8B_BPHLCD11_SHIFT 7
bogdanm 0:9b334a45a8ff 2797 #define LCD_WF8B_BPHLCD10_MASK 0x80u
bogdanm 0:9b334a45a8ff 2798 #define LCD_WF8B_BPHLCD10_SHIFT 7
bogdanm 0:9b334a45a8ff 2799 #define LCD_WF8B_BPHLCD9_MASK 0x80u
bogdanm 0:9b334a45a8ff 2800 #define LCD_WF8B_BPHLCD9_SHIFT 7
bogdanm 0:9b334a45a8ff 2801 #define LCD_WF8B_BPHLCD8_MASK 0x80u
bogdanm 0:9b334a45a8ff 2802 #define LCD_WF8B_BPHLCD8_SHIFT 7
bogdanm 0:9b334a45a8ff 2803 #define LCD_WF8B_BPHLCD7_MASK 0x80u
bogdanm 0:9b334a45a8ff 2804 #define LCD_WF8B_BPHLCD7_SHIFT 7
bogdanm 0:9b334a45a8ff 2805
bogdanm 0:9b334a45a8ff 2806 /*!
bogdanm 0:9b334a45a8ff 2807 * @}
bogdanm 0:9b334a45a8ff 2808 */ /* end of group LCD_Register_Masks */
bogdanm 0:9b334a45a8ff 2809
bogdanm 0:9b334a45a8ff 2810
bogdanm 0:9b334a45a8ff 2811 /* LCD - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 2812 /** Peripheral LCD base address */
bogdanm 0:9b334a45a8ff 2813 #define LCD_BASE (0x40053000u)
bogdanm 0:9b334a45a8ff 2814 /** Peripheral LCD base pointer */
bogdanm 0:9b334a45a8ff 2815 #define LCD ((LCD_Type *)LCD_BASE)
bogdanm 0:9b334a45a8ff 2816 /** Array initializer of LCD peripheral base pointers */
bogdanm 0:9b334a45a8ff 2817 #define LCD_BASES { LCD }
bogdanm 0:9b334a45a8ff 2818
bogdanm 0:9b334a45a8ff 2819 /*!
bogdanm 0:9b334a45a8ff 2820 * @}
bogdanm 0:9b334a45a8ff 2821 */ /* end of group LCD_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 2822
bogdanm 0:9b334a45a8ff 2823
bogdanm 0:9b334a45a8ff 2824 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 2825 -- LLWU Peripheral Access Layer
bogdanm 0:9b334a45a8ff 2826 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 2827
bogdanm 0:9b334a45a8ff 2828 /*!
bogdanm 0:9b334a45a8ff 2829 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
bogdanm 0:9b334a45a8ff 2830 * @{
bogdanm 0:9b334a45a8ff 2831 */
bogdanm 0:9b334a45a8ff 2832
bogdanm 0:9b334a45a8ff 2833 /** LLWU - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 2834 typedef struct {
bogdanm 0:9b334a45a8ff 2835 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
bogdanm 0:9b334a45a8ff 2836 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
bogdanm 0:9b334a45a8ff 2837 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
bogdanm 0:9b334a45a8ff 2838 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
bogdanm 0:9b334a45a8ff 2839 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
bogdanm 0:9b334a45a8ff 2840 __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
bogdanm 0:9b334a45a8ff 2841 __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
bogdanm 0:9b334a45a8ff 2842 __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
bogdanm 0:9b334a45a8ff 2843 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
bogdanm 0:9b334a45a8ff 2844 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
bogdanm 0:9b334a45a8ff 2845 } LLWU_Type;
bogdanm 0:9b334a45a8ff 2846
bogdanm 0:9b334a45a8ff 2847 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 2848 -- LLWU Register Masks
bogdanm 0:9b334a45a8ff 2849 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 2850
bogdanm 0:9b334a45a8ff 2851 /*!
bogdanm 0:9b334a45a8ff 2852 * @addtogroup LLWU_Register_Masks LLWU Register Masks
bogdanm 0:9b334a45a8ff 2853 * @{
bogdanm 0:9b334a45a8ff 2854 */
bogdanm 0:9b334a45a8ff 2855
bogdanm 0:9b334a45a8ff 2856 /* PE1 Bit Fields */
bogdanm 0:9b334a45a8ff 2857 #define LLWU_PE1_WUPE0_MASK 0x3u
bogdanm 0:9b334a45a8ff 2858 #define LLWU_PE1_WUPE0_SHIFT 0
bogdanm 0:9b334a45a8ff 2859 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
bogdanm 0:9b334a45a8ff 2860 #define LLWU_PE1_WUPE1_MASK 0xCu
bogdanm 0:9b334a45a8ff 2861 #define LLWU_PE1_WUPE1_SHIFT 2
bogdanm 0:9b334a45a8ff 2862 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
bogdanm 0:9b334a45a8ff 2863 #define LLWU_PE1_WUPE2_MASK 0x30u
bogdanm 0:9b334a45a8ff 2864 #define LLWU_PE1_WUPE2_SHIFT 4
bogdanm 0:9b334a45a8ff 2865 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
bogdanm 0:9b334a45a8ff 2866 #define LLWU_PE1_WUPE3_MASK 0xC0u
bogdanm 0:9b334a45a8ff 2867 #define LLWU_PE1_WUPE3_SHIFT 6
bogdanm 0:9b334a45a8ff 2868 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
bogdanm 0:9b334a45a8ff 2869 /* PE2 Bit Fields */
bogdanm 0:9b334a45a8ff 2870 #define LLWU_PE2_WUPE4_MASK 0x3u
bogdanm 0:9b334a45a8ff 2871 #define LLWU_PE2_WUPE4_SHIFT 0
bogdanm 0:9b334a45a8ff 2872 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
bogdanm 0:9b334a45a8ff 2873 #define LLWU_PE2_WUPE5_MASK 0xCu
bogdanm 0:9b334a45a8ff 2874 #define LLWU_PE2_WUPE5_SHIFT 2
bogdanm 0:9b334a45a8ff 2875 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
bogdanm 0:9b334a45a8ff 2876 #define LLWU_PE2_WUPE6_MASK 0x30u
bogdanm 0:9b334a45a8ff 2877 #define LLWU_PE2_WUPE6_SHIFT 4
bogdanm 0:9b334a45a8ff 2878 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
bogdanm 0:9b334a45a8ff 2879 #define LLWU_PE2_WUPE7_MASK 0xC0u
bogdanm 0:9b334a45a8ff 2880 #define LLWU_PE2_WUPE7_SHIFT 6
bogdanm 0:9b334a45a8ff 2881 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
bogdanm 0:9b334a45a8ff 2882 /* PE3 Bit Fields */
bogdanm 0:9b334a45a8ff 2883 #define LLWU_PE3_WUPE8_MASK 0x3u
bogdanm 0:9b334a45a8ff 2884 #define LLWU_PE3_WUPE8_SHIFT 0
bogdanm 0:9b334a45a8ff 2885 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
bogdanm 0:9b334a45a8ff 2886 #define LLWU_PE3_WUPE9_MASK 0xCu
bogdanm 0:9b334a45a8ff 2887 #define LLWU_PE3_WUPE9_SHIFT 2
bogdanm 0:9b334a45a8ff 2888 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
bogdanm 0:9b334a45a8ff 2889 #define LLWU_PE3_WUPE10_MASK 0x30u
bogdanm 0:9b334a45a8ff 2890 #define LLWU_PE3_WUPE10_SHIFT 4
bogdanm 0:9b334a45a8ff 2891 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
bogdanm 0:9b334a45a8ff 2892 #define LLWU_PE3_WUPE11_MASK 0xC0u
bogdanm 0:9b334a45a8ff 2893 #define LLWU_PE3_WUPE11_SHIFT 6
bogdanm 0:9b334a45a8ff 2894 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
bogdanm 0:9b334a45a8ff 2895 /* PE4 Bit Fields */
bogdanm 0:9b334a45a8ff 2896 #define LLWU_PE4_WUPE12_MASK 0x3u
bogdanm 0:9b334a45a8ff 2897 #define LLWU_PE4_WUPE12_SHIFT 0
bogdanm 0:9b334a45a8ff 2898 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
bogdanm 0:9b334a45a8ff 2899 #define LLWU_PE4_WUPE13_MASK 0xCu
bogdanm 0:9b334a45a8ff 2900 #define LLWU_PE4_WUPE13_SHIFT 2
bogdanm 0:9b334a45a8ff 2901 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
bogdanm 0:9b334a45a8ff 2902 #define LLWU_PE4_WUPE14_MASK 0x30u
bogdanm 0:9b334a45a8ff 2903 #define LLWU_PE4_WUPE14_SHIFT 4
bogdanm 0:9b334a45a8ff 2904 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
bogdanm 0:9b334a45a8ff 2905 #define LLWU_PE4_WUPE15_MASK 0xC0u
bogdanm 0:9b334a45a8ff 2906 #define LLWU_PE4_WUPE15_SHIFT 6
bogdanm 0:9b334a45a8ff 2907 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
bogdanm 0:9b334a45a8ff 2908 /* ME Bit Fields */
bogdanm 0:9b334a45a8ff 2909 #define LLWU_ME_WUME0_MASK 0x1u
bogdanm 0:9b334a45a8ff 2910 #define LLWU_ME_WUME0_SHIFT 0
bogdanm 0:9b334a45a8ff 2911 #define LLWU_ME_WUME1_MASK 0x2u
bogdanm 0:9b334a45a8ff 2912 #define LLWU_ME_WUME1_SHIFT 1
bogdanm 0:9b334a45a8ff 2913 #define LLWU_ME_WUME2_MASK 0x4u
bogdanm 0:9b334a45a8ff 2914 #define LLWU_ME_WUME2_SHIFT 2
bogdanm 0:9b334a45a8ff 2915 #define LLWU_ME_WUME3_MASK 0x8u
bogdanm 0:9b334a45a8ff 2916 #define LLWU_ME_WUME3_SHIFT 3
bogdanm 0:9b334a45a8ff 2917 #define LLWU_ME_WUME4_MASK 0x10u
bogdanm 0:9b334a45a8ff 2918 #define LLWU_ME_WUME4_SHIFT 4
bogdanm 0:9b334a45a8ff 2919 #define LLWU_ME_WUME5_MASK 0x20u
bogdanm 0:9b334a45a8ff 2920 #define LLWU_ME_WUME5_SHIFT 5
bogdanm 0:9b334a45a8ff 2921 #define LLWU_ME_WUME6_MASK 0x40u
bogdanm 0:9b334a45a8ff 2922 #define LLWU_ME_WUME6_SHIFT 6
bogdanm 0:9b334a45a8ff 2923 #define LLWU_ME_WUME7_MASK 0x80u
bogdanm 0:9b334a45a8ff 2924 #define LLWU_ME_WUME7_SHIFT 7
bogdanm 0:9b334a45a8ff 2925 /* F1 Bit Fields */
bogdanm 0:9b334a45a8ff 2926 #define LLWU_F1_WUF0_MASK 0x1u
bogdanm 0:9b334a45a8ff 2927 #define LLWU_F1_WUF0_SHIFT 0
bogdanm 0:9b334a45a8ff 2928 #define LLWU_F1_WUF1_MASK 0x2u
bogdanm 0:9b334a45a8ff 2929 #define LLWU_F1_WUF1_SHIFT 1
bogdanm 0:9b334a45a8ff 2930 #define LLWU_F1_WUF2_MASK 0x4u
bogdanm 0:9b334a45a8ff 2931 #define LLWU_F1_WUF2_SHIFT 2
bogdanm 0:9b334a45a8ff 2932 #define LLWU_F1_WUF3_MASK 0x8u
bogdanm 0:9b334a45a8ff 2933 #define LLWU_F1_WUF3_SHIFT 3
bogdanm 0:9b334a45a8ff 2934 #define LLWU_F1_WUF4_MASK 0x10u
bogdanm 0:9b334a45a8ff 2935 #define LLWU_F1_WUF4_SHIFT 4
bogdanm 0:9b334a45a8ff 2936 #define LLWU_F1_WUF5_MASK 0x20u
bogdanm 0:9b334a45a8ff 2937 #define LLWU_F1_WUF5_SHIFT 5
bogdanm 0:9b334a45a8ff 2938 #define LLWU_F1_WUF6_MASK 0x40u
bogdanm 0:9b334a45a8ff 2939 #define LLWU_F1_WUF6_SHIFT 6
bogdanm 0:9b334a45a8ff 2940 #define LLWU_F1_WUF7_MASK 0x80u
bogdanm 0:9b334a45a8ff 2941 #define LLWU_F1_WUF7_SHIFT 7
bogdanm 0:9b334a45a8ff 2942 /* F2 Bit Fields */
bogdanm 0:9b334a45a8ff 2943 #define LLWU_F2_WUF8_MASK 0x1u
bogdanm 0:9b334a45a8ff 2944 #define LLWU_F2_WUF8_SHIFT 0
bogdanm 0:9b334a45a8ff 2945 #define LLWU_F2_WUF9_MASK 0x2u
bogdanm 0:9b334a45a8ff 2946 #define LLWU_F2_WUF9_SHIFT 1
bogdanm 0:9b334a45a8ff 2947 #define LLWU_F2_WUF10_MASK 0x4u
bogdanm 0:9b334a45a8ff 2948 #define LLWU_F2_WUF10_SHIFT 2
bogdanm 0:9b334a45a8ff 2949 #define LLWU_F2_WUF11_MASK 0x8u
bogdanm 0:9b334a45a8ff 2950 #define LLWU_F2_WUF11_SHIFT 3
bogdanm 0:9b334a45a8ff 2951 #define LLWU_F2_WUF12_MASK 0x10u
bogdanm 0:9b334a45a8ff 2952 #define LLWU_F2_WUF12_SHIFT 4
bogdanm 0:9b334a45a8ff 2953 #define LLWU_F2_WUF13_MASK 0x20u
bogdanm 0:9b334a45a8ff 2954 #define LLWU_F2_WUF13_SHIFT 5
bogdanm 0:9b334a45a8ff 2955 #define LLWU_F2_WUF14_MASK 0x40u
bogdanm 0:9b334a45a8ff 2956 #define LLWU_F2_WUF14_SHIFT 6
bogdanm 0:9b334a45a8ff 2957 #define LLWU_F2_WUF15_MASK 0x80u
bogdanm 0:9b334a45a8ff 2958 #define LLWU_F2_WUF15_SHIFT 7
bogdanm 0:9b334a45a8ff 2959 /* F3 Bit Fields */
bogdanm 0:9b334a45a8ff 2960 #define LLWU_F3_MWUF0_MASK 0x1u
bogdanm 0:9b334a45a8ff 2961 #define LLWU_F3_MWUF0_SHIFT 0
bogdanm 0:9b334a45a8ff 2962 #define LLWU_F3_MWUF1_MASK 0x2u
bogdanm 0:9b334a45a8ff 2963 #define LLWU_F3_MWUF1_SHIFT 1
bogdanm 0:9b334a45a8ff 2964 #define LLWU_F3_MWUF2_MASK 0x4u
bogdanm 0:9b334a45a8ff 2965 #define LLWU_F3_MWUF2_SHIFT 2
bogdanm 0:9b334a45a8ff 2966 #define LLWU_F3_MWUF3_MASK 0x8u
bogdanm 0:9b334a45a8ff 2967 #define LLWU_F3_MWUF3_SHIFT 3
bogdanm 0:9b334a45a8ff 2968 #define LLWU_F3_MWUF4_MASK 0x10u
bogdanm 0:9b334a45a8ff 2969 #define LLWU_F3_MWUF4_SHIFT 4
bogdanm 0:9b334a45a8ff 2970 #define LLWU_F3_MWUF5_MASK 0x20u
bogdanm 0:9b334a45a8ff 2971 #define LLWU_F3_MWUF5_SHIFT 5
bogdanm 0:9b334a45a8ff 2972 #define LLWU_F3_MWUF6_MASK 0x40u
bogdanm 0:9b334a45a8ff 2973 #define LLWU_F3_MWUF6_SHIFT 6
bogdanm 0:9b334a45a8ff 2974 #define LLWU_F3_MWUF7_MASK 0x80u
bogdanm 0:9b334a45a8ff 2975 #define LLWU_F3_MWUF7_SHIFT 7
bogdanm 0:9b334a45a8ff 2976 /* FILT1 Bit Fields */
bogdanm 0:9b334a45a8ff 2977 #define LLWU_FILT1_FILTSEL_MASK 0xFu
bogdanm 0:9b334a45a8ff 2978 #define LLWU_FILT1_FILTSEL_SHIFT 0
bogdanm 0:9b334a45a8ff 2979 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
bogdanm 0:9b334a45a8ff 2980 #define LLWU_FILT1_FILTE_MASK 0x60u
bogdanm 0:9b334a45a8ff 2981 #define LLWU_FILT1_FILTE_SHIFT 5
bogdanm 0:9b334a45a8ff 2982 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
bogdanm 0:9b334a45a8ff 2983 #define LLWU_FILT1_FILTF_MASK 0x80u
bogdanm 0:9b334a45a8ff 2984 #define LLWU_FILT1_FILTF_SHIFT 7
bogdanm 0:9b334a45a8ff 2985 /* FILT2 Bit Fields */
bogdanm 0:9b334a45a8ff 2986 #define LLWU_FILT2_FILTSEL_MASK 0xFu
bogdanm 0:9b334a45a8ff 2987 #define LLWU_FILT2_FILTSEL_SHIFT 0
bogdanm 0:9b334a45a8ff 2988 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
bogdanm 0:9b334a45a8ff 2989 #define LLWU_FILT2_FILTE_MASK 0x60u
bogdanm 0:9b334a45a8ff 2990 #define LLWU_FILT2_FILTE_SHIFT 5
bogdanm 0:9b334a45a8ff 2991 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
bogdanm 0:9b334a45a8ff 2992 #define LLWU_FILT2_FILTF_MASK 0x80u
bogdanm 0:9b334a45a8ff 2993 #define LLWU_FILT2_FILTF_SHIFT 7
bogdanm 0:9b334a45a8ff 2994
bogdanm 0:9b334a45a8ff 2995 /*!
bogdanm 0:9b334a45a8ff 2996 * @}
bogdanm 0:9b334a45a8ff 2997 */ /* end of group LLWU_Register_Masks */
bogdanm 0:9b334a45a8ff 2998
bogdanm 0:9b334a45a8ff 2999
bogdanm 0:9b334a45a8ff 3000 /* LLWU - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 3001 /** Peripheral LLWU base address */
bogdanm 0:9b334a45a8ff 3002 #define LLWU_BASE (0x4007C000u)
bogdanm 0:9b334a45a8ff 3003 /** Peripheral LLWU base pointer */
bogdanm 0:9b334a45a8ff 3004 #define LLWU ((LLWU_Type *)LLWU_BASE)
bogdanm 0:9b334a45a8ff 3005 /** Array initializer of LLWU peripheral base pointers */
bogdanm 0:9b334a45a8ff 3006 #define LLWU_BASES { LLWU }
bogdanm 0:9b334a45a8ff 3007
bogdanm 0:9b334a45a8ff 3008 /*!
bogdanm 0:9b334a45a8ff 3009 * @}
bogdanm 0:9b334a45a8ff 3010 */ /* end of group LLWU_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 3011
bogdanm 0:9b334a45a8ff 3012
bogdanm 0:9b334a45a8ff 3013 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 3014 -- LPTMR Peripheral Access Layer
bogdanm 0:9b334a45a8ff 3015 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 3016
bogdanm 0:9b334a45a8ff 3017 /*!
bogdanm 0:9b334a45a8ff 3018 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
bogdanm 0:9b334a45a8ff 3019 * @{
bogdanm 0:9b334a45a8ff 3020 */
bogdanm 0:9b334a45a8ff 3021
bogdanm 0:9b334a45a8ff 3022 /** LPTMR - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 3023 typedef struct {
bogdanm 0:9b334a45a8ff 3024 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
bogdanm 0:9b334a45a8ff 3025 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
bogdanm 0:9b334a45a8ff 3026 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
bogdanm 0:9b334a45a8ff 3027 __I uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
bogdanm 0:9b334a45a8ff 3028 } LPTMR_Type;
bogdanm 0:9b334a45a8ff 3029
bogdanm 0:9b334a45a8ff 3030 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 3031 -- LPTMR Register Masks
bogdanm 0:9b334a45a8ff 3032 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 3033
bogdanm 0:9b334a45a8ff 3034 /*!
bogdanm 0:9b334a45a8ff 3035 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
bogdanm 0:9b334a45a8ff 3036 * @{
bogdanm 0:9b334a45a8ff 3037 */
bogdanm 0:9b334a45a8ff 3038
bogdanm 0:9b334a45a8ff 3039 /* CSR Bit Fields */
bogdanm 0:9b334a45a8ff 3040 #define LPTMR_CSR_TEN_MASK 0x1u
bogdanm 0:9b334a45a8ff 3041 #define LPTMR_CSR_TEN_SHIFT 0
bogdanm 0:9b334a45a8ff 3042 #define LPTMR_CSR_TMS_MASK 0x2u
bogdanm 0:9b334a45a8ff 3043 #define LPTMR_CSR_TMS_SHIFT 1
bogdanm 0:9b334a45a8ff 3044 #define LPTMR_CSR_TFC_MASK 0x4u
bogdanm 0:9b334a45a8ff 3045 #define LPTMR_CSR_TFC_SHIFT 2
bogdanm 0:9b334a45a8ff 3046 #define LPTMR_CSR_TPP_MASK 0x8u
bogdanm 0:9b334a45a8ff 3047 #define LPTMR_CSR_TPP_SHIFT 3
bogdanm 0:9b334a45a8ff 3048 #define LPTMR_CSR_TPS_MASK 0x30u
bogdanm 0:9b334a45a8ff 3049 #define LPTMR_CSR_TPS_SHIFT 4
bogdanm 0:9b334a45a8ff 3050 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
bogdanm 0:9b334a45a8ff 3051 #define LPTMR_CSR_TIE_MASK 0x40u
bogdanm 0:9b334a45a8ff 3052 #define LPTMR_CSR_TIE_SHIFT 6
bogdanm 0:9b334a45a8ff 3053 #define LPTMR_CSR_TCF_MASK 0x80u
bogdanm 0:9b334a45a8ff 3054 #define LPTMR_CSR_TCF_SHIFT 7
bogdanm 0:9b334a45a8ff 3055 /* PSR Bit Fields */
bogdanm 0:9b334a45a8ff 3056 #define LPTMR_PSR_PCS_MASK 0x3u
bogdanm 0:9b334a45a8ff 3057 #define LPTMR_PSR_PCS_SHIFT 0
bogdanm 0:9b334a45a8ff 3058 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
bogdanm 0:9b334a45a8ff 3059 #define LPTMR_PSR_PBYP_MASK 0x4u
bogdanm 0:9b334a45a8ff 3060 #define LPTMR_PSR_PBYP_SHIFT 2
bogdanm 0:9b334a45a8ff 3061 #define LPTMR_PSR_PRESCALE_MASK 0x78u
bogdanm 0:9b334a45a8ff 3062 #define LPTMR_PSR_PRESCALE_SHIFT 3
bogdanm 0:9b334a45a8ff 3063 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
bogdanm 0:9b334a45a8ff 3064 /* CMR Bit Fields */
bogdanm 0:9b334a45a8ff 3065 #define LPTMR_CMR_COMPARE_MASK 0xFFFFu
bogdanm 0:9b334a45a8ff 3066 #define LPTMR_CMR_COMPARE_SHIFT 0
bogdanm 0:9b334a45a8ff 3067 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
bogdanm 0:9b334a45a8ff 3068 /* CNR Bit Fields */
bogdanm 0:9b334a45a8ff 3069 #define LPTMR_CNR_COUNTER_MASK 0xFFFFu
bogdanm 0:9b334a45a8ff 3070 #define LPTMR_CNR_COUNTER_SHIFT 0
bogdanm 0:9b334a45a8ff 3071 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
bogdanm 0:9b334a45a8ff 3072
bogdanm 0:9b334a45a8ff 3073 /*!
bogdanm 0:9b334a45a8ff 3074 * @}
bogdanm 0:9b334a45a8ff 3075 */ /* end of group LPTMR_Register_Masks */
bogdanm 0:9b334a45a8ff 3076
bogdanm 0:9b334a45a8ff 3077
bogdanm 0:9b334a45a8ff 3078 /* LPTMR - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 3079 /** Peripheral LPTMR0 base address */
bogdanm 0:9b334a45a8ff 3080 #define LPTMR0_BASE (0x40040000u)
bogdanm 0:9b334a45a8ff 3081 /** Peripheral LPTMR0 base pointer */
bogdanm 0:9b334a45a8ff 3082 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
bogdanm 0:9b334a45a8ff 3083 /** Array initializer of LPTMR peripheral base pointers */
bogdanm 0:9b334a45a8ff 3084 #define LPTMR_BASES { LPTMR0 }
bogdanm 0:9b334a45a8ff 3085
bogdanm 0:9b334a45a8ff 3086 /*!
bogdanm 0:9b334a45a8ff 3087 * @}
bogdanm 0:9b334a45a8ff 3088 */ /* end of group LPTMR_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 3089
bogdanm 0:9b334a45a8ff 3090
bogdanm 0:9b334a45a8ff 3091 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 3092 -- MCG Peripheral Access Layer
bogdanm 0:9b334a45a8ff 3093 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 3094
bogdanm 0:9b334a45a8ff 3095 /*!
bogdanm 0:9b334a45a8ff 3096 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
bogdanm 0:9b334a45a8ff 3097 * @{
bogdanm 0:9b334a45a8ff 3098 */
bogdanm 0:9b334a45a8ff 3099
bogdanm 0:9b334a45a8ff 3100 /** MCG - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 3101 typedef struct {
bogdanm 0:9b334a45a8ff 3102 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
bogdanm 0:9b334a45a8ff 3103 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
bogdanm 0:9b334a45a8ff 3104 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
bogdanm 0:9b334a45a8ff 3105 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
bogdanm 0:9b334a45a8ff 3106 __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
bogdanm 0:9b334a45a8ff 3107 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
bogdanm 0:9b334a45a8ff 3108 __I uint8_t S; /**< MCG Status Register, offset: 0x6 */
bogdanm 0:9b334a45a8ff 3109 uint8_t RESERVED_0[1];
bogdanm 0:9b334a45a8ff 3110 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
bogdanm 0:9b334a45a8ff 3111 uint8_t RESERVED_1[1];
bogdanm 0:9b334a45a8ff 3112 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
bogdanm 0:9b334a45a8ff 3113 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
bogdanm 0:9b334a45a8ff 3114 __I uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
bogdanm 0:9b334a45a8ff 3115 __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
bogdanm 0:9b334a45a8ff 3116 __I uint8_t C9; /**< MCG Control 9 Register, offset: 0xE */
bogdanm 0:9b334a45a8ff 3117 __I uint8_t C10; /**< MCG Control 10 Register, offset: 0xF */
bogdanm 0:9b334a45a8ff 3118 } MCG_Type;
bogdanm 0:9b334a45a8ff 3119
bogdanm 0:9b334a45a8ff 3120 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 3121 -- MCG Register Masks
bogdanm 0:9b334a45a8ff 3122 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 3123
bogdanm 0:9b334a45a8ff 3124 /*!
bogdanm 0:9b334a45a8ff 3125 * @addtogroup MCG_Register_Masks MCG Register Masks
bogdanm 0:9b334a45a8ff 3126 * @{
bogdanm 0:9b334a45a8ff 3127 */
bogdanm 0:9b334a45a8ff 3128
bogdanm 0:9b334a45a8ff 3129 /* C1 Bit Fields */
bogdanm 0:9b334a45a8ff 3130 #define MCG_C1_IREFSTEN_MASK 0x1u
bogdanm 0:9b334a45a8ff 3131 #define MCG_C1_IREFSTEN_SHIFT 0
bogdanm 0:9b334a45a8ff 3132 #define MCG_C1_IRCLKEN_MASK 0x2u
bogdanm 0:9b334a45a8ff 3133 #define MCG_C1_IRCLKEN_SHIFT 1
bogdanm 0:9b334a45a8ff 3134 #define MCG_C1_IREFS_MASK 0x4u
bogdanm 0:9b334a45a8ff 3135 #define MCG_C1_IREFS_SHIFT 2
bogdanm 0:9b334a45a8ff 3136 #define MCG_C1_FRDIV_MASK 0x38u
bogdanm 0:9b334a45a8ff 3137 #define MCG_C1_FRDIV_SHIFT 3
bogdanm 0:9b334a45a8ff 3138 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
bogdanm 0:9b334a45a8ff 3139 #define MCG_C1_CLKS_MASK 0xC0u
bogdanm 0:9b334a45a8ff 3140 #define MCG_C1_CLKS_SHIFT 6
bogdanm 0:9b334a45a8ff 3141 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
bogdanm 0:9b334a45a8ff 3142 /* C2 Bit Fields */
bogdanm 0:9b334a45a8ff 3143 #define MCG_C2_IRCS_MASK 0x1u
bogdanm 0:9b334a45a8ff 3144 #define MCG_C2_IRCS_SHIFT 0
bogdanm 0:9b334a45a8ff 3145 #define MCG_C2_LP_MASK 0x2u
bogdanm 0:9b334a45a8ff 3146 #define MCG_C2_LP_SHIFT 1
bogdanm 0:9b334a45a8ff 3147 #define MCG_C2_EREFS0_MASK 0x4u
bogdanm 0:9b334a45a8ff 3148 #define MCG_C2_EREFS0_SHIFT 2
bogdanm 0:9b334a45a8ff 3149 #define MCG_C2_HGO0_MASK 0x8u
bogdanm 0:9b334a45a8ff 3150 #define MCG_C2_HGO0_SHIFT 3
bogdanm 0:9b334a45a8ff 3151 #define MCG_C2_RANGE0_MASK 0x30u
bogdanm 0:9b334a45a8ff 3152 #define MCG_C2_RANGE0_SHIFT 4
bogdanm 0:9b334a45a8ff 3153 #define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
bogdanm 0:9b334a45a8ff 3154 #define MCG_C2_FCFTRIM_MASK 0x40u
bogdanm 0:9b334a45a8ff 3155 #define MCG_C2_FCFTRIM_SHIFT 6
bogdanm 0:9b334a45a8ff 3156 #define MCG_C2_LOCRE0_MASK 0x80u
bogdanm 0:9b334a45a8ff 3157 #define MCG_C2_LOCRE0_SHIFT 7
bogdanm 0:9b334a45a8ff 3158 /* C3 Bit Fields */
bogdanm 0:9b334a45a8ff 3159 #define MCG_C3_SCTRIM_MASK 0xFFu
bogdanm 0:9b334a45a8ff 3160 #define MCG_C3_SCTRIM_SHIFT 0
bogdanm 0:9b334a45a8ff 3161 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
bogdanm 0:9b334a45a8ff 3162 /* C4 Bit Fields */
bogdanm 0:9b334a45a8ff 3163 #define MCG_C4_SCFTRIM_MASK 0x1u
bogdanm 0:9b334a45a8ff 3164 #define MCG_C4_SCFTRIM_SHIFT 0
bogdanm 0:9b334a45a8ff 3165 #define MCG_C4_FCTRIM_MASK 0x1Eu
bogdanm 0:9b334a45a8ff 3166 #define MCG_C4_FCTRIM_SHIFT 1
bogdanm 0:9b334a45a8ff 3167 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
bogdanm 0:9b334a45a8ff 3168 #define MCG_C4_DRST_DRS_MASK 0x60u
bogdanm 0:9b334a45a8ff 3169 #define MCG_C4_DRST_DRS_SHIFT 5
bogdanm 0:9b334a45a8ff 3170 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
bogdanm 0:9b334a45a8ff 3171 #define MCG_C4_DMX32_MASK 0x80u
bogdanm 0:9b334a45a8ff 3172 #define MCG_C4_DMX32_SHIFT 7
bogdanm 0:9b334a45a8ff 3173 /* C5 Bit Fields */
bogdanm 0:9b334a45a8ff 3174 #define MCG_C5_PRDIV0_MASK 0x1Fu
bogdanm 0:9b334a45a8ff 3175 #define MCG_C5_PRDIV0_SHIFT 0
bogdanm 0:9b334a45a8ff 3176 #define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
bogdanm 0:9b334a45a8ff 3177 #define MCG_C5_PLLSTEN0_MASK 0x20u
bogdanm 0:9b334a45a8ff 3178 #define MCG_C5_PLLSTEN0_SHIFT 5
bogdanm 0:9b334a45a8ff 3179 #define MCG_C5_PLLCLKEN0_MASK 0x40u
bogdanm 0:9b334a45a8ff 3180 #define MCG_C5_PLLCLKEN0_SHIFT 6
bogdanm 0:9b334a45a8ff 3181 /* C6 Bit Fields */
bogdanm 0:9b334a45a8ff 3182 #define MCG_C6_VDIV0_MASK 0x1Fu
bogdanm 0:9b334a45a8ff 3183 #define MCG_C6_VDIV0_SHIFT 0
bogdanm 0:9b334a45a8ff 3184 #define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
bogdanm 0:9b334a45a8ff 3185 #define MCG_C6_CME0_MASK 0x20u
bogdanm 0:9b334a45a8ff 3186 #define MCG_C6_CME0_SHIFT 5
bogdanm 0:9b334a45a8ff 3187 #define MCG_C6_PLLS_MASK 0x40u
bogdanm 0:9b334a45a8ff 3188 #define MCG_C6_PLLS_SHIFT 6
bogdanm 0:9b334a45a8ff 3189 #define MCG_C6_LOLIE0_MASK 0x80u
bogdanm 0:9b334a45a8ff 3190 #define MCG_C6_LOLIE0_SHIFT 7
bogdanm 0:9b334a45a8ff 3191 /* S Bit Fields */
bogdanm 0:9b334a45a8ff 3192 #define MCG_S_IRCST_MASK 0x1u
bogdanm 0:9b334a45a8ff 3193 #define MCG_S_IRCST_SHIFT 0
bogdanm 0:9b334a45a8ff 3194 #define MCG_S_OSCINIT0_MASK 0x2u
bogdanm 0:9b334a45a8ff 3195 #define MCG_S_OSCINIT0_SHIFT 1
bogdanm 0:9b334a45a8ff 3196 #define MCG_S_CLKST_MASK 0xCu
bogdanm 0:9b334a45a8ff 3197 #define MCG_S_CLKST_SHIFT 2
bogdanm 0:9b334a45a8ff 3198 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
bogdanm 0:9b334a45a8ff 3199 #define MCG_S_IREFST_MASK 0x10u
bogdanm 0:9b334a45a8ff 3200 #define MCG_S_IREFST_SHIFT 4
bogdanm 0:9b334a45a8ff 3201 #define MCG_S_PLLST_MASK 0x20u
bogdanm 0:9b334a45a8ff 3202 #define MCG_S_PLLST_SHIFT 5
bogdanm 0:9b334a45a8ff 3203 #define MCG_S_LOCK0_MASK 0x40u
bogdanm 0:9b334a45a8ff 3204 #define MCG_S_LOCK0_SHIFT 6
bogdanm 0:9b334a45a8ff 3205 #define MCG_S_LOLS_MASK 0x80u
bogdanm 0:9b334a45a8ff 3206 #define MCG_S_LOLS_SHIFT 7
bogdanm 0:9b334a45a8ff 3207 /* SC Bit Fields */
bogdanm 0:9b334a45a8ff 3208 #define MCG_SC_LOCS0_MASK 0x1u
bogdanm 0:9b334a45a8ff 3209 #define MCG_SC_LOCS0_SHIFT 0
bogdanm 0:9b334a45a8ff 3210 #define MCG_SC_FCRDIV_MASK 0xEu
bogdanm 0:9b334a45a8ff 3211 #define MCG_SC_FCRDIV_SHIFT 1
bogdanm 0:9b334a45a8ff 3212 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
bogdanm 0:9b334a45a8ff 3213 #define MCG_SC_FLTPRSRV_MASK 0x10u
bogdanm 0:9b334a45a8ff 3214 #define MCG_SC_FLTPRSRV_SHIFT 4
bogdanm 0:9b334a45a8ff 3215 #define MCG_SC_ATMF_MASK 0x20u
bogdanm 0:9b334a45a8ff 3216 #define MCG_SC_ATMF_SHIFT 5
bogdanm 0:9b334a45a8ff 3217 #define MCG_SC_ATMS_MASK 0x40u
bogdanm 0:9b334a45a8ff 3218 #define MCG_SC_ATMS_SHIFT 6
bogdanm 0:9b334a45a8ff 3219 #define MCG_SC_ATME_MASK 0x80u
bogdanm 0:9b334a45a8ff 3220 #define MCG_SC_ATME_SHIFT 7
bogdanm 0:9b334a45a8ff 3221 /* ATCVH Bit Fields */
bogdanm 0:9b334a45a8ff 3222 #define MCG_ATCVH_ATCVH_MASK 0xFFu
bogdanm 0:9b334a45a8ff 3223 #define MCG_ATCVH_ATCVH_SHIFT 0
bogdanm 0:9b334a45a8ff 3224 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
bogdanm 0:9b334a45a8ff 3225 /* ATCVL Bit Fields */
bogdanm 0:9b334a45a8ff 3226 #define MCG_ATCVL_ATCVL_MASK 0xFFu
bogdanm 0:9b334a45a8ff 3227 #define MCG_ATCVL_ATCVL_SHIFT 0
bogdanm 0:9b334a45a8ff 3228 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
bogdanm 0:9b334a45a8ff 3229 /* C8 Bit Fields */
bogdanm 0:9b334a45a8ff 3230 #define MCG_C8_LOLRE_MASK 0x40u
bogdanm 0:9b334a45a8ff 3231 #define MCG_C8_LOLRE_SHIFT 6
bogdanm 0:9b334a45a8ff 3232
bogdanm 0:9b334a45a8ff 3233 /*!
bogdanm 0:9b334a45a8ff 3234 * @}
bogdanm 0:9b334a45a8ff 3235 */ /* end of group MCG_Register_Masks */
bogdanm 0:9b334a45a8ff 3236
bogdanm 0:9b334a45a8ff 3237
bogdanm 0:9b334a45a8ff 3238 /* MCG - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 3239 /** Peripheral MCG base address */
bogdanm 0:9b334a45a8ff 3240 #define MCG_BASE (0x40064000u)
bogdanm 0:9b334a45a8ff 3241 /** Peripheral MCG base pointer */
bogdanm 0:9b334a45a8ff 3242 #define MCG ((MCG_Type *)MCG_BASE)
bogdanm 0:9b334a45a8ff 3243 /** Array initializer of MCG peripheral base pointers */
bogdanm 0:9b334a45a8ff 3244 #define MCG_BASES { MCG }
bogdanm 0:9b334a45a8ff 3245
bogdanm 0:9b334a45a8ff 3246 /*!
bogdanm 0:9b334a45a8ff 3247 * @}
bogdanm 0:9b334a45a8ff 3248 */ /* end of group MCG_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 3249
bogdanm 0:9b334a45a8ff 3250
bogdanm 0:9b334a45a8ff 3251 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 3252 -- MCM Peripheral Access Layer
bogdanm 0:9b334a45a8ff 3253 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 3254
bogdanm 0:9b334a45a8ff 3255 /*!
bogdanm 0:9b334a45a8ff 3256 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
bogdanm 0:9b334a45a8ff 3257 * @{
bogdanm 0:9b334a45a8ff 3258 */
bogdanm 0:9b334a45a8ff 3259
bogdanm 0:9b334a45a8ff 3260 /** MCM - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 3261 typedef struct {
bogdanm 0:9b334a45a8ff 3262 uint8_t RESERVED_0[8];
bogdanm 0:9b334a45a8ff 3263 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
bogdanm 0:9b334a45a8ff 3264 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
bogdanm 0:9b334a45a8ff 3265 __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */
bogdanm 0:9b334a45a8ff 3266 uint8_t RESERVED_1[48];
bogdanm 0:9b334a45a8ff 3267 __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
bogdanm 0:9b334a45a8ff 3268 } MCM_Type;
bogdanm 0:9b334a45a8ff 3269
bogdanm 0:9b334a45a8ff 3270 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 3271 -- MCM Register Masks
bogdanm 0:9b334a45a8ff 3272 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 3273
bogdanm 0:9b334a45a8ff 3274 /*!
bogdanm 0:9b334a45a8ff 3275 * @addtogroup MCM_Register_Masks MCM Register Masks
bogdanm 0:9b334a45a8ff 3276 * @{
bogdanm 0:9b334a45a8ff 3277 */
bogdanm 0:9b334a45a8ff 3278
bogdanm 0:9b334a45a8ff 3279 /* PLASC Bit Fields */
bogdanm 0:9b334a45a8ff 3280 #define MCM_PLASC_ASC_MASK 0xFFu
bogdanm 0:9b334a45a8ff 3281 #define MCM_PLASC_ASC_SHIFT 0
bogdanm 0:9b334a45a8ff 3282 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
bogdanm 0:9b334a45a8ff 3283 /* PLAMC Bit Fields */
bogdanm 0:9b334a45a8ff 3284 #define MCM_PLAMC_AMC_MASK 0xFFu
bogdanm 0:9b334a45a8ff 3285 #define MCM_PLAMC_AMC_SHIFT 0
bogdanm 0:9b334a45a8ff 3286 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
bogdanm 0:9b334a45a8ff 3287 /* PLACR Bit Fields */
bogdanm 0:9b334a45a8ff 3288 #define MCM_PLACR_ARB_MASK 0x200u
bogdanm 0:9b334a45a8ff 3289 #define MCM_PLACR_ARB_SHIFT 9
bogdanm 0:9b334a45a8ff 3290 #define MCM_PLACR_CFCC_MASK 0x400u
bogdanm 0:9b334a45a8ff 3291 #define MCM_PLACR_CFCC_SHIFT 10
bogdanm 0:9b334a45a8ff 3292 #define MCM_PLACR_DFCDA_MASK 0x800u
bogdanm 0:9b334a45a8ff 3293 #define MCM_PLACR_DFCDA_SHIFT 11
bogdanm 0:9b334a45a8ff 3294 #define MCM_PLACR_DFCIC_MASK 0x1000u
bogdanm 0:9b334a45a8ff 3295 #define MCM_PLACR_DFCIC_SHIFT 12
bogdanm 0:9b334a45a8ff 3296 #define MCM_PLACR_DFCC_MASK 0x2000u
bogdanm 0:9b334a45a8ff 3297 #define MCM_PLACR_DFCC_SHIFT 13
bogdanm 0:9b334a45a8ff 3298 #define MCM_PLACR_EFDS_MASK 0x4000u
bogdanm 0:9b334a45a8ff 3299 #define MCM_PLACR_EFDS_SHIFT 14
bogdanm 0:9b334a45a8ff 3300 #define MCM_PLACR_DFCS_MASK 0x8000u
bogdanm 0:9b334a45a8ff 3301 #define MCM_PLACR_DFCS_SHIFT 15
bogdanm 0:9b334a45a8ff 3302 #define MCM_PLACR_ESFC_MASK 0x10000u
bogdanm 0:9b334a45a8ff 3303 #define MCM_PLACR_ESFC_SHIFT 16
bogdanm 0:9b334a45a8ff 3304 /* CPO Bit Fields */
bogdanm 0:9b334a45a8ff 3305 #define MCM_CPO_CPOREQ_MASK 0x1u
bogdanm 0:9b334a45a8ff 3306 #define MCM_CPO_CPOREQ_SHIFT 0
bogdanm 0:9b334a45a8ff 3307 #define MCM_CPO_CPOACK_MASK 0x2u
bogdanm 0:9b334a45a8ff 3308 #define MCM_CPO_CPOACK_SHIFT 1
bogdanm 0:9b334a45a8ff 3309 #define MCM_CPO_CPOWOI_MASK 0x4u
bogdanm 0:9b334a45a8ff 3310 #define MCM_CPO_CPOWOI_SHIFT 2
bogdanm 0:9b334a45a8ff 3311
bogdanm 0:9b334a45a8ff 3312 /*!
bogdanm 0:9b334a45a8ff 3313 * @}
bogdanm 0:9b334a45a8ff 3314 */ /* end of group MCM_Register_Masks */
bogdanm 0:9b334a45a8ff 3315
bogdanm 0:9b334a45a8ff 3316
bogdanm 0:9b334a45a8ff 3317 /* MCM - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 3318 /** Peripheral MCM base address */
bogdanm 0:9b334a45a8ff 3319 #define MCM_BASE (0xF0003000u)
bogdanm 0:9b334a45a8ff 3320 /** Peripheral MCM base pointer */
bogdanm 0:9b334a45a8ff 3321 #define MCM ((MCM_Type *)MCM_BASE)
bogdanm 0:9b334a45a8ff 3322 /** Array initializer of MCM peripheral base pointers */
bogdanm 0:9b334a45a8ff 3323 #define MCM_BASES { MCM }
bogdanm 0:9b334a45a8ff 3324
bogdanm 0:9b334a45a8ff 3325 /*!
bogdanm 0:9b334a45a8ff 3326 * @}
bogdanm 0:9b334a45a8ff 3327 */ /* end of group MCM_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 3328
bogdanm 0:9b334a45a8ff 3329
bogdanm 0:9b334a45a8ff 3330 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 3331 -- MTB Peripheral Access Layer
bogdanm 0:9b334a45a8ff 3332 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 3333
bogdanm 0:9b334a45a8ff 3334 /*!
bogdanm 0:9b334a45a8ff 3335 * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
bogdanm 0:9b334a45a8ff 3336 * @{
bogdanm 0:9b334a45a8ff 3337 */
bogdanm 0:9b334a45a8ff 3338
bogdanm 0:9b334a45a8ff 3339 /** MTB - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 3340 typedef struct {
bogdanm 0:9b334a45a8ff 3341 __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */
bogdanm 0:9b334a45a8ff 3342 __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */
bogdanm 0:9b334a45a8ff 3343 __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */
bogdanm 0:9b334a45a8ff 3344 __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */
bogdanm 0:9b334a45a8ff 3345 uint8_t RESERVED_0[3824];
bogdanm 0:9b334a45a8ff 3346 __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */
bogdanm 0:9b334a45a8ff 3347 uint8_t RESERVED_1[156];
bogdanm 0:9b334a45a8ff 3348 __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */
bogdanm 0:9b334a45a8ff 3349 __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */
bogdanm 0:9b334a45a8ff 3350 uint8_t RESERVED_2[8];
bogdanm 0:9b334a45a8ff 3351 __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */
bogdanm 0:9b334a45a8ff 3352 __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */
bogdanm 0:9b334a45a8ff 3353 __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */
bogdanm 0:9b334a45a8ff 3354 __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */
bogdanm 0:9b334a45a8ff 3355 uint8_t RESERVED_3[8];
bogdanm 0:9b334a45a8ff 3356 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
bogdanm 0:9b334a45a8ff 3357 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
bogdanm 0:9b334a45a8ff 3358 __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
bogdanm 0:9b334a45a8ff 3359 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
bogdanm 0:9b334a45a8ff 3360 } MTB_Type;
bogdanm 0:9b334a45a8ff 3361
bogdanm 0:9b334a45a8ff 3362 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 3363 -- MTB Register Masks
bogdanm 0:9b334a45a8ff 3364 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 3365
bogdanm 0:9b334a45a8ff 3366 /*!
bogdanm 0:9b334a45a8ff 3367 * @addtogroup MTB_Register_Masks MTB Register Masks
bogdanm 0:9b334a45a8ff 3368 * @{
bogdanm 0:9b334a45a8ff 3369 */
bogdanm 0:9b334a45a8ff 3370
bogdanm 0:9b334a45a8ff 3371 /* POSITION Bit Fields */
bogdanm 0:9b334a45a8ff 3372 #define MTB_POSITION_WRAP_MASK 0x4u
bogdanm 0:9b334a45a8ff 3373 #define MTB_POSITION_WRAP_SHIFT 2
bogdanm 0:9b334a45a8ff 3374 #define MTB_POSITION_POINTER_MASK 0xFFFFFFF8u
bogdanm 0:9b334a45a8ff 3375 #define MTB_POSITION_POINTER_SHIFT 3
bogdanm 0:9b334a45a8ff 3376 #define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_POINTER_SHIFT))&MTB_POSITION_POINTER_MASK)
bogdanm 0:9b334a45a8ff 3377 /* MASTER Bit Fields */
bogdanm 0:9b334a45a8ff 3378 #define MTB_MASTER_MASK_MASK 0x1Fu
bogdanm 0:9b334a45a8ff 3379 #define MTB_MASTER_MASK_SHIFT 0
bogdanm 0:9b334a45a8ff 3380 #define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_MASK_SHIFT))&MTB_MASTER_MASK_MASK)
bogdanm 0:9b334a45a8ff 3381 #define MTB_MASTER_TSTARTEN_MASK 0x20u
bogdanm 0:9b334a45a8ff 3382 #define MTB_MASTER_TSTARTEN_SHIFT 5
bogdanm 0:9b334a45a8ff 3383 #define MTB_MASTER_TSTOPEN_MASK 0x40u
bogdanm 0:9b334a45a8ff 3384 #define MTB_MASTER_TSTOPEN_SHIFT 6
bogdanm 0:9b334a45a8ff 3385 #define MTB_MASTER_SFRWPRIV_MASK 0x80u
bogdanm 0:9b334a45a8ff 3386 #define MTB_MASTER_SFRWPRIV_SHIFT 7
bogdanm 0:9b334a45a8ff 3387 #define MTB_MASTER_RAMPRIV_MASK 0x100u
bogdanm 0:9b334a45a8ff 3388 #define MTB_MASTER_RAMPRIV_SHIFT 8
bogdanm 0:9b334a45a8ff 3389 #define MTB_MASTER_HALTREQ_MASK 0x200u
bogdanm 0:9b334a45a8ff 3390 #define MTB_MASTER_HALTREQ_SHIFT 9
bogdanm 0:9b334a45a8ff 3391 #define MTB_MASTER_EN_MASK 0x80000000u
bogdanm 0:9b334a45a8ff 3392 #define MTB_MASTER_EN_SHIFT 31
bogdanm 0:9b334a45a8ff 3393 /* FLOW Bit Fields */
bogdanm 0:9b334a45a8ff 3394 #define MTB_FLOW_AUTOSTOP_MASK 0x1u
bogdanm 0:9b334a45a8ff 3395 #define MTB_FLOW_AUTOSTOP_SHIFT 0
bogdanm 0:9b334a45a8ff 3396 #define MTB_FLOW_AUTOHALT_MASK 0x2u
bogdanm 0:9b334a45a8ff 3397 #define MTB_FLOW_AUTOHALT_SHIFT 1
bogdanm 0:9b334a45a8ff 3398 #define MTB_FLOW_WATERMARK_MASK 0xFFFFFFF8u
bogdanm 0:9b334a45a8ff 3399 #define MTB_FLOW_WATERMARK_SHIFT 3
bogdanm 0:9b334a45a8ff 3400 #define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_WATERMARK_SHIFT))&MTB_FLOW_WATERMARK_MASK)
bogdanm 0:9b334a45a8ff 3401 /* BASE Bit Fields */
bogdanm 0:9b334a45a8ff 3402 #define MTB_BASE_BASEADDR_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 3403 #define MTB_BASE_BASEADDR_SHIFT 0
bogdanm 0:9b334a45a8ff 3404 #define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x))<<MTB_BASE_BASEADDR_SHIFT))&MTB_BASE_BASEADDR_MASK)
bogdanm 0:9b334a45a8ff 3405 /* MODECTRL Bit Fields */
bogdanm 0:9b334a45a8ff 3406 #define MTB_MODECTRL_MODECTRL_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 3407 #define MTB_MODECTRL_MODECTRL_SHIFT 0
bogdanm 0:9b334a45a8ff 3408 #define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x))<<MTB_MODECTRL_MODECTRL_SHIFT))&MTB_MODECTRL_MODECTRL_MASK)
bogdanm 0:9b334a45a8ff 3409 /* TAGSET Bit Fields */
bogdanm 0:9b334a45a8ff 3410 #define MTB_TAGSET_TAGSET_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 3411 #define MTB_TAGSET_TAGSET_SHIFT 0
bogdanm 0:9b334a45a8ff 3412 #define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGSET_TAGSET_SHIFT))&MTB_TAGSET_TAGSET_MASK)
bogdanm 0:9b334a45a8ff 3413 /* TAGCLEAR Bit Fields */
bogdanm 0:9b334a45a8ff 3414 #define MTB_TAGCLEAR_TAGCLEAR_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 3415 #define MTB_TAGCLEAR_TAGCLEAR_SHIFT 0
bogdanm 0:9b334a45a8ff 3416 #define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGCLEAR_TAGCLEAR_SHIFT))&MTB_TAGCLEAR_TAGCLEAR_MASK)
bogdanm 0:9b334a45a8ff 3417 /* LOCKACCESS Bit Fields */
bogdanm 0:9b334a45a8ff 3418 #define MTB_LOCKACCESS_LOCKACCESS_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 3419 #define MTB_LOCKACCESS_LOCKACCESS_SHIFT 0
bogdanm 0:9b334a45a8ff 3420 #define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKACCESS_LOCKACCESS_SHIFT))&MTB_LOCKACCESS_LOCKACCESS_MASK)
bogdanm 0:9b334a45a8ff 3421 /* LOCKSTAT Bit Fields */
bogdanm 0:9b334a45a8ff 3422 #define MTB_LOCKSTAT_LOCKSTAT_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 3423 #define MTB_LOCKSTAT_LOCKSTAT_SHIFT 0
bogdanm 0:9b334a45a8ff 3424 #define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKSTAT_LOCKSTAT_SHIFT))&MTB_LOCKSTAT_LOCKSTAT_MASK)
bogdanm 0:9b334a45a8ff 3425 /* AUTHSTAT Bit Fields */
bogdanm 0:9b334a45a8ff 3426 #define MTB_AUTHSTAT_BIT0_MASK 0x1u
bogdanm 0:9b334a45a8ff 3427 #define MTB_AUTHSTAT_BIT0_SHIFT 0
bogdanm 0:9b334a45a8ff 3428 #define MTB_AUTHSTAT_BIT1_MASK 0x2u
bogdanm 0:9b334a45a8ff 3429 #define MTB_AUTHSTAT_BIT1_SHIFT 1
bogdanm 0:9b334a45a8ff 3430 #define MTB_AUTHSTAT_BIT2_MASK 0x4u
bogdanm 0:9b334a45a8ff 3431 #define MTB_AUTHSTAT_BIT2_SHIFT 2
bogdanm 0:9b334a45a8ff 3432 #define MTB_AUTHSTAT_BIT3_MASK 0x8u
bogdanm 0:9b334a45a8ff 3433 #define MTB_AUTHSTAT_BIT3_SHIFT 3
bogdanm 0:9b334a45a8ff 3434 /* DEVICEARCH Bit Fields */
bogdanm 0:9b334a45a8ff 3435 #define MTB_DEVICEARCH_DEVICEARCH_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 3436 #define MTB_DEVICEARCH_DEVICEARCH_SHIFT 0
bogdanm 0:9b334a45a8ff 3437 #define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICEARCH_DEVICEARCH_SHIFT))&MTB_DEVICEARCH_DEVICEARCH_MASK)
bogdanm 0:9b334a45a8ff 3438 /* DEVICECFG Bit Fields */
bogdanm 0:9b334a45a8ff 3439 #define MTB_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 3440 #define MTB_DEVICECFG_DEVICECFG_SHIFT 0
bogdanm 0:9b334a45a8ff 3441 #define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICECFG_DEVICECFG_SHIFT))&MTB_DEVICECFG_DEVICECFG_MASK)
bogdanm 0:9b334a45a8ff 3442 /* DEVICETYPID Bit Fields */
bogdanm 0:9b334a45a8ff 3443 #define MTB_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 3444 #define MTB_DEVICETYPID_DEVICETYPID_SHIFT 0
bogdanm 0:9b334a45a8ff 3445 #define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICETYPID_DEVICETYPID_SHIFT))&MTB_DEVICETYPID_DEVICETYPID_MASK)
bogdanm 0:9b334a45a8ff 3446 /* PERIPHID Bit Fields */
bogdanm 0:9b334a45a8ff 3447 #define MTB_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 3448 #define MTB_PERIPHID_PERIPHID_SHIFT 0
bogdanm 0:9b334a45a8ff 3449 #define MTB_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTB_PERIPHID_PERIPHID_SHIFT))&MTB_PERIPHID_PERIPHID_MASK)
bogdanm 0:9b334a45a8ff 3450 /* COMPID Bit Fields */
bogdanm 0:9b334a45a8ff 3451 #define MTB_COMPID_COMPID_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 3452 #define MTB_COMPID_COMPID_SHIFT 0
bogdanm 0:9b334a45a8ff 3453 #define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_COMPID_COMPID_SHIFT))&MTB_COMPID_COMPID_MASK)
bogdanm 0:9b334a45a8ff 3454
bogdanm 0:9b334a45a8ff 3455 /*!
bogdanm 0:9b334a45a8ff 3456 * @}
bogdanm 0:9b334a45a8ff 3457 */ /* end of group MTB_Register_Masks */
bogdanm 0:9b334a45a8ff 3458
bogdanm 0:9b334a45a8ff 3459
bogdanm 0:9b334a45a8ff 3460 /* MTB - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 3461 /** Peripheral MTB base address */
bogdanm 0:9b334a45a8ff 3462 #define MTB_BASE (0xF0000000u)
bogdanm 0:9b334a45a8ff 3463 /** Peripheral MTB base pointer */
bogdanm 0:9b334a45a8ff 3464 #define MTB ((MTB_Type *)MTB_BASE)
bogdanm 0:9b334a45a8ff 3465 /** Array initializer of MTB peripheral base pointers */
bogdanm 0:9b334a45a8ff 3466 #define MTB_BASES { MTB }
bogdanm 0:9b334a45a8ff 3467
bogdanm 0:9b334a45a8ff 3468 /*!
bogdanm 0:9b334a45a8ff 3469 * @}
bogdanm 0:9b334a45a8ff 3470 */ /* end of group MTB_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 3471
bogdanm 0:9b334a45a8ff 3472
bogdanm 0:9b334a45a8ff 3473 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 3474 -- MTBDWT Peripheral Access Layer
bogdanm 0:9b334a45a8ff 3475 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 3476
bogdanm 0:9b334a45a8ff 3477 /*!
bogdanm 0:9b334a45a8ff 3478 * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
bogdanm 0:9b334a45a8ff 3479 * @{
bogdanm 0:9b334a45a8ff 3480 */
bogdanm 0:9b334a45a8ff 3481
bogdanm 0:9b334a45a8ff 3482 /** MTBDWT - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 3483 typedef struct {
bogdanm 0:9b334a45a8ff 3484 __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */
bogdanm 0:9b334a45a8ff 3485 uint8_t RESERVED_0[28];
bogdanm 0:9b334a45a8ff 3486 struct { /* offset: 0x20, array step: 0x10 */
bogdanm 0:9b334a45a8ff 3487 __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */
bogdanm 0:9b334a45a8ff 3488 __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
bogdanm 0:9b334a45a8ff 3489 __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */
bogdanm 0:9b334a45a8ff 3490 uint8_t RESERVED_0[4];
bogdanm 0:9b334a45a8ff 3491 } COMPARATOR[2];
bogdanm 0:9b334a45a8ff 3492 uint8_t RESERVED_1[448];
bogdanm 0:9b334a45a8ff 3493 __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */
bogdanm 0:9b334a45a8ff 3494 uint8_t RESERVED_2[3524];
bogdanm 0:9b334a45a8ff 3495 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
bogdanm 0:9b334a45a8ff 3496 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
bogdanm 0:9b334a45a8ff 3497 __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
bogdanm 0:9b334a45a8ff 3498 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
bogdanm 0:9b334a45a8ff 3499 } MTBDWT_Type;
bogdanm 0:9b334a45a8ff 3500
bogdanm 0:9b334a45a8ff 3501 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 3502 -- MTBDWT Register Masks
bogdanm 0:9b334a45a8ff 3503 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 3504
bogdanm 0:9b334a45a8ff 3505 /*!
bogdanm 0:9b334a45a8ff 3506 * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
bogdanm 0:9b334a45a8ff 3507 * @{
bogdanm 0:9b334a45a8ff 3508 */
bogdanm 0:9b334a45a8ff 3509
bogdanm 0:9b334a45a8ff 3510 /* CTRL Bit Fields */
bogdanm 0:9b334a45a8ff 3511 #define MTBDWT_CTRL_DWTCFGCTRL_MASK 0xFFFFFFFu
bogdanm 0:9b334a45a8ff 3512 #define MTBDWT_CTRL_DWTCFGCTRL_SHIFT 0
bogdanm 0:9b334a45a8ff 3513 #define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_DWTCFGCTRL_SHIFT))&MTBDWT_CTRL_DWTCFGCTRL_MASK)
bogdanm 0:9b334a45a8ff 3514 #define MTBDWT_CTRL_NUMCMP_MASK 0xF0000000u
bogdanm 0:9b334a45a8ff 3515 #define MTBDWT_CTRL_NUMCMP_SHIFT 28
bogdanm 0:9b334a45a8ff 3516 #define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_NUMCMP_SHIFT))&MTBDWT_CTRL_NUMCMP_MASK)
bogdanm 0:9b334a45a8ff 3517 /* COMP Bit Fields */
bogdanm 0:9b334a45a8ff 3518 #define MTBDWT_COMP_COMP_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 3519 #define MTBDWT_COMP_COMP_SHIFT 0
bogdanm 0:9b334a45a8ff 3520 #define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMP_COMP_SHIFT))&MTBDWT_COMP_COMP_MASK)
bogdanm 0:9b334a45a8ff 3521 /* MASK Bit Fields */
bogdanm 0:9b334a45a8ff 3522 #define MTBDWT_MASK_MASK_MASK 0x1Fu
bogdanm 0:9b334a45a8ff 3523 #define MTBDWT_MASK_MASK_SHIFT 0
bogdanm 0:9b334a45a8ff 3524 #define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_MASK_MASK_SHIFT))&MTBDWT_MASK_MASK_MASK)
bogdanm 0:9b334a45a8ff 3525 /* FCT Bit Fields */
bogdanm 0:9b334a45a8ff 3526 #define MTBDWT_FCT_FUNCTION_MASK 0xFu
bogdanm 0:9b334a45a8ff 3527 #define MTBDWT_FCT_FUNCTION_SHIFT 0
bogdanm 0:9b334a45a8ff 3528 #define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_FUNCTION_SHIFT))&MTBDWT_FCT_FUNCTION_MASK)
bogdanm 0:9b334a45a8ff 3529 #define MTBDWT_FCT_DATAVMATCH_MASK 0x100u
bogdanm 0:9b334a45a8ff 3530 #define MTBDWT_FCT_DATAVMATCH_SHIFT 8
bogdanm 0:9b334a45a8ff 3531 #define MTBDWT_FCT_DATAVSIZE_MASK 0xC00u
bogdanm 0:9b334a45a8ff 3532 #define MTBDWT_FCT_DATAVSIZE_SHIFT 10
bogdanm 0:9b334a45a8ff 3533 #define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVSIZE_SHIFT))&MTBDWT_FCT_DATAVSIZE_MASK)
bogdanm 0:9b334a45a8ff 3534 #define MTBDWT_FCT_DATAVADDR0_MASK 0xF000u
bogdanm 0:9b334a45a8ff 3535 #define MTBDWT_FCT_DATAVADDR0_SHIFT 12
bogdanm 0:9b334a45a8ff 3536 #define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVADDR0_SHIFT))&MTBDWT_FCT_DATAVADDR0_MASK)
bogdanm 0:9b334a45a8ff 3537 #define MTBDWT_FCT_MATCHED_MASK 0x1000000u
bogdanm 0:9b334a45a8ff 3538 #define MTBDWT_FCT_MATCHED_SHIFT 24
bogdanm 0:9b334a45a8ff 3539 /* TBCTRL Bit Fields */
bogdanm 0:9b334a45a8ff 3540 #define MTBDWT_TBCTRL_ACOMP0_MASK 0x1u
bogdanm 0:9b334a45a8ff 3541 #define MTBDWT_TBCTRL_ACOMP0_SHIFT 0
bogdanm 0:9b334a45a8ff 3542 #define MTBDWT_TBCTRL_ACOMP1_MASK 0x2u
bogdanm 0:9b334a45a8ff 3543 #define MTBDWT_TBCTRL_ACOMP1_SHIFT 1
bogdanm 0:9b334a45a8ff 3544 #define MTBDWT_TBCTRL_NUMCOMP_MASK 0xF0000000u
bogdanm 0:9b334a45a8ff 3545 #define MTBDWT_TBCTRL_NUMCOMP_SHIFT 28
bogdanm 0:9b334a45a8ff 3546 #define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_NUMCOMP_SHIFT))&MTBDWT_TBCTRL_NUMCOMP_MASK)
bogdanm 0:9b334a45a8ff 3547 /* DEVICECFG Bit Fields */
bogdanm 0:9b334a45a8ff 3548 #define MTBDWT_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 3549 #define MTBDWT_DEVICECFG_DEVICECFG_SHIFT 0
bogdanm 0:9b334a45a8ff 3550 #define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICECFG_DEVICECFG_SHIFT))&MTBDWT_DEVICECFG_DEVICECFG_MASK)
bogdanm 0:9b334a45a8ff 3551 /* DEVICETYPID Bit Fields */
bogdanm 0:9b334a45a8ff 3552 #define MTBDWT_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 3553 #define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT 0
bogdanm 0:9b334a45a8ff 3554 #define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT))&MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
bogdanm 0:9b334a45a8ff 3555 /* PERIPHID Bit Fields */
bogdanm 0:9b334a45a8ff 3556 #define MTBDWT_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 3557 #define MTBDWT_PERIPHID_PERIPHID_SHIFT 0
bogdanm 0:9b334a45a8ff 3558 #define MTBDWT_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_PERIPHID_PERIPHID_SHIFT))&MTBDWT_PERIPHID_PERIPHID_MASK)
bogdanm 0:9b334a45a8ff 3559 /* COMPID Bit Fields */
bogdanm 0:9b334a45a8ff 3560 #define MTBDWT_COMPID_COMPID_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 3561 #define MTBDWT_COMPID_COMPID_SHIFT 0
bogdanm 0:9b334a45a8ff 3562 #define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMPID_COMPID_SHIFT))&MTBDWT_COMPID_COMPID_MASK)
bogdanm 0:9b334a45a8ff 3563
bogdanm 0:9b334a45a8ff 3564 /*!
bogdanm 0:9b334a45a8ff 3565 * @}
bogdanm 0:9b334a45a8ff 3566 */ /* end of group MTBDWT_Register_Masks */
bogdanm 0:9b334a45a8ff 3567
bogdanm 0:9b334a45a8ff 3568
bogdanm 0:9b334a45a8ff 3569 /* MTBDWT - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 3570 /** Peripheral MTBDWT base address */
bogdanm 0:9b334a45a8ff 3571 #define MTBDWT_BASE (0xF0001000u)
bogdanm 0:9b334a45a8ff 3572 /** Peripheral MTBDWT base pointer */
bogdanm 0:9b334a45a8ff 3573 #define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE)
bogdanm 0:9b334a45a8ff 3574 /** Array initializer of MTBDWT peripheral base pointers */
bogdanm 0:9b334a45a8ff 3575 #define MTBDWT_BASES { MTBDWT }
bogdanm 0:9b334a45a8ff 3576
bogdanm 0:9b334a45a8ff 3577 /*!
bogdanm 0:9b334a45a8ff 3578 * @}
bogdanm 0:9b334a45a8ff 3579 */ /* end of group MTBDWT_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 3580
bogdanm 0:9b334a45a8ff 3581
bogdanm 0:9b334a45a8ff 3582 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 3583 -- NV Peripheral Access Layer
bogdanm 0:9b334a45a8ff 3584 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 3585
bogdanm 0:9b334a45a8ff 3586 /*!
bogdanm 0:9b334a45a8ff 3587 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
bogdanm 0:9b334a45a8ff 3588 * @{
bogdanm 0:9b334a45a8ff 3589 */
bogdanm 0:9b334a45a8ff 3590
bogdanm 0:9b334a45a8ff 3591 /** NV - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 3592 typedef struct {
bogdanm 0:9b334a45a8ff 3593 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
bogdanm 0:9b334a45a8ff 3594 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
bogdanm 0:9b334a45a8ff 3595 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
bogdanm 0:9b334a45a8ff 3596 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
bogdanm 0:9b334a45a8ff 3597 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
bogdanm 0:9b334a45a8ff 3598 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
bogdanm 0:9b334a45a8ff 3599 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
bogdanm 0:9b334a45a8ff 3600 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
bogdanm 0:9b334a45a8ff 3601 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
bogdanm 0:9b334a45a8ff 3602 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
bogdanm 0:9b334a45a8ff 3603 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
bogdanm 0:9b334a45a8ff 3604 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
bogdanm 0:9b334a45a8ff 3605 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
bogdanm 0:9b334a45a8ff 3606 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
bogdanm 0:9b334a45a8ff 3607 } NV_Type;
bogdanm 0:9b334a45a8ff 3608
bogdanm 0:9b334a45a8ff 3609 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 3610 -- NV Register Masks
bogdanm 0:9b334a45a8ff 3611 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 3612
bogdanm 0:9b334a45a8ff 3613 /*!
bogdanm 0:9b334a45a8ff 3614 * @addtogroup NV_Register_Masks NV Register Masks
bogdanm 0:9b334a45a8ff 3615 * @{
bogdanm 0:9b334a45a8ff 3616 */
bogdanm 0:9b334a45a8ff 3617
bogdanm 0:9b334a45a8ff 3618 /* BACKKEY3 Bit Fields */
bogdanm 0:9b334a45a8ff 3619 #define NV_BACKKEY3_KEY_MASK 0xFFu
bogdanm 0:9b334a45a8ff 3620 #define NV_BACKKEY3_KEY_SHIFT 0
bogdanm 0:9b334a45a8ff 3621 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
bogdanm 0:9b334a45a8ff 3622 /* BACKKEY2 Bit Fields */
bogdanm 0:9b334a45a8ff 3623 #define NV_BACKKEY2_KEY_MASK 0xFFu
bogdanm 0:9b334a45a8ff 3624 #define NV_BACKKEY2_KEY_SHIFT 0
bogdanm 0:9b334a45a8ff 3625 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
bogdanm 0:9b334a45a8ff 3626 /* BACKKEY1 Bit Fields */
bogdanm 0:9b334a45a8ff 3627 #define NV_BACKKEY1_KEY_MASK 0xFFu
bogdanm 0:9b334a45a8ff 3628 #define NV_BACKKEY1_KEY_SHIFT 0
bogdanm 0:9b334a45a8ff 3629 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
bogdanm 0:9b334a45a8ff 3630 /* BACKKEY0 Bit Fields */
bogdanm 0:9b334a45a8ff 3631 #define NV_BACKKEY0_KEY_MASK 0xFFu
bogdanm 0:9b334a45a8ff 3632 #define NV_BACKKEY0_KEY_SHIFT 0
bogdanm 0:9b334a45a8ff 3633 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
bogdanm 0:9b334a45a8ff 3634 /* BACKKEY7 Bit Fields */
bogdanm 0:9b334a45a8ff 3635 #define NV_BACKKEY7_KEY_MASK 0xFFu
bogdanm 0:9b334a45a8ff 3636 #define NV_BACKKEY7_KEY_SHIFT 0
bogdanm 0:9b334a45a8ff 3637 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
bogdanm 0:9b334a45a8ff 3638 /* BACKKEY6 Bit Fields */
bogdanm 0:9b334a45a8ff 3639 #define NV_BACKKEY6_KEY_MASK 0xFFu
bogdanm 0:9b334a45a8ff 3640 #define NV_BACKKEY6_KEY_SHIFT 0
bogdanm 0:9b334a45a8ff 3641 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
bogdanm 0:9b334a45a8ff 3642 /* BACKKEY5 Bit Fields */
bogdanm 0:9b334a45a8ff 3643 #define NV_BACKKEY5_KEY_MASK 0xFFu
bogdanm 0:9b334a45a8ff 3644 #define NV_BACKKEY5_KEY_SHIFT 0
bogdanm 0:9b334a45a8ff 3645 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
bogdanm 0:9b334a45a8ff 3646 /* BACKKEY4 Bit Fields */
bogdanm 0:9b334a45a8ff 3647 #define NV_BACKKEY4_KEY_MASK 0xFFu
bogdanm 0:9b334a45a8ff 3648 #define NV_BACKKEY4_KEY_SHIFT 0
bogdanm 0:9b334a45a8ff 3649 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
bogdanm 0:9b334a45a8ff 3650 /* FPROT3 Bit Fields */
bogdanm 0:9b334a45a8ff 3651 #define NV_FPROT3_PROT_MASK 0xFFu
bogdanm 0:9b334a45a8ff 3652 #define NV_FPROT3_PROT_SHIFT 0
bogdanm 0:9b334a45a8ff 3653 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
bogdanm 0:9b334a45a8ff 3654 /* FPROT2 Bit Fields */
bogdanm 0:9b334a45a8ff 3655 #define NV_FPROT2_PROT_MASK 0xFFu
bogdanm 0:9b334a45a8ff 3656 #define NV_FPROT2_PROT_SHIFT 0
bogdanm 0:9b334a45a8ff 3657 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
bogdanm 0:9b334a45a8ff 3658 /* FPROT1 Bit Fields */
bogdanm 0:9b334a45a8ff 3659 #define NV_FPROT1_PROT_MASK 0xFFu
bogdanm 0:9b334a45a8ff 3660 #define NV_FPROT1_PROT_SHIFT 0
bogdanm 0:9b334a45a8ff 3661 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
bogdanm 0:9b334a45a8ff 3662 /* FPROT0 Bit Fields */
bogdanm 0:9b334a45a8ff 3663 #define NV_FPROT0_PROT_MASK 0xFFu
bogdanm 0:9b334a45a8ff 3664 #define NV_FPROT0_PROT_SHIFT 0
bogdanm 0:9b334a45a8ff 3665 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
bogdanm 0:9b334a45a8ff 3666 /* FSEC Bit Fields */
bogdanm 0:9b334a45a8ff 3667 #define NV_FSEC_SEC_MASK 0x3u
bogdanm 0:9b334a45a8ff 3668 #define NV_FSEC_SEC_SHIFT 0
bogdanm 0:9b334a45a8ff 3669 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
bogdanm 0:9b334a45a8ff 3670 #define NV_FSEC_FSLACC_MASK 0xCu
bogdanm 0:9b334a45a8ff 3671 #define NV_FSEC_FSLACC_SHIFT 2
bogdanm 0:9b334a45a8ff 3672 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
bogdanm 0:9b334a45a8ff 3673 #define NV_FSEC_MEEN_MASK 0x30u
bogdanm 0:9b334a45a8ff 3674 #define NV_FSEC_MEEN_SHIFT 4
bogdanm 0:9b334a45a8ff 3675 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
bogdanm 0:9b334a45a8ff 3676 #define NV_FSEC_KEYEN_MASK 0xC0u
bogdanm 0:9b334a45a8ff 3677 #define NV_FSEC_KEYEN_SHIFT 6
bogdanm 0:9b334a45a8ff 3678 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
bogdanm 0:9b334a45a8ff 3679 /* FOPT Bit Fields */
bogdanm 0:9b334a45a8ff 3680 #define NV_FOPT_LPBOOT0_MASK 0x1u
bogdanm 0:9b334a45a8ff 3681 #define NV_FOPT_LPBOOT0_SHIFT 0
bogdanm 0:9b334a45a8ff 3682 #define NV_FOPT_NMI_DIS_MASK 0x4u
bogdanm 0:9b334a45a8ff 3683 #define NV_FOPT_NMI_DIS_SHIFT 2
bogdanm 0:9b334a45a8ff 3684 #define NV_FOPT_RESET_PIN_CFG_MASK 0x8u
bogdanm 0:9b334a45a8ff 3685 #define NV_FOPT_RESET_PIN_CFG_SHIFT 3
bogdanm 0:9b334a45a8ff 3686 #define NV_FOPT_LPBOOT1_MASK 0x10u
bogdanm 0:9b334a45a8ff 3687 #define NV_FOPT_LPBOOT1_SHIFT 4
bogdanm 0:9b334a45a8ff 3688 #define NV_FOPT_FAST_INIT_MASK 0x20u
bogdanm 0:9b334a45a8ff 3689 #define NV_FOPT_FAST_INIT_SHIFT 5
bogdanm 0:9b334a45a8ff 3690
bogdanm 0:9b334a45a8ff 3691 /*!
bogdanm 0:9b334a45a8ff 3692 * @}
bogdanm 0:9b334a45a8ff 3693 */ /* end of group NV_Register_Masks */
bogdanm 0:9b334a45a8ff 3694
bogdanm 0:9b334a45a8ff 3695
bogdanm 0:9b334a45a8ff 3696 /* NV - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 3697 /** Peripheral FTFA_FlashConfig base address */
bogdanm 0:9b334a45a8ff 3698 #define FTFA_FlashConfig_BASE (0x400u)
bogdanm 0:9b334a45a8ff 3699 /** Peripheral FTFA_FlashConfig base pointer */
bogdanm 0:9b334a45a8ff 3700 #define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
bogdanm 0:9b334a45a8ff 3701 /** Array initializer of NV peripheral base pointers */
bogdanm 0:9b334a45a8ff 3702 #define NV_BASES { FTFA_FlashConfig }
bogdanm 0:9b334a45a8ff 3703
bogdanm 0:9b334a45a8ff 3704 /*!
bogdanm 0:9b334a45a8ff 3705 * @}
bogdanm 0:9b334a45a8ff 3706 */ /* end of group NV_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 3707
bogdanm 0:9b334a45a8ff 3708
bogdanm 0:9b334a45a8ff 3709 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 3710 -- OSC Peripheral Access Layer
bogdanm 0:9b334a45a8ff 3711 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 3712
bogdanm 0:9b334a45a8ff 3713 /*!
bogdanm 0:9b334a45a8ff 3714 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
bogdanm 0:9b334a45a8ff 3715 * @{
bogdanm 0:9b334a45a8ff 3716 */
bogdanm 0:9b334a45a8ff 3717
bogdanm 0:9b334a45a8ff 3718 /** OSC - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 3719 typedef struct {
bogdanm 0:9b334a45a8ff 3720 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
bogdanm 0:9b334a45a8ff 3721 } OSC_Type;
bogdanm 0:9b334a45a8ff 3722
bogdanm 0:9b334a45a8ff 3723 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 3724 -- OSC Register Masks
bogdanm 0:9b334a45a8ff 3725 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 3726
bogdanm 0:9b334a45a8ff 3727 /*!
bogdanm 0:9b334a45a8ff 3728 * @addtogroup OSC_Register_Masks OSC Register Masks
bogdanm 0:9b334a45a8ff 3729 * @{
bogdanm 0:9b334a45a8ff 3730 */
bogdanm 0:9b334a45a8ff 3731
bogdanm 0:9b334a45a8ff 3732 /* CR Bit Fields */
bogdanm 0:9b334a45a8ff 3733 #define OSC_CR_SC16P_MASK 0x1u
bogdanm 0:9b334a45a8ff 3734 #define OSC_CR_SC16P_SHIFT 0
bogdanm 0:9b334a45a8ff 3735 #define OSC_CR_SC8P_MASK 0x2u
bogdanm 0:9b334a45a8ff 3736 #define OSC_CR_SC8P_SHIFT 1
bogdanm 0:9b334a45a8ff 3737 #define OSC_CR_SC4P_MASK 0x4u
bogdanm 0:9b334a45a8ff 3738 #define OSC_CR_SC4P_SHIFT 2
bogdanm 0:9b334a45a8ff 3739 #define OSC_CR_SC2P_MASK 0x8u
bogdanm 0:9b334a45a8ff 3740 #define OSC_CR_SC2P_SHIFT 3
bogdanm 0:9b334a45a8ff 3741 #define OSC_CR_EREFSTEN_MASK 0x20u
bogdanm 0:9b334a45a8ff 3742 #define OSC_CR_EREFSTEN_SHIFT 5
bogdanm 0:9b334a45a8ff 3743 #define OSC_CR_ERCLKEN_MASK 0x80u
bogdanm 0:9b334a45a8ff 3744 #define OSC_CR_ERCLKEN_SHIFT 7
bogdanm 0:9b334a45a8ff 3745
bogdanm 0:9b334a45a8ff 3746 /*!
bogdanm 0:9b334a45a8ff 3747 * @}
bogdanm 0:9b334a45a8ff 3748 */ /* end of group OSC_Register_Masks */
bogdanm 0:9b334a45a8ff 3749
bogdanm 0:9b334a45a8ff 3750
bogdanm 0:9b334a45a8ff 3751 /* OSC - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 3752 /** Peripheral OSC0 base address */
bogdanm 0:9b334a45a8ff 3753 #define OSC0_BASE (0x40065000u)
bogdanm 0:9b334a45a8ff 3754 /** Peripheral OSC0 base pointer */
bogdanm 0:9b334a45a8ff 3755 #define OSC0 ((OSC_Type *)OSC0_BASE)
bogdanm 0:9b334a45a8ff 3756 /** Array initializer of OSC peripheral base pointers */
bogdanm 0:9b334a45a8ff 3757 #define OSC_BASES { OSC0 }
bogdanm 0:9b334a45a8ff 3758
bogdanm 0:9b334a45a8ff 3759 /*!
bogdanm 0:9b334a45a8ff 3760 * @}
bogdanm 0:9b334a45a8ff 3761 */ /* end of group OSC_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 3762
bogdanm 0:9b334a45a8ff 3763
bogdanm 0:9b334a45a8ff 3764 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 3765 -- PIT Peripheral Access Layer
bogdanm 0:9b334a45a8ff 3766 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 3767
bogdanm 0:9b334a45a8ff 3768 /*!
bogdanm 0:9b334a45a8ff 3769 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
bogdanm 0:9b334a45a8ff 3770 * @{
bogdanm 0:9b334a45a8ff 3771 */
bogdanm 0:9b334a45a8ff 3772
bogdanm 0:9b334a45a8ff 3773 /** PIT - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 3774 typedef struct {
bogdanm 0:9b334a45a8ff 3775 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
bogdanm 0:9b334a45a8ff 3776 uint8_t RESERVED_0[220];
bogdanm 0:9b334a45a8ff 3777 __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
bogdanm 0:9b334a45a8ff 3778 __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
bogdanm 0:9b334a45a8ff 3779 uint8_t RESERVED_1[24];
bogdanm 0:9b334a45a8ff 3780 struct { /* offset: 0x100, array step: 0x10 */
bogdanm 0:9b334a45a8ff 3781 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
bogdanm 0:9b334a45a8ff 3782 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
bogdanm 0:9b334a45a8ff 3783 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
bogdanm 0:9b334a45a8ff 3784 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
bogdanm 0:9b334a45a8ff 3785 } CHANNEL[2];
bogdanm 0:9b334a45a8ff 3786 } PIT_Type;
bogdanm 0:9b334a45a8ff 3787
bogdanm 0:9b334a45a8ff 3788 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 3789 -- PIT Register Masks
bogdanm 0:9b334a45a8ff 3790 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 3791
bogdanm 0:9b334a45a8ff 3792 /*!
bogdanm 0:9b334a45a8ff 3793 * @addtogroup PIT_Register_Masks PIT Register Masks
bogdanm 0:9b334a45a8ff 3794 * @{
bogdanm 0:9b334a45a8ff 3795 */
bogdanm 0:9b334a45a8ff 3796
bogdanm 0:9b334a45a8ff 3797 /* MCR Bit Fields */
bogdanm 0:9b334a45a8ff 3798 #define PIT_MCR_FRZ_MASK 0x1u
bogdanm 0:9b334a45a8ff 3799 #define PIT_MCR_FRZ_SHIFT 0
bogdanm 0:9b334a45a8ff 3800 #define PIT_MCR_MDIS_MASK 0x2u
bogdanm 0:9b334a45a8ff 3801 #define PIT_MCR_MDIS_SHIFT 1
bogdanm 0:9b334a45a8ff 3802 /* LTMR64H Bit Fields */
bogdanm 0:9b334a45a8ff 3803 #define PIT_LTMR64H_LTH_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 3804 #define PIT_LTMR64H_LTH_SHIFT 0
bogdanm 0:9b334a45a8ff 3805 #define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64H_LTH_SHIFT))&PIT_LTMR64H_LTH_MASK)
bogdanm 0:9b334a45a8ff 3806 /* LTMR64L Bit Fields */
bogdanm 0:9b334a45a8ff 3807 #define PIT_LTMR64L_LTL_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 3808 #define PIT_LTMR64L_LTL_SHIFT 0
bogdanm 0:9b334a45a8ff 3809 #define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64L_LTL_SHIFT))&PIT_LTMR64L_LTL_MASK)
bogdanm 0:9b334a45a8ff 3810 /* LDVAL Bit Fields */
bogdanm 0:9b334a45a8ff 3811 #define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 3812 #define PIT_LDVAL_TSV_SHIFT 0
bogdanm 0:9b334a45a8ff 3813 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
bogdanm 0:9b334a45a8ff 3814 /* CVAL Bit Fields */
bogdanm 0:9b334a45a8ff 3815 #define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 3816 #define PIT_CVAL_TVL_SHIFT 0
bogdanm 0:9b334a45a8ff 3817 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
bogdanm 0:9b334a45a8ff 3818 /* TCTRL Bit Fields */
bogdanm 0:9b334a45a8ff 3819 #define PIT_TCTRL_TEN_MASK 0x1u
bogdanm 0:9b334a45a8ff 3820 #define PIT_TCTRL_TEN_SHIFT 0
bogdanm 0:9b334a45a8ff 3821 #define PIT_TCTRL_TIE_MASK 0x2u
bogdanm 0:9b334a45a8ff 3822 #define PIT_TCTRL_TIE_SHIFT 1
bogdanm 0:9b334a45a8ff 3823 #define PIT_TCTRL_CHN_MASK 0x4u
bogdanm 0:9b334a45a8ff 3824 #define PIT_TCTRL_CHN_SHIFT 2
bogdanm 0:9b334a45a8ff 3825 /* TFLG Bit Fields */
bogdanm 0:9b334a45a8ff 3826 #define PIT_TFLG_TIF_MASK 0x1u
bogdanm 0:9b334a45a8ff 3827 #define PIT_TFLG_TIF_SHIFT 0
bogdanm 0:9b334a45a8ff 3828
bogdanm 0:9b334a45a8ff 3829 /*!
bogdanm 0:9b334a45a8ff 3830 * @}
bogdanm 0:9b334a45a8ff 3831 */ /* end of group PIT_Register_Masks */
bogdanm 0:9b334a45a8ff 3832
bogdanm 0:9b334a45a8ff 3833
bogdanm 0:9b334a45a8ff 3834 /* PIT - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 3835 /** Peripheral PIT base address */
bogdanm 0:9b334a45a8ff 3836 #define PIT_BASE (0x40037000u)
bogdanm 0:9b334a45a8ff 3837 /** Peripheral PIT base pointer */
bogdanm 0:9b334a45a8ff 3838 #define PIT ((PIT_Type *)PIT_BASE)
bogdanm 0:9b334a45a8ff 3839 /** Array initializer of PIT peripheral base pointers */
bogdanm 0:9b334a45a8ff 3840 #define PIT_BASES { PIT }
bogdanm 0:9b334a45a8ff 3841
bogdanm 0:9b334a45a8ff 3842 /*!
bogdanm 0:9b334a45a8ff 3843 * @}
bogdanm 0:9b334a45a8ff 3844 */ /* end of group PIT_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 3845
bogdanm 0:9b334a45a8ff 3846
bogdanm 0:9b334a45a8ff 3847 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 3848 -- PMC Peripheral Access Layer
bogdanm 0:9b334a45a8ff 3849 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 3850
bogdanm 0:9b334a45a8ff 3851 /*!
bogdanm 0:9b334a45a8ff 3852 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
bogdanm 0:9b334a45a8ff 3853 * @{
bogdanm 0:9b334a45a8ff 3854 */
bogdanm 0:9b334a45a8ff 3855
bogdanm 0:9b334a45a8ff 3856 /** PMC - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 3857 typedef struct {
bogdanm 0:9b334a45a8ff 3858 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
bogdanm 0:9b334a45a8ff 3859 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
bogdanm 0:9b334a45a8ff 3860 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
bogdanm 0:9b334a45a8ff 3861 } PMC_Type;
bogdanm 0:9b334a45a8ff 3862
bogdanm 0:9b334a45a8ff 3863 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 3864 -- PMC Register Masks
bogdanm 0:9b334a45a8ff 3865 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 3866
bogdanm 0:9b334a45a8ff 3867 /*!
bogdanm 0:9b334a45a8ff 3868 * @addtogroup PMC_Register_Masks PMC Register Masks
bogdanm 0:9b334a45a8ff 3869 * @{
bogdanm 0:9b334a45a8ff 3870 */
bogdanm 0:9b334a45a8ff 3871
bogdanm 0:9b334a45a8ff 3872 /* LVDSC1 Bit Fields */
bogdanm 0:9b334a45a8ff 3873 #define PMC_LVDSC1_LVDV_MASK 0x3u
bogdanm 0:9b334a45a8ff 3874 #define PMC_LVDSC1_LVDV_SHIFT 0
bogdanm 0:9b334a45a8ff 3875 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
bogdanm 0:9b334a45a8ff 3876 #define PMC_LVDSC1_LVDRE_MASK 0x10u
bogdanm 0:9b334a45a8ff 3877 #define PMC_LVDSC1_LVDRE_SHIFT 4
bogdanm 0:9b334a45a8ff 3878 #define PMC_LVDSC1_LVDIE_MASK 0x20u
bogdanm 0:9b334a45a8ff 3879 #define PMC_LVDSC1_LVDIE_SHIFT 5
bogdanm 0:9b334a45a8ff 3880 #define PMC_LVDSC1_LVDACK_MASK 0x40u
bogdanm 0:9b334a45a8ff 3881 #define PMC_LVDSC1_LVDACK_SHIFT 6
bogdanm 0:9b334a45a8ff 3882 #define PMC_LVDSC1_LVDF_MASK 0x80u
bogdanm 0:9b334a45a8ff 3883 #define PMC_LVDSC1_LVDF_SHIFT 7
bogdanm 0:9b334a45a8ff 3884 /* LVDSC2 Bit Fields */
bogdanm 0:9b334a45a8ff 3885 #define PMC_LVDSC2_LVWV_MASK 0x3u
bogdanm 0:9b334a45a8ff 3886 #define PMC_LVDSC2_LVWV_SHIFT 0
bogdanm 0:9b334a45a8ff 3887 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
bogdanm 0:9b334a45a8ff 3888 #define PMC_LVDSC2_LVWIE_MASK 0x20u
bogdanm 0:9b334a45a8ff 3889 #define PMC_LVDSC2_LVWIE_SHIFT 5
bogdanm 0:9b334a45a8ff 3890 #define PMC_LVDSC2_LVWACK_MASK 0x40u
bogdanm 0:9b334a45a8ff 3891 #define PMC_LVDSC2_LVWACK_SHIFT 6
bogdanm 0:9b334a45a8ff 3892 #define PMC_LVDSC2_LVWF_MASK 0x80u
bogdanm 0:9b334a45a8ff 3893 #define PMC_LVDSC2_LVWF_SHIFT 7
bogdanm 0:9b334a45a8ff 3894 /* REGSC Bit Fields */
bogdanm 0:9b334a45a8ff 3895 #define PMC_REGSC_BGBE_MASK 0x1u
bogdanm 0:9b334a45a8ff 3896 #define PMC_REGSC_BGBE_SHIFT 0
bogdanm 0:9b334a45a8ff 3897 #define PMC_REGSC_REGONS_MASK 0x4u
bogdanm 0:9b334a45a8ff 3898 #define PMC_REGSC_REGONS_SHIFT 2
bogdanm 0:9b334a45a8ff 3899 #define PMC_REGSC_ACKISO_MASK 0x8u
bogdanm 0:9b334a45a8ff 3900 #define PMC_REGSC_ACKISO_SHIFT 3
bogdanm 0:9b334a45a8ff 3901 #define PMC_REGSC_BGEN_MASK 0x10u
bogdanm 0:9b334a45a8ff 3902 #define PMC_REGSC_BGEN_SHIFT 4
bogdanm 0:9b334a45a8ff 3903
bogdanm 0:9b334a45a8ff 3904 /*!
bogdanm 0:9b334a45a8ff 3905 * @}
bogdanm 0:9b334a45a8ff 3906 */ /* end of group PMC_Register_Masks */
bogdanm 0:9b334a45a8ff 3907
bogdanm 0:9b334a45a8ff 3908
bogdanm 0:9b334a45a8ff 3909 /* PMC - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 3910 /** Peripheral PMC base address */
bogdanm 0:9b334a45a8ff 3911 #define PMC_BASE (0x4007D000u)
bogdanm 0:9b334a45a8ff 3912 /** Peripheral PMC base pointer */
bogdanm 0:9b334a45a8ff 3913 #define PMC ((PMC_Type *)PMC_BASE)
bogdanm 0:9b334a45a8ff 3914 /** Array initializer of PMC peripheral base pointers */
bogdanm 0:9b334a45a8ff 3915 #define PMC_BASES { PMC }
bogdanm 0:9b334a45a8ff 3916
bogdanm 0:9b334a45a8ff 3917 /*!
bogdanm 0:9b334a45a8ff 3918 * @}
bogdanm 0:9b334a45a8ff 3919 */ /* end of group PMC_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 3920
bogdanm 0:9b334a45a8ff 3921
bogdanm 0:9b334a45a8ff 3922 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 3923 -- PORT Peripheral Access Layer
bogdanm 0:9b334a45a8ff 3924 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 3925
bogdanm 0:9b334a45a8ff 3926 /*!
bogdanm 0:9b334a45a8ff 3927 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
bogdanm 0:9b334a45a8ff 3928 * @{
bogdanm 0:9b334a45a8ff 3929 */
bogdanm 0:9b334a45a8ff 3930
bogdanm 0:9b334a45a8ff 3931 /** PORT - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 3932 typedef struct {
bogdanm 0:9b334a45a8ff 3933 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
bogdanm 0:9b334a45a8ff 3934 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
bogdanm 0:9b334a45a8ff 3935 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
bogdanm 0:9b334a45a8ff 3936 uint8_t RESERVED_0[24];
bogdanm 0:9b334a45a8ff 3937 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
bogdanm 0:9b334a45a8ff 3938 } PORT_Type;
bogdanm 0:9b334a45a8ff 3939
bogdanm 0:9b334a45a8ff 3940 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 3941 -- PORT Register Masks
bogdanm 0:9b334a45a8ff 3942 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 3943
bogdanm 0:9b334a45a8ff 3944 /*!
bogdanm 0:9b334a45a8ff 3945 * @addtogroup PORT_Register_Masks PORT Register Masks
bogdanm 0:9b334a45a8ff 3946 * @{
bogdanm 0:9b334a45a8ff 3947 */
bogdanm 0:9b334a45a8ff 3948
bogdanm 0:9b334a45a8ff 3949 /* PCR Bit Fields */
bogdanm 0:9b334a45a8ff 3950 #define PORT_PCR_PS_MASK 0x1u
bogdanm 0:9b334a45a8ff 3951 #define PORT_PCR_PS_SHIFT 0
bogdanm 0:9b334a45a8ff 3952 #define PORT_PCR_PE_MASK 0x2u
bogdanm 0:9b334a45a8ff 3953 #define PORT_PCR_PE_SHIFT 1
bogdanm 0:9b334a45a8ff 3954 #define PORT_PCR_SRE_MASK 0x4u
bogdanm 0:9b334a45a8ff 3955 #define PORT_PCR_SRE_SHIFT 2
bogdanm 0:9b334a45a8ff 3956 #define PORT_PCR_PFE_MASK 0x10u
bogdanm 0:9b334a45a8ff 3957 #define PORT_PCR_PFE_SHIFT 4
bogdanm 0:9b334a45a8ff 3958 #define PORT_PCR_DSE_MASK 0x40u
bogdanm 0:9b334a45a8ff 3959 #define PORT_PCR_DSE_SHIFT 6
bogdanm 0:9b334a45a8ff 3960 #define PORT_PCR_MUX_MASK 0x700u
bogdanm 0:9b334a45a8ff 3961 #define PORT_PCR_MUX_SHIFT 8
bogdanm 0:9b334a45a8ff 3962 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
bogdanm 0:9b334a45a8ff 3963 #define PORT_PCR_IRQC_MASK 0xF0000u
bogdanm 0:9b334a45a8ff 3964 #define PORT_PCR_IRQC_SHIFT 16
bogdanm 0:9b334a45a8ff 3965 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
bogdanm 0:9b334a45a8ff 3966 #define PORT_PCR_ISF_MASK 0x1000000u
bogdanm 0:9b334a45a8ff 3967 #define PORT_PCR_ISF_SHIFT 24
bogdanm 0:9b334a45a8ff 3968 /* GPCLR Bit Fields */
bogdanm 0:9b334a45a8ff 3969 #define PORT_GPCLR_GPWD_MASK 0xFFFFu
bogdanm 0:9b334a45a8ff 3970 #define PORT_GPCLR_GPWD_SHIFT 0
bogdanm 0:9b334a45a8ff 3971 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
bogdanm 0:9b334a45a8ff 3972 #define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
bogdanm 0:9b334a45a8ff 3973 #define PORT_GPCLR_GPWE_SHIFT 16
bogdanm 0:9b334a45a8ff 3974 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
bogdanm 0:9b334a45a8ff 3975 /* GPCHR Bit Fields */
bogdanm 0:9b334a45a8ff 3976 #define PORT_GPCHR_GPWD_MASK 0xFFFFu
bogdanm 0:9b334a45a8ff 3977 #define PORT_GPCHR_GPWD_SHIFT 0
bogdanm 0:9b334a45a8ff 3978 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
bogdanm 0:9b334a45a8ff 3979 #define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
bogdanm 0:9b334a45a8ff 3980 #define PORT_GPCHR_GPWE_SHIFT 16
bogdanm 0:9b334a45a8ff 3981 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
bogdanm 0:9b334a45a8ff 3982 /* ISFR Bit Fields */
bogdanm 0:9b334a45a8ff 3983 #define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 3984 #define PORT_ISFR_ISF_SHIFT 0
bogdanm 0:9b334a45a8ff 3985 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
bogdanm 0:9b334a45a8ff 3986
bogdanm 0:9b334a45a8ff 3987 /*!
bogdanm 0:9b334a45a8ff 3988 * @}
bogdanm 0:9b334a45a8ff 3989 */ /* end of group PORT_Register_Masks */
bogdanm 0:9b334a45a8ff 3990
bogdanm 0:9b334a45a8ff 3991
bogdanm 0:9b334a45a8ff 3992 /* PORT - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 3993 /** Peripheral PORTA base address */
bogdanm 0:9b334a45a8ff 3994 #define PORTA_BASE (0x40049000u)
bogdanm 0:9b334a45a8ff 3995 /** Peripheral PORTA base pointer */
bogdanm 0:9b334a45a8ff 3996 #define PORTA ((PORT_Type *)PORTA_BASE)
bogdanm 0:9b334a45a8ff 3997 /** Peripheral PORTB base address */
bogdanm 0:9b334a45a8ff 3998 #define PORTB_BASE (0x4004A000u)
bogdanm 0:9b334a45a8ff 3999 /** Peripheral PORTB base pointer */
bogdanm 0:9b334a45a8ff 4000 #define PORTB ((PORT_Type *)PORTB_BASE)
bogdanm 0:9b334a45a8ff 4001 /** Peripheral PORTC base address */
bogdanm 0:9b334a45a8ff 4002 #define PORTC_BASE (0x4004B000u)
bogdanm 0:9b334a45a8ff 4003 /** Peripheral PORTC base pointer */
bogdanm 0:9b334a45a8ff 4004 #define PORTC ((PORT_Type *)PORTC_BASE)
bogdanm 0:9b334a45a8ff 4005 /** Peripheral PORTD base address */
bogdanm 0:9b334a45a8ff 4006 #define PORTD_BASE (0x4004C000u)
bogdanm 0:9b334a45a8ff 4007 /** Peripheral PORTD base pointer */
bogdanm 0:9b334a45a8ff 4008 #define PORTD ((PORT_Type *)PORTD_BASE)
bogdanm 0:9b334a45a8ff 4009 /** Peripheral PORTE base address */
bogdanm 0:9b334a45a8ff 4010 #define PORTE_BASE (0x4004D000u)
bogdanm 0:9b334a45a8ff 4011 /** Peripheral PORTE base pointer */
bogdanm 0:9b334a45a8ff 4012 #define PORTE ((PORT_Type *)PORTE_BASE)
bogdanm 0:9b334a45a8ff 4013 /** Array initializer of PORT peripheral base pointers */
bogdanm 0:9b334a45a8ff 4014 #define PORT_BASES { PORTA, PORTB, PORTC, PORTD, PORTE }
bogdanm 0:9b334a45a8ff 4015
bogdanm 0:9b334a45a8ff 4016 /*!
bogdanm 0:9b334a45a8ff 4017 * @}
bogdanm 0:9b334a45a8ff 4018 */ /* end of group PORT_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 4019
bogdanm 0:9b334a45a8ff 4020
bogdanm 0:9b334a45a8ff 4021 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 4022 -- RCM Peripheral Access Layer
bogdanm 0:9b334a45a8ff 4023 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 4024
bogdanm 0:9b334a45a8ff 4025 /*!
bogdanm 0:9b334a45a8ff 4026 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
bogdanm 0:9b334a45a8ff 4027 * @{
bogdanm 0:9b334a45a8ff 4028 */
bogdanm 0:9b334a45a8ff 4029
bogdanm 0:9b334a45a8ff 4030 /** RCM - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 4031 typedef struct {
bogdanm 0:9b334a45a8ff 4032 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
bogdanm 0:9b334a45a8ff 4033 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
bogdanm 0:9b334a45a8ff 4034 uint8_t RESERVED_0[2];
bogdanm 0:9b334a45a8ff 4035 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
bogdanm 0:9b334a45a8ff 4036 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
bogdanm 0:9b334a45a8ff 4037 } RCM_Type;
bogdanm 0:9b334a45a8ff 4038
bogdanm 0:9b334a45a8ff 4039 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 4040 -- RCM Register Masks
bogdanm 0:9b334a45a8ff 4041 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 4042
bogdanm 0:9b334a45a8ff 4043 /*!
bogdanm 0:9b334a45a8ff 4044 * @addtogroup RCM_Register_Masks RCM Register Masks
bogdanm 0:9b334a45a8ff 4045 * @{
bogdanm 0:9b334a45a8ff 4046 */
bogdanm 0:9b334a45a8ff 4047
bogdanm 0:9b334a45a8ff 4048 /* SRS0 Bit Fields */
bogdanm 0:9b334a45a8ff 4049 #define RCM_SRS0_WAKEUP_MASK 0x1u
bogdanm 0:9b334a45a8ff 4050 #define RCM_SRS0_WAKEUP_SHIFT 0
bogdanm 0:9b334a45a8ff 4051 #define RCM_SRS0_LVD_MASK 0x2u
bogdanm 0:9b334a45a8ff 4052 #define RCM_SRS0_LVD_SHIFT 1
bogdanm 0:9b334a45a8ff 4053 #define RCM_SRS0_LOC_MASK 0x4u
bogdanm 0:9b334a45a8ff 4054 #define RCM_SRS0_LOC_SHIFT 2
bogdanm 0:9b334a45a8ff 4055 #define RCM_SRS0_LOL_MASK 0x8u
bogdanm 0:9b334a45a8ff 4056 #define RCM_SRS0_LOL_SHIFT 3
bogdanm 0:9b334a45a8ff 4057 #define RCM_SRS0_WDOG_MASK 0x20u
bogdanm 0:9b334a45a8ff 4058 #define RCM_SRS0_WDOG_SHIFT 5
bogdanm 0:9b334a45a8ff 4059 #define RCM_SRS0_PIN_MASK 0x40u
bogdanm 0:9b334a45a8ff 4060 #define RCM_SRS0_PIN_SHIFT 6
bogdanm 0:9b334a45a8ff 4061 #define RCM_SRS0_POR_MASK 0x80u
bogdanm 0:9b334a45a8ff 4062 #define RCM_SRS0_POR_SHIFT 7
bogdanm 0:9b334a45a8ff 4063 /* SRS1 Bit Fields */
bogdanm 0:9b334a45a8ff 4064 #define RCM_SRS1_LOCKUP_MASK 0x2u
bogdanm 0:9b334a45a8ff 4065 #define RCM_SRS1_LOCKUP_SHIFT 1
bogdanm 0:9b334a45a8ff 4066 #define RCM_SRS1_SW_MASK 0x4u
bogdanm 0:9b334a45a8ff 4067 #define RCM_SRS1_SW_SHIFT 2
bogdanm 0:9b334a45a8ff 4068 #define RCM_SRS1_MDM_AP_MASK 0x8u
bogdanm 0:9b334a45a8ff 4069 #define RCM_SRS1_MDM_AP_SHIFT 3
bogdanm 0:9b334a45a8ff 4070 #define RCM_SRS1_SACKERR_MASK 0x20u
bogdanm 0:9b334a45a8ff 4071 #define RCM_SRS1_SACKERR_SHIFT 5
bogdanm 0:9b334a45a8ff 4072 /* RPFC Bit Fields */
bogdanm 0:9b334a45a8ff 4073 #define RCM_RPFC_RSTFLTSRW_MASK 0x3u
bogdanm 0:9b334a45a8ff 4074 #define RCM_RPFC_RSTFLTSRW_SHIFT 0
bogdanm 0:9b334a45a8ff 4075 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
bogdanm 0:9b334a45a8ff 4076 #define RCM_RPFC_RSTFLTSS_MASK 0x4u
bogdanm 0:9b334a45a8ff 4077 #define RCM_RPFC_RSTFLTSS_SHIFT 2
bogdanm 0:9b334a45a8ff 4078 /* RPFW Bit Fields */
bogdanm 0:9b334a45a8ff 4079 #define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
bogdanm 0:9b334a45a8ff 4080 #define RCM_RPFW_RSTFLTSEL_SHIFT 0
bogdanm 0:9b334a45a8ff 4081 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
bogdanm 0:9b334a45a8ff 4082
bogdanm 0:9b334a45a8ff 4083 /*!
bogdanm 0:9b334a45a8ff 4084 * @}
bogdanm 0:9b334a45a8ff 4085 */ /* end of group RCM_Register_Masks */
bogdanm 0:9b334a45a8ff 4086
bogdanm 0:9b334a45a8ff 4087
bogdanm 0:9b334a45a8ff 4088 /* RCM - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 4089 /** Peripheral RCM base address */
bogdanm 0:9b334a45a8ff 4090 #define RCM_BASE (0x4007F000u)
bogdanm 0:9b334a45a8ff 4091 /** Peripheral RCM base pointer */
bogdanm 0:9b334a45a8ff 4092 #define RCM ((RCM_Type *)RCM_BASE)
bogdanm 0:9b334a45a8ff 4093 /** Array initializer of RCM peripheral base pointers */
bogdanm 0:9b334a45a8ff 4094 #define RCM_BASES { RCM }
bogdanm 0:9b334a45a8ff 4095
bogdanm 0:9b334a45a8ff 4096 /*!
bogdanm 0:9b334a45a8ff 4097 * @}
bogdanm 0:9b334a45a8ff 4098 */ /* end of group RCM_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 4099
bogdanm 0:9b334a45a8ff 4100
bogdanm 0:9b334a45a8ff 4101 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 4102 -- ROM Peripheral Access Layer
bogdanm 0:9b334a45a8ff 4103 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 4104
bogdanm 0:9b334a45a8ff 4105 /*!
bogdanm 0:9b334a45a8ff 4106 * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
bogdanm 0:9b334a45a8ff 4107 * @{
bogdanm 0:9b334a45a8ff 4108 */
bogdanm 0:9b334a45a8ff 4109
bogdanm 0:9b334a45a8ff 4110 /** ROM - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 4111 typedef struct {
bogdanm 0:9b334a45a8ff 4112 __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */
bogdanm 0:9b334a45a8ff 4113 __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */
bogdanm 0:9b334a45a8ff 4114 uint8_t RESERVED_0[4028];
bogdanm 0:9b334a45a8ff 4115 __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */
bogdanm 0:9b334a45a8ff 4116 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
bogdanm 0:9b334a45a8ff 4117 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
bogdanm 0:9b334a45a8ff 4118 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
bogdanm 0:9b334a45a8ff 4119 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
bogdanm 0:9b334a45a8ff 4120 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
bogdanm 0:9b334a45a8ff 4121 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
bogdanm 0:9b334a45a8ff 4122 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
bogdanm 0:9b334a45a8ff 4123 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
bogdanm 0:9b334a45a8ff 4124 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
bogdanm 0:9b334a45a8ff 4125 } ROM_Type;
bogdanm 0:9b334a45a8ff 4126
bogdanm 0:9b334a45a8ff 4127 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 4128 -- ROM Register Masks
bogdanm 0:9b334a45a8ff 4129 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 4130
bogdanm 0:9b334a45a8ff 4131 /*!
bogdanm 0:9b334a45a8ff 4132 * @addtogroup ROM_Register_Masks ROM Register Masks
bogdanm 0:9b334a45a8ff 4133 * @{
bogdanm 0:9b334a45a8ff 4134 */
bogdanm 0:9b334a45a8ff 4135
bogdanm 0:9b334a45a8ff 4136 /* ENTRY Bit Fields */
bogdanm 0:9b334a45a8ff 4137 #define ROM_ENTRY_ENTRY_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 4138 #define ROM_ENTRY_ENTRY_SHIFT 0
bogdanm 0:9b334a45a8ff 4139 #define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x))<<ROM_ENTRY_ENTRY_SHIFT))&ROM_ENTRY_ENTRY_MASK)
bogdanm 0:9b334a45a8ff 4140 /* TABLEMARK Bit Fields */
bogdanm 0:9b334a45a8ff 4141 #define ROM_TABLEMARK_MARK_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 4142 #define ROM_TABLEMARK_MARK_SHIFT 0
bogdanm 0:9b334a45a8ff 4143 #define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x))<<ROM_TABLEMARK_MARK_SHIFT))&ROM_TABLEMARK_MARK_MASK)
bogdanm 0:9b334a45a8ff 4144 /* SYSACCESS Bit Fields */
bogdanm 0:9b334a45a8ff 4145 #define ROM_SYSACCESS_SYSACCESS_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 4146 #define ROM_SYSACCESS_SYSACCESS_SHIFT 0
bogdanm 0:9b334a45a8ff 4147 #define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x))<<ROM_SYSACCESS_SYSACCESS_SHIFT))&ROM_SYSACCESS_SYSACCESS_MASK)
bogdanm 0:9b334a45a8ff 4148 /* PERIPHID4 Bit Fields */
bogdanm 0:9b334a45a8ff 4149 #define ROM_PERIPHID4_PERIPHID_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 4150 #define ROM_PERIPHID4_PERIPHID_SHIFT 0
bogdanm 0:9b334a45a8ff 4151 #define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID4_PERIPHID_SHIFT))&ROM_PERIPHID4_PERIPHID_MASK)
bogdanm 0:9b334a45a8ff 4152 /* PERIPHID5 Bit Fields */
bogdanm 0:9b334a45a8ff 4153 #define ROM_PERIPHID5_PERIPHID_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 4154 #define ROM_PERIPHID5_PERIPHID_SHIFT 0
bogdanm 0:9b334a45a8ff 4155 #define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID5_PERIPHID_SHIFT))&ROM_PERIPHID5_PERIPHID_MASK)
bogdanm 0:9b334a45a8ff 4156 /* PERIPHID6 Bit Fields */
bogdanm 0:9b334a45a8ff 4157 #define ROM_PERIPHID6_PERIPHID_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 4158 #define ROM_PERIPHID6_PERIPHID_SHIFT 0
bogdanm 0:9b334a45a8ff 4159 #define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID6_PERIPHID_SHIFT))&ROM_PERIPHID6_PERIPHID_MASK)
bogdanm 0:9b334a45a8ff 4160 /* PERIPHID7 Bit Fields */
bogdanm 0:9b334a45a8ff 4161 #define ROM_PERIPHID7_PERIPHID_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 4162 #define ROM_PERIPHID7_PERIPHID_SHIFT 0
bogdanm 0:9b334a45a8ff 4163 #define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID7_PERIPHID_SHIFT))&ROM_PERIPHID7_PERIPHID_MASK)
bogdanm 0:9b334a45a8ff 4164 /* PERIPHID0 Bit Fields */
bogdanm 0:9b334a45a8ff 4165 #define ROM_PERIPHID0_PERIPHID_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 4166 #define ROM_PERIPHID0_PERIPHID_SHIFT 0
bogdanm 0:9b334a45a8ff 4167 #define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID0_PERIPHID_SHIFT))&ROM_PERIPHID0_PERIPHID_MASK)
bogdanm 0:9b334a45a8ff 4168 /* PERIPHID1 Bit Fields */
bogdanm 0:9b334a45a8ff 4169 #define ROM_PERIPHID1_PERIPHID_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 4170 #define ROM_PERIPHID1_PERIPHID_SHIFT 0
bogdanm 0:9b334a45a8ff 4171 #define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID1_PERIPHID_SHIFT))&ROM_PERIPHID1_PERIPHID_MASK)
bogdanm 0:9b334a45a8ff 4172 /* PERIPHID2 Bit Fields */
bogdanm 0:9b334a45a8ff 4173 #define ROM_PERIPHID2_PERIPHID_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 4174 #define ROM_PERIPHID2_PERIPHID_SHIFT 0
bogdanm 0:9b334a45a8ff 4175 #define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID2_PERIPHID_SHIFT))&ROM_PERIPHID2_PERIPHID_MASK)
bogdanm 0:9b334a45a8ff 4176 /* PERIPHID3 Bit Fields */
bogdanm 0:9b334a45a8ff 4177 #define ROM_PERIPHID3_PERIPHID_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 4178 #define ROM_PERIPHID3_PERIPHID_SHIFT 0
bogdanm 0:9b334a45a8ff 4179 #define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID3_PERIPHID_SHIFT))&ROM_PERIPHID3_PERIPHID_MASK)
bogdanm 0:9b334a45a8ff 4180 /* COMPID Bit Fields */
bogdanm 0:9b334a45a8ff 4181 #define ROM_COMPID_COMPID_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 4182 #define ROM_COMPID_COMPID_SHIFT 0
bogdanm 0:9b334a45a8ff 4183 #define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<ROM_COMPID_COMPID_SHIFT))&ROM_COMPID_COMPID_MASK)
bogdanm 0:9b334a45a8ff 4184
bogdanm 0:9b334a45a8ff 4185 /*!
bogdanm 0:9b334a45a8ff 4186 * @}
bogdanm 0:9b334a45a8ff 4187 */ /* end of group ROM_Register_Masks */
bogdanm 0:9b334a45a8ff 4188
bogdanm 0:9b334a45a8ff 4189
bogdanm 0:9b334a45a8ff 4190 /* ROM - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 4191 /** Peripheral ROM base address */
bogdanm 0:9b334a45a8ff 4192 #define ROM_BASE (0xF0002000u)
bogdanm 0:9b334a45a8ff 4193 /** Peripheral ROM base pointer */
bogdanm 0:9b334a45a8ff 4194 #define ROM ((ROM_Type *)ROM_BASE)
bogdanm 0:9b334a45a8ff 4195 /** Array initializer of ROM peripheral base pointers */
bogdanm 0:9b334a45a8ff 4196 #define ROM_BASES { ROM }
bogdanm 0:9b334a45a8ff 4197
bogdanm 0:9b334a45a8ff 4198 /*!
bogdanm 0:9b334a45a8ff 4199 * @}
bogdanm 0:9b334a45a8ff 4200 */ /* end of group ROM_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 4201
bogdanm 0:9b334a45a8ff 4202
bogdanm 0:9b334a45a8ff 4203 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 4204 -- RTC Peripheral Access Layer
bogdanm 0:9b334a45a8ff 4205 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 4206
bogdanm 0:9b334a45a8ff 4207 /*!
bogdanm 0:9b334a45a8ff 4208 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
bogdanm 0:9b334a45a8ff 4209 * @{
bogdanm 0:9b334a45a8ff 4210 */
bogdanm 0:9b334a45a8ff 4211
bogdanm 0:9b334a45a8ff 4212 /** RTC - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 4213 typedef struct {
bogdanm 0:9b334a45a8ff 4214 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
bogdanm 0:9b334a45a8ff 4215 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
bogdanm 0:9b334a45a8ff 4216 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
bogdanm 0:9b334a45a8ff 4217 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
bogdanm 0:9b334a45a8ff 4218 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
bogdanm 0:9b334a45a8ff 4219 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
bogdanm 0:9b334a45a8ff 4220 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
bogdanm 0:9b334a45a8ff 4221 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
bogdanm 0:9b334a45a8ff 4222 } RTC_Type;
bogdanm 0:9b334a45a8ff 4223
bogdanm 0:9b334a45a8ff 4224 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 4225 -- RTC Register Masks
bogdanm 0:9b334a45a8ff 4226 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 4227
bogdanm 0:9b334a45a8ff 4228 /*!
bogdanm 0:9b334a45a8ff 4229 * @addtogroup RTC_Register_Masks RTC Register Masks
bogdanm 0:9b334a45a8ff 4230 * @{
bogdanm 0:9b334a45a8ff 4231 */
bogdanm 0:9b334a45a8ff 4232
bogdanm 0:9b334a45a8ff 4233 /* TSR Bit Fields */
bogdanm 0:9b334a45a8ff 4234 #define RTC_TSR_TSR_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 4235 #define RTC_TSR_TSR_SHIFT 0
bogdanm 0:9b334a45a8ff 4236 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
bogdanm 0:9b334a45a8ff 4237 /* TPR Bit Fields */
bogdanm 0:9b334a45a8ff 4238 #define RTC_TPR_TPR_MASK 0xFFFFu
bogdanm 0:9b334a45a8ff 4239 #define RTC_TPR_TPR_SHIFT 0
bogdanm 0:9b334a45a8ff 4240 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
bogdanm 0:9b334a45a8ff 4241 /* TAR Bit Fields */
bogdanm 0:9b334a45a8ff 4242 #define RTC_TAR_TAR_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 4243 #define RTC_TAR_TAR_SHIFT 0
bogdanm 0:9b334a45a8ff 4244 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
bogdanm 0:9b334a45a8ff 4245 /* TCR Bit Fields */
bogdanm 0:9b334a45a8ff 4246 #define RTC_TCR_TCR_MASK 0xFFu
bogdanm 0:9b334a45a8ff 4247 #define RTC_TCR_TCR_SHIFT 0
bogdanm 0:9b334a45a8ff 4248 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
bogdanm 0:9b334a45a8ff 4249 #define RTC_TCR_CIR_MASK 0xFF00u
bogdanm 0:9b334a45a8ff 4250 #define RTC_TCR_CIR_SHIFT 8
bogdanm 0:9b334a45a8ff 4251 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
bogdanm 0:9b334a45a8ff 4252 #define RTC_TCR_TCV_MASK 0xFF0000u
bogdanm 0:9b334a45a8ff 4253 #define RTC_TCR_TCV_SHIFT 16
bogdanm 0:9b334a45a8ff 4254 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
bogdanm 0:9b334a45a8ff 4255 #define RTC_TCR_CIC_MASK 0xFF000000u
bogdanm 0:9b334a45a8ff 4256 #define RTC_TCR_CIC_SHIFT 24
bogdanm 0:9b334a45a8ff 4257 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
bogdanm 0:9b334a45a8ff 4258 /* CR Bit Fields */
bogdanm 0:9b334a45a8ff 4259 #define RTC_CR_SWR_MASK 0x1u
bogdanm 0:9b334a45a8ff 4260 #define RTC_CR_SWR_SHIFT 0
bogdanm 0:9b334a45a8ff 4261 #define RTC_CR_WPE_MASK 0x2u
bogdanm 0:9b334a45a8ff 4262 #define RTC_CR_WPE_SHIFT 1
bogdanm 0:9b334a45a8ff 4263 #define RTC_CR_SUP_MASK 0x4u
bogdanm 0:9b334a45a8ff 4264 #define RTC_CR_SUP_SHIFT 2
bogdanm 0:9b334a45a8ff 4265 #define RTC_CR_UM_MASK 0x8u
bogdanm 0:9b334a45a8ff 4266 #define RTC_CR_UM_SHIFT 3
bogdanm 0:9b334a45a8ff 4267 #define RTC_CR_OSCE_MASK 0x100u
bogdanm 0:9b334a45a8ff 4268 #define RTC_CR_OSCE_SHIFT 8
bogdanm 0:9b334a45a8ff 4269 #define RTC_CR_CLKO_MASK 0x200u
bogdanm 0:9b334a45a8ff 4270 #define RTC_CR_CLKO_SHIFT 9
bogdanm 0:9b334a45a8ff 4271 #define RTC_CR_SC16P_MASK 0x400u
bogdanm 0:9b334a45a8ff 4272 #define RTC_CR_SC16P_SHIFT 10
bogdanm 0:9b334a45a8ff 4273 #define RTC_CR_SC8P_MASK 0x800u
bogdanm 0:9b334a45a8ff 4274 #define RTC_CR_SC8P_SHIFT 11
bogdanm 0:9b334a45a8ff 4275 #define RTC_CR_SC4P_MASK 0x1000u
bogdanm 0:9b334a45a8ff 4276 #define RTC_CR_SC4P_SHIFT 12
bogdanm 0:9b334a45a8ff 4277 #define RTC_CR_SC2P_MASK 0x2000u
bogdanm 0:9b334a45a8ff 4278 #define RTC_CR_SC2P_SHIFT 13
bogdanm 0:9b334a45a8ff 4279 /* SR Bit Fields */
bogdanm 0:9b334a45a8ff 4280 #define RTC_SR_TIF_MASK 0x1u
bogdanm 0:9b334a45a8ff 4281 #define RTC_SR_TIF_SHIFT 0
bogdanm 0:9b334a45a8ff 4282 #define RTC_SR_TOF_MASK 0x2u
bogdanm 0:9b334a45a8ff 4283 #define RTC_SR_TOF_SHIFT 1
bogdanm 0:9b334a45a8ff 4284 #define RTC_SR_TAF_MASK 0x4u
bogdanm 0:9b334a45a8ff 4285 #define RTC_SR_TAF_SHIFT 2
bogdanm 0:9b334a45a8ff 4286 #define RTC_SR_TCE_MASK 0x10u
bogdanm 0:9b334a45a8ff 4287 #define RTC_SR_TCE_SHIFT 4
bogdanm 0:9b334a45a8ff 4288 /* LR Bit Fields */
bogdanm 0:9b334a45a8ff 4289 #define RTC_LR_TCL_MASK 0x8u
bogdanm 0:9b334a45a8ff 4290 #define RTC_LR_TCL_SHIFT 3
bogdanm 0:9b334a45a8ff 4291 #define RTC_LR_CRL_MASK 0x10u
bogdanm 0:9b334a45a8ff 4292 #define RTC_LR_CRL_SHIFT 4
bogdanm 0:9b334a45a8ff 4293 #define RTC_LR_SRL_MASK 0x20u
bogdanm 0:9b334a45a8ff 4294 #define RTC_LR_SRL_SHIFT 5
bogdanm 0:9b334a45a8ff 4295 #define RTC_LR_LRL_MASK 0x40u
bogdanm 0:9b334a45a8ff 4296 #define RTC_LR_LRL_SHIFT 6
bogdanm 0:9b334a45a8ff 4297 /* IER Bit Fields */
bogdanm 0:9b334a45a8ff 4298 #define RTC_IER_TIIE_MASK 0x1u
bogdanm 0:9b334a45a8ff 4299 #define RTC_IER_TIIE_SHIFT 0
bogdanm 0:9b334a45a8ff 4300 #define RTC_IER_TOIE_MASK 0x2u
bogdanm 0:9b334a45a8ff 4301 #define RTC_IER_TOIE_SHIFT 1
bogdanm 0:9b334a45a8ff 4302 #define RTC_IER_TAIE_MASK 0x4u
bogdanm 0:9b334a45a8ff 4303 #define RTC_IER_TAIE_SHIFT 2
bogdanm 0:9b334a45a8ff 4304 #define RTC_IER_TSIE_MASK 0x10u
bogdanm 0:9b334a45a8ff 4305 #define RTC_IER_TSIE_SHIFT 4
bogdanm 0:9b334a45a8ff 4306 #define RTC_IER_WPON_MASK 0x80u
bogdanm 0:9b334a45a8ff 4307 #define RTC_IER_WPON_SHIFT 7
bogdanm 0:9b334a45a8ff 4308
bogdanm 0:9b334a45a8ff 4309 /*!
bogdanm 0:9b334a45a8ff 4310 * @}
bogdanm 0:9b334a45a8ff 4311 */ /* end of group RTC_Register_Masks */
bogdanm 0:9b334a45a8ff 4312
bogdanm 0:9b334a45a8ff 4313
bogdanm 0:9b334a45a8ff 4314 /* RTC - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 4315 /** Peripheral RTC base address */
bogdanm 0:9b334a45a8ff 4316 #define RTC_BASE (0x4003D000u)
bogdanm 0:9b334a45a8ff 4317 /** Peripheral RTC base pointer */
bogdanm 0:9b334a45a8ff 4318 #define RTC ((RTC_Type *)RTC_BASE)
bogdanm 0:9b334a45a8ff 4319 /** Array initializer of RTC peripheral base pointers */
bogdanm 0:9b334a45a8ff 4320 #define RTC_BASES { RTC }
bogdanm 0:9b334a45a8ff 4321
bogdanm 0:9b334a45a8ff 4322 /*!
bogdanm 0:9b334a45a8ff 4323 * @}
bogdanm 0:9b334a45a8ff 4324 */ /* end of group RTC_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 4325
bogdanm 0:9b334a45a8ff 4326
bogdanm 0:9b334a45a8ff 4327 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 4328 -- SIM Peripheral Access Layer
bogdanm 0:9b334a45a8ff 4329 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 4330
bogdanm 0:9b334a45a8ff 4331 /*!
bogdanm 0:9b334a45a8ff 4332 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
bogdanm 0:9b334a45a8ff 4333 * @{
bogdanm 0:9b334a45a8ff 4334 */
bogdanm 0:9b334a45a8ff 4335
bogdanm 0:9b334a45a8ff 4336 /** SIM - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 4337 typedef struct {
bogdanm 0:9b334a45a8ff 4338 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
bogdanm 0:9b334a45a8ff 4339 __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
bogdanm 0:9b334a45a8ff 4340 uint8_t RESERVED_0[4092];
bogdanm 0:9b334a45a8ff 4341 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
bogdanm 0:9b334a45a8ff 4342 uint8_t RESERVED_1[4];
bogdanm 0:9b334a45a8ff 4343 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
bogdanm 0:9b334a45a8ff 4344 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
bogdanm 0:9b334a45a8ff 4345 uint8_t RESERVED_2[4];
bogdanm 0:9b334a45a8ff 4346 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
bogdanm 0:9b334a45a8ff 4347 uint8_t RESERVED_3[8];
bogdanm 0:9b334a45a8ff 4348 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
bogdanm 0:9b334a45a8ff 4349 uint8_t RESERVED_4[12];
bogdanm 0:9b334a45a8ff 4350 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
bogdanm 0:9b334a45a8ff 4351 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
bogdanm 0:9b334a45a8ff 4352 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
bogdanm 0:9b334a45a8ff 4353 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
bogdanm 0:9b334a45a8ff 4354 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
bogdanm 0:9b334a45a8ff 4355 uint8_t RESERVED_5[4];
bogdanm 0:9b334a45a8ff 4356 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
bogdanm 0:9b334a45a8ff 4357 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
bogdanm 0:9b334a45a8ff 4358 uint8_t RESERVED_6[4];
bogdanm 0:9b334a45a8ff 4359 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
bogdanm 0:9b334a45a8ff 4360 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
bogdanm 0:9b334a45a8ff 4361 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
bogdanm 0:9b334a45a8ff 4362 uint8_t RESERVED_7[156];
bogdanm 0:9b334a45a8ff 4363 __IO uint32_t COPC; /**< COP Control Register, offset: 0x1100 */
bogdanm 0:9b334a45a8ff 4364 __O uint32_t SRVCOP; /**< Service COP Register, offset: 0x1104 */
bogdanm 0:9b334a45a8ff 4365 } SIM_Type;
bogdanm 0:9b334a45a8ff 4366
bogdanm 0:9b334a45a8ff 4367 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 4368 -- SIM Register Masks
bogdanm 0:9b334a45a8ff 4369 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 4370
bogdanm 0:9b334a45a8ff 4371 /*!
bogdanm 0:9b334a45a8ff 4372 * @addtogroup SIM_Register_Masks SIM Register Masks
bogdanm 0:9b334a45a8ff 4373 * @{
bogdanm 0:9b334a45a8ff 4374 */
bogdanm 0:9b334a45a8ff 4375
bogdanm 0:9b334a45a8ff 4376 /* SOPT1 Bit Fields */
bogdanm 0:9b334a45a8ff 4377 #define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
bogdanm 0:9b334a45a8ff 4378 #define SIM_SOPT1_OSC32KSEL_SHIFT 18
bogdanm 0:9b334a45a8ff 4379 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
bogdanm 0:9b334a45a8ff 4380 #define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
bogdanm 0:9b334a45a8ff 4381 #define SIM_SOPT1_USBVSTBY_SHIFT 29
bogdanm 0:9b334a45a8ff 4382 #define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
bogdanm 0:9b334a45a8ff 4383 #define SIM_SOPT1_USBSSTBY_SHIFT 30
bogdanm 0:9b334a45a8ff 4384 #define SIM_SOPT1_USBREGEN_MASK 0x80000000u
bogdanm 0:9b334a45a8ff 4385 #define SIM_SOPT1_USBREGEN_SHIFT 31
bogdanm 0:9b334a45a8ff 4386 /* SOPT1CFG Bit Fields */
bogdanm 0:9b334a45a8ff 4387 #define SIM_SOPT1CFG_URWE_MASK 0x1000000u
bogdanm 0:9b334a45a8ff 4388 #define SIM_SOPT1CFG_URWE_SHIFT 24
bogdanm 0:9b334a45a8ff 4389 #define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
bogdanm 0:9b334a45a8ff 4390 #define SIM_SOPT1CFG_UVSWE_SHIFT 25
bogdanm 0:9b334a45a8ff 4391 #define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
bogdanm 0:9b334a45a8ff 4392 #define SIM_SOPT1CFG_USSWE_SHIFT 26
bogdanm 0:9b334a45a8ff 4393 /* SOPT2 Bit Fields */
bogdanm 0:9b334a45a8ff 4394 #define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
bogdanm 0:9b334a45a8ff 4395 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
bogdanm 0:9b334a45a8ff 4396 #define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
bogdanm 0:9b334a45a8ff 4397 #define SIM_SOPT2_CLKOUTSEL_SHIFT 5
bogdanm 0:9b334a45a8ff 4398 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
bogdanm 0:9b334a45a8ff 4399 #define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u
bogdanm 0:9b334a45a8ff 4400 #define SIM_SOPT2_PLLFLLSEL_SHIFT 16
bogdanm 0:9b334a45a8ff 4401 #define SIM_SOPT2_USBSRC_MASK 0x40000u
bogdanm 0:9b334a45a8ff 4402 #define SIM_SOPT2_USBSRC_SHIFT 18
bogdanm 0:9b334a45a8ff 4403 #define SIM_SOPT2_TPMSRC_MASK 0x3000000u
bogdanm 0:9b334a45a8ff 4404 #define SIM_SOPT2_TPMSRC_SHIFT 24
bogdanm 0:9b334a45a8ff 4405 #define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TPMSRC_SHIFT))&SIM_SOPT2_TPMSRC_MASK)
bogdanm 0:9b334a45a8ff 4406 #define SIM_SOPT2_UART0SRC_MASK 0xC000000u
bogdanm 0:9b334a45a8ff 4407 #define SIM_SOPT2_UART0SRC_SHIFT 26
bogdanm 0:9b334a45a8ff 4408 #define SIM_SOPT2_UART0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_UART0SRC_SHIFT))&SIM_SOPT2_UART0SRC_MASK)
bogdanm 0:9b334a45a8ff 4409 /* SOPT4 Bit Fields */
bogdanm 0:9b334a45a8ff 4410 #define SIM_SOPT4_TPM1CH0SRC_MASK 0xC0000u
bogdanm 0:9b334a45a8ff 4411 #define SIM_SOPT4_TPM1CH0SRC_SHIFT 18
bogdanm 0:9b334a45a8ff 4412 #define SIM_SOPT4_TPM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_TPM1CH0SRC_SHIFT))&SIM_SOPT4_TPM1CH0SRC_MASK)
bogdanm 0:9b334a45a8ff 4413 #define SIM_SOPT4_TPM2CH0SRC_MASK 0x100000u
bogdanm 0:9b334a45a8ff 4414 #define SIM_SOPT4_TPM2CH0SRC_SHIFT 20
bogdanm 0:9b334a45a8ff 4415 #define SIM_SOPT4_TPM0CLKSEL_MASK 0x1000000u
bogdanm 0:9b334a45a8ff 4416 #define SIM_SOPT4_TPM0CLKSEL_SHIFT 24
bogdanm 0:9b334a45a8ff 4417 #define SIM_SOPT4_TPM1CLKSEL_MASK 0x2000000u
bogdanm 0:9b334a45a8ff 4418 #define SIM_SOPT4_TPM1CLKSEL_SHIFT 25
bogdanm 0:9b334a45a8ff 4419 #define SIM_SOPT4_TPM2CLKSEL_MASK 0x4000000u
bogdanm 0:9b334a45a8ff 4420 #define SIM_SOPT4_TPM2CLKSEL_SHIFT 26
bogdanm 0:9b334a45a8ff 4421 /* SOPT5 Bit Fields */
bogdanm 0:9b334a45a8ff 4422 #define SIM_SOPT5_UART0TXSRC_MASK 0x3u
bogdanm 0:9b334a45a8ff 4423 #define SIM_SOPT5_UART0TXSRC_SHIFT 0
bogdanm 0:9b334a45a8ff 4424 #define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
bogdanm 0:9b334a45a8ff 4425 #define SIM_SOPT5_UART0RXSRC_MASK 0x4u
bogdanm 0:9b334a45a8ff 4426 #define SIM_SOPT5_UART0RXSRC_SHIFT 2
bogdanm 0:9b334a45a8ff 4427 #define SIM_SOPT5_UART1TXSRC_MASK 0x30u
bogdanm 0:9b334a45a8ff 4428 #define SIM_SOPT5_UART1TXSRC_SHIFT 4
bogdanm 0:9b334a45a8ff 4429 #define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
bogdanm 0:9b334a45a8ff 4430 #define SIM_SOPT5_UART1RXSRC_MASK 0x40u
bogdanm 0:9b334a45a8ff 4431 #define SIM_SOPT5_UART1RXSRC_SHIFT 6
bogdanm 0:9b334a45a8ff 4432 #define SIM_SOPT5_UART0ODE_MASK 0x10000u
bogdanm 0:9b334a45a8ff 4433 #define SIM_SOPT5_UART0ODE_SHIFT 16
bogdanm 0:9b334a45a8ff 4434 #define SIM_SOPT5_UART1ODE_MASK 0x20000u
bogdanm 0:9b334a45a8ff 4435 #define SIM_SOPT5_UART1ODE_SHIFT 17
bogdanm 0:9b334a45a8ff 4436 #define SIM_SOPT5_UART2ODE_MASK 0x40000u
bogdanm 0:9b334a45a8ff 4437 #define SIM_SOPT5_UART2ODE_SHIFT 18
bogdanm 0:9b334a45a8ff 4438 /* SOPT7 Bit Fields */
bogdanm 0:9b334a45a8ff 4439 #define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
bogdanm 0:9b334a45a8ff 4440 #define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
bogdanm 0:9b334a45a8ff 4441 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
bogdanm 0:9b334a45a8ff 4442 #define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
bogdanm 0:9b334a45a8ff 4443 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
bogdanm 0:9b334a45a8ff 4444 #define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
bogdanm 0:9b334a45a8ff 4445 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
bogdanm 0:9b334a45a8ff 4446 /* SDID Bit Fields */
bogdanm 0:9b334a45a8ff 4447 #define SIM_SDID_PINID_MASK 0xFu
bogdanm 0:9b334a45a8ff 4448 #define SIM_SDID_PINID_SHIFT 0
bogdanm 0:9b334a45a8ff 4449 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
bogdanm 0:9b334a45a8ff 4450 #define SIM_SDID_DIEID_MASK 0xF80u
bogdanm 0:9b334a45a8ff 4451 #define SIM_SDID_DIEID_SHIFT 7
bogdanm 0:9b334a45a8ff 4452 #define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
bogdanm 0:9b334a45a8ff 4453 #define SIM_SDID_REVID_MASK 0xF000u
bogdanm 0:9b334a45a8ff 4454 #define SIM_SDID_REVID_SHIFT 12
bogdanm 0:9b334a45a8ff 4455 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
bogdanm 0:9b334a45a8ff 4456 #define SIM_SDID_SRAMSIZE_MASK 0xF0000u
bogdanm 0:9b334a45a8ff 4457 #define SIM_SDID_SRAMSIZE_SHIFT 16
bogdanm 0:9b334a45a8ff 4458 #define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SRAMSIZE_SHIFT))&SIM_SDID_SRAMSIZE_MASK)
bogdanm 0:9b334a45a8ff 4459 #define SIM_SDID_SERIESID_MASK 0xF00000u
bogdanm 0:9b334a45a8ff 4460 #define SIM_SDID_SERIESID_SHIFT 20
bogdanm 0:9b334a45a8ff 4461 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
bogdanm 0:9b334a45a8ff 4462 #define SIM_SDID_SUBFAMID_MASK 0xF000000u
bogdanm 0:9b334a45a8ff 4463 #define SIM_SDID_SUBFAMID_SHIFT 24
bogdanm 0:9b334a45a8ff 4464 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
bogdanm 0:9b334a45a8ff 4465 #define SIM_SDID_FAMID_MASK 0xF0000000u
bogdanm 0:9b334a45a8ff 4466 #define SIM_SDID_FAMID_SHIFT 28
bogdanm 0:9b334a45a8ff 4467 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
bogdanm 0:9b334a45a8ff 4468 /* SCGC4 Bit Fields */
bogdanm 0:9b334a45a8ff 4469 #define SIM_SCGC4_I2C0_MASK 0x40u
bogdanm 0:9b334a45a8ff 4470 #define SIM_SCGC4_I2C0_SHIFT 6
bogdanm 0:9b334a45a8ff 4471 #define SIM_SCGC4_I2C1_MASK 0x80u
bogdanm 0:9b334a45a8ff 4472 #define SIM_SCGC4_I2C1_SHIFT 7
bogdanm 0:9b334a45a8ff 4473 #define SIM_SCGC4_UART0_MASK 0x400u
bogdanm 0:9b334a45a8ff 4474 #define SIM_SCGC4_UART0_SHIFT 10
bogdanm 0:9b334a45a8ff 4475 #define SIM_SCGC4_UART1_MASK 0x800u
bogdanm 0:9b334a45a8ff 4476 #define SIM_SCGC4_UART1_SHIFT 11
bogdanm 0:9b334a45a8ff 4477 #define SIM_SCGC4_UART2_MASK 0x1000u
bogdanm 0:9b334a45a8ff 4478 #define SIM_SCGC4_UART2_SHIFT 12
bogdanm 0:9b334a45a8ff 4479 #define SIM_SCGC4_USBOTG_MASK 0x40000u
bogdanm 0:9b334a45a8ff 4480 #define SIM_SCGC4_USBOTG_SHIFT 18
bogdanm 0:9b334a45a8ff 4481 #define SIM_SCGC4_CMP_MASK 0x80000u
bogdanm 0:9b334a45a8ff 4482 #define SIM_SCGC4_CMP_SHIFT 19
bogdanm 0:9b334a45a8ff 4483 #define SIM_SCGC4_SPI0_MASK 0x400000u
bogdanm 0:9b334a45a8ff 4484 #define SIM_SCGC4_SPI0_SHIFT 22
bogdanm 0:9b334a45a8ff 4485 #define SIM_SCGC4_SPI1_MASK 0x800000u
bogdanm 0:9b334a45a8ff 4486 #define SIM_SCGC4_SPI1_SHIFT 23
bogdanm 0:9b334a45a8ff 4487 /* SCGC5 Bit Fields */
bogdanm 0:9b334a45a8ff 4488 #define SIM_SCGC5_LPTMR_MASK 0x1u
bogdanm 0:9b334a45a8ff 4489 #define SIM_SCGC5_LPTMR_SHIFT 0
bogdanm 0:9b334a45a8ff 4490 #define SIM_SCGC5_TSI_MASK 0x20u
bogdanm 0:9b334a45a8ff 4491 #define SIM_SCGC5_TSI_SHIFT 5
bogdanm 0:9b334a45a8ff 4492 #define SIM_SCGC5_PORTA_MASK 0x200u
bogdanm 0:9b334a45a8ff 4493 #define SIM_SCGC5_PORTA_SHIFT 9
bogdanm 0:9b334a45a8ff 4494 #define SIM_SCGC5_PORTB_MASK 0x400u
bogdanm 0:9b334a45a8ff 4495 #define SIM_SCGC5_PORTB_SHIFT 10
bogdanm 0:9b334a45a8ff 4496 #define SIM_SCGC5_PORTC_MASK 0x800u
bogdanm 0:9b334a45a8ff 4497 #define SIM_SCGC5_PORTC_SHIFT 11
bogdanm 0:9b334a45a8ff 4498 #define SIM_SCGC5_PORTD_MASK 0x1000u
bogdanm 0:9b334a45a8ff 4499 #define SIM_SCGC5_PORTD_SHIFT 12
bogdanm 0:9b334a45a8ff 4500 #define SIM_SCGC5_PORTE_MASK 0x2000u
bogdanm 0:9b334a45a8ff 4501 #define SIM_SCGC5_PORTE_SHIFT 13
bogdanm 0:9b334a45a8ff 4502 #define SIM_SCGC5_SLCD_MASK 0x80000u
bogdanm 0:9b334a45a8ff 4503 #define SIM_SCGC5_SLCD_SHIFT 19
bogdanm 0:9b334a45a8ff 4504 /* SCGC6 Bit Fields */
bogdanm 0:9b334a45a8ff 4505 #define SIM_SCGC6_FTF_MASK 0x1u
bogdanm 0:9b334a45a8ff 4506 #define SIM_SCGC6_FTF_SHIFT 0
bogdanm 0:9b334a45a8ff 4507 #define SIM_SCGC6_DMAMUX_MASK 0x2u
bogdanm 0:9b334a45a8ff 4508 #define SIM_SCGC6_DMAMUX_SHIFT 1
bogdanm 0:9b334a45a8ff 4509 #define SIM_SCGC6_I2S_MASK 0x8000u
bogdanm 0:9b334a45a8ff 4510 #define SIM_SCGC6_I2S_SHIFT 15
bogdanm 0:9b334a45a8ff 4511 #define SIM_SCGC6_PIT_MASK 0x800000u
bogdanm 0:9b334a45a8ff 4512 #define SIM_SCGC6_PIT_SHIFT 23
bogdanm 0:9b334a45a8ff 4513 #define SIM_SCGC6_TPM0_MASK 0x1000000u
bogdanm 0:9b334a45a8ff 4514 #define SIM_SCGC6_TPM0_SHIFT 24
bogdanm 0:9b334a45a8ff 4515 #define SIM_SCGC6_TPM1_MASK 0x2000000u
bogdanm 0:9b334a45a8ff 4516 #define SIM_SCGC6_TPM1_SHIFT 25
bogdanm 0:9b334a45a8ff 4517 #define SIM_SCGC6_TPM2_MASK 0x4000000u
bogdanm 0:9b334a45a8ff 4518 #define SIM_SCGC6_TPM2_SHIFT 26
bogdanm 0:9b334a45a8ff 4519 #define SIM_SCGC6_ADC0_MASK 0x8000000u
bogdanm 0:9b334a45a8ff 4520 #define SIM_SCGC6_ADC0_SHIFT 27
bogdanm 0:9b334a45a8ff 4521 #define SIM_SCGC6_RTC_MASK 0x20000000u
bogdanm 0:9b334a45a8ff 4522 #define SIM_SCGC6_RTC_SHIFT 29
bogdanm 0:9b334a45a8ff 4523 #define SIM_SCGC6_DAC0_MASK 0x80000000u
bogdanm 0:9b334a45a8ff 4524 #define SIM_SCGC6_DAC0_SHIFT 31
bogdanm 0:9b334a45a8ff 4525 /* SCGC7 Bit Fields */
bogdanm 0:9b334a45a8ff 4526 #define SIM_SCGC7_DMA_MASK 0x100u
bogdanm 0:9b334a45a8ff 4527 #define SIM_SCGC7_DMA_SHIFT 8
bogdanm 0:9b334a45a8ff 4528 /* CLKDIV1 Bit Fields */
bogdanm 0:9b334a45a8ff 4529 #define SIM_CLKDIV1_OUTDIV4_MASK 0x70000u
bogdanm 0:9b334a45a8ff 4530 #define SIM_CLKDIV1_OUTDIV4_SHIFT 16
bogdanm 0:9b334a45a8ff 4531 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
bogdanm 0:9b334a45a8ff 4532 #define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
bogdanm 0:9b334a45a8ff 4533 #define SIM_CLKDIV1_OUTDIV1_SHIFT 28
bogdanm 0:9b334a45a8ff 4534 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
bogdanm 0:9b334a45a8ff 4535 /* FCFG1 Bit Fields */
bogdanm 0:9b334a45a8ff 4536 #define SIM_FCFG1_FLASHDIS_MASK 0x1u
bogdanm 0:9b334a45a8ff 4537 #define SIM_FCFG1_FLASHDIS_SHIFT 0
bogdanm 0:9b334a45a8ff 4538 #define SIM_FCFG1_FLASHDOZE_MASK 0x2u
bogdanm 0:9b334a45a8ff 4539 #define SIM_FCFG1_FLASHDOZE_SHIFT 1
bogdanm 0:9b334a45a8ff 4540 #define SIM_FCFG1_PFSIZE_MASK 0xF000000u
bogdanm 0:9b334a45a8ff 4541 #define SIM_FCFG1_PFSIZE_SHIFT 24
bogdanm 0:9b334a45a8ff 4542 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
bogdanm 0:9b334a45a8ff 4543 /* FCFG2 Bit Fields */
bogdanm 0:9b334a45a8ff 4544 #define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
bogdanm 0:9b334a45a8ff 4545 #define SIM_FCFG2_MAXADDR1_SHIFT 16
bogdanm 0:9b334a45a8ff 4546 #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
bogdanm 0:9b334a45a8ff 4547 #define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
bogdanm 0:9b334a45a8ff 4548 #define SIM_FCFG2_MAXADDR0_SHIFT 24
bogdanm 0:9b334a45a8ff 4549 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
bogdanm 0:9b334a45a8ff 4550 /* UIDMH Bit Fields */
bogdanm 0:9b334a45a8ff 4551 #define SIM_UIDMH_UID_MASK 0xFFFFu
bogdanm 0:9b334a45a8ff 4552 #define SIM_UIDMH_UID_SHIFT 0
bogdanm 0:9b334a45a8ff 4553 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
bogdanm 0:9b334a45a8ff 4554 /* UIDML Bit Fields */
bogdanm 0:9b334a45a8ff 4555 #define SIM_UIDML_UID_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 4556 #define SIM_UIDML_UID_SHIFT 0
bogdanm 0:9b334a45a8ff 4557 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
bogdanm 0:9b334a45a8ff 4558 /* UIDL Bit Fields */
bogdanm 0:9b334a45a8ff 4559 #define SIM_UIDL_UID_MASK 0xFFFFFFFFu
bogdanm 0:9b334a45a8ff 4560 #define SIM_UIDL_UID_SHIFT 0
bogdanm 0:9b334a45a8ff 4561 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
bogdanm 0:9b334a45a8ff 4562 /* COPC Bit Fields */
bogdanm 0:9b334a45a8ff 4563 #define SIM_COPC_COPW_MASK 0x1u
bogdanm 0:9b334a45a8ff 4564 #define SIM_COPC_COPW_SHIFT 0
bogdanm 0:9b334a45a8ff 4565 #define SIM_COPC_COPCLKS_MASK 0x2u
bogdanm 0:9b334a45a8ff 4566 #define SIM_COPC_COPCLKS_SHIFT 1
bogdanm 0:9b334a45a8ff 4567 #define SIM_COPC_COPT_MASK 0xCu
bogdanm 0:9b334a45a8ff 4568 #define SIM_COPC_COPT_SHIFT 2
bogdanm 0:9b334a45a8ff 4569 #define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPT_SHIFT))&SIM_COPC_COPT_MASK)
bogdanm 0:9b334a45a8ff 4570 /* SRVCOP Bit Fields */
bogdanm 0:9b334a45a8ff 4571 #define SIM_SRVCOP_SRVCOP_MASK 0xFFu
bogdanm 0:9b334a45a8ff 4572 #define SIM_SRVCOP_SRVCOP_SHIFT 0
bogdanm 0:9b334a45a8ff 4573 #define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x))<<SIM_SRVCOP_SRVCOP_SHIFT))&SIM_SRVCOP_SRVCOP_MASK)
bogdanm 0:9b334a45a8ff 4574
bogdanm 0:9b334a45a8ff 4575 /*!
bogdanm 0:9b334a45a8ff 4576 * @}
bogdanm 0:9b334a45a8ff 4577 */ /* end of group SIM_Register_Masks */
bogdanm 0:9b334a45a8ff 4578
bogdanm 0:9b334a45a8ff 4579
bogdanm 0:9b334a45a8ff 4580 /* SIM - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 4581 /** Peripheral SIM base address */
bogdanm 0:9b334a45a8ff 4582 #define SIM_BASE (0x40047000u)
bogdanm 0:9b334a45a8ff 4583 /** Peripheral SIM base pointer */
bogdanm 0:9b334a45a8ff 4584 #define SIM ((SIM_Type *)SIM_BASE)
bogdanm 0:9b334a45a8ff 4585 /** Array initializer of SIM peripheral base pointers */
bogdanm 0:9b334a45a8ff 4586 #define SIM_BASES { SIM }
bogdanm 0:9b334a45a8ff 4587
bogdanm 0:9b334a45a8ff 4588 /*!
bogdanm 0:9b334a45a8ff 4589 * @}
bogdanm 0:9b334a45a8ff 4590 */ /* end of group SIM_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 4591
bogdanm 0:9b334a45a8ff 4592
bogdanm 0:9b334a45a8ff 4593 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 4594 -- SMC Peripheral Access Layer
bogdanm 0:9b334a45a8ff 4595 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 4596
bogdanm 0:9b334a45a8ff 4597 /*!
bogdanm 0:9b334a45a8ff 4598 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
bogdanm 0:9b334a45a8ff 4599 * @{
bogdanm 0:9b334a45a8ff 4600 */
bogdanm 0:9b334a45a8ff 4601
bogdanm 0:9b334a45a8ff 4602 /** SMC - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 4603 typedef struct {
bogdanm 0:9b334a45a8ff 4604 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
bogdanm 0:9b334a45a8ff 4605 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
bogdanm 0:9b334a45a8ff 4606 __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
bogdanm 0:9b334a45a8ff 4607 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
bogdanm 0:9b334a45a8ff 4608 } SMC_Type;
bogdanm 0:9b334a45a8ff 4609
bogdanm 0:9b334a45a8ff 4610 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 4611 -- SMC Register Masks
bogdanm 0:9b334a45a8ff 4612 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 4613
bogdanm 0:9b334a45a8ff 4614 /*!
bogdanm 0:9b334a45a8ff 4615 * @addtogroup SMC_Register_Masks SMC Register Masks
bogdanm 0:9b334a45a8ff 4616 * @{
bogdanm 0:9b334a45a8ff 4617 */
bogdanm 0:9b334a45a8ff 4618
bogdanm 0:9b334a45a8ff 4619 /* PMPROT Bit Fields */
bogdanm 0:9b334a45a8ff 4620 #define SMC_PMPROT_AVLLS_MASK 0x2u
bogdanm 0:9b334a45a8ff 4621 #define SMC_PMPROT_AVLLS_SHIFT 1
bogdanm 0:9b334a45a8ff 4622 #define SMC_PMPROT_ALLS_MASK 0x8u
bogdanm 0:9b334a45a8ff 4623 #define SMC_PMPROT_ALLS_SHIFT 3
bogdanm 0:9b334a45a8ff 4624 #define SMC_PMPROT_AVLP_MASK 0x20u
bogdanm 0:9b334a45a8ff 4625 #define SMC_PMPROT_AVLP_SHIFT 5
bogdanm 0:9b334a45a8ff 4626 /* PMCTRL Bit Fields */
bogdanm 0:9b334a45a8ff 4627 #define SMC_PMCTRL_STOPM_MASK 0x7u
bogdanm 0:9b334a45a8ff 4628 #define SMC_PMCTRL_STOPM_SHIFT 0
bogdanm 0:9b334a45a8ff 4629 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
bogdanm 0:9b334a45a8ff 4630 #define SMC_PMCTRL_STOPA_MASK 0x8u
bogdanm 0:9b334a45a8ff 4631 #define SMC_PMCTRL_STOPA_SHIFT 3
bogdanm 0:9b334a45a8ff 4632 #define SMC_PMCTRL_RUNM_MASK 0x60u
bogdanm 0:9b334a45a8ff 4633 #define SMC_PMCTRL_RUNM_SHIFT 5
bogdanm 0:9b334a45a8ff 4634 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
bogdanm 0:9b334a45a8ff 4635 /* STOPCTRL Bit Fields */
bogdanm 0:9b334a45a8ff 4636 #define SMC_STOPCTRL_VLLSM_MASK 0x7u
bogdanm 0:9b334a45a8ff 4637 #define SMC_STOPCTRL_VLLSM_SHIFT 0
bogdanm 0:9b334a45a8ff 4638 #define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_VLLSM_SHIFT))&SMC_STOPCTRL_VLLSM_MASK)
bogdanm 0:9b334a45a8ff 4639 #define SMC_STOPCTRL_PORPO_MASK 0x20u
bogdanm 0:9b334a45a8ff 4640 #define SMC_STOPCTRL_PORPO_SHIFT 5
bogdanm 0:9b334a45a8ff 4641 #define SMC_STOPCTRL_PSTOPO_MASK 0xC0u
bogdanm 0:9b334a45a8ff 4642 #define SMC_STOPCTRL_PSTOPO_SHIFT 6
bogdanm 0:9b334a45a8ff 4643 #define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
bogdanm 0:9b334a45a8ff 4644 /* PMSTAT Bit Fields */
bogdanm 0:9b334a45a8ff 4645 #define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
bogdanm 0:9b334a45a8ff 4646 #define SMC_PMSTAT_PMSTAT_SHIFT 0
bogdanm 0:9b334a45a8ff 4647 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
bogdanm 0:9b334a45a8ff 4648
bogdanm 0:9b334a45a8ff 4649 /*!
bogdanm 0:9b334a45a8ff 4650 * @}
bogdanm 0:9b334a45a8ff 4651 */ /* end of group SMC_Register_Masks */
bogdanm 0:9b334a45a8ff 4652
bogdanm 0:9b334a45a8ff 4653
bogdanm 0:9b334a45a8ff 4654 /* SMC - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 4655 /** Peripheral SMC base address */
bogdanm 0:9b334a45a8ff 4656 #define SMC_BASE (0x4007E000u)
bogdanm 0:9b334a45a8ff 4657 /** Peripheral SMC base pointer */
bogdanm 0:9b334a45a8ff 4658 #define SMC ((SMC_Type *)SMC_BASE)
bogdanm 0:9b334a45a8ff 4659 /** Array initializer of SMC peripheral base pointers */
bogdanm 0:9b334a45a8ff 4660 #define SMC_BASES { SMC }
bogdanm 0:9b334a45a8ff 4661
bogdanm 0:9b334a45a8ff 4662 /*!
bogdanm 0:9b334a45a8ff 4663 * @}
bogdanm 0:9b334a45a8ff 4664 */ /* end of group SMC_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 4665
bogdanm 0:9b334a45a8ff 4666
bogdanm 0:9b334a45a8ff 4667 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 4668 -- SPI Peripheral Access Layer
bogdanm 0:9b334a45a8ff 4669 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 4670
bogdanm 0:9b334a45a8ff 4671 /*!
bogdanm 0:9b334a45a8ff 4672 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
bogdanm 0:9b334a45a8ff 4673 * @{
bogdanm 0:9b334a45a8ff 4674 */
bogdanm 0:9b334a45a8ff 4675
bogdanm 0:9b334a45a8ff 4676 /** SPI - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 4677 typedef struct {
bogdanm 0:9b334a45a8ff 4678 __I uint8_t S; /**< SPI status register, offset: 0x0 */
bogdanm 0:9b334a45a8ff 4679 __IO uint8_t BR; /**< SPI baud rate register, offset: 0x1 */
bogdanm 0:9b334a45a8ff 4680 __IO uint8_t C2; /**< SPI control register 2, offset: 0x2 */
bogdanm 0:9b334a45a8ff 4681 __IO uint8_t C1; /**< SPI control register 1, offset: 0x3 */
bogdanm 0:9b334a45a8ff 4682 __IO uint8_t ML; /**< SPI match register low, offset: 0x4 */
bogdanm 0:9b334a45a8ff 4683 __IO uint8_t MH; /**< SPI match register high, offset: 0x5 */
bogdanm 0:9b334a45a8ff 4684 __IO uint8_t DL; /**< SPI data register low, offset: 0x6 */
bogdanm 0:9b334a45a8ff 4685 __IO uint8_t DH; /**< SPI data register high, offset: 0x7 */
bogdanm 0:9b334a45a8ff 4686 uint8_t RESERVED_0[2];
bogdanm 0:9b334a45a8ff 4687 __IO uint8_t CI; /**< SPI clear interrupt register, offset: 0xA */
bogdanm 0:9b334a45a8ff 4688 __IO uint8_t C3; /**< SPI control register 3, offset: 0xB */
bogdanm 0:9b334a45a8ff 4689 } SPI_Type;
bogdanm 0:9b334a45a8ff 4690
bogdanm 0:9b334a45a8ff 4691 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 4692 -- SPI Register Masks
bogdanm 0:9b334a45a8ff 4693 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 4694
bogdanm 0:9b334a45a8ff 4695 /*!
bogdanm 0:9b334a45a8ff 4696 * @addtogroup SPI_Register_Masks SPI Register Masks
bogdanm 0:9b334a45a8ff 4697 * @{
bogdanm 0:9b334a45a8ff 4698 */
bogdanm 0:9b334a45a8ff 4699
bogdanm 0:9b334a45a8ff 4700 /* S Bit Fields */
bogdanm 0:9b334a45a8ff 4701 #define SPI_S_RFIFOEF_MASK 0x1u
bogdanm 0:9b334a45a8ff 4702 #define SPI_S_RFIFOEF_SHIFT 0
bogdanm 0:9b334a45a8ff 4703 #define SPI_S_TXFULLF_MASK 0x2u
bogdanm 0:9b334a45a8ff 4704 #define SPI_S_TXFULLF_SHIFT 1
bogdanm 0:9b334a45a8ff 4705 #define SPI_S_TNEAREF_MASK 0x4u
bogdanm 0:9b334a45a8ff 4706 #define SPI_S_TNEAREF_SHIFT 2
bogdanm 0:9b334a45a8ff 4707 #define SPI_S_RNFULLF_MASK 0x8u
bogdanm 0:9b334a45a8ff 4708 #define SPI_S_RNFULLF_SHIFT 3
bogdanm 0:9b334a45a8ff 4709 #define SPI_S_MODF_MASK 0x10u
bogdanm 0:9b334a45a8ff 4710 #define SPI_S_MODF_SHIFT 4
bogdanm 0:9b334a45a8ff 4711 #define SPI_S_SPTEF_MASK 0x20u
bogdanm 0:9b334a45a8ff 4712 #define SPI_S_SPTEF_SHIFT 5
bogdanm 0:9b334a45a8ff 4713 #define SPI_S_SPMF_MASK 0x40u
bogdanm 0:9b334a45a8ff 4714 #define SPI_S_SPMF_SHIFT 6
bogdanm 0:9b334a45a8ff 4715 #define SPI_S_SPRF_MASK 0x80u
bogdanm 0:9b334a45a8ff 4716 #define SPI_S_SPRF_SHIFT 7
bogdanm 0:9b334a45a8ff 4717 /* BR Bit Fields */
bogdanm 0:9b334a45a8ff 4718 #define SPI_BR_SPR_MASK 0xFu
bogdanm 0:9b334a45a8ff 4719 #define SPI_BR_SPR_SHIFT 0
bogdanm 0:9b334a45a8ff 4720 #define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPR_SHIFT))&SPI_BR_SPR_MASK)
bogdanm 0:9b334a45a8ff 4721 #define SPI_BR_SPPR_MASK 0x70u
bogdanm 0:9b334a45a8ff 4722 #define SPI_BR_SPPR_SHIFT 4
bogdanm 0:9b334a45a8ff 4723 #define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPPR_SHIFT))&SPI_BR_SPPR_MASK)
bogdanm 0:9b334a45a8ff 4724 /* C2 Bit Fields */
bogdanm 0:9b334a45a8ff 4725 #define SPI_C2_SPC0_MASK 0x1u
bogdanm 0:9b334a45a8ff 4726 #define SPI_C2_SPC0_SHIFT 0
bogdanm 0:9b334a45a8ff 4727 #define SPI_C2_SPISWAI_MASK 0x2u
bogdanm 0:9b334a45a8ff 4728 #define SPI_C2_SPISWAI_SHIFT 1
bogdanm 0:9b334a45a8ff 4729 #define SPI_C2_RXDMAE_MASK 0x4u
bogdanm 0:9b334a45a8ff 4730 #define SPI_C2_RXDMAE_SHIFT 2
bogdanm 0:9b334a45a8ff 4731 #define SPI_C2_BIDIROE_MASK 0x8u
bogdanm 0:9b334a45a8ff 4732 #define SPI_C2_BIDIROE_SHIFT 3
bogdanm 0:9b334a45a8ff 4733 #define SPI_C2_MODFEN_MASK 0x10u
bogdanm 0:9b334a45a8ff 4734 #define SPI_C2_MODFEN_SHIFT 4
bogdanm 0:9b334a45a8ff 4735 #define SPI_C2_TXDMAE_MASK 0x20u
bogdanm 0:9b334a45a8ff 4736 #define SPI_C2_TXDMAE_SHIFT 5
bogdanm 0:9b334a45a8ff 4737 #define SPI_C2_SPIMODE_MASK 0x40u
bogdanm 0:9b334a45a8ff 4738 #define SPI_C2_SPIMODE_SHIFT 6
bogdanm 0:9b334a45a8ff 4739 #define SPI_C2_SPMIE_MASK 0x80u
bogdanm 0:9b334a45a8ff 4740 #define SPI_C2_SPMIE_SHIFT 7
bogdanm 0:9b334a45a8ff 4741 /* C1 Bit Fields */
bogdanm 0:9b334a45a8ff 4742 #define SPI_C1_LSBFE_MASK 0x1u
bogdanm 0:9b334a45a8ff 4743 #define SPI_C1_LSBFE_SHIFT 0
bogdanm 0:9b334a45a8ff 4744 #define SPI_C1_SSOE_MASK 0x2u
bogdanm 0:9b334a45a8ff 4745 #define SPI_C1_SSOE_SHIFT 1
bogdanm 0:9b334a45a8ff 4746 #define SPI_C1_CPHA_MASK 0x4u
bogdanm 0:9b334a45a8ff 4747 #define SPI_C1_CPHA_SHIFT 2
bogdanm 0:9b334a45a8ff 4748 #define SPI_C1_CPOL_MASK 0x8u
bogdanm 0:9b334a45a8ff 4749 #define SPI_C1_CPOL_SHIFT 3
bogdanm 0:9b334a45a8ff 4750 #define SPI_C1_MSTR_MASK 0x10u
bogdanm 0:9b334a45a8ff 4751 #define SPI_C1_MSTR_SHIFT 4
bogdanm 0:9b334a45a8ff 4752 #define SPI_C1_SPTIE_MASK 0x20u
bogdanm 0:9b334a45a8ff 4753 #define SPI_C1_SPTIE_SHIFT 5
bogdanm 0:9b334a45a8ff 4754 #define SPI_C1_SPE_MASK 0x40u
bogdanm 0:9b334a45a8ff 4755 #define SPI_C1_SPE_SHIFT 6
bogdanm 0:9b334a45a8ff 4756 #define SPI_C1_SPIE_MASK 0x80u
bogdanm 0:9b334a45a8ff 4757 #define SPI_C1_SPIE_SHIFT 7
bogdanm 0:9b334a45a8ff 4758 /* ML Bit Fields */
bogdanm 0:9b334a45a8ff 4759 #define SPI_ML_Bits_MASK 0xFFu
bogdanm 0:9b334a45a8ff 4760 #define SPI_ML_Bits_SHIFT 0
bogdanm 0:9b334a45a8ff 4761 #define SPI_ML_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_ML_Bits_SHIFT))&SPI_ML_Bits_MASK)
bogdanm 0:9b334a45a8ff 4762 /* MH Bit Fields */
bogdanm 0:9b334a45a8ff 4763 #define SPI_MH_Bits_MASK 0xFFu
bogdanm 0:9b334a45a8ff 4764 #define SPI_MH_Bits_SHIFT 0
bogdanm 0:9b334a45a8ff 4765 #define SPI_MH_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_MH_Bits_SHIFT))&SPI_MH_Bits_MASK)
bogdanm 0:9b334a45a8ff 4766 /* DL Bit Fields */
bogdanm 0:9b334a45a8ff 4767 #define SPI_DL_Bits_MASK 0xFFu
bogdanm 0:9b334a45a8ff 4768 #define SPI_DL_Bits_SHIFT 0
bogdanm 0:9b334a45a8ff 4769 #define SPI_DL_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_DL_Bits_SHIFT))&SPI_DL_Bits_MASK)
bogdanm 0:9b334a45a8ff 4770 /* DH Bit Fields */
bogdanm 0:9b334a45a8ff 4771 #define SPI_DH_Bits_MASK 0xFFu
bogdanm 0:9b334a45a8ff 4772 #define SPI_DH_Bits_SHIFT 0
bogdanm 0:9b334a45a8ff 4773 #define SPI_DH_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_DH_Bits_SHIFT))&SPI_DH_Bits_MASK)
bogdanm 0:9b334a45a8ff 4774 /* CI Bit Fields */
bogdanm 0:9b334a45a8ff 4775 #define SPI_CI_SPRFCI_MASK 0x1u
bogdanm 0:9b334a45a8ff 4776 #define SPI_CI_SPRFCI_SHIFT 0
bogdanm 0:9b334a45a8ff 4777 #define SPI_CI_SPTEFCI_MASK 0x2u
bogdanm 0:9b334a45a8ff 4778 #define SPI_CI_SPTEFCI_SHIFT 1
bogdanm 0:9b334a45a8ff 4779 #define SPI_CI_RNFULLFCI_MASK 0x4u
bogdanm 0:9b334a45a8ff 4780 #define SPI_CI_RNFULLFCI_SHIFT 2
bogdanm 0:9b334a45a8ff 4781 #define SPI_CI_TNEAREFCI_MASK 0x8u
bogdanm 0:9b334a45a8ff 4782 #define SPI_CI_TNEAREFCI_SHIFT 3
bogdanm 0:9b334a45a8ff 4783 #define SPI_CI_RXFOF_MASK 0x10u
bogdanm 0:9b334a45a8ff 4784 #define SPI_CI_RXFOF_SHIFT 4
bogdanm 0:9b334a45a8ff 4785 #define SPI_CI_TXFOF_MASK 0x20u
bogdanm 0:9b334a45a8ff 4786 #define SPI_CI_TXFOF_SHIFT 5
bogdanm 0:9b334a45a8ff 4787 #define SPI_CI_RXFERR_MASK 0x40u
bogdanm 0:9b334a45a8ff 4788 #define SPI_CI_RXFERR_SHIFT 6
bogdanm 0:9b334a45a8ff 4789 #define SPI_CI_TXFERR_MASK 0x80u
bogdanm 0:9b334a45a8ff 4790 #define SPI_CI_TXFERR_SHIFT 7
bogdanm 0:9b334a45a8ff 4791 /* C3 Bit Fields */
bogdanm 0:9b334a45a8ff 4792 #define SPI_C3_FIFOMODE_MASK 0x1u
bogdanm 0:9b334a45a8ff 4793 #define SPI_C3_FIFOMODE_SHIFT 0
bogdanm 0:9b334a45a8ff 4794 #define SPI_C3_RNFULLIEN_MASK 0x2u
bogdanm 0:9b334a45a8ff 4795 #define SPI_C3_RNFULLIEN_SHIFT 1
bogdanm 0:9b334a45a8ff 4796 #define SPI_C3_TNEARIEN_MASK 0x4u
bogdanm 0:9b334a45a8ff 4797 #define SPI_C3_TNEARIEN_SHIFT 2
bogdanm 0:9b334a45a8ff 4798 #define SPI_C3_INTCLR_MASK 0x8u
bogdanm 0:9b334a45a8ff 4799 #define SPI_C3_INTCLR_SHIFT 3
bogdanm 0:9b334a45a8ff 4800 #define SPI_C3_RNFULLF_MARK_MASK 0x10u
bogdanm 0:9b334a45a8ff 4801 #define SPI_C3_RNFULLF_MARK_SHIFT 4
bogdanm 0:9b334a45a8ff 4802 #define SPI_C3_TNEAREF_MARK_MASK 0x20u
bogdanm 0:9b334a45a8ff 4803 #define SPI_C3_TNEAREF_MARK_SHIFT 5
bogdanm 0:9b334a45a8ff 4804
bogdanm 0:9b334a45a8ff 4805 /*!
bogdanm 0:9b334a45a8ff 4806 * @}
bogdanm 0:9b334a45a8ff 4807 */ /* end of group SPI_Register_Masks */
bogdanm 0:9b334a45a8ff 4808
bogdanm 0:9b334a45a8ff 4809
bogdanm 0:9b334a45a8ff 4810 /* SPI - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 4811 /** Peripheral SPI0 base address */
bogdanm 0:9b334a45a8ff 4812 #define SPI0_BASE (0x40076000u)
bogdanm 0:9b334a45a8ff 4813 /** Peripheral SPI0 base pointer */
bogdanm 0:9b334a45a8ff 4814 #define SPI0 ((SPI_Type *)SPI0_BASE)
bogdanm 0:9b334a45a8ff 4815 /** Peripheral SPI1 base address */
bogdanm 0:9b334a45a8ff 4816 #define SPI1_BASE (0x40077000u)
bogdanm 0:9b334a45a8ff 4817 /** Peripheral SPI1 base pointer */
bogdanm 0:9b334a45a8ff 4818 #define SPI1 ((SPI_Type *)SPI1_BASE)
bogdanm 0:9b334a45a8ff 4819 /** Array initializer of SPI peripheral base pointers */
bogdanm 0:9b334a45a8ff 4820 #define SPI_BASES { SPI0, SPI1 }
bogdanm 0:9b334a45a8ff 4821
bogdanm 0:9b334a45a8ff 4822 /*!
bogdanm 0:9b334a45a8ff 4823 * @}
bogdanm 0:9b334a45a8ff 4824 */ /* end of group SPI_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 4825
bogdanm 0:9b334a45a8ff 4826
bogdanm 0:9b334a45a8ff 4827 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 4828 -- TPM Peripheral Access Layer
bogdanm 0:9b334a45a8ff 4829 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 4830
bogdanm 0:9b334a45a8ff 4831 /*!
bogdanm 0:9b334a45a8ff 4832 * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
bogdanm 0:9b334a45a8ff 4833 * @{
bogdanm 0:9b334a45a8ff 4834 */
bogdanm 0:9b334a45a8ff 4835
bogdanm 0:9b334a45a8ff 4836 /** TPM - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 4837 typedef struct {
bogdanm 0:9b334a45a8ff 4838 __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
bogdanm 0:9b334a45a8ff 4839 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
bogdanm 0:9b334a45a8ff 4840 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
bogdanm 0:9b334a45a8ff 4841 struct { /* offset: 0xC, array step: 0x8 */
bogdanm 0:9b334a45a8ff 4842 __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
bogdanm 0:9b334a45a8ff 4843 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
bogdanm 0:9b334a45a8ff 4844 } CONTROLS[6];
bogdanm 0:9b334a45a8ff 4845 uint8_t RESERVED_0[20];
bogdanm 0:9b334a45a8ff 4846 __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
bogdanm 0:9b334a45a8ff 4847 uint8_t RESERVED_1[48];
bogdanm 0:9b334a45a8ff 4848 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
bogdanm 0:9b334a45a8ff 4849 } TPM_Type;
bogdanm 0:9b334a45a8ff 4850
bogdanm 0:9b334a45a8ff 4851 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 4852 -- TPM Register Masks
bogdanm 0:9b334a45a8ff 4853 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 4854
bogdanm 0:9b334a45a8ff 4855 /*!
bogdanm 0:9b334a45a8ff 4856 * @addtogroup TPM_Register_Masks TPM Register Masks
bogdanm 0:9b334a45a8ff 4857 * @{
bogdanm 0:9b334a45a8ff 4858 */
bogdanm 0:9b334a45a8ff 4859
bogdanm 0:9b334a45a8ff 4860 /* SC Bit Fields */
bogdanm 0:9b334a45a8ff 4861 #define TPM_SC_PS_MASK 0x7u
bogdanm 0:9b334a45a8ff 4862 #define TPM_SC_PS_SHIFT 0
bogdanm 0:9b334a45a8ff 4863 #define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_PS_SHIFT))&TPM_SC_PS_MASK)
bogdanm 0:9b334a45a8ff 4864 #define TPM_SC_CMOD_MASK 0x18u
bogdanm 0:9b334a45a8ff 4865 #define TPM_SC_CMOD_SHIFT 3
bogdanm 0:9b334a45a8ff 4866 #define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_CMOD_SHIFT))&TPM_SC_CMOD_MASK)
bogdanm 0:9b334a45a8ff 4867 #define TPM_SC_CPWMS_MASK 0x20u
bogdanm 0:9b334a45a8ff 4868 #define TPM_SC_CPWMS_SHIFT 5
bogdanm 0:9b334a45a8ff 4869 #define TPM_SC_TOIE_MASK 0x40u
bogdanm 0:9b334a45a8ff 4870 #define TPM_SC_TOIE_SHIFT 6
bogdanm 0:9b334a45a8ff 4871 #define TPM_SC_TOF_MASK 0x80u
bogdanm 0:9b334a45a8ff 4872 #define TPM_SC_TOF_SHIFT 7
bogdanm 0:9b334a45a8ff 4873 #define TPM_SC_DMA_MASK 0x100u
bogdanm 0:9b334a45a8ff 4874 #define TPM_SC_DMA_SHIFT 8
bogdanm 0:9b334a45a8ff 4875 /* CNT Bit Fields */
bogdanm 0:9b334a45a8ff 4876 #define TPM_CNT_COUNT_MASK 0xFFFFu
bogdanm 0:9b334a45a8ff 4877 #define TPM_CNT_COUNT_SHIFT 0
bogdanm 0:9b334a45a8ff 4878 #define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CNT_COUNT_SHIFT))&TPM_CNT_COUNT_MASK)
bogdanm 0:9b334a45a8ff 4879 /* MOD Bit Fields */
bogdanm 0:9b334a45a8ff 4880 #define TPM_MOD_MOD_MASK 0xFFFFu
bogdanm 0:9b334a45a8ff 4881 #define TPM_MOD_MOD_SHIFT 0
bogdanm 0:9b334a45a8ff 4882 #define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_MOD_MOD_SHIFT))&TPM_MOD_MOD_MASK)
bogdanm 0:9b334a45a8ff 4883 /* CnSC Bit Fields */
bogdanm 0:9b334a45a8ff 4884 #define TPM_CnSC_DMA_MASK 0x1u
bogdanm 0:9b334a45a8ff 4885 #define TPM_CnSC_DMA_SHIFT 0
bogdanm 0:9b334a45a8ff 4886 #define TPM_CnSC_ELSA_MASK 0x4u
bogdanm 0:9b334a45a8ff 4887 #define TPM_CnSC_ELSA_SHIFT 2
bogdanm 0:9b334a45a8ff 4888 #define TPM_CnSC_ELSB_MASK 0x8u
bogdanm 0:9b334a45a8ff 4889 #define TPM_CnSC_ELSB_SHIFT 3
bogdanm 0:9b334a45a8ff 4890 #define TPM_CnSC_MSA_MASK 0x10u
bogdanm 0:9b334a45a8ff 4891 #define TPM_CnSC_MSA_SHIFT 4
bogdanm 0:9b334a45a8ff 4892 #define TPM_CnSC_MSB_MASK 0x20u
bogdanm 0:9b334a45a8ff 4893 #define TPM_CnSC_MSB_SHIFT 5
bogdanm 0:9b334a45a8ff 4894 #define TPM_CnSC_CHIE_MASK 0x40u
bogdanm 0:9b334a45a8ff 4895 #define TPM_CnSC_CHIE_SHIFT 6
bogdanm 0:9b334a45a8ff 4896 #define TPM_CnSC_CHF_MASK 0x80u
bogdanm 0:9b334a45a8ff 4897 #define TPM_CnSC_CHF_SHIFT 7
bogdanm 0:9b334a45a8ff 4898 /* CnV Bit Fields */
bogdanm 0:9b334a45a8ff 4899 #define TPM_CnV_VAL_MASK 0xFFFFu
bogdanm 0:9b334a45a8ff 4900 #define TPM_CnV_VAL_SHIFT 0
bogdanm 0:9b334a45a8ff 4901 #define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnV_VAL_SHIFT))&TPM_CnV_VAL_MASK)
bogdanm 0:9b334a45a8ff 4902 /* STATUS Bit Fields */
bogdanm 0:9b334a45a8ff 4903 #define TPM_STATUS_CH0F_MASK 0x1u
bogdanm 0:9b334a45a8ff 4904 #define TPM_STATUS_CH0F_SHIFT 0
bogdanm 0:9b334a45a8ff 4905 #define TPM_STATUS_CH1F_MASK 0x2u
bogdanm 0:9b334a45a8ff 4906 #define TPM_STATUS_CH1F_SHIFT 1
bogdanm 0:9b334a45a8ff 4907 #define TPM_STATUS_CH2F_MASK 0x4u
bogdanm 0:9b334a45a8ff 4908 #define TPM_STATUS_CH2F_SHIFT 2
bogdanm 0:9b334a45a8ff 4909 #define TPM_STATUS_CH3F_MASK 0x8u
bogdanm 0:9b334a45a8ff 4910 #define TPM_STATUS_CH3F_SHIFT 3
bogdanm 0:9b334a45a8ff 4911 #define TPM_STATUS_CH4F_MASK 0x10u
bogdanm 0:9b334a45a8ff 4912 #define TPM_STATUS_CH4F_SHIFT 4
bogdanm 0:9b334a45a8ff 4913 #define TPM_STATUS_CH5F_MASK 0x20u
bogdanm 0:9b334a45a8ff 4914 #define TPM_STATUS_CH5F_SHIFT 5
bogdanm 0:9b334a45a8ff 4915 #define TPM_STATUS_TOF_MASK 0x100u
bogdanm 0:9b334a45a8ff 4916 #define TPM_STATUS_TOF_SHIFT 8
bogdanm 0:9b334a45a8ff 4917 /* CONF Bit Fields */
bogdanm 0:9b334a45a8ff 4918 #define TPM_CONF_DOZEEN_MASK 0x20u
bogdanm 0:9b334a45a8ff 4919 #define TPM_CONF_DOZEEN_SHIFT 5
bogdanm 0:9b334a45a8ff 4920 #define TPM_CONF_DBGMODE_MASK 0xC0u
bogdanm 0:9b334a45a8ff 4921 #define TPM_CONF_DBGMODE_SHIFT 6
bogdanm 0:9b334a45a8ff 4922 #define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DBGMODE_SHIFT))&TPM_CONF_DBGMODE_MASK)
bogdanm 0:9b334a45a8ff 4923 #define TPM_CONF_GTBEEN_MASK 0x200u
bogdanm 0:9b334a45a8ff 4924 #define TPM_CONF_GTBEEN_SHIFT 9
bogdanm 0:9b334a45a8ff 4925 #define TPM_CONF_CSOT_MASK 0x10000u
bogdanm 0:9b334a45a8ff 4926 #define TPM_CONF_CSOT_SHIFT 16
bogdanm 0:9b334a45a8ff 4927 #define TPM_CONF_CSOO_MASK 0x20000u
bogdanm 0:9b334a45a8ff 4928 #define TPM_CONF_CSOO_SHIFT 17
bogdanm 0:9b334a45a8ff 4929 #define TPM_CONF_CROT_MASK 0x40000u
bogdanm 0:9b334a45a8ff 4930 #define TPM_CONF_CROT_SHIFT 18
bogdanm 0:9b334a45a8ff 4931 #define TPM_CONF_TRGSEL_MASK 0xF000000u
bogdanm 0:9b334a45a8ff 4932 #define TPM_CONF_TRGSEL_SHIFT 24
bogdanm 0:9b334a45a8ff 4933 #define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSEL_SHIFT))&TPM_CONF_TRGSEL_MASK)
bogdanm 0:9b334a45a8ff 4934
bogdanm 0:9b334a45a8ff 4935 /*!
bogdanm 0:9b334a45a8ff 4936 * @}
bogdanm 0:9b334a45a8ff 4937 */ /* end of group TPM_Register_Masks */
bogdanm 0:9b334a45a8ff 4938
bogdanm 0:9b334a45a8ff 4939
bogdanm 0:9b334a45a8ff 4940 /* TPM - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 4941 /** Peripheral TPM0 base address */
bogdanm 0:9b334a45a8ff 4942 #define TPM0_BASE (0x40038000u)
bogdanm 0:9b334a45a8ff 4943 /** Peripheral TPM0 base pointer */
bogdanm 0:9b334a45a8ff 4944 #define TPM0 ((TPM_Type *)TPM0_BASE)
bogdanm 0:9b334a45a8ff 4945 /** Peripheral TPM1 base address */
bogdanm 0:9b334a45a8ff 4946 #define TPM1_BASE (0x40039000u)
bogdanm 0:9b334a45a8ff 4947 /** Peripheral TPM1 base pointer */
bogdanm 0:9b334a45a8ff 4948 #define TPM1 ((TPM_Type *)TPM1_BASE)
bogdanm 0:9b334a45a8ff 4949 /** Peripheral TPM2 base address */
bogdanm 0:9b334a45a8ff 4950 #define TPM2_BASE (0x4003A000u)
bogdanm 0:9b334a45a8ff 4951 /** Peripheral TPM2 base pointer */
bogdanm 0:9b334a45a8ff 4952 #define TPM2 ((TPM_Type *)TPM2_BASE)
bogdanm 0:9b334a45a8ff 4953 /** Array initializer of TPM peripheral base pointers */
bogdanm 0:9b334a45a8ff 4954 #define TPM_BASES { TPM0, TPM1, TPM2 }
bogdanm 0:9b334a45a8ff 4955
bogdanm 0:9b334a45a8ff 4956 /*!
bogdanm 0:9b334a45a8ff 4957 * @}
bogdanm 0:9b334a45a8ff 4958 */ /* end of group TPM_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 4959
bogdanm 0:9b334a45a8ff 4960
bogdanm 0:9b334a45a8ff 4961 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 4962 -- TSI Peripheral Access Layer
bogdanm 0:9b334a45a8ff 4963 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 4964
bogdanm 0:9b334a45a8ff 4965 /*!
bogdanm 0:9b334a45a8ff 4966 * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
bogdanm 0:9b334a45a8ff 4967 * @{
bogdanm 0:9b334a45a8ff 4968 */
bogdanm 0:9b334a45a8ff 4969
bogdanm 0:9b334a45a8ff 4970 /** TSI - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 4971 typedef struct {
bogdanm 0:9b334a45a8ff 4972 __IO uint32_t GENCS; /**< TSI General Control and Status Register, offset: 0x0 */
bogdanm 0:9b334a45a8ff 4973 __IO uint32_t DATA; /**< TSI DATA Register, offset: 0x4 */
bogdanm 0:9b334a45a8ff 4974 __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */
bogdanm 0:9b334a45a8ff 4975 } TSI_Type;
bogdanm 0:9b334a45a8ff 4976
bogdanm 0:9b334a45a8ff 4977 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 4978 -- TSI Register Masks
bogdanm 0:9b334a45a8ff 4979 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 4980
bogdanm 0:9b334a45a8ff 4981 /*!
bogdanm 0:9b334a45a8ff 4982 * @addtogroup TSI_Register_Masks TSI Register Masks
bogdanm 0:9b334a45a8ff 4983 * @{
bogdanm 0:9b334a45a8ff 4984 */
bogdanm 0:9b334a45a8ff 4985
bogdanm 0:9b334a45a8ff 4986 /* GENCS Bit Fields */
bogdanm 0:9b334a45a8ff 4987 #define TSI_GENCS_CURSW_MASK 0x2u
bogdanm 0:9b334a45a8ff 4988 #define TSI_GENCS_CURSW_SHIFT 1
bogdanm 0:9b334a45a8ff 4989 #define TSI_GENCS_EOSF_MASK 0x4u
bogdanm 0:9b334a45a8ff 4990 #define TSI_GENCS_EOSF_SHIFT 2
bogdanm 0:9b334a45a8ff 4991 #define TSI_GENCS_SCNIP_MASK 0x8u
bogdanm 0:9b334a45a8ff 4992 #define TSI_GENCS_SCNIP_SHIFT 3
bogdanm 0:9b334a45a8ff 4993 #define TSI_GENCS_STM_MASK 0x10u
bogdanm 0:9b334a45a8ff 4994 #define TSI_GENCS_STM_SHIFT 4
bogdanm 0:9b334a45a8ff 4995 #define TSI_GENCS_STPE_MASK 0x20u
bogdanm 0:9b334a45a8ff 4996 #define TSI_GENCS_STPE_SHIFT 5
bogdanm 0:9b334a45a8ff 4997 #define TSI_GENCS_TSIIEN_MASK 0x40u
bogdanm 0:9b334a45a8ff 4998 #define TSI_GENCS_TSIIEN_SHIFT 6
bogdanm 0:9b334a45a8ff 4999 #define TSI_GENCS_TSIEN_MASK 0x80u
bogdanm 0:9b334a45a8ff 5000 #define TSI_GENCS_TSIEN_SHIFT 7
bogdanm 0:9b334a45a8ff 5001 #define TSI_GENCS_NSCN_MASK 0x1F00u
bogdanm 0:9b334a45a8ff 5002 #define TSI_GENCS_NSCN_SHIFT 8
bogdanm 0:9b334a45a8ff 5003 #define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
bogdanm 0:9b334a45a8ff 5004 #define TSI_GENCS_PS_MASK 0xE000u
bogdanm 0:9b334a45a8ff 5005 #define TSI_GENCS_PS_SHIFT 13
bogdanm 0:9b334a45a8ff 5006 #define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
bogdanm 0:9b334a45a8ff 5007 #define TSI_GENCS_EXTCHRG_MASK 0x70000u
bogdanm 0:9b334a45a8ff 5008 #define TSI_GENCS_EXTCHRG_SHIFT 16
bogdanm 0:9b334a45a8ff 5009 #define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_EXTCHRG_SHIFT))&TSI_GENCS_EXTCHRG_MASK)
bogdanm 0:9b334a45a8ff 5010 #define TSI_GENCS_DVOLT_MASK 0x180000u
bogdanm 0:9b334a45a8ff 5011 #define TSI_GENCS_DVOLT_SHIFT 19
bogdanm 0:9b334a45a8ff 5012 #define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_DVOLT_SHIFT))&TSI_GENCS_DVOLT_MASK)
bogdanm 0:9b334a45a8ff 5013 #define TSI_GENCS_REFCHRG_MASK 0xE00000u
bogdanm 0:9b334a45a8ff 5014 #define TSI_GENCS_REFCHRG_SHIFT 21
bogdanm 0:9b334a45a8ff 5015 #define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_REFCHRG_SHIFT))&TSI_GENCS_REFCHRG_MASK)
bogdanm 0:9b334a45a8ff 5016 #define TSI_GENCS_MODE_MASK 0xF000000u
bogdanm 0:9b334a45a8ff 5017 #define TSI_GENCS_MODE_SHIFT 24
bogdanm 0:9b334a45a8ff 5018 #define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_MODE_SHIFT))&TSI_GENCS_MODE_MASK)
bogdanm 0:9b334a45a8ff 5019 #define TSI_GENCS_ESOR_MASK 0x10000000u
bogdanm 0:9b334a45a8ff 5020 #define TSI_GENCS_ESOR_SHIFT 28
bogdanm 0:9b334a45a8ff 5021 #define TSI_GENCS_OUTRGF_MASK 0x80000000u
bogdanm 0:9b334a45a8ff 5022 #define TSI_GENCS_OUTRGF_SHIFT 31
bogdanm 0:9b334a45a8ff 5023 /* DATA Bit Fields */
bogdanm 0:9b334a45a8ff 5024 #define TSI_DATA_TSICNT_MASK 0xFFFFu
bogdanm 0:9b334a45a8ff 5025 #define TSI_DATA_TSICNT_SHIFT 0
bogdanm 0:9b334a45a8ff 5026 #define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICNT_SHIFT))&TSI_DATA_TSICNT_MASK)
bogdanm 0:9b334a45a8ff 5027 #define TSI_DATA_SWTS_MASK 0x400000u
bogdanm 0:9b334a45a8ff 5028 #define TSI_DATA_SWTS_SHIFT 22
bogdanm 0:9b334a45a8ff 5029 #define TSI_DATA_DMAEN_MASK 0x800000u
bogdanm 0:9b334a45a8ff 5030 #define TSI_DATA_DMAEN_SHIFT 23
bogdanm 0:9b334a45a8ff 5031 #define TSI_DATA_TSICH_MASK 0xF0000000u
bogdanm 0:9b334a45a8ff 5032 #define TSI_DATA_TSICH_SHIFT 28
bogdanm 0:9b334a45a8ff 5033 #define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICH_SHIFT))&TSI_DATA_TSICH_MASK)
bogdanm 0:9b334a45a8ff 5034 /* TSHD Bit Fields */
bogdanm 0:9b334a45a8ff 5035 #define TSI_TSHD_THRESL_MASK 0xFFFFu
bogdanm 0:9b334a45a8ff 5036 #define TSI_TSHD_THRESL_SHIFT 0
bogdanm 0:9b334a45a8ff 5037 #define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESL_SHIFT))&TSI_TSHD_THRESL_MASK)
bogdanm 0:9b334a45a8ff 5038 #define TSI_TSHD_THRESH_MASK 0xFFFF0000u
bogdanm 0:9b334a45a8ff 5039 #define TSI_TSHD_THRESH_SHIFT 16
bogdanm 0:9b334a45a8ff 5040 #define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESH_SHIFT))&TSI_TSHD_THRESH_MASK)
bogdanm 0:9b334a45a8ff 5041
bogdanm 0:9b334a45a8ff 5042 /*!
bogdanm 0:9b334a45a8ff 5043 * @}
bogdanm 0:9b334a45a8ff 5044 */ /* end of group TSI_Register_Masks */
bogdanm 0:9b334a45a8ff 5045
bogdanm 0:9b334a45a8ff 5046
bogdanm 0:9b334a45a8ff 5047 /* TSI - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 5048 /** Peripheral TSI0 base address */
bogdanm 0:9b334a45a8ff 5049 #define TSI0_BASE (0x40045000u)
bogdanm 0:9b334a45a8ff 5050 /** Peripheral TSI0 base pointer */
bogdanm 0:9b334a45a8ff 5051 #define TSI0 ((TSI_Type *)TSI0_BASE)
bogdanm 0:9b334a45a8ff 5052 /** Array initializer of TSI peripheral base pointers */
bogdanm 0:9b334a45a8ff 5053 #define TSI_BASES { TSI0 }
bogdanm 0:9b334a45a8ff 5054
bogdanm 0:9b334a45a8ff 5055 /*!
bogdanm 0:9b334a45a8ff 5056 * @}
bogdanm 0:9b334a45a8ff 5057 */ /* end of group TSI_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 5058
bogdanm 0:9b334a45a8ff 5059
bogdanm 0:9b334a45a8ff 5060 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 5061 -- UART Peripheral Access Layer
bogdanm 0:9b334a45a8ff 5062 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 5063
bogdanm 0:9b334a45a8ff 5064 /*!
bogdanm 0:9b334a45a8ff 5065 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
bogdanm 0:9b334a45a8ff 5066 * @{
bogdanm 0:9b334a45a8ff 5067 */
bogdanm 0:9b334a45a8ff 5068
bogdanm 0:9b334a45a8ff 5069 /** UART - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 5070 typedef struct {
bogdanm 0:9b334a45a8ff 5071 __IO uint8_t BDH; /**< UART Baud Rate Register: High, offset: 0x0 */
bogdanm 0:9b334a45a8ff 5072 __IO uint8_t BDL; /**< UART Baud Rate Register: Low, offset: 0x1 */
bogdanm 0:9b334a45a8ff 5073 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
bogdanm 0:9b334a45a8ff 5074 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
bogdanm 0:9b334a45a8ff 5075 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
bogdanm 0:9b334a45a8ff 5076 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
bogdanm 0:9b334a45a8ff 5077 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
bogdanm 0:9b334a45a8ff 5078 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
bogdanm 0:9b334a45a8ff 5079 __IO uint8_t C4; /**< UART Control Register 4, offset: 0x8 */
bogdanm 0:9b334a45a8ff 5080 } UART_Type;
bogdanm 0:9b334a45a8ff 5081
bogdanm 0:9b334a45a8ff 5082 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 5083 -- UART Register Masks
bogdanm 0:9b334a45a8ff 5084 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 5085
bogdanm 0:9b334a45a8ff 5086 /*!
bogdanm 0:9b334a45a8ff 5087 * @addtogroup UART_Register_Masks UART Register Masks
bogdanm 0:9b334a45a8ff 5088 * @{
bogdanm 0:9b334a45a8ff 5089 */
bogdanm 0:9b334a45a8ff 5090
bogdanm 0:9b334a45a8ff 5091 /* BDH Bit Fields */
bogdanm 0:9b334a45a8ff 5092 #define UART_BDH_SBR_MASK 0x1Fu
bogdanm 0:9b334a45a8ff 5093 #define UART_BDH_SBR_SHIFT 0
bogdanm 0:9b334a45a8ff 5094 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
bogdanm 0:9b334a45a8ff 5095 #define UART_BDH_SBNS_MASK 0x20u
bogdanm 0:9b334a45a8ff 5096 #define UART_BDH_SBNS_SHIFT 5
bogdanm 0:9b334a45a8ff 5097 #define UART_BDH_RXEDGIE_MASK 0x40u
bogdanm 0:9b334a45a8ff 5098 #define UART_BDH_RXEDGIE_SHIFT 6
bogdanm 0:9b334a45a8ff 5099 #define UART_BDH_LBKDIE_MASK 0x80u
bogdanm 0:9b334a45a8ff 5100 #define UART_BDH_LBKDIE_SHIFT 7
bogdanm 0:9b334a45a8ff 5101 /* BDL Bit Fields */
bogdanm 0:9b334a45a8ff 5102 #define UART_BDL_SBR_MASK 0xFFu
bogdanm 0:9b334a45a8ff 5103 #define UART_BDL_SBR_SHIFT 0
bogdanm 0:9b334a45a8ff 5104 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
bogdanm 0:9b334a45a8ff 5105 /* C1 Bit Fields */
bogdanm 0:9b334a45a8ff 5106 #define UART_C1_PT_MASK 0x1u
bogdanm 0:9b334a45a8ff 5107 #define UART_C1_PT_SHIFT 0
bogdanm 0:9b334a45a8ff 5108 #define UART_C1_PE_MASK 0x2u
bogdanm 0:9b334a45a8ff 5109 #define UART_C1_PE_SHIFT 1
bogdanm 0:9b334a45a8ff 5110 #define UART_C1_ILT_MASK 0x4u
bogdanm 0:9b334a45a8ff 5111 #define UART_C1_ILT_SHIFT 2
bogdanm 0:9b334a45a8ff 5112 #define UART_C1_WAKE_MASK 0x8u
bogdanm 0:9b334a45a8ff 5113 #define UART_C1_WAKE_SHIFT 3
bogdanm 0:9b334a45a8ff 5114 #define UART_C1_M_MASK 0x10u
bogdanm 0:9b334a45a8ff 5115 #define UART_C1_M_SHIFT 4
bogdanm 0:9b334a45a8ff 5116 #define UART_C1_RSRC_MASK 0x20u
bogdanm 0:9b334a45a8ff 5117 #define UART_C1_RSRC_SHIFT 5
bogdanm 0:9b334a45a8ff 5118 #define UART_C1_UARTSWAI_MASK 0x40u
bogdanm 0:9b334a45a8ff 5119 #define UART_C1_UARTSWAI_SHIFT 6
bogdanm 0:9b334a45a8ff 5120 #define UART_C1_LOOPS_MASK 0x80u
bogdanm 0:9b334a45a8ff 5121 #define UART_C1_LOOPS_SHIFT 7
bogdanm 0:9b334a45a8ff 5122 /* C2 Bit Fields */
bogdanm 0:9b334a45a8ff 5123 #define UART_C2_SBK_MASK 0x1u
bogdanm 0:9b334a45a8ff 5124 #define UART_C2_SBK_SHIFT 0
bogdanm 0:9b334a45a8ff 5125 #define UART_C2_RWU_MASK 0x2u
bogdanm 0:9b334a45a8ff 5126 #define UART_C2_RWU_SHIFT 1
bogdanm 0:9b334a45a8ff 5127 #define UART_C2_RE_MASK 0x4u
bogdanm 0:9b334a45a8ff 5128 #define UART_C2_RE_SHIFT 2
bogdanm 0:9b334a45a8ff 5129 #define UART_C2_TE_MASK 0x8u
bogdanm 0:9b334a45a8ff 5130 #define UART_C2_TE_SHIFT 3
bogdanm 0:9b334a45a8ff 5131 #define UART_C2_ILIE_MASK 0x10u
bogdanm 0:9b334a45a8ff 5132 #define UART_C2_ILIE_SHIFT 4
bogdanm 0:9b334a45a8ff 5133 #define UART_C2_RIE_MASK 0x20u
bogdanm 0:9b334a45a8ff 5134 #define UART_C2_RIE_SHIFT 5
bogdanm 0:9b334a45a8ff 5135 #define UART_C2_TCIE_MASK 0x40u
bogdanm 0:9b334a45a8ff 5136 #define UART_C2_TCIE_SHIFT 6
bogdanm 0:9b334a45a8ff 5137 #define UART_C2_TIE_MASK 0x80u
bogdanm 0:9b334a45a8ff 5138 #define UART_C2_TIE_SHIFT 7
bogdanm 0:9b334a45a8ff 5139 /* S1 Bit Fields */
bogdanm 0:9b334a45a8ff 5140 #define UART_S1_PF_MASK 0x1u
bogdanm 0:9b334a45a8ff 5141 #define UART_S1_PF_SHIFT 0
bogdanm 0:9b334a45a8ff 5142 #define UART_S1_FE_MASK 0x2u
bogdanm 0:9b334a45a8ff 5143 #define UART_S1_FE_SHIFT 1
bogdanm 0:9b334a45a8ff 5144 #define UART_S1_NF_MASK 0x4u
bogdanm 0:9b334a45a8ff 5145 #define UART_S1_NF_SHIFT 2
bogdanm 0:9b334a45a8ff 5146 #define UART_S1_OR_MASK 0x8u
bogdanm 0:9b334a45a8ff 5147 #define UART_S1_OR_SHIFT 3
bogdanm 0:9b334a45a8ff 5148 #define UART_S1_IDLE_MASK 0x10u
bogdanm 0:9b334a45a8ff 5149 #define UART_S1_IDLE_SHIFT 4
bogdanm 0:9b334a45a8ff 5150 #define UART_S1_RDRF_MASK 0x20u
bogdanm 0:9b334a45a8ff 5151 #define UART_S1_RDRF_SHIFT 5
bogdanm 0:9b334a45a8ff 5152 #define UART_S1_TC_MASK 0x40u
bogdanm 0:9b334a45a8ff 5153 #define UART_S1_TC_SHIFT 6
bogdanm 0:9b334a45a8ff 5154 #define UART_S1_TDRE_MASK 0x80u
bogdanm 0:9b334a45a8ff 5155 #define UART_S1_TDRE_SHIFT 7
bogdanm 0:9b334a45a8ff 5156 /* S2 Bit Fields */
bogdanm 0:9b334a45a8ff 5157 #define UART_S2_RAF_MASK 0x1u
bogdanm 0:9b334a45a8ff 5158 #define UART_S2_RAF_SHIFT 0
bogdanm 0:9b334a45a8ff 5159 #define UART_S2_LBKDE_MASK 0x2u
bogdanm 0:9b334a45a8ff 5160 #define UART_S2_LBKDE_SHIFT 1
bogdanm 0:9b334a45a8ff 5161 #define UART_S2_BRK13_MASK 0x4u
bogdanm 0:9b334a45a8ff 5162 #define UART_S2_BRK13_SHIFT 2
bogdanm 0:9b334a45a8ff 5163 #define UART_S2_RWUID_MASK 0x8u
bogdanm 0:9b334a45a8ff 5164 #define UART_S2_RWUID_SHIFT 3
bogdanm 0:9b334a45a8ff 5165 #define UART_S2_RXINV_MASK 0x10u
bogdanm 0:9b334a45a8ff 5166 #define UART_S2_RXINV_SHIFT 4
bogdanm 0:9b334a45a8ff 5167 #define UART_S2_RXEDGIF_MASK 0x40u
bogdanm 0:9b334a45a8ff 5168 #define UART_S2_RXEDGIF_SHIFT 6
bogdanm 0:9b334a45a8ff 5169 #define UART_S2_LBKDIF_MASK 0x80u
bogdanm 0:9b334a45a8ff 5170 #define UART_S2_LBKDIF_SHIFT 7
bogdanm 0:9b334a45a8ff 5171 /* C3 Bit Fields */
bogdanm 0:9b334a45a8ff 5172 #define UART_C3_PEIE_MASK 0x1u
bogdanm 0:9b334a45a8ff 5173 #define UART_C3_PEIE_SHIFT 0
bogdanm 0:9b334a45a8ff 5174 #define UART_C3_FEIE_MASK 0x2u
bogdanm 0:9b334a45a8ff 5175 #define UART_C3_FEIE_SHIFT 1
bogdanm 0:9b334a45a8ff 5176 #define UART_C3_NEIE_MASK 0x4u
bogdanm 0:9b334a45a8ff 5177 #define UART_C3_NEIE_SHIFT 2
bogdanm 0:9b334a45a8ff 5178 #define UART_C3_ORIE_MASK 0x8u
bogdanm 0:9b334a45a8ff 5179 #define UART_C3_ORIE_SHIFT 3
bogdanm 0:9b334a45a8ff 5180 #define UART_C3_TXINV_MASK 0x10u
bogdanm 0:9b334a45a8ff 5181 #define UART_C3_TXINV_SHIFT 4
bogdanm 0:9b334a45a8ff 5182 #define UART_C3_TXDIR_MASK 0x20u
bogdanm 0:9b334a45a8ff 5183 #define UART_C3_TXDIR_SHIFT 5
bogdanm 0:9b334a45a8ff 5184 #define UART_C3_T8_MASK 0x40u
bogdanm 0:9b334a45a8ff 5185 #define UART_C3_T8_SHIFT 6
bogdanm 0:9b334a45a8ff 5186 #define UART_C3_R8_MASK 0x80u
bogdanm 0:9b334a45a8ff 5187 #define UART_C3_R8_SHIFT 7
bogdanm 0:9b334a45a8ff 5188 /* D Bit Fields */
bogdanm 0:9b334a45a8ff 5189 #define UART_D_R0T0_MASK 0x1u
bogdanm 0:9b334a45a8ff 5190 #define UART_D_R0T0_SHIFT 0
bogdanm 0:9b334a45a8ff 5191 #define UART_D_R1T1_MASK 0x2u
bogdanm 0:9b334a45a8ff 5192 #define UART_D_R1T1_SHIFT 1
bogdanm 0:9b334a45a8ff 5193 #define UART_D_R2T2_MASK 0x4u
bogdanm 0:9b334a45a8ff 5194 #define UART_D_R2T2_SHIFT 2
bogdanm 0:9b334a45a8ff 5195 #define UART_D_R3T3_MASK 0x8u
bogdanm 0:9b334a45a8ff 5196 #define UART_D_R3T3_SHIFT 3
bogdanm 0:9b334a45a8ff 5197 #define UART_D_R4T4_MASK 0x10u
bogdanm 0:9b334a45a8ff 5198 #define UART_D_R4T4_SHIFT 4
bogdanm 0:9b334a45a8ff 5199 #define UART_D_R5T5_MASK 0x20u
bogdanm 0:9b334a45a8ff 5200 #define UART_D_R5T5_SHIFT 5
bogdanm 0:9b334a45a8ff 5201 #define UART_D_R6T6_MASK 0x40u
bogdanm 0:9b334a45a8ff 5202 #define UART_D_R6T6_SHIFT 6
bogdanm 0:9b334a45a8ff 5203 #define UART_D_R7T7_MASK 0x80u
bogdanm 0:9b334a45a8ff 5204 #define UART_D_R7T7_SHIFT 7
bogdanm 0:9b334a45a8ff 5205 /* C4 Bit Fields */
bogdanm 0:9b334a45a8ff 5206 #define UART_C4_RDMAS_MASK 0x20u
bogdanm 0:9b334a45a8ff 5207 #define UART_C4_RDMAS_SHIFT 5
bogdanm 0:9b334a45a8ff 5208 #define UART_C4_TDMAS_MASK 0x80u
bogdanm 0:9b334a45a8ff 5209 #define UART_C4_TDMAS_SHIFT 7
bogdanm 0:9b334a45a8ff 5210
bogdanm 0:9b334a45a8ff 5211 /*!
bogdanm 0:9b334a45a8ff 5212 * @}
bogdanm 0:9b334a45a8ff 5213 */ /* end of group UART_Register_Masks */
bogdanm 0:9b334a45a8ff 5214
bogdanm 0:9b334a45a8ff 5215
bogdanm 0:9b334a45a8ff 5216 /* UART - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 5217 /** Peripheral UART1 base address */
bogdanm 0:9b334a45a8ff 5218 #define UART1_BASE (0x4006B000u)
bogdanm 0:9b334a45a8ff 5219 /** Peripheral UART1 base pointer */
bogdanm 0:9b334a45a8ff 5220 #define UART1 ((UART_Type *)UART1_BASE)
bogdanm 0:9b334a45a8ff 5221 /** Peripheral UART2 base address */
bogdanm 0:9b334a45a8ff 5222 #define UART2_BASE (0x4006C000u)
bogdanm 0:9b334a45a8ff 5223 /** Peripheral UART2 base pointer */
bogdanm 0:9b334a45a8ff 5224 #define UART2 ((UART_Type *)UART2_BASE)
bogdanm 0:9b334a45a8ff 5225 /** Array initializer of UART peripheral base pointers */
bogdanm 0:9b334a45a8ff 5226 #define UART_BASES { UART1, UART2 }
bogdanm 0:9b334a45a8ff 5227
bogdanm 0:9b334a45a8ff 5228 /*!
bogdanm 0:9b334a45a8ff 5229 * @}
bogdanm 0:9b334a45a8ff 5230 */ /* end of group UART_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 5231
bogdanm 0:9b334a45a8ff 5232
bogdanm 0:9b334a45a8ff 5233 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 5234 -- UART0 Peripheral Access Layer
bogdanm 0:9b334a45a8ff 5235 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 5236
bogdanm 0:9b334a45a8ff 5237 /*!
bogdanm 0:9b334a45a8ff 5238 * @addtogroup UART0_Peripheral_Access_Layer UART0 Peripheral Access Layer
bogdanm 0:9b334a45a8ff 5239 * @{
bogdanm 0:9b334a45a8ff 5240 */
bogdanm 0:9b334a45a8ff 5241
bogdanm 0:9b334a45a8ff 5242 /** UART0 - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 5243 typedef struct {
bogdanm 0:9b334a45a8ff 5244 __IO uint8_t BDH; /**< UART Baud Rate Register High, offset: 0x0 */
bogdanm 0:9b334a45a8ff 5245 __IO uint8_t BDL; /**< UART Baud Rate Register Low, offset: 0x1 */
bogdanm 0:9b334a45a8ff 5246 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
bogdanm 0:9b334a45a8ff 5247 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
bogdanm 0:9b334a45a8ff 5248 __IO uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
bogdanm 0:9b334a45a8ff 5249 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
bogdanm 0:9b334a45a8ff 5250 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
bogdanm 0:9b334a45a8ff 5251 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
bogdanm 0:9b334a45a8ff 5252 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
bogdanm 0:9b334a45a8ff 5253 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
bogdanm 0:9b334a45a8ff 5254 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
bogdanm 0:9b334a45a8ff 5255 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
bogdanm 0:9b334a45a8ff 5256 } UART0_Type;
bogdanm 0:9b334a45a8ff 5257
bogdanm 0:9b334a45a8ff 5258 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 5259 -- UART0 Register Masks
bogdanm 0:9b334a45a8ff 5260 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 5261
bogdanm 0:9b334a45a8ff 5262 /*!
bogdanm 0:9b334a45a8ff 5263 * @addtogroup UART0_Register_Masks UART0 Register Masks
bogdanm 0:9b334a45a8ff 5264 * @{
bogdanm 0:9b334a45a8ff 5265 */
bogdanm 0:9b334a45a8ff 5266
bogdanm 0:9b334a45a8ff 5267 /* BDH Bit Fields */
bogdanm 0:9b334a45a8ff 5268 #define UART0_BDH_SBR_MASK 0x1Fu
bogdanm 0:9b334a45a8ff 5269 #define UART0_BDH_SBR_SHIFT 0
bogdanm 0:9b334a45a8ff 5270 #define UART0_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART0_BDH_SBR_SHIFT))&UART0_BDH_SBR_MASK)
bogdanm 0:9b334a45a8ff 5271 #define UART0_BDH_SBNS_MASK 0x20u
bogdanm 0:9b334a45a8ff 5272 #define UART0_BDH_SBNS_SHIFT 5
bogdanm 0:9b334a45a8ff 5273 #define UART0_BDH_RXEDGIE_MASK 0x40u
bogdanm 0:9b334a45a8ff 5274 #define UART0_BDH_RXEDGIE_SHIFT 6
bogdanm 0:9b334a45a8ff 5275 #define UART0_BDH_LBKDIE_MASK 0x80u
bogdanm 0:9b334a45a8ff 5276 #define UART0_BDH_LBKDIE_SHIFT 7
bogdanm 0:9b334a45a8ff 5277 /* BDL Bit Fields */
bogdanm 0:9b334a45a8ff 5278 #define UART0_BDL_SBR_MASK 0xFFu
bogdanm 0:9b334a45a8ff 5279 #define UART0_BDL_SBR_SHIFT 0
bogdanm 0:9b334a45a8ff 5280 #define UART0_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART0_BDL_SBR_SHIFT))&UART0_BDL_SBR_MASK)
bogdanm 0:9b334a45a8ff 5281 /* C1 Bit Fields */
bogdanm 0:9b334a45a8ff 5282 #define UART0_C1_PT_MASK 0x1u
bogdanm 0:9b334a45a8ff 5283 #define UART0_C1_PT_SHIFT 0
bogdanm 0:9b334a45a8ff 5284 #define UART0_C1_PE_MASK 0x2u
bogdanm 0:9b334a45a8ff 5285 #define UART0_C1_PE_SHIFT 1
bogdanm 0:9b334a45a8ff 5286 #define UART0_C1_ILT_MASK 0x4u
bogdanm 0:9b334a45a8ff 5287 #define UART0_C1_ILT_SHIFT 2
bogdanm 0:9b334a45a8ff 5288 #define UART0_C1_WAKE_MASK 0x8u
bogdanm 0:9b334a45a8ff 5289 #define UART0_C1_WAKE_SHIFT 3
bogdanm 0:9b334a45a8ff 5290 #define UART0_C1_M_MASK 0x10u
bogdanm 0:9b334a45a8ff 5291 #define UART0_C1_M_SHIFT 4
bogdanm 0:9b334a45a8ff 5292 #define UART0_C1_RSRC_MASK 0x20u
bogdanm 0:9b334a45a8ff 5293 #define UART0_C1_RSRC_SHIFT 5
bogdanm 0:9b334a45a8ff 5294 #define UART0_C1_DOZEEN_MASK 0x40u
bogdanm 0:9b334a45a8ff 5295 #define UART0_C1_DOZEEN_SHIFT 6
bogdanm 0:9b334a45a8ff 5296 #define UART0_C1_LOOPS_MASK 0x80u
bogdanm 0:9b334a45a8ff 5297 #define UART0_C1_LOOPS_SHIFT 7
bogdanm 0:9b334a45a8ff 5298 /* C2 Bit Fields */
bogdanm 0:9b334a45a8ff 5299 #define UART0_C2_SBK_MASK 0x1u
bogdanm 0:9b334a45a8ff 5300 #define UART0_C2_SBK_SHIFT 0
bogdanm 0:9b334a45a8ff 5301 #define UART0_C2_RWU_MASK 0x2u
bogdanm 0:9b334a45a8ff 5302 #define UART0_C2_RWU_SHIFT 1
bogdanm 0:9b334a45a8ff 5303 #define UART0_C2_RE_MASK 0x4u
bogdanm 0:9b334a45a8ff 5304 #define UART0_C2_RE_SHIFT 2
bogdanm 0:9b334a45a8ff 5305 #define UART0_C2_TE_MASK 0x8u
bogdanm 0:9b334a45a8ff 5306 #define UART0_C2_TE_SHIFT 3
bogdanm 0:9b334a45a8ff 5307 #define UART0_C2_ILIE_MASK 0x10u
bogdanm 0:9b334a45a8ff 5308 #define UART0_C2_ILIE_SHIFT 4
bogdanm 0:9b334a45a8ff 5309 #define UART0_C2_RIE_MASK 0x20u
bogdanm 0:9b334a45a8ff 5310 #define UART0_C2_RIE_SHIFT 5
bogdanm 0:9b334a45a8ff 5311 #define UART0_C2_TCIE_MASK 0x40u
bogdanm 0:9b334a45a8ff 5312 #define UART0_C2_TCIE_SHIFT 6
bogdanm 0:9b334a45a8ff 5313 #define UART0_C2_TIE_MASK 0x80u
bogdanm 0:9b334a45a8ff 5314 #define UART0_C2_TIE_SHIFT 7
bogdanm 0:9b334a45a8ff 5315 /* S1 Bit Fields */
bogdanm 0:9b334a45a8ff 5316 #define UART0_S1_PF_MASK 0x1u
bogdanm 0:9b334a45a8ff 5317 #define UART0_S1_PF_SHIFT 0
bogdanm 0:9b334a45a8ff 5318 #define UART0_S1_FE_MASK 0x2u
bogdanm 0:9b334a45a8ff 5319 #define UART0_S1_FE_SHIFT 1
bogdanm 0:9b334a45a8ff 5320 #define UART0_S1_NF_MASK 0x4u
bogdanm 0:9b334a45a8ff 5321 #define UART0_S1_NF_SHIFT 2
bogdanm 0:9b334a45a8ff 5322 #define UART0_S1_OR_MASK 0x8u
bogdanm 0:9b334a45a8ff 5323 #define UART0_S1_OR_SHIFT 3
bogdanm 0:9b334a45a8ff 5324 #define UART0_S1_IDLE_MASK 0x10u
bogdanm 0:9b334a45a8ff 5325 #define UART0_S1_IDLE_SHIFT 4
bogdanm 0:9b334a45a8ff 5326 #define UART0_S1_RDRF_MASK 0x20u
bogdanm 0:9b334a45a8ff 5327 #define UART0_S1_RDRF_SHIFT 5
bogdanm 0:9b334a45a8ff 5328 #define UART0_S1_TC_MASK 0x40u
bogdanm 0:9b334a45a8ff 5329 #define UART0_S1_TC_SHIFT 6
bogdanm 0:9b334a45a8ff 5330 #define UART0_S1_TDRE_MASK 0x80u
bogdanm 0:9b334a45a8ff 5331 #define UART0_S1_TDRE_SHIFT 7
bogdanm 0:9b334a45a8ff 5332 /* S2 Bit Fields */
bogdanm 0:9b334a45a8ff 5333 #define UART0_S2_RAF_MASK 0x1u
bogdanm 0:9b334a45a8ff 5334 #define UART0_S2_RAF_SHIFT 0
bogdanm 0:9b334a45a8ff 5335 #define UART0_S2_LBKDE_MASK 0x2u
bogdanm 0:9b334a45a8ff 5336 #define UART0_S2_LBKDE_SHIFT 1
bogdanm 0:9b334a45a8ff 5337 #define UART0_S2_BRK13_MASK 0x4u
bogdanm 0:9b334a45a8ff 5338 #define UART0_S2_BRK13_SHIFT 2
bogdanm 0:9b334a45a8ff 5339 #define UART0_S2_RWUID_MASK 0x8u
bogdanm 0:9b334a45a8ff 5340 #define UART0_S2_RWUID_SHIFT 3
bogdanm 0:9b334a45a8ff 5341 #define UART0_S2_RXINV_MASK 0x10u
bogdanm 0:9b334a45a8ff 5342 #define UART0_S2_RXINV_SHIFT 4
bogdanm 0:9b334a45a8ff 5343 #define UART0_S2_MSBF_MASK 0x20u
bogdanm 0:9b334a45a8ff 5344 #define UART0_S2_MSBF_SHIFT 5
bogdanm 0:9b334a45a8ff 5345 #define UART0_S2_RXEDGIF_MASK 0x40u
bogdanm 0:9b334a45a8ff 5346 #define UART0_S2_RXEDGIF_SHIFT 6
bogdanm 0:9b334a45a8ff 5347 #define UART0_S2_LBKDIF_MASK 0x80u
bogdanm 0:9b334a45a8ff 5348 #define UART0_S2_LBKDIF_SHIFT 7
bogdanm 0:9b334a45a8ff 5349 /* C3 Bit Fields */
bogdanm 0:9b334a45a8ff 5350 #define UART0_C3_PEIE_MASK 0x1u
bogdanm 0:9b334a45a8ff 5351 #define UART0_C3_PEIE_SHIFT 0
bogdanm 0:9b334a45a8ff 5352 #define UART0_C3_FEIE_MASK 0x2u
bogdanm 0:9b334a45a8ff 5353 #define UART0_C3_FEIE_SHIFT 1
bogdanm 0:9b334a45a8ff 5354 #define UART0_C3_NEIE_MASK 0x4u
bogdanm 0:9b334a45a8ff 5355 #define UART0_C3_NEIE_SHIFT 2
bogdanm 0:9b334a45a8ff 5356 #define UART0_C3_ORIE_MASK 0x8u
bogdanm 0:9b334a45a8ff 5357 #define UART0_C3_ORIE_SHIFT 3
bogdanm 0:9b334a45a8ff 5358 #define UART0_C3_TXINV_MASK 0x10u
bogdanm 0:9b334a45a8ff 5359 #define UART0_C3_TXINV_SHIFT 4
bogdanm 0:9b334a45a8ff 5360 #define UART0_C3_TXDIR_MASK 0x20u
bogdanm 0:9b334a45a8ff 5361 #define UART0_C3_TXDIR_SHIFT 5
bogdanm 0:9b334a45a8ff 5362 #define UART0_C3_R9T8_MASK 0x40u
bogdanm 0:9b334a45a8ff 5363 #define UART0_C3_R9T8_SHIFT 6
bogdanm 0:9b334a45a8ff 5364 #define UART0_C3_R8T9_MASK 0x80u
bogdanm 0:9b334a45a8ff 5365 #define UART0_C3_R8T9_SHIFT 7
bogdanm 0:9b334a45a8ff 5366 /* D Bit Fields */
bogdanm 0:9b334a45a8ff 5367 #define UART0_D_R0T0_MASK 0x1u
bogdanm 0:9b334a45a8ff 5368 #define UART0_D_R0T0_SHIFT 0
bogdanm 0:9b334a45a8ff 5369 #define UART0_D_R1T1_MASK 0x2u
bogdanm 0:9b334a45a8ff 5370 #define UART0_D_R1T1_SHIFT 1
bogdanm 0:9b334a45a8ff 5371 #define UART0_D_R2T2_MASK 0x4u
bogdanm 0:9b334a45a8ff 5372 #define UART0_D_R2T2_SHIFT 2
bogdanm 0:9b334a45a8ff 5373 #define UART0_D_R3T3_MASK 0x8u
bogdanm 0:9b334a45a8ff 5374 #define UART0_D_R3T3_SHIFT 3
bogdanm 0:9b334a45a8ff 5375 #define UART0_D_R4T4_MASK 0x10u
bogdanm 0:9b334a45a8ff 5376 #define UART0_D_R4T4_SHIFT 4
bogdanm 0:9b334a45a8ff 5377 #define UART0_D_R5T5_MASK 0x20u
bogdanm 0:9b334a45a8ff 5378 #define UART0_D_R5T5_SHIFT 5
bogdanm 0:9b334a45a8ff 5379 #define UART0_D_R6T6_MASK 0x40u
bogdanm 0:9b334a45a8ff 5380 #define UART0_D_R6T6_SHIFT 6
bogdanm 0:9b334a45a8ff 5381 #define UART0_D_R7T7_MASK 0x80u
bogdanm 0:9b334a45a8ff 5382 #define UART0_D_R7T7_SHIFT 7
bogdanm 0:9b334a45a8ff 5383 /* MA1 Bit Fields */
bogdanm 0:9b334a45a8ff 5384 #define UART0_MA1_MA_MASK 0xFFu
bogdanm 0:9b334a45a8ff 5385 #define UART0_MA1_MA_SHIFT 0
bogdanm 0:9b334a45a8ff 5386 #define UART0_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART0_MA1_MA_SHIFT))&UART0_MA1_MA_MASK)
bogdanm 0:9b334a45a8ff 5387 /* MA2 Bit Fields */
bogdanm 0:9b334a45a8ff 5388 #define UART0_MA2_MA_MASK 0xFFu
bogdanm 0:9b334a45a8ff 5389 #define UART0_MA2_MA_SHIFT 0
bogdanm 0:9b334a45a8ff 5390 #define UART0_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART0_MA2_MA_SHIFT))&UART0_MA2_MA_MASK)
bogdanm 0:9b334a45a8ff 5391 /* C4 Bit Fields */
bogdanm 0:9b334a45a8ff 5392 #define UART0_C4_OSR_MASK 0x1Fu
bogdanm 0:9b334a45a8ff 5393 #define UART0_C4_OSR_SHIFT 0
bogdanm 0:9b334a45a8ff 5394 #define UART0_C4_OSR(x) (((uint8_t)(((uint8_t)(x))<<UART0_C4_OSR_SHIFT))&UART0_C4_OSR_MASK)
bogdanm 0:9b334a45a8ff 5395 #define UART0_C4_M10_MASK 0x20u
bogdanm 0:9b334a45a8ff 5396 #define UART0_C4_M10_SHIFT 5
bogdanm 0:9b334a45a8ff 5397 #define UART0_C4_MAEN2_MASK 0x40u
bogdanm 0:9b334a45a8ff 5398 #define UART0_C4_MAEN2_SHIFT 6
bogdanm 0:9b334a45a8ff 5399 #define UART0_C4_MAEN1_MASK 0x80u
bogdanm 0:9b334a45a8ff 5400 #define UART0_C4_MAEN1_SHIFT 7
bogdanm 0:9b334a45a8ff 5401 /* C5 Bit Fields */
bogdanm 0:9b334a45a8ff 5402 #define UART0_C5_RESYNCDIS_MASK 0x1u
bogdanm 0:9b334a45a8ff 5403 #define UART0_C5_RESYNCDIS_SHIFT 0
bogdanm 0:9b334a45a8ff 5404 #define UART0_C5_BOTHEDGE_MASK 0x2u
bogdanm 0:9b334a45a8ff 5405 #define UART0_C5_BOTHEDGE_SHIFT 1
bogdanm 0:9b334a45a8ff 5406 #define UART0_C5_RDMAE_MASK 0x20u
bogdanm 0:9b334a45a8ff 5407 #define UART0_C5_RDMAE_SHIFT 5
bogdanm 0:9b334a45a8ff 5408 #define UART0_C5_TDMAE_MASK 0x80u
bogdanm 0:9b334a45a8ff 5409 #define UART0_C5_TDMAE_SHIFT 7
bogdanm 0:9b334a45a8ff 5410
bogdanm 0:9b334a45a8ff 5411 /*!
bogdanm 0:9b334a45a8ff 5412 * @}
bogdanm 0:9b334a45a8ff 5413 */ /* end of group UART0_Register_Masks */
bogdanm 0:9b334a45a8ff 5414
bogdanm 0:9b334a45a8ff 5415
bogdanm 0:9b334a45a8ff 5416 /* UART0 - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 5417 /** Peripheral UART0 base address */
bogdanm 0:9b334a45a8ff 5418 #define UART0_BASE (0x4006A000u)
bogdanm 0:9b334a45a8ff 5419 /** Peripheral UART0 base pointer */
bogdanm 0:9b334a45a8ff 5420 #define UART0 ((UART0_Type *)UART0_BASE)
bogdanm 0:9b334a45a8ff 5421 /** Array initializer of UART0 peripheral base pointers */
bogdanm 0:9b334a45a8ff 5422 #define UART0_BASES { UART0 }
bogdanm 0:9b334a45a8ff 5423
bogdanm 0:9b334a45a8ff 5424 /*!
bogdanm 0:9b334a45a8ff 5425 * @}
bogdanm 0:9b334a45a8ff 5426 */ /* end of group UART0_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 5427
bogdanm 0:9b334a45a8ff 5428
bogdanm 0:9b334a45a8ff 5429 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 5430 -- USB Peripheral Access Layer
bogdanm 0:9b334a45a8ff 5431 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 5432
bogdanm 0:9b334a45a8ff 5433 /*!
bogdanm 0:9b334a45a8ff 5434 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
bogdanm 0:9b334a45a8ff 5435 * @{
bogdanm 0:9b334a45a8ff 5436 */
bogdanm 0:9b334a45a8ff 5437
bogdanm 0:9b334a45a8ff 5438 /** USB - Register Layout Typedef */
bogdanm 0:9b334a45a8ff 5439 typedef struct {
bogdanm 0:9b334a45a8ff 5440 __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
bogdanm 0:9b334a45a8ff 5441 uint8_t RESERVED_0[3];
bogdanm 0:9b334a45a8ff 5442 __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
bogdanm 0:9b334a45a8ff 5443 uint8_t RESERVED_1[3];
bogdanm 0:9b334a45a8ff 5444 __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
bogdanm 0:9b334a45a8ff 5445 uint8_t RESERVED_2[3];
bogdanm 0:9b334a45a8ff 5446 __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
bogdanm 0:9b334a45a8ff 5447 uint8_t RESERVED_3[3];
bogdanm 0:9b334a45a8ff 5448 __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
bogdanm 0:9b334a45a8ff 5449 uint8_t RESERVED_4[3];
bogdanm 0:9b334a45a8ff 5450 __IO uint8_t OTGICR; /**< OTG Interrupt Control Register, offset: 0x14 */
bogdanm 0:9b334a45a8ff 5451 uint8_t RESERVED_5[3];
bogdanm 0:9b334a45a8ff 5452 __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
bogdanm 0:9b334a45a8ff 5453 uint8_t RESERVED_6[3];
bogdanm 0:9b334a45a8ff 5454 __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
bogdanm 0:9b334a45a8ff 5455 uint8_t RESERVED_7[99];
bogdanm 0:9b334a45a8ff 5456 __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
bogdanm 0:9b334a45a8ff 5457 uint8_t RESERVED_8[3];
bogdanm 0:9b334a45a8ff 5458 __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
bogdanm 0:9b334a45a8ff 5459 uint8_t RESERVED_9[3];
bogdanm 0:9b334a45a8ff 5460 __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
bogdanm 0:9b334a45a8ff 5461 uint8_t RESERVED_10[3];
bogdanm 0:9b334a45a8ff 5462 __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
bogdanm 0:9b334a45a8ff 5463 uint8_t RESERVED_11[3];
bogdanm 0:9b334a45a8ff 5464 __I uint8_t STAT; /**< Status register, offset: 0x90 */
bogdanm 0:9b334a45a8ff 5465 uint8_t RESERVED_12[3];
bogdanm 0:9b334a45a8ff 5466 __IO uint8_t CTL; /**< Control register, offset: 0x94 */
bogdanm 0:9b334a45a8ff 5467 uint8_t RESERVED_13[3];
bogdanm 0:9b334a45a8ff 5468 __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
bogdanm 0:9b334a45a8ff 5469 uint8_t RESERVED_14[3];
bogdanm 0:9b334a45a8ff 5470 __IO uint8_t BDTPAGE1; /**< BDT Page Register 1, offset: 0x9C */
bogdanm 0:9b334a45a8ff 5471 uint8_t RESERVED_15[3];
bogdanm 0:9b334a45a8ff 5472 __IO uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */
bogdanm 0:9b334a45a8ff 5473 uint8_t RESERVED_16[3];
bogdanm 0:9b334a45a8ff 5474 __IO uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */
bogdanm 0:9b334a45a8ff 5475 uint8_t RESERVED_17[3];
bogdanm 0:9b334a45a8ff 5476 __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
bogdanm 0:9b334a45a8ff 5477 uint8_t RESERVED_18[3];
bogdanm 0:9b334a45a8ff 5478 __IO uint8_t SOFTHLD; /**< SOF Threshold Register, offset: 0xAC */
bogdanm 0:9b334a45a8ff 5479 uint8_t RESERVED_19[3];
bogdanm 0:9b334a45a8ff 5480 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
bogdanm 0:9b334a45a8ff 5481 uint8_t RESERVED_20[3];
bogdanm 0:9b334a45a8ff 5482 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
bogdanm 0:9b334a45a8ff 5483 uint8_t RESERVED_21[11];
bogdanm 0:9b334a45a8ff 5484 struct { /* offset: 0xC0, array step: 0x4 */
bogdanm 0:9b334a45a8ff 5485 __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
bogdanm 0:9b334a45a8ff 5486 uint8_t RESERVED_0[3];
bogdanm 0:9b334a45a8ff 5487 } ENDPOINT[16];
bogdanm 0:9b334a45a8ff 5488 __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
bogdanm 0:9b334a45a8ff 5489 uint8_t RESERVED_22[3];
bogdanm 0:9b334a45a8ff 5490 __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
bogdanm 0:9b334a45a8ff 5491 uint8_t RESERVED_23[3];
bogdanm 0:9b334a45a8ff 5492 __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
bogdanm 0:9b334a45a8ff 5493 uint8_t RESERVED_24[3];
bogdanm 0:9b334a45a8ff 5494 __IO uint8_t USBTRC0; /**< USB Transceiver Control Register 0, offset: 0x10C */
bogdanm 0:9b334a45a8ff 5495 uint8_t RESERVED_25[7];
bogdanm 0:9b334a45a8ff 5496 __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
bogdanm 0:9b334a45a8ff 5497 } USB_Type;
bogdanm 0:9b334a45a8ff 5498
bogdanm 0:9b334a45a8ff 5499 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 5500 -- USB Register Masks
bogdanm 0:9b334a45a8ff 5501 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 5502
bogdanm 0:9b334a45a8ff 5503 /*!
bogdanm 0:9b334a45a8ff 5504 * @addtogroup USB_Register_Masks USB Register Masks
bogdanm 0:9b334a45a8ff 5505 * @{
bogdanm 0:9b334a45a8ff 5506 */
bogdanm 0:9b334a45a8ff 5507
bogdanm 0:9b334a45a8ff 5508 /* PERID Bit Fields */
bogdanm 0:9b334a45a8ff 5509 #define USB_PERID_ID_MASK 0x3Fu
bogdanm 0:9b334a45a8ff 5510 #define USB_PERID_ID_SHIFT 0
bogdanm 0:9b334a45a8ff 5511 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
bogdanm 0:9b334a45a8ff 5512 /* IDCOMP Bit Fields */
bogdanm 0:9b334a45a8ff 5513 #define USB_IDCOMP_NID_MASK 0x3Fu
bogdanm 0:9b334a45a8ff 5514 #define USB_IDCOMP_NID_SHIFT 0
bogdanm 0:9b334a45a8ff 5515 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
bogdanm 0:9b334a45a8ff 5516 /* REV Bit Fields */
bogdanm 0:9b334a45a8ff 5517 #define USB_REV_REV_MASK 0xFFu
bogdanm 0:9b334a45a8ff 5518 #define USB_REV_REV_SHIFT 0
bogdanm 0:9b334a45a8ff 5519 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
bogdanm 0:9b334a45a8ff 5520 /* ADDINFO Bit Fields */
bogdanm 0:9b334a45a8ff 5521 #define USB_ADDINFO_IEHOST_MASK 0x1u
bogdanm 0:9b334a45a8ff 5522 #define USB_ADDINFO_IEHOST_SHIFT 0
bogdanm 0:9b334a45a8ff 5523 #define USB_ADDINFO_IRQNUM_MASK 0xF8u
bogdanm 0:9b334a45a8ff 5524 #define USB_ADDINFO_IRQNUM_SHIFT 3
bogdanm 0:9b334a45a8ff 5525 #define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
bogdanm 0:9b334a45a8ff 5526 /* OTGISTAT Bit Fields */
bogdanm 0:9b334a45a8ff 5527 #define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
bogdanm 0:9b334a45a8ff 5528 #define USB_OTGISTAT_AVBUSCHG_SHIFT 0
bogdanm 0:9b334a45a8ff 5529 #define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
bogdanm 0:9b334a45a8ff 5530 #define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
bogdanm 0:9b334a45a8ff 5531 #define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
bogdanm 0:9b334a45a8ff 5532 #define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
bogdanm 0:9b334a45a8ff 5533 #define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
bogdanm 0:9b334a45a8ff 5534 #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
bogdanm 0:9b334a45a8ff 5535 #define USB_OTGISTAT_ONEMSEC_MASK 0x40u
bogdanm 0:9b334a45a8ff 5536 #define USB_OTGISTAT_ONEMSEC_SHIFT 6
bogdanm 0:9b334a45a8ff 5537 #define USB_OTGISTAT_IDCHG_MASK 0x80u
bogdanm 0:9b334a45a8ff 5538 #define USB_OTGISTAT_IDCHG_SHIFT 7
bogdanm 0:9b334a45a8ff 5539 /* OTGICR Bit Fields */
bogdanm 0:9b334a45a8ff 5540 #define USB_OTGICR_AVBUSEN_MASK 0x1u
bogdanm 0:9b334a45a8ff 5541 #define USB_OTGICR_AVBUSEN_SHIFT 0
bogdanm 0:9b334a45a8ff 5542 #define USB_OTGICR_BSESSEN_MASK 0x4u
bogdanm 0:9b334a45a8ff 5543 #define USB_OTGICR_BSESSEN_SHIFT 2
bogdanm 0:9b334a45a8ff 5544 #define USB_OTGICR_SESSVLDEN_MASK 0x8u
bogdanm 0:9b334a45a8ff 5545 #define USB_OTGICR_SESSVLDEN_SHIFT 3
bogdanm 0:9b334a45a8ff 5546 #define USB_OTGICR_LINESTATEEN_MASK 0x20u
bogdanm 0:9b334a45a8ff 5547 #define USB_OTGICR_LINESTATEEN_SHIFT 5
bogdanm 0:9b334a45a8ff 5548 #define USB_OTGICR_ONEMSECEN_MASK 0x40u
bogdanm 0:9b334a45a8ff 5549 #define USB_OTGICR_ONEMSECEN_SHIFT 6
bogdanm 0:9b334a45a8ff 5550 #define USB_OTGICR_IDEN_MASK 0x80u
bogdanm 0:9b334a45a8ff 5551 #define USB_OTGICR_IDEN_SHIFT 7
bogdanm 0:9b334a45a8ff 5552 /* OTGSTAT Bit Fields */
bogdanm 0:9b334a45a8ff 5553 #define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
bogdanm 0:9b334a45a8ff 5554 #define USB_OTGSTAT_AVBUSVLD_SHIFT 0
bogdanm 0:9b334a45a8ff 5555 #define USB_OTGSTAT_BSESSEND_MASK 0x4u
bogdanm 0:9b334a45a8ff 5556 #define USB_OTGSTAT_BSESSEND_SHIFT 2
bogdanm 0:9b334a45a8ff 5557 #define USB_OTGSTAT_SESS_VLD_MASK 0x8u
bogdanm 0:9b334a45a8ff 5558 #define USB_OTGSTAT_SESS_VLD_SHIFT 3
bogdanm 0:9b334a45a8ff 5559 #define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
bogdanm 0:9b334a45a8ff 5560 #define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
bogdanm 0:9b334a45a8ff 5561 #define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
bogdanm 0:9b334a45a8ff 5562 #define USB_OTGSTAT_ONEMSECEN_SHIFT 6
bogdanm 0:9b334a45a8ff 5563 #define USB_OTGSTAT_ID_MASK 0x80u
bogdanm 0:9b334a45a8ff 5564 #define USB_OTGSTAT_ID_SHIFT 7
bogdanm 0:9b334a45a8ff 5565 /* OTGCTL Bit Fields */
bogdanm 0:9b334a45a8ff 5566 #define USB_OTGCTL_OTGEN_MASK 0x4u
bogdanm 0:9b334a45a8ff 5567 #define USB_OTGCTL_OTGEN_SHIFT 2
bogdanm 0:9b334a45a8ff 5568 #define USB_OTGCTL_DMLOW_MASK 0x10u
bogdanm 0:9b334a45a8ff 5569 #define USB_OTGCTL_DMLOW_SHIFT 4
bogdanm 0:9b334a45a8ff 5570 #define USB_OTGCTL_DPLOW_MASK 0x20u
bogdanm 0:9b334a45a8ff 5571 #define USB_OTGCTL_DPLOW_SHIFT 5
bogdanm 0:9b334a45a8ff 5572 #define USB_OTGCTL_DPHIGH_MASK 0x80u
bogdanm 0:9b334a45a8ff 5573 #define USB_OTGCTL_DPHIGH_SHIFT 7
bogdanm 0:9b334a45a8ff 5574 /* ISTAT Bit Fields */
bogdanm 0:9b334a45a8ff 5575 #define USB_ISTAT_USBRST_MASK 0x1u
bogdanm 0:9b334a45a8ff 5576 #define USB_ISTAT_USBRST_SHIFT 0
bogdanm 0:9b334a45a8ff 5577 #define USB_ISTAT_ERROR_MASK 0x2u
bogdanm 0:9b334a45a8ff 5578 #define USB_ISTAT_ERROR_SHIFT 1
bogdanm 0:9b334a45a8ff 5579 #define USB_ISTAT_SOFTOK_MASK 0x4u
bogdanm 0:9b334a45a8ff 5580 #define USB_ISTAT_SOFTOK_SHIFT 2
bogdanm 0:9b334a45a8ff 5581 #define USB_ISTAT_TOKDNE_MASK 0x8u
bogdanm 0:9b334a45a8ff 5582 #define USB_ISTAT_TOKDNE_SHIFT 3
bogdanm 0:9b334a45a8ff 5583 #define USB_ISTAT_SLEEP_MASK 0x10u
bogdanm 0:9b334a45a8ff 5584 #define USB_ISTAT_SLEEP_SHIFT 4
bogdanm 0:9b334a45a8ff 5585 #define USB_ISTAT_RESUME_MASK 0x20u
bogdanm 0:9b334a45a8ff 5586 #define USB_ISTAT_RESUME_SHIFT 5
bogdanm 0:9b334a45a8ff 5587 #define USB_ISTAT_ATTACH_MASK 0x40u
bogdanm 0:9b334a45a8ff 5588 #define USB_ISTAT_ATTACH_SHIFT 6
bogdanm 0:9b334a45a8ff 5589 #define USB_ISTAT_STALL_MASK 0x80u
bogdanm 0:9b334a45a8ff 5590 #define USB_ISTAT_STALL_SHIFT 7
bogdanm 0:9b334a45a8ff 5591 /* INTEN Bit Fields */
bogdanm 0:9b334a45a8ff 5592 #define USB_INTEN_USBRSTEN_MASK 0x1u
bogdanm 0:9b334a45a8ff 5593 #define USB_INTEN_USBRSTEN_SHIFT 0
bogdanm 0:9b334a45a8ff 5594 #define USB_INTEN_ERROREN_MASK 0x2u
bogdanm 0:9b334a45a8ff 5595 #define USB_INTEN_ERROREN_SHIFT 1
bogdanm 0:9b334a45a8ff 5596 #define USB_INTEN_SOFTOKEN_MASK 0x4u
bogdanm 0:9b334a45a8ff 5597 #define USB_INTEN_SOFTOKEN_SHIFT 2
bogdanm 0:9b334a45a8ff 5598 #define USB_INTEN_TOKDNEEN_MASK 0x8u
bogdanm 0:9b334a45a8ff 5599 #define USB_INTEN_TOKDNEEN_SHIFT 3
bogdanm 0:9b334a45a8ff 5600 #define USB_INTEN_SLEEPEN_MASK 0x10u
bogdanm 0:9b334a45a8ff 5601 #define USB_INTEN_SLEEPEN_SHIFT 4
bogdanm 0:9b334a45a8ff 5602 #define USB_INTEN_RESUMEEN_MASK 0x20u
bogdanm 0:9b334a45a8ff 5603 #define USB_INTEN_RESUMEEN_SHIFT 5
bogdanm 0:9b334a45a8ff 5604 #define USB_INTEN_ATTACHEN_MASK 0x40u
bogdanm 0:9b334a45a8ff 5605 #define USB_INTEN_ATTACHEN_SHIFT 6
bogdanm 0:9b334a45a8ff 5606 #define USB_INTEN_STALLEN_MASK 0x80u
bogdanm 0:9b334a45a8ff 5607 #define USB_INTEN_STALLEN_SHIFT 7
bogdanm 0:9b334a45a8ff 5608 /* ERRSTAT Bit Fields */
bogdanm 0:9b334a45a8ff 5609 #define USB_ERRSTAT_PIDERR_MASK 0x1u
bogdanm 0:9b334a45a8ff 5610 #define USB_ERRSTAT_PIDERR_SHIFT 0
bogdanm 0:9b334a45a8ff 5611 #define USB_ERRSTAT_CRC5EOF_MASK 0x2u
bogdanm 0:9b334a45a8ff 5612 #define USB_ERRSTAT_CRC5EOF_SHIFT 1
bogdanm 0:9b334a45a8ff 5613 #define USB_ERRSTAT_CRC16_MASK 0x4u
bogdanm 0:9b334a45a8ff 5614 #define USB_ERRSTAT_CRC16_SHIFT 2
bogdanm 0:9b334a45a8ff 5615 #define USB_ERRSTAT_DFN8_MASK 0x8u
bogdanm 0:9b334a45a8ff 5616 #define USB_ERRSTAT_DFN8_SHIFT 3
bogdanm 0:9b334a45a8ff 5617 #define USB_ERRSTAT_BTOERR_MASK 0x10u
bogdanm 0:9b334a45a8ff 5618 #define USB_ERRSTAT_BTOERR_SHIFT 4
bogdanm 0:9b334a45a8ff 5619 #define USB_ERRSTAT_DMAERR_MASK 0x20u
bogdanm 0:9b334a45a8ff 5620 #define USB_ERRSTAT_DMAERR_SHIFT 5
bogdanm 0:9b334a45a8ff 5621 #define USB_ERRSTAT_BTSERR_MASK 0x80u
bogdanm 0:9b334a45a8ff 5622 #define USB_ERRSTAT_BTSERR_SHIFT 7
bogdanm 0:9b334a45a8ff 5623 /* ERREN Bit Fields */
bogdanm 0:9b334a45a8ff 5624 #define USB_ERREN_PIDERREN_MASK 0x1u
bogdanm 0:9b334a45a8ff 5625 #define USB_ERREN_PIDERREN_SHIFT 0
bogdanm 0:9b334a45a8ff 5626 #define USB_ERREN_CRC5EOFEN_MASK 0x2u
bogdanm 0:9b334a45a8ff 5627 #define USB_ERREN_CRC5EOFEN_SHIFT 1
bogdanm 0:9b334a45a8ff 5628 #define USB_ERREN_CRC16EN_MASK 0x4u
bogdanm 0:9b334a45a8ff 5629 #define USB_ERREN_CRC16EN_SHIFT 2
bogdanm 0:9b334a45a8ff 5630 #define USB_ERREN_DFN8EN_MASK 0x8u
bogdanm 0:9b334a45a8ff 5631 #define USB_ERREN_DFN8EN_SHIFT 3
bogdanm 0:9b334a45a8ff 5632 #define USB_ERREN_BTOERREN_MASK 0x10u
bogdanm 0:9b334a45a8ff 5633 #define USB_ERREN_BTOERREN_SHIFT 4
bogdanm 0:9b334a45a8ff 5634 #define USB_ERREN_DMAERREN_MASK 0x20u
bogdanm 0:9b334a45a8ff 5635 #define USB_ERREN_DMAERREN_SHIFT 5
bogdanm 0:9b334a45a8ff 5636 #define USB_ERREN_BTSERREN_MASK 0x80u
bogdanm 0:9b334a45a8ff 5637 #define USB_ERREN_BTSERREN_SHIFT 7
bogdanm 0:9b334a45a8ff 5638 /* STAT Bit Fields */
bogdanm 0:9b334a45a8ff 5639 #define USB_STAT_ODD_MASK 0x4u
bogdanm 0:9b334a45a8ff 5640 #define USB_STAT_ODD_SHIFT 2
bogdanm 0:9b334a45a8ff 5641 #define USB_STAT_TX_MASK 0x8u
bogdanm 0:9b334a45a8ff 5642 #define USB_STAT_TX_SHIFT 3
bogdanm 0:9b334a45a8ff 5643 #define USB_STAT_ENDP_MASK 0xF0u
bogdanm 0:9b334a45a8ff 5644 #define USB_STAT_ENDP_SHIFT 4
bogdanm 0:9b334a45a8ff 5645 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
bogdanm 0:9b334a45a8ff 5646 /* CTL Bit Fields */
bogdanm 0:9b334a45a8ff 5647 #define USB_CTL_USBENSOFEN_MASK 0x1u
bogdanm 0:9b334a45a8ff 5648 #define USB_CTL_USBENSOFEN_SHIFT 0
bogdanm 0:9b334a45a8ff 5649 #define USB_CTL_ODDRST_MASK 0x2u
bogdanm 0:9b334a45a8ff 5650 #define USB_CTL_ODDRST_SHIFT 1
bogdanm 0:9b334a45a8ff 5651 #define USB_CTL_RESUME_MASK 0x4u
bogdanm 0:9b334a45a8ff 5652 #define USB_CTL_RESUME_SHIFT 2
bogdanm 0:9b334a45a8ff 5653 #define USB_CTL_HOSTMODEEN_MASK 0x8u
bogdanm 0:9b334a45a8ff 5654 #define USB_CTL_HOSTMODEEN_SHIFT 3
bogdanm 0:9b334a45a8ff 5655 #define USB_CTL_RESET_MASK 0x10u
bogdanm 0:9b334a45a8ff 5656 #define USB_CTL_RESET_SHIFT 4
bogdanm 0:9b334a45a8ff 5657 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
bogdanm 0:9b334a45a8ff 5658 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
bogdanm 0:9b334a45a8ff 5659 #define USB_CTL_SE0_MASK 0x40u
bogdanm 0:9b334a45a8ff 5660 #define USB_CTL_SE0_SHIFT 6
bogdanm 0:9b334a45a8ff 5661 #define USB_CTL_JSTATE_MASK 0x80u
bogdanm 0:9b334a45a8ff 5662 #define USB_CTL_JSTATE_SHIFT 7
bogdanm 0:9b334a45a8ff 5663 /* ADDR Bit Fields */
bogdanm 0:9b334a45a8ff 5664 #define USB_ADDR_ADDR_MASK 0x7Fu
bogdanm 0:9b334a45a8ff 5665 #define USB_ADDR_ADDR_SHIFT 0
bogdanm 0:9b334a45a8ff 5666 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
bogdanm 0:9b334a45a8ff 5667 #define USB_ADDR_LSEN_MASK 0x80u
bogdanm 0:9b334a45a8ff 5668 #define USB_ADDR_LSEN_SHIFT 7
bogdanm 0:9b334a45a8ff 5669 /* BDTPAGE1 Bit Fields */
bogdanm 0:9b334a45a8ff 5670 #define USB_BDTPAGE1_BDTBA_MASK 0xFEu
bogdanm 0:9b334a45a8ff 5671 #define USB_BDTPAGE1_BDTBA_SHIFT 1
bogdanm 0:9b334a45a8ff 5672 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
bogdanm 0:9b334a45a8ff 5673 /* FRMNUML Bit Fields */
bogdanm 0:9b334a45a8ff 5674 #define USB_FRMNUML_FRM_MASK 0xFFu
bogdanm 0:9b334a45a8ff 5675 #define USB_FRMNUML_FRM_SHIFT 0
bogdanm 0:9b334a45a8ff 5676 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
bogdanm 0:9b334a45a8ff 5677 /* FRMNUMH Bit Fields */
bogdanm 0:9b334a45a8ff 5678 #define USB_FRMNUMH_FRM_MASK 0x7u
bogdanm 0:9b334a45a8ff 5679 #define USB_FRMNUMH_FRM_SHIFT 0
bogdanm 0:9b334a45a8ff 5680 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
bogdanm 0:9b334a45a8ff 5681 /* TOKEN Bit Fields */
bogdanm 0:9b334a45a8ff 5682 #define USB_TOKEN_TOKENENDPT_MASK 0xFu
bogdanm 0:9b334a45a8ff 5683 #define USB_TOKEN_TOKENENDPT_SHIFT 0
bogdanm 0:9b334a45a8ff 5684 #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
bogdanm 0:9b334a45a8ff 5685 #define USB_TOKEN_TOKENPID_MASK 0xF0u
bogdanm 0:9b334a45a8ff 5686 #define USB_TOKEN_TOKENPID_SHIFT 4
bogdanm 0:9b334a45a8ff 5687 #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
bogdanm 0:9b334a45a8ff 5688 /* SOFTHLD Bit Fields */
bogdanm 0:9b334a45a8ff 5689 #define USB_SOFTHLD_CNT_MASK 0xFFu
bogdanm 0:9b334a45a8ff 5690 #define USB_SOFTHLD_CNT_SHIFT 0
bogdanm 0:9b334a45a8ff 5691 #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
bogdanm 0:9b334a45a8ff 5692 /* BDTPAGE2 Bit Fields */
bogdanm 0:9b334a45a8ff 5693 #define USB_BDTPAGE2_BDTBA_MASK 0xFFu
bogdanm 0:9b334a45a8ff 5694 #define USB_BDTPAGE2_BDTBA_SHIFT 0
bogdanm 0:9b334a45a8ff 5695 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
bogdanm 0:9b334a45a8ff 5696 /* BDTPAGE3 Bit Fields */
bogdanm 0:9b334a45a8ff 5697 #define USB_BDTPAGE3_BDTBA_MASK 0xFFu
bogdanm 0:9b334a45a8ff 5698 #define USB_BDTPAGE3_BDTBA_SHIFT 0
bogdanm 0:9b334a45a8ff 5699 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
bogdanm 0:9b334a45a8ff 5700 /* ENDPT Bit Fields */
bogdanm 0:9b334a45a8ff 5701 #define USB_ENDPT_EPHSHK_MASK 0x1u
bogdanm 0:9b334a45a8ff 5702 #define USB_ENDPT_EPHSHK_SHIFT 0
bogdanm 0:9b334a45a8ff 5703 #define USB_ENDPT_EPSTALL_MASK 0x2u
bogdanm 0:9b334a45a8ff 5704 #define USB_ENDPT_EPSTALL_SHIFT 1
bogdanm 0:9b334a45a8ff 5705 #define USB_ENDPT_EPTXEN_MASK 0x4u
bogdanm 0:9b334a45a8ff 5706 #define USB_ENDPT_EPTXEN_SHIFT 2
bogdanm 0:9b334a45a8ff 5707 #define USB_ENDPT_EPRXEN_MASK 0x8u
bogdanm 0:9b334a45a8ff 5708 #define USB_ENDPT_EPRXEN_SHIFT 3
bogdanm 0:9b334a45a8ff 5709 #define USB_ENDPT_EPCTLDIS_MASK 0x10u
bogdanm 0:9b334a45a8ff 5710 #define USB_ENDPT_EPCTLDIS_SHIFT 4
bogdanm 0:9b334a45a8ff 5711 #define USB_ENDPT_RETRYDIS_MASK 0x40u
bogdanm 0:9b334a45a8ff 5712 #define USB_ENDPT_RETRYDIS_SHIFT 6
bogdanm 0:9b334a45a8ff 5713 #define USB_ENDPT_HOSTWOHUB_MASK 0x80u
bogdanm 0:9b334a45a8ff 5714 #define USB_ENDPT_HOSTWOHUB_SHIFT 7
bogdanm 0:9b334a45a8ff 5715 /* USBCTRL Bit Fields */
bogdanm 0:9b334a45a8ff 5716 #define USB_USBCTRL_PDE_MASK 0x40u
bogdanm 0:9b334a45a8ff 5717 #define USB_USBCTRL_PDE_SHIFT 6
bogdanm 0:9b334a45a8ff 5718 #define USB_USBCTRL_SUSP_MASK 0x80u
bogdanm 0:9b334a45a8ff 5719 #define USB_USBCTRL_SUSP_SHIFT 7
bogdanm 0:9b334a45a8ff 5720 /* OBSERVE Bit Fields */
bogdanm 0:9b334a45a8ff 5721 #define USB_OBSERVE_DMPD_MASK 0x10u
bogdanm 0:9b334a45a8ff 5722 #define USB_OBSERVE_DMPD_SHIFT 4
bogdanm 0:9b334a45a8ff 5723 #define USB_OBSERVE_DPPD_MASK 0x40u
bogdanm 0:9b334a45a8ff 5724 #define USB_OBSERVE_DPPD_SHIFT 6
bogdanm 0:9b334a45a8ff 5725 #define USB_OBSERVE_DPPU_MASK 0x80u
bogdanm 0:9b334a45a8ff 5726 #define USB_OBSERVE_DPPU_SHIFT 7
bogdanm 0:9b334a45a8ff 5727 /* CONTROL Bit Fields */
bogdanm 0:9b334a45a8ff 5728 #define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
bogdanm 0:9b334a45a8ff 5729 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
bogdanm 0:9b334a45a8ff 5730 /* USBTRC0 Bit Fields */
bogdanm 0:9b334a45a8ff 5731 #define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
bogdanm 0:9b334a45a8ff 5732 #define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
bogdanm 0:9b334a45a8ff 5733 #define USB_USBTRC0_SYNC_DET_MASK 0x2u
bogdanm 0:9b334a45a8ff 5734 #define USB_USBTRC0_SYNC_DET_SHIFT 1
bogdanm 0:9b334a45a8ff 5735 #define USB_USBTRC0_USBRESMEN_MASK 0x20u
bogdanm 0:9b334a45a8ff 5736 #define USB_USBTRC0_USBRESMEN_SHIFT 5
bogdanm 0:9b334a45a8ff 5737 #define USB_USBTRC0_USBRESET_MASK 0x80u
bogdanm 0:9b334a45a8ff 5738 #define USB_USBTRC0_USBRESET_SHIFT 7
bogdanm 0:9b334a45a8ff 5739 /* USBFRMADJUST Bit Fields */
bogdanm 0:9b334a45a8ff 5740 #define USB_USBFRMADJUST_ADJ_MASK 0xFFu
bogdanm 0:9b334a45a8ff 5741 #define USB_USBFRMADJUST_ADJ_SHIFT 0
bogdanm 0:9b334a45a8ff 5742 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
bogdanm 0:9b334a45a8ff 5743
bogdanm 0:9b334a45a8ff 5744 /*!
bogdanm 0:9b334a45a8ff 5745 * @}
bogdanm 0:9b334a45a8ff 5746 */ /* end of group USB_Register_Masks */
bogdanm 0:9b334a45a8ff 5747
bogdanm 0:9b334a45a8ff 5748
bogdanm 0:9b334a45a8ff 5749 /* USB - Peripheral instance base addresses */
bogdanm 0:9b334a45a8ff 5750 /** Peripheral USB0 base address */
bogdanm 0:9b334a45a8ff 5751 #define USB0_BASE (0x40072000u)
bogdanm 0:9b334a45a8ff 5752 /** Peripheral USB0 base pointer */
bogdanm 0:9b334a45a8ff 5753 #define USB0 ((USB_Type *)USB0_BASE)
bogdanm 0:9b334a45a8ff 5754 /** Array initializer of USB peripheral base pointers */
bogdanm 0:9b334a45a8ff 5755 #define USB_BASES { USB0 }
bogdanm 0:9b334a45a8ff 5756
bogdanm 0:9b334a45a8ff 5757 /*!
bogdanm 0:9b334a45a8ff 5758 * @}
bogdanm 0:9b334a45a8ff 5759 */ /* end of group USB_Peripheral_Access_Layer */
bogdanm 0:9b334a45a8ff 5760
bogdanm 0:9b334a45a8ff 5761
bogdanm 0:9b334a45a8ff 5762 /*
bogdanm 0:9b334a45a8ff 5763 ** End of section using anonymous unions
bogdanm 0:9b334a45a8ff 5764 */
bogdanm 0:9b334a45a8ff 5765
bogdanm 0:9b334a45a8ff 5766 #if defined(__ARMCC_VERSION)
bogdanm 0:9b334a45a8ff 5767 #pragma pop
bogdanm 0:9b334a45a8ff 5768 #elif defined(__CWCC__)
bogdanm 0:9b334a45a8ff 5769 #pragma pop
bogdanm 0:9b334a45a8ff 5770 #elif defined(__GNUC__)
bogdanm 0:9b334a45a8ff 5771 /* leave anonymous unions enabled */
bogdanm 0:9b334a45a8ff 5772 #elif defined(__IAR_SYSTEMS_ICC__)
bogdanm 0:9b334a45a8ff 5773 #pragma language=default
bogdanm 0:9b334a45a8ff 5774 #else
bogdanm 0:9b334a45a8ff 5775 #error Not supported compiler type
bogdanm 0:9b334a45a8ff 5776 #endif
bogdanm 0:9b334a45a8ff 5777
bogdanm 0:9b334a45a8ff 5778 /*!
bogdanm 0:9b334a45a8ff 5779 * @}
bogdanm 0:9b334a45a8ff 5780 */ /* end of group Peripheral_access_layer */
bogdanm 0:9b334a45a8ff 5781
bogdanm 0:9b334a45a8ff 5782
bogdanm 0:9b334a45a8ff 5783 /* ----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 5784 -- Backward Compatibility
bogdanm 0:9b334a45a8ff 5785 ---------------------------------------------------------------------------- */
bogdanm 0:9b334a45a8ff 5786
bogdanm 0:9b334a45a8ff 5787 /*!
bogdanm 0:9b334a45a8ff 5788 * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
bogdanm 0:9b334a45a8ff 5789 * @{
bogdanm 0:9b334a45a8ff 5790 */
bogdanm 0:9b334a45a8ff 5791
bogdanm 0:9b334a45a8ff 5792 /* No backward compatibility issues. */
bogdanm 0:9b334a45a8ff 5793
bogdanm 0:9b334a45a8ff 5794 /*!
bogdanm 0:9b334a45a8ff 5795 * @}
bogdanm 0:9b334a45a8ff 5796 */ /* end of group Backward_Compatibility_Symbols */
bogdanm 0:9b334a45a8ff 5797
bogdanm 0:9b334a45a8ff 5798
bogdanm 0:9b334a45a8ff 5799 #endif /* #if !defined(MKL46Z4_H_) */
bogdanm 0:9b334a45a8ff 5800
bogdanm 0:9b334a45a8ff 5801 /* MKL46Z4.h, eof. */