Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F51212.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
121:7f86b4238bec
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /*
bogdanm 0:9b334a45a8ff 2 ** ###################################################################
bogdanm 0:9b334a45a8ff 3 ** Compilers: Keil ARM C/C++ Compiler
bogdanm 0:9b334a45a8ff 4 ** Freescale C/C++ for Embedded ARM
bogdanm 0:9b334a45a8ff 5 ** GNU C Compiler
bogdanm 0:9b334a45a8ff 6 ** GNU C Compiler - CodeSourcery Sourcery G++
bogdanm 0:9b334a45a8ff 7 ** IAR ANSI C/C++ Compiler for ARM
bogdanm 0:9b334a45a8ff 8 **
bogdanm 0:9b334a45a8ff 9 ** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
bogdanm 0:9b334a45a8ff 10 ** Version: rev. 2.5, 2014-05-06
bogdanm 0:9b334a45a8ff 11 ** Build: b140611
bogdanm 0:9b334a45a8ff 12 **
bogdanm 0:9b334a45a8ff 13 ** Abstract:
bogdanm 0:9b334a45a8ff 14 ** Provides a system configuration function and a global variable that
bogdanm 0:9b334a45a8ff 15 ** contains the system frequency. It configures the device and initializes
bogdanm 0:9b334a45a8ff 16 ** the oscillator (PLL) that is part of the microcontroller device.
bogdanm 0:9b334a45a8ff 17 **
bogdanm 0:9b334a45a8ff 18 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
bogdanm 0:9b334a45a8ff 19 ** All rights reserved.
bogdanm 0:9b334a45a8ff 20 **
bogdanm 0:9b334a45a8ff 21 ** Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 22 ** are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 23 **
bogdanm 0:9b334a45a8ff 24 ** o Redistributions of source code must retain the above copyright notice, this list
bogdanm 0:9b334a45a8ff 25 ** of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 26 **
bogdanm 0:9b334a45a8ff 27 ** o Redistributions in binary form must reproduce the above copyright notice, this
bogdanm 0:9b334a45a8ff 28 ** list of conditions and the following disclaimer in the documentation and/or
bogdanm 0:9b334a45a8ff 29 ** other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 30 **
bogdanm 0:9b334a45a8ff 31 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
bogdanm 0:9b334a45a8ff 32 ** contributors may be used to endorse or promote products derived from this
bogdanm 0:9b334a45a8ff 33 ** software without specific prior written permission.
bogdanm 0:9b334a45a8ff 34 **
bogdanm 0:9b334a45a8ff 35 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
bogdanm 0:9b334a45a8ff 36 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
bogdanm 0:9b334a45a8ff 37 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 38 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
bogdanm 0:9b334a45a8ff 39 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
bogdanm 0:9b334a45a8ff 40 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
bogdanm 0:9b334a45a8ff 41 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
bogdanm 0:9b334a45a8ff 42 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
bogdanm 0:9b334a45a8ff 43 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
bogdanm 0:9b334a45a8ff 44 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 45 **
bogdanm 0:9b334a45a8ff 46 ** http: www.freescale.com
bogdanm 0:9b334a45a8ff 47 ** mail: support@freescale.com
bogdanm 0:9b334a45a8ff 48 **
bogdanm 0:9b334a45a8ff 49 ** Revisions:
bogdanm 0:9b334a45a8ff 50 ** - rev. 1.0 (2013-07-23)
bogdanm 0:9b334a45a8ff 51 ** Initial version.
bogdanm 0:9b334a45a8ff 52 ** - rev. 1.1 (2013-09-17)
bogdanm 0:9b334a45a8ff 53 ** RM rev. 0.4 update.
bogdanm 0:9b334a45a8ff 54 ** - rev. 2.0 (2013-10-29)
bogdanm 0:9b334a45a8ff 55 ** Register accessor macros added to the memory map.
bogdanm 0:9b334a45a8ff 56 ** Symbols for Processor Expert memory map compatibility added to the memory map.
bogdanm 0:9b334a45a8ff 57 ** Startup file for gcc has been updated according to CMSIS 3.2.
bogdanm 0:9b334a45a8ff 58 ** System initialization updated.
bogdanm 0:9b334a45a8ff 59 ** - rev. 2.1 (2013-10-30)
bogdanm 0:9b334a45a8ff 60 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
bogdanm 0:9b334a45a8ff 61 ** - rev. 2.2 (2013-12-20)
bogdanm 0:9b334a45a8ff 62 ** Update according to reference manual rev. 0.6,
bogdanm 0:9b334a45a8ff 63 ** - rev. 2.3 (2014-01-13)
bogdanm 0:9b334a45a8ff 64 ** Update according to reference manual rev. 0.61,
bogdanm 0:9b334a45a8ff 65 ** - rev. 2.4 (2014-02-10)
bogdanm 0:9b334a45a8ff 66 ** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
bogdanm 0:9b334a45a8ff 67 ** - rev. 2.5 (2014-05-06)
bogdanm 0:9b334a45a8ff 68 ** Update according to reference manual rev. 1.0,
bogdanm 0:9b334a45a8ff 69 ** Update of system and startup files.
bogdanm 0:9b334a45a8ff 70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
bogdanm 0:9b334a45a8ff 71 **
bogdanm 0:9b334a45a8ff 72 ** ###################################################################
bogdanm 0:9b334a45a8ff 73 */
bogdanm 0:9b334a45a8ff 74
bogdanm 0:9b334a45a8ff 75 /*!
bogdanm 0:9b334a45a8ff 76 * @file MK22F51212
bogdanm 0:9b334a45a8ff 77 * @version 2.5
bogdanm 0:9b334a45a8ff 78 * @date 2014-05-06
bogdanm 0:9b334a45a8ff 79 * @brief Device specific configuration file for MK22F51212 (header file)
bogdanm 0:9b334a45a8ff 80 *
bogdanm 0:9b334a45a8ff 81 * Provides a system configuration function and a global variable that contains
bogdanm 0:9b334a45a8ff 82 * the system frequency. It configures the device and initializes the oscillator
bogdanm 0:9b334a45a8ff 83 * (PLL) that is part of the microcontroller device.
bogdanm 0:9b334a45a8ff 84 */
bogdanm 0:9b334a45a8ff 85
bogdanm 0:9b334a45a8ff 86 #ifndef SYSTEM_MK22F51212_H_
bogdanm 0:9b334a45a8ff 87 #define SYSTEM_MK22F51212_H_ /**< Symbol preventing repeated inclusion */
bogdanm 0:9b334a45a8ff 88
bogdanm 0:9b334a45a8ff 89 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 90 extern "C" {
bogdanm 0:9b334a45a8ff 91 #endif
bogdanm 0:9b334a45a8ff 92
bogdanm 0:9b334a45a8ff 93 #include <stdint.h>
bogdanm 0:9b334a45a8ff 94
bogdanm 0:9b334a45a8ff 95
bogdanm 0:9b334a45a8ff 96 #define DISABLE_WDOG 1
bogdanm 0:9b334a45a8ff 97
bogdanm 0:9b334a45a8ff 98 #ifndef CLOCK_SETUP
bogdanm 0:9b334a45a8ff 99 #define CLOCK_SETUP 4
bogdanm 0:9b334a45a8ff 100 #endif
bogdanm 0:9b334a45a8ff 101
bogdanm 0:9b334a45a8ff 102 /* MCG mode constants */
bogdanm 0:9b334a45a8ff 103
bogdanm 0:9b334a45a8ff 104 #define MCG_MODE_FEI 0U
bogdanm 0:9b334a45a8ff 105 #define MCG_MODE_FBI 1U
bogdanm 0:9b334a45a8ff 106 #define MCG_MODE_BLPI 2U
bogdanm 0:9b334a45a8ff 107 #define MCG_MODE_FEE 3U
bogdanm 0:9b334a45a8ff 108 #define MCG_MODE_FBE 4U
bogdanm 0:9b334a45a8ff 109 #define MCG_MODE_BLPE 5U
bogdanm 0:9b334a45a8ff 110 #define MCG_MODE_PBE 6U
bogdanm 0:9b334a45a8ff 111 #define MCG_MODE_PEE 7U
bogdanm 0:9b334a45a8ff 112
bogdanm 0:9b334a45a8ff 113 /* Predefined clock setups
bogdanm 0:9b334a45a8ff 114 0 ... Default part configuration
bogdanm 0:9b334a45a8ff 115 Multipurpose Clock Generator (MCG) in FEI mode.
bogdanm 0:9b334a45a8ff 116 Reference clock source for MCG module: Slow internal reference clock
bogdanm 0:9b334a45a8ff 117 Core clock = 20.97152MHz
bogdanm 0:9b334a45a8ff 118 Bus clock = 20.97152MHz
bogdanm 0:9b334a45a8ff 119 1 ... Maximum achievable clock frequency configuration
bogdanm 0:9b334a45a8ff 120 Multipurpose Clock Generator (MCG) in PEE mode.
bogdanm 0:9b334a45a8ff 121 Reference clock source for MCG module: System oscillator 0 reference clock
bogdanm 0:9b334a45a8ff 122 Core clock = 120MHz
bogdanm 0:9b334a45a8ff 123 Bus clock = 60MHz
bogdanm 0:9b334a45a8ff 124 2 ... Chip internaly clocked, ready for Very Low Power Run mode.
bogdanm 0:9b334a45a8ff 125 Multipurpose Clock Generator (MCG) in BLPI mode.
bogdanm 0:9b334a45a8ff 126 Reference clock source for MCG module: Fast internal reference clock
bogdanm 0:9b334a45a8ff 127 Core clock = 4MHz
bogdanm 0:9b334a45a8ff 128 Bus clock = 4MHz
bogdanm 0:9b334a45a8ff 129 3 ... Chip externally clocked, ready for Very Low Power Run mode.
bogdanm 0:9b334a45a8ff 130 Multipurpose Clock Generator (MCG) in BLPE mode.
bogdanm 0:9b334a45a8ff 131 Reference clock source for MCG module: System oscillator 0 reference clock
bogdanm 0:9b334a45a8ff 132 Core clock = 4MHz
bogdanm 0:9b334a45a8ff 133 Bus clock = 4MHz
bogdanm 0:9b334a45a8ff 134 4 ... USB clock setup
bogdanm 0:9b334a45a8ff 135 Multipurpose Clock Generator (MCG) in PEE mode.
bogdanm 0:9b334a45a8ff 136 Reference clock source for MCG module: System oscillator 0 reference clock
bogdanm 0:9b334a45a8ff 137 Core clock = 120MHz
bogdanm 0:9b334a45a8ff 138 Bus clock = 60MHz
bogdanm 0:9b334a45a8ff 139 5 ... Maximum achievable clock frequency configuration in RUN mode
bogdanm 0:9b334a45a8ff 140 Multipurpose Clock Generator (MCG) in PEE mode.
bogdanm 0:9b334a45a8ff 141 Reference clock source for MCG module: System oscillator 0 reference clock
bogdanm 0:9b334a45a8ff 142 Core clock = 80MHz
bogdanm 0:9b334a45a8ff 143 Bus clock = 40MHz
bogdanm 0:9b334a45a8ff 144 */
bogdanm 0:9b334a45a8ff 145
bogdanm 0:9b334a45a8ff 146 /* Define clock source values */
bogdanm 0:9b334a45a8ff 147
bogdanm 0:9b334a45a8ff 148 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
bogdanm 0:9b334a45a8ff 149 #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
bogdanm 0:9b334a45a8ff 150 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
bogdanm 0:9b334a45a8ff 151 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
bogdanm 0:9b334a45a8ff 152 #define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
bogdanm 0:9b334a45a8ff 153
bogdanm 0:9b334a45a8ff 154 /* RTC oscillator setting */
bogdanm 0:9b334a45a8ff 155 /* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */
bogdanm 0:9b334a45a8ff 156 #define SYSTEM_RTC_CR_VALUE 0x0300U /* RTC_CR */
bogdanm 0:9b334a45a8ff 157
bogdanm 0:9b334a45a8ff 158 /* Low power mode enable */
bogdanm 0:9b334a45a8ff 159 /* SMC_PMPROT: AHSRUN=1,AVLP=1,ALLS=1,AVLLS=1 */
bogdanm 0:9b334a45a8ff 160 #define SYSTEM_SMC_PMPROT_VALUE 0xAAU /* SMC_PMPROT */
bogdanm 0:9b334a45a8ff 161
bogdanm 0:9b334a45a8ff 162 /* Internal reference clock trim */
bogdanm 0:9b334a45a8ff 163 /* #undef SLOW_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
bogdanm 0:9b334a45a8ff 164 /* #undef SLOW_FINE_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
bogdanm 0:9b334a45a8ff 165 /* #undef FAST_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
bogdanm 0:9b334a45a8ff 166 /* #undef FAST_FINE_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
bogdanm 0:9b334a45a8ff 167
bogdanm 0:9b334a45a8ff 168 #if (CLOCK_SETUP == 0)
bogdanm 0:9b334a45a8ff 169 #define DEFAULT_SYSTEM_CLOCK 20971520u /* Default System clock value */
bogdanm 0:9b334a45a8ff 170 #define MCG_MODE MCG_MODE_FEI /* Clock generator mode */
bogdanm 0:9b334a45a8ff 171 /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
bogdanm 0:9b334a45a8ff 172 #define SYSTEM_MCG_C1_VALUE 0x06U /* MCG_C1 */
bogdanm 0:9b334a45a8ff 173 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
bogdanm 0:9b334a45a8ff 174 #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
bogdanm 0:9b334a45a8ff 175 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
bogdanm 0:9b334a45a8ff 176 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
bogdanm 0:9b334a45a8ff 177 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
bogdanm 0:9b334a45a8ff 178 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
bogdanm 0:9b334a45a8ff 179 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
bogdanm 0:9b334a45a8ff 180 #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
bogdanm 0:9b334a45a8ff 181 /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
bogdanm 0:9b334a45a8ff 182 #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
bogdanm 0:9b334a45a8ff 183 /* MCG_C7: OSCSEL=0 */
bogdanm 0:9b334a45a8ff 184 #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
bogdanm 0:9b334a45a8ff 185 /* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
bogdanm 0:9b334a45a8ff 186 #define SYSTEM_OSC_CR_VALUE 0x00U /* OSC_CR */
bogdanm 0:9b334a45a8ff 187 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
bogdanm 0:9b334a45a8ff 188 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
bogdanm 0:9b334a45a8ff 189 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1 */
bogdanm 0:9b334a45a8ff 190 #define SYSTEM_SIM_CLKDIV1_VALUE 0x00110000U /* SIM_CLKDIV1 */
bogdanm 0:9b334a45a8ff 191 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
bogdanm 0:9b334a45a8ff 192 #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
bogdanm 0:9b334a45a8ff 193 /* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
bogdanm 0:9b334a45a8ff 194 #define SYSTEM_SIM_SOPT2_VALUE 0x00U /* SIM_SOPT2 */
bogdanm 0:9b334a45a8ff 195 #elif (CLOCK_SETUP == 1)
bogdanm 0:9b334a45a8ff 196 #define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
bogdanm 0:9b334a45a8ff 197 #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
bogdanm 0:9b334a45a8ff 198 /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
bogdanm 0:9b334a45a8ff 199 #define SYSTEM_MCG_C1_VALUE 0x1AU /* MCG_C1 */
bogdanm 0:9b334a45a8ff 200 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
bogdanm 0:9b334a45a8ff 201 #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
bogdanm 0:9b334a45a8ff 202 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
bogdanm 0:9b334a45a8ff 203 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
bogdanm 0:9b334a45a8ff 204 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
bogdanm 0:9b334a45a8ff 205 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
bogdanm 0:9b334a45a8ff 206 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
bogdanm 0:9b334a45a8ff 207 #define SYSTEM_MCG_C5_VALUE 0x01U /* MCG_C5 */
bogdanm 0:9b334a45a8ff 208 /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=6 */
bogdanm 0:9b334a45a8ff 209 #define SYSTEM_MCG_C6_VALUE 0x46U /* MCG_C6 */
bogdanm 0:9b334a45a8ff 210 /* MCG_C7: OSCSEL=0 */
bogdanm 0:9b334a45a8ff 211 #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
bogdanm 0:9b334a45a8ff 212 /* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
bogdanm 0:9b334a45a8ff 213 #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
bogdanm 0:9b334a45a8ff 214 /* SMC_PMCTRL: RUNM=3,STOPA=0,STOPM=0 */
bogdanm 0:9b334a45a8ff 215 #define SYSTEM_SMC_PMCTRL_VALUE 0x60U /* SMC_PMCTRL */
bogdanm 0:9b334a45a8ff 216 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
bogdanm 0:9b334a45a8ff 217 #define SYSTEM_SIM_CLKDIV1_VALUE 0x01140000U /* SIM_CLKDIV1 */
bogdanm 0:9b334a45a8ff 218 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
bogdanm 0:9b334a45a8ff 219 #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
bogdanm 0:9b334a45a8ff 220 /* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
bogdanm 0:9b334a45a8ff 221 #define SYSTEM_SIM_SOPT2_VALUE 0x00010000U /* SIM_SOPT2 */
bogdanm 0:9b334a45a8ff 222 #elif (CLOCK_SETUP == 2)
bogdanm 0:9b334a45a8ff 223 #define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
bogdanm 0:9b334a45a8ff 224 #define MCG_MODE MCG_MODE_BLPI /* Clock generator mode */
bogdanm 0:9b334a45a8ff 225 /* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
bogdanm 0:9b334a45a8ff 226 #define SYSTEM_MCG_C1_VALUE 0x46U /* MCG_C1 */
bogdanm 0:9b334a45a8ff 227 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=1,IRCS=1 */
bogdanm 0:9b334a45a8ff 228 #define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */
bogdanm 0:9b334a45a8ff 229 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
bogdanm 0:9b334a45a8ff 230 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
bogdanm 0:9b334a45a8ff 231 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
bogdanm 0:9b334a45a8ff 232 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
bogdanm 0:9b334a45a8ff 233 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
bogdanm 0:9b334a45a8ff 234 #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
bogdanm 0:9b334a45a8ff 235 /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
bogdanm 0:9b334a45a8ff 236 #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
bogdanm 0:9b334a45a8ff 237 /* MCG_C7: OSCSEL=0 */
bogdanm 0:9b334a45a8ff 238 #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
bogdanm 0:9b334a45a8ff 239 /* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
bogdanm 0:9b334a45a8ff 240 #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
bogdanm 0:9b334a45a8ff 241 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
bogdanm 0:9b334a45a8ff 242 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
bogdanm 0:9b334a45a8ff 243 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=4 */
bogdanm 0:9b334a45a8ff 244 #define SYSTEM_SIM_CLKDIV1_VALUE 0x00040000U /* SIM_CLKDIV1 */
bogdanm 0:9b334a45a8ff 245 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
bogdanm 0:9b334a45a8ff 246 #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
bogdanm 0:9b334a45a8ff 247 /* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
bogdanm 0:9b334a45a8ff 248 #define SYSTEM_SIM_SOPT2_VALUE 0x00030000U /* SIM_SOPT2 */
bogdanm 0:9b334a45a8ff 249 #elif (CLOCK_SETUP == 3)
bogdanm 0:9b334a45a8ff 250 #define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
bogdanm 0:9b334a45a8ff 251 #define MCG_MODE MCG_MODE_BLPE /* Clock generator mode */
bogdanm 0:9b334a45a8ff 252 /* MCG_C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
bogdanm 0:9b334a45a8ff 253 #define SYSTEM_MCG_C1_VALUE 0x9AU /* MCG_C1 */
bogdanm 0:9b334a45a8ff 254 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=1,IRCS=1 */
bogdanm 0:9b334a45a8ff 255 #define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */
bogdanm 0:9b334a45a8ff 256 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
bogdanm 0:9b334a45a8ff 257 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
bogdanm 0:9b334a45a8ff 258 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=1,LOCS0=0 */
bogdanm 0:9b334a45a8ff 259 #define SYSTEM_MCG_SC_VALUE 0x02U /* MCG_SC */
bogdanm 0:9b334a45a8ff 260 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
bogdanm 0:9b334a45a8ff 261 #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
bogdanm 0:9b334a45a8ff 262 /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
bogdanm 0:9b334a45a8ff 263 #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
bogdanm 0:9b334a45a8ff 264 /* MCG_C7: OSCSEL=0 */
bogdanm 0:9b334a45a8ff 265 #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
bogdanm 0:9b334a45a8ff 266 /* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
bogdanm 0:9b334a45a8ff 267 #define SYSTEM_OSC_CR_VALUE 0x00U /* OSC_CR */
bogdanm 0:9b334a45a8ff 268 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
bogdanm 0:9b334a45a8ff 269 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
bogdanm 0:9b334a45a8ff 270 /* SIM_CLKDIV1: OUTDIV1=1,OUTDIV2=1,OUTDIV3=1,OUTDIV4=7 */
bogdanm 0:9b334a45a8ff 271 #define SYSTEM_SIM_CLKDIV1_VALUE 0x11170000U /* SIM_CLKDIV1 */
bogdanm 0:9b334a45a8ff 272 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
bogdanm 0:9b334a45a8ff 273 #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
bogdanm 0:9b334a45a8ff 274 /* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
bogdanm 0:9b334a45a8ff 275 #define SYSTEM_SIM_SOPT2_VALUE 0x00030000U /* SIM_SOPT2 */
bogdanm 0:9b334a45a8ff 276 #elif (CLOCK_SETUP == 4)
bogdanm 0:9b334a45a8ff 277 #define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
bogdanm 0:9b334a45a8ff 278 #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
bogdanm 0:9b334a45a8ff 279 /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
bogdanm 0:9b334a45a8ff 280 #define SYSTEM_MCG_C1_VALUE 0x1AU /* MCG_C1 */
bogdanm 0:9b334a45a8ff 281 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
bogdanm 0:9b334a45a8ff 282 #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
bogdanm 0:9b334a45a8ff 283 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
bogdanm 0:9b334a45a8ff 284 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
bogdanm 0:9b334a45a8ff 285 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
bogdanm 0:9b334a45a8ff 286 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
bogdanm 0:9b334a45a8ff 287 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
bogdanm 0:9b334a45a8ff 288 #define SYSTEM_MCG_C5_VALUE 0x01U /* MCG_C5 */
bogdanm 0:9b334a45a8ff 289 /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=6 */
bogdanm 0:9b334a45a8ff 290 #define SYSTEM_MCG_C6_VALUE 0x46U /* MCG_C6 */
bogdanm 0:9b334a45a8ff 291 /* MCG_C7: OSCSEL=0 */
bogdanm 0:9b334a45a8ff 292 #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
bogdanm 0:9b334a45a8ff 293 /* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
bogdanm 0:9b334a45a8ff 294 #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
bogdanm 0:9b334a45a8ff 295 /* SMC_PMCTRL: RUNM=3,STOPA=0,STOPM=0 */
bogdanm 0:9b334a45a8ff 296 #define SYSTEM_SMC_PMCTRL_VALUE 0x60U /* SMC_PMCTRL */
bogdanm 0:9b334a45a8ff 297 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
bogdanm 0:9b334a45a8ff 298 #define SYSTEM_SIM_CLKDIV1_VALUE 0x01140000U /* SIM_CLKDIV1 */
bogdanm 0:9b334a45a8ff 299 /* SIM_CLKDIV2: USBDIV=4,USBFRAC=1 */
bogdanm 0:9b334a45a8ff 300 #define SYSTEM_SIM_CLKDIV2_VALUE 0x09U /* SIM_CLKDIV2 */
bogdanm 0:9b334a45a8ff 301 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
bogdanm 0:9b334a45a8ff 302 #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
bogdanm 0:9b334a45a8ff 303 /* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
bogdanm 0:9b334a45a8ff 304 #define SYSTEM_SIM_SOPT2_VALUE 0x00010000U /* SIM_SOPT2 */
bogdanm 0:9b334a45a8ff 305 #elif (CLOCK_SETUP == 5)
bogdanm 0:9b334a45a8ff 306 #define DEFAULT_SYSTEM_CLOCK 80000000u /* Default System clock value */
bogdanm 0:9b334a45a8ff 307 #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
bogdanm 0:9b334a45a8ff 308 /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
bogdanm 0:9b334a45a8ff 309 #define SYSTEM_MCG_C1_VALUE 0x1AU /* MCG_C1 */
bogdanm 0:9b334a45a8ff 310 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
bogdanm 0:9b334a45a8ff 311 #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
bogdanm 0:9b334a45a8ff 312 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
bogdanm 0:9b334a45a8ff 313 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
bogdanm 0:9b334a45a8ff 314 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
bogdanm 0:9b334a45a8ff 315 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
bogdanm 0:9b334a45a8ff 316 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=3 */
bogdanm 0:9b334a45a8ff 317 #define SYSTEM_MCG_C5_VALUE 0x03U /* MCG_C5 */
bogdanm 0:9b334a45a8ff 318 /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x10 */
bogdanm 0:9b334a45a8ff 319 #define SYSTEM_MCG_C6_VALUE 0x50U /* MCG_C6 */
bogdanm 0:9b334a45a8ff 320 /* MCG_C7: OSCSEL=0 */
bogdanm 0:9b334a45a8ff 321 #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
bogdanm 0:9b334a45a8ff 322 /* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
bogdanm 0:9b334a45a8ff 323 #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
bogdanm 0:9b334a45a8ff 324 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
bogdanm 0:9b334a45a8ff 325 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
bogdanm 0:9b334a45a8ff 326 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=3 */
bogdanm 0:9b334a45a8ff 327 #define SYSTEM_SIM_CLKDIV1_VALUE 0x01130000U /* SIM_CLKDIV1 */
bogdanm 0:9b334a45a8ff 328 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
bogdanm 0:9b334a45a8ff 329 #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
bogdanm 0:9b334a45a8ff 330 /* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
bogdanm 0:9b334a45a8ff 331 #define SYSTEM_SIM_SOPT2_VALUE 0x00010000U /* SIM_SOPT2 */
bogdanm 0:9b334a45a8ff 332 #endif
bogdanm 0:9b334a45a8ff 333
bogdanm 0:9b334a45a8ff 334 /**
bogdanm 0:9b334a45a8ff 335 * @brief System clock frequency (core clock)
bogdanm 0:9b334a45a8ff 336 *
bogdanm 0:9b334a45a8ff 337 * The system clock frequency supplied to the SysTick timer and the processor
bogdanm 0:9b334a45a8ff 338 * core clock. This variable can be used by the user application to setup the
bogdanm 0:9b334a45a8ff 339 * SysTick timer or configure other parameters. It may also be used by debugger to
bogdanm 0:9b334a45a8ff 340 * query the frequency of the debug timer or configure the trace clock speed
bogdanm 0:9b334a45a8ff 341 * SystemCoreClock is initialized with a correct predefined value.
bogdanm 0:9b334a45a8ff 342 */
bogdanm 0:9b334a45a8ff 343 extern uint32_t SystemCoreClock;
bogdanm 0:9b334a45a8ff 344
bogdanm 0:9b334a45a8ff 345 /**
bogdanm 0:9b334a45a8ff 346 * @brief Setup the microcontroller system.
bogdanm 0:9b334a45a8ff 347 *
bogdanm 0:9b334a45a8ff 348 * Typically this function configures the oscillator (PLL) that is part of the
bogdanm 0:9b334a45a8ff 349 * microcontroller device. For systems with variable clock speed it also updates
bogdanm 0:9b334a45a8ff 350 * the variable SystemCoreClock. SystemInit is called from startup_device file.
bogdanm 0:9b334a45a8ff 351 */
bogdanm 0:9b334a45a8ff 352 void SystemInit (void);
bogdanm 0:9b334a45a8ff 353
bogdanm 0:9b334a45a8ff 354 /**
bogdanm 0:9b334a45a8ff 355 * @brief Updates the SystemCoreClock variable.
bogdanm 0:9b334a45a8ff 356 *
bogdanm 0:9b334a45a8ff 357 * It must be called whenever the core clock is changed during program
bogdanm 0:9b334a45a8ff 358 * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
bogdanm 0:9b334a45a8ff 359 * the current core clock.
bogdanm 0:9b334a45a8ff 360 */
bogdanm 0:9b334a45a8ff 361 void SystemCoreClockUpdate (void);
bogdanm 0:9b334a45a8ff 362
bogdanm 0:9b334a45a8ff 363 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 364 }
bogdanm 0:9b334a45a8ff 365 #endif
bogdanm 0:9b334a45a8ff 366
bogdanm 0:9b334a45a8ff 367 #endif /* #if !defined(SYSTEM_MK22F51212_H_) */