added prescaler for 16 bit pwm in LPC1347 target
Fork of mbed-dev by
targets/cmsis/TARGET_Freescale/TARGET_KL27Z/MKL27Z644.h@121:7f86b4238bec, 2016-05-03 (annotated)
- Committer:
- mbed_official
- Date:
- Tue May 03 00:15:16 2016 +0100
- Revision:
- 121:7f86b4238bec
Synchronized with git revision 9cef243de23875778f461bbe9a8c1bc47e65212b
Full URL: https://github.com/mbedmicro/mbed/commit/9cef243de23875778f461bbe9a8c1bc47e65212b/
Switch to KSDK 2.0
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 121:7f86b4238bec | 1 | /* |
mbed_official | 121:7f86b4238bec | 2 | ** ################################################################### |
mbed_official | 121:7f86b4238bec | 3 | ** Processors: MKL27Z32VDA4 |
mbed_official | 121:7f86b4238bec | 4 | ** MKL27Z32VFM4 |
mbed_official | 121:7f86b4238bec | 5 | ** MKL27Z32VFT4 |
mbed_official | 121:7f86b4238bec | 6 | ** MKL27Z32VLH4 |
mbed_official | 121:7f86b4238bec | 7 | ** MKL27Z32VMP4 |
mbed_official | 121:7f86b4238bec | 8 | ** MKL27Z64VDA4 |
mbed_official | 121:7f86b4238bec | 9 | ** MKL27Z64VFM4 |
mbed_official | 121:7f86b4238bec | 10 | ** MKL27Z64VFT4 |
mbed_official | 121:7f86b4238bec | 11 | ** MKL27Z64VLH4 |
mbed_official | 121:7f86b4238bec | 12 | ** MKL27Z64VMP4 |
mbed_official | 121:7f86b4238bec | 13 | ** |
mbed_official | 121:7f86b4238bec | 14 | ** Compilers: Keil ARM C/C++ Compiler |
mbed_official | 121:7f86b4238bec | 15 | ** Freescale C/C++ for Embedded ARM |
mbed_official | 121:7f86b4238bec | 16 | ** GNU C Compiler |
mbed_official | 121:7f86b4238bec | 17 | ** IAR ANSI C/C++ Compiler for ARM |
mbed_official | 121:7f86b4238bec | 18 | ** |
mbed_official | 121:7f86b4238bec | 19 | ** Reference manual: KL27P64M48SF2RM, Rev. 1, Sep 2014 |
mbed_official | 121:7f86b4238bec | 20 | ** Version: rev. 1.4, 2014-09-22 |
mbed_official | 121:7f86b4238bec | 21 | ** Build: b151221 |
mbed_official | 121:7f86b4238bec | 22 | ** |
mbed_official | 121:7f86b4238bec | 23 | ** Abstract: |
mbed_official | 121:7f86b4238bec | 24 | ** CMSIS Peripheral Access Layer for MKL27Z644 |
mbed_official | 121:7f86b4238bec | 25 | ** |
mbed_official | 121:7f86b4238bec | 26 | ** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. |
mbed_official | 121:7f86b4238bec | 27 | ** All rights reserved. |
mbed_official | 121:7f86b4238bec | 28 | ** |
mbed_official | 121:7f86b4238bec | 29 | ** Redistribution and use in source and binary forms, with or without modification, |
mbed_official | 121:7f86b4238bec | 30 | ** are permitted provided that the following conditions are met: |
mbed_official | 121:7f86b4238bec | 31 | ** |
mbed_official | 121:7f86b4238bec | 32 | ** o Redistributions of source code must retain the above copyright notice, this list |
mbed_official | 121:7f86b4238bec | 33 | ** of conditions and the following disclaimer. |
mbed_official | 121:7f86b4238bec | 34 | ** |
mbed_official | 121:7f86b4238bec | 35 | ** o Redistributions in binary form must reproduce the above copyright notice, this |
mbed_official | 121:7f86b4238bec | 36 | ** list of conditions and the following disclaimer in the documentation and/or |
mbed_official | 121:7f86b4238bec | 37 | ** other materials provided with the distribution. |
mbed_official | 121:7f86b4238bec | 38 | ** |
mbed_official | 121:7f86b4238bec | 39 | ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
mbed_official | 121:7f86b4238bec | 40 | ** contributors may be used to endorse or promote products derived from this |
mbed_official | 121:7f86b4238bec | 41 | ** software without specific prior written permission. |
mbed_official | 121:7f86b4238bec | 42 | ** |
mbed_official | 121:7f86b4238bec | 43 | ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
mbed_official | 121:7f86b4238bec | 44 | ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
mbed_official | 121:7f86b4238bec | 45 | ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
mbed_official | 121:7f86b4238bec | 46 | ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
mbed_official | 121:7f86b4238bec | 47 | ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
mbed_official | 121:7f86b4238bec | 48 | ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
mbed_official | 121:7f86b4238bec | 49 | ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
mbed_official | 121:7f86b4238bec | 50 | ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
mbed_official | 121:7f86b4238bec | 51 | ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
mbed_official | 121:7f86b4238bec | 52 | ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
mbed_official | 121:7f86b4238bec | 53 | ** |
mbed_official | 121:7f86b4238bec | 54 | ** http: www.freescale.com |
mbed_official | 121:7f86b4238bec | 55 | ** mail: support@freescale.com |
mbed_official | 121:7f86b4238bec | 56 | ** |
mbed_official | 121:7f86b4238bec | 57 | ** Revisions: |
mbed_official | 121:7f86b4238bec | 58 | ** - rev. 1.0 (2014-05-12) |
mbed_official | 121:7f86b4238bec | 59 | ** Initial version. |
mbed_official | 121:7f86b4238bec | 60 | ** - rev. 1.1 (2014-07-10) |
mbed_official | 121:7f86b4238bec | 61 | ** UART0 - UART0 module renamed to UART2. |
mbed_official | 121:7f86b4238bec | 62 | ** - rev. 1.2 (2014-08-12) |
mbed_official | 121:7f86b4238bec | 63 | ** CRC - CRC register renamed to DATA. |
mbed_official | 121:7f86b4238bec | 64 | ** - rev. 1.3 (2014-09-02) |
mbed_official | 121:7f86b4238bec | 65 | ** USB - USB0_CTL0 was renamed to USB0_OTGCTL register. |
mbed_official | 121:7f86b4238bec | 66 | ** USB - USB0_CTL1 was renamed to USB0_CTL register. |
mbed_official | 121:7f86b4238bec | 67 | ** USB - Two new bitfields (STOP_ACK_DLY_EN, AHB_DLY_EN) was added to the USB0_KEEP_ALIVE_CTRL register. |
mbed_official | 121:7f86b4238bec | 68 | ** - rev. 1.4 (2014-09-22) |
mbed_official | 121:7f86b4238bec | 69 | ** FLEXIO - Offsets of the SHIFTBUFBIS registers were interchanged with offsets of the SHIFTBUFBBS registers. |
mbed_official | 121:7f86b4238bec | 70 | ** SIM - Changed bitfield value MCGIRCLK to LIRC_CLK of bitfield CLKOUTSEL in SOPT2 register. |
mbed_official | 121:7f86b4238bec | 71 | ** SIM - Removed bitfield DIEID in SDID register. |
mbed_official | 121:7f86b4238bec | 72 | ** UART2 - Removed ED register. |
mbed_official | 121:7f86b4238bec | 73 | ** UART2 - Removed MODEM register. |
mbed_official | 121:7f86b4238bec | 74 | ** UART2 - Removed IR register. |
mbed_official | 121:7f86b4238bec | 75 | ** UART2 - Removed PFIFO register. |
mbed_official | 121:7f86b4238bec | 76 | ** UART2 - Removed CFIFO register. |
mbed_official | 121:7f86b4238bec | 77 | ** UART2 - Removed SFIFO register. |
mbed_official | 121:7f86b4238bec | 78 | ** UART2 - Removed TWFIFO register. |
mbed_official | 121:7f86b4238bec | 79 | ** UART2 - Removed TCFIFO register. |
mbed_official | 121:7f86b4238bec | 80 | ** UART2 - Removed RWFIFO register. |
mbed_official | 121:7f86b4238bec | 81 | ** UART2 - Removed RCFIFO register. |
mbed_official | 121:7f86b4238bec | 82 | ** USB - Removed bitfield REG_EN in CLK_RECOVER_IRC_EN register. |
mbed_official | 121:7f86b4238bec | 83 | ** USB - Renamed USBEN bitfield of USB0_CTL was renamed to USBENSOFEN. |
mbed_official | 121:7f86b4238bec | 84 | ** |
mbed_official | 121:7f86b4238bec | 85 | ** ################################################################### |
mbed_official | 121:7f86b4238bec | 86 | */ |
mbed_official | 121:7f86b4238bec | 87 | |
mbed_official | 121:7f86b4238bec | 88 | /*! |
mbed_official | 121:7f86b4238bec | 89 | * @file MKL27Z644.h |
mbed_official | 121:7f86b4238bec | 90 | * @version 1.4 |
mbed_official | 121:7f86b4238bec | 91 | * @date 2014-09-22 |
mbed_official | 121:7f86b4238bec | 92 | * @brief CMSIS Peripheral Access Layer for MKL27Z644 |
mbed_official | 121:7f86b4238bec | 93 | * |
mbed_official | 121:7f86b4238bec | 94 | * CMSIS Peripheral Access Layer for MKL27Z644 |
mbed_official | 121:7f86b4238bec | 95 | */ |
mbed_official | 121:7f86b4238bec | 96 | |
mbed_official | 121:7f86b4238bec | 97 | #ifndef _MKL27Z644_H_ |
mbed_official | 121:7f86b4238bec | 98 | #define _MKL27Z644_H_ /**< Symbol preventing repeated inclusion */ |
mbed_official | 121:7f86b4238bec | 99 | |
mbed_official | 121:7f86b4238bec | 100 | /** Memory map major version (memory maps with equal major version number are |
mbed_official | 121:7f86b4238bec | 101 | * compatible) */ |
mbed_official | 121:7f86b4238bec | 102 | #define MCU_MEM_MAP_VERSION 0x0100U |
mbed_official | 121:7f86b4238bec | 103 | /** Memory map minor version */ |
mbed_official | 121:7f86b4238bec | 104 | #define MCU_MEM_MAP_VERSION_MINOR 0x0004U |
mbed_official | 121:7f86b4238bec | 105 | |
mbed_official | 121:7f86b4238bec | 106 | |
mbed_official | 121:7f86b4238bec | 107 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 108 | -- Interrupt vector numbers |
mbed_official | 121:7f86b4238bec | 109 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 110 | |
mbed_official | 121:7f86b4238bec | 111 | /*! |
mbed_official | 121:7f86b4238bec | 112 | * @addtogroup Interrupt_vector_numbers Interrupt vector numbers |
mbed_official | 121:7f86b4238bec | 113 | * @{ |
mbed_official | 121:7f86b4238bec | 114 | */ |
mbed_official | 121:7f86b4238bec | 115 | |
mbed_official | 121:7f86b4238bec | 116 | /** Interrupt Number Definitions */ |
mbed_official | 121:7f86b4238bec | 117 | #define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */ |
mbed_official | 121:7f86b4238bec | 118 | |
mbed_official | 121:7f86b4238bec | 119 | typedef enum IRQn { |
mbed_official | 121:7f86b4238bec | 120 | /* Auxiliary constants */ |
mbed_official | 121:7f86b4238bec | 121 | NotAvail_IRQn = -128, /**< Not available device specific interrupt */ |
mbed_official | 121:7f86b4238bec | 122 | |
mbed_official | 121:7f86b4238bec | 123 | /* Core interrupts */ |
mbed_official | 121:7f86b4238bec | 124 | NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ |
mbed_official | 121:7f86b4238bec | 125 | HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */ |
mbed_official | 121:7f86b4238bec | 126 | SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */ |
mbed_official | 121:7f86b4238bec | 127 | PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */ |
mbed_official | 121:7f86b4238bec | 128 | SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */ |
mbed_official | 121:7f86b4238bec | 129 | |
mbed_official | 121:7f86b4238bec | 130 | /* Device specific interrupts */ |
mbed_official | 121:7f86b4238bec | 131 | DMA0_IRQn = 0, /**< DMA channel 0 transfer complete */ |
mbed_official | 121:7f86b4238bec | 132 | DMA1_IRQn = 1, /**< DMA channel 1 transfer complete */ |
mbed_official | 121:7f86b4238bec | 133 | DMA2_IRQn = 2, /**< DMA channel 2 transfer complete */ |
mbed_official | 121:7f86b4238bec | 134 | DMA3_IRQn = 3, /**< DMA channel 3 transfer complete */ |
mbed_official | 121:7f86b4238bec | 135 | Reserved20_IRQn = 4, /**< Reserved interrupt */ |
mbed_official | 121:7f86b4238bec | 136 | FTFA_IRQn = 5, /**< Command complete and read collision */ |
mbed_official | 121:7f86b4238bec | 137 | PMC_IRQn = 6, /**< Low-voltage detect, low-voltage warning */ |
mbed_official | 121:7f86b4238bec | 138 | LLWU_IRQn = 7, /**< Low leakage wakeup */ |
mbed_official | 121:7f86b4238bec | 139 | I2C0_IRQn = 8, /**< I2C0 interrupt */ |
mbed_official | 121:7f86b4238bec | 140 | I2C1_IRQn = 9, /**< I2C1 interrupt */ |
mbed_official | 121:7f86b4238bec | 141 | SPI0_IRQn = 10, /**< SPI0 single interrupt vector for all sources */ |
mbed_official | 121:7f86b4238bec | 142 | SPI1_IRQn = 11, /**< SPI1 single interrupt vector for all sources */ |
mbed_official | 121:7f86b4238bec | 143 | LPUART0_IRQn = 12, /**< LPUART0 status and error */ |
mbed_official | 121:7f86b4238bec | 144 | LPUART1_IRQn = 13, /**< LPUART1 status and error */ |
mbed_official | 121:7f86b4238bec | 145 | UART2_FLEXIO_IRQn = 14, /**< UART2 or FLEXIO */ |
mbed_official | 121:7f86b4238bec | 146 | ADC0_IRQn = 15, /**< ADC0 interrupt */ |
mbed_official | 121:7f86b4238bec | 147 | CMP0_IRQn = 16, /**< CMP0 interrupt */ |
mbed_official | 121:7f86b4238bec | 148 | TPM0_IRQn = 17, /**< TPM0 single interrupt vector for all sources */ |
mbed_official | 121:7f86b4238bec | 149 | TPM1_IRQn = 18, /**< TPM1 single interrupt vector for all sources */ |
mbed_official | 121:7f86b4238bec | 150 | TPM2_IRQn = 19, /**< TPM2 single interrupt vector for all sources */ |
mbed_official | 121:7f86b4238bec | 151 | RTC_IRQn = 20, /**< RTC alarm */ |
mbed_official | 121:7f86b4238bec | 152 | RTC_Seconds_IRQn = 21, /**< RTC seconds */ |
mbed_official | 121:7f86b4238bec | 153 | PIT_IRQn = 22, /**< PIT interrupt */ |
mbed_official | 121:7f86b4238bec | 154 | Reserved39_IRQn = 23, /**< Reserved interrupt */ |
mbed_official | 121:7f86b4238bec | 155 | USB0_IRQn = 24, /**< USB0 interrupt */ |
mbed_official | 121:7f86b4238bec | 156 | Reserved41_IRQn = 25, /**< Reserved interrupt */ |
mbed_official | 121:7f86b4238bec | 157 | Reserved42_IRQn = 26, /**< Reserved interrupt */ |
mbed_official | 121:7f86b4238bec | 158 | Reserved43_IRQn = 27, /**< Reserved interrupt */ |
mbed_official | 121:7f86b4238bec | 159 | LPTMR0_IRQn = 28, /**< LPTMR0 interrupt */ |
mbed_official | 121:7f86b4238bec | 160 | Reserved45_IRQn = 29, /**< Reserved interrupt */ |
mbed_official | 121:7f86b4238bec | 161 | PORTA_IRQn = 30, /**< PORTA Pin detect */ |
mbed_official | 121:7f86b4238bec | 162 | PORTB_PORTC_PORTD_PORTE_IRQn = 31 /**< Single interrupt vector for PORTB,PORTC,PORTD,PORTE */ |
mbed_official | 121:7f86b4238bec | 163 | } IRQn_Type; |
mbed_official | 121:7f86b4238bec | 164 | |
mbed_official | 121:7f86b4238bec | 165 | /*! |
mbed_official | 121:7f86b4238bec | 166 | * @} |
mbed_official | 121:7f86b4238bec | 167 | */ /* end of group Interrupt_vector_numbers */ |
mbed_official | 121:7f86b4238bec | 168 | |
mbed_official | 121:7f86b4238bec | 169 | |
mbed_official | 121:7f86b4238bec | 170 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 171 | -- Cortex M0 Core Configuration |
mbed_official | 121:7f86b4238bec | 172 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 173 | |
mbed_official | 121:7f86b4238bec | 174 | /*! |
mbed_official | 121:7f86b4238bec | 175 | * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration |
mbed_official | 121:7f86b4238bec | 176 | * @{ |
mbed_official | 121:7f86b4238bec | 177 | */ |
mbed_official | 121:7f86b4238bec | 178 | |
mbed_official | 121:7f86b4238bec | 179 | #define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */ |
mbed_official | 121:7f86b4238bec | 180 | #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ |
mbed_official | 121:7f86b4238bec | 181 | #define __VTOR_PRESENT 1 /**< Defines if an MPU is present or not */ |
mbed_official | 121:7f86b4238bec | 182 | #define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */ |
mbed_official | 121:7f86b4238bec | 183 | #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ |
mbed_official | 121:7f86b4238bec | 184 | |
mbed_official | 121:7f86b4238bec | 185 | #include "core_cm0plus.h" /* Core Peripheral Access Layer */ |
mbed_official | 121:7f86b4238bec | 186 | #include "system_MKL27Z644.h" /* Device specific configuration file */ |
mbed_official | 121:7f86b4238bec | 187 | |
mbed_official | 121:7f86b4238bec | 188 | /*! |
mbed_official | 121:7f86b4238bec | 189 | * @} |
mbed_official | 121:7f86b4238bec | 190 | */ /* end of group Cortex_Core_Configuration */ |
mbed_official | 121:7f86b4238bec | 191 | |
mbed_official | 121:7f86b4238bec | 192 | |
mbed_official | 121:7f86b4238bec | 193 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 194 | -- Mapping Information |
mbed_official | 121:7f86b4238bec | 195 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 196 | |
mbed_official | 121:7f86b4238bec | 197 | /*! |
mbed_official | 121:7f86b4238bec | 198 | * @addtogroup Mapping_Information Mapping Information |
mbed_official | 121:7f86b4238bec | 199 | * @{ |
mbed_official | 121:7f86b4238bec | 200 | */ |
mbed_official | 121:7f86b4238bec | 201 | |
mbed_official | 121:7f86b4238bec | 202 | /** Mapping Information */ |
mbed_official | 121:7f86b4238bec | 203 | /*! |
mbed_official | 121:7f86b4238bec | 204 | * @addtogroup edma_request |
mbed_official | 121:7f86b4238bec | 205 | * @{ |
mbed_official | 121:7f86b4238bec | 206 | */ |
mbed_official | 121:7f86b4238bec | 207 | |
mbed_official | 121:7f86b4238bec | 208 | /******************************************************************************* |
mbed_official | 121:7f86b4238bec | 209 | * Definitions |
mbed_official | 121:7f86b4238bec | 210 | ******************************************************************************/ |
mbed_official | 121:7f86b4238bec | 211 | |
mbed_official | 121:7f86b4238bec | 212 | /*! |
mbed_official | 121:7f86b4238bec | 213 | * @brief Structure for the DMA hardware request |
mbed_official | 121:7f86b4238bec | 214 | * |
mbed_official | 121:7f86b4238bec | 215 | * Defines the structure for the DMA hardware request collections. The user can configure the |
mbed_official | 121:7f86b4238bec | 216 | * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index |
mbed_official | 121:7f86b4238bec | 217 | * of the hardware request varies according to the to SoC. |
mbed_official | 121:7f86b4238bec | 218 | */ |
mbed_official | 121:7f86b4238bec | 219 | typedef enum _dma_request_source |
mbed_official | 121:7f86b4238bec | 220 | { |
mbed_official | 121:7f86b4238bec | 221 | kDmaRequestMux0Disable = 0|0x100U, /**< DMAMUX TriggerDisabled. */ |
mbed_official | 121:7f86b4238bec | 222 | kDmaRequestMux0Reserved1 = 1|0x100U, /**< Reserved1 */ |
mbed_official | 121:7f86b4238bec | 223 | kDmaRequestMux0LPUART0Rx = 2|0x100U, /**< LPUART0 Receive. */ |
mbed_official | 121:7f86b4238bec | 224 | kDmaRequestMux0LPUART0Tx = 3|0x100U, /**< LPUART0 Transmit. */ |
mbed_official | 121:7f86b4238bec | 225 | kDmaRequestMux0LPUART1Rx = 4|0x100U, /**< LPUART1 Receive. */ |
mbed_official | 121:7f86b4238bec | 226 | kDmaRequestMux0LPUART1Tx = 5|0x100U, /**< LPUART1 Transmit. */ |
mbed_official | 121:7f86b4238bec | 227 | kDmaRequestMux0UART2Rx = 6|0x100U, /**< UART2 Receive. */ |
mbed_official | 121:7f86b4238bec | 228 | kDmaRequestMux0UART2Tx = 7|0x100U, /**< UART2 Transmit. */ |
mbed_official | 121:7f86b4238bec | 229 | kDmaRequestMux0Reserved8 = 8|0x100U, /**< Reserved8 */ |
mbed_official | 121:7f86b4238bec | 230 | kDmaRequestMux0Reserved9 = 9|0x100U, /**< Reserved9 */ |
mbed_official | 121:7f86b4238bec | 231 | kDmaRequestMux0FlexIOChannel0 = 10|0x100U, /**< FLEXIO. */ |
mbed_official | 121:7f86b4238bec | 232 | kDmaRequestMux0FlexIOChannel1 = 11|0x100U, /**< FLEXIO. */ |
mbed_official | 121:7f86b4238bec | 233 | kDmaRequestMux0FlexIOChannel2 = 12|0x100U, /**< FLEXIO. */ |
mbed_official | 121:7f86b4238bec | 234 | kDmaRequestMux0FlexIOChannel3 = 13|0x100U, /**< FLEXIO. */ |
mbed_official | 121:7f86b4238bec | 235 | kDmaRequestMux0Reserved14 = 14|0x100U, /**< Reserved14 */ |
mbed_official | 121:7f86b4238bec | 236 | kDmaRequestMux0Reserved15 = 15|0x100U, /**< Reserved15 */ |
mbed_official | 121:7f86b4238bec | 237 | kDmaRequestMux0SPI0Rx = 16|0x100U, /**< SPI0 Receive. */ |
mbed_official | 121:7f86b4238bec | 238 | kDmaRequestMux0SPI0Tx = 17|0x100U, /**< SPI0 Transmit. */ |
mbed_official | 121:7f86b4238bec | 239 | kDmaRequestMux0SPI1Rx = 18|0x100U, /**< SPI1 Receive. */ |
mbed_official | 121:7f86b4238bec | 240 | kDmaRequestMux0SPI1Tx = 19|0x100U, /**< SPI1 Transmit. */ |
mbed_official | 121:7f86b4238bec | 241 | kDmaRequestMux0Reserved20 = 20|0x100U, /**< Reserved20 */ |
mbed_official | 121:7f86b4238bec | 242 | kDmaRequestMux0Reserved21 = 21|0x100U, /**< Reserved21 */ |
mbed_official | 121:7f86b4238bec | 243 | kDmaRequestMux0I2C0 = 22|0x100U, /**< I2C0. */ |
mbed_official | 121:7f86b4238bec | 244 | kDmaRequestMux0I2C1 = 23|0x100U, /**< I2C1. */ |
mbed_official | 121:7f86b4238bec | 245 | kDmaRequestMux0TPM0Channel0 = 24|0x100U, /**< TPM0 C0V. */ |
mbed_official | 121:7f86b4238bec | 246 | kDmaRequestMux0TPM0Channel1 = 25|0x100U, /**< TPM0 C1V. */ |
mbed_official | 121:7f86b4238bec | 247 | kDmaRequestMux0TPM0Channel2 = 26|0x100U, /**< TPM0 C2V. */ |
mbed_official | 121:7f86b4238bec | 248 | kDmaRequestMux0TPM0Channel3 = 27|0x100U, /**< TPM0 C3V. */ |
mbed_official | 121:7f86b4238bec | 249 | kDmaRequestMux0TPM0Channel4 = 28|0x100U, /**< TPM0 C4V. */ |
mbed_official | 121:7f86b4238bec | 250 | kDmaRequestMux0TPM0Channel5 = 29|0x100U, /**< TPM0 C5V. */ |
mbed_official | 121:7f86b4238bec | 251 | kDmaRequestMux0Reserved30 = 30|0x100U, /**< Reserved30 */ |
mbed_official | 121:7f86b4238bec | 252 | kDmaRequestMux0Reserved31 = 31|0x100U, /**< Reserved31 */ |
mbed_official | 121:7f86b4238bec | 253 | kDmaRequestMux0TPM1Channel0 = 32|0x100U, /**< TPM1 C0V. */ |
mbed_official | 121:7f86b4238bec | 254 | kDmaRequestMux0TPM1Channel1 = 33|0x100U, /**< TPM1 C1V. */ |
mbed_official | 121:7f86b4238bec | 255 | kDmaRequestMux0TPM2Channel0 = 34|0x100U, /**< TPM2 C0V. */ |
mbed_official | 121:7f86b4238bec | 256 | kDmaRequestMux0TPM2Channel1 = 35|0x100U, /**< TPM2 C1V. */ |
mbed_official | 121:7f86b4238bec | 257 | kDmaRequestMux0Reserved36 = 36|0x100U, /**< Reserved36 */ |
mbed_official | 121:7f86b4238bec | 258 | kDmaRequestMux0Reserved37 = 37|0x100U, /**< Reserved37 */ |
mbed_official | 121:7f86b4238bec | 259 | kDmaRequestMux0Reserved38 = 38|0x100U, /**< Reserved38 */ |
mbed_official | 121:7f86b4238bec | 260 | kDmaRequestMux0Reserved39 = 39|0x100U, /**< Reserved39 */ |
mbed_official | 121:7f86b4238bec | 261 | kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0. */ |
mbed_official | 121:7f86b4238bec | 262 | kDmaRequestMux0Reserved41 = 41|0x100U, /**< Reserved41 */ |
mbed_official | 121:7f86b4238bec | 263 | kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0. */ |
mbed_official | 121:7f86b4238bec | 264 | kDmaRequestMux0Reserved43 = 43|0x100U, /**< Reserved43 */ |
mbed_official | 121:7f86b4238bec | 265 | kDmaRequestMux0Reserved44 = 44|0x100U, /**< Reserved44 */ |
mbed_official | 121:7f86b4238bec | 266 | kDmaRequestMux0Reserved45 = 45|0x100U, /**< Reserved45 */ |
mbed_official | 121:7f86b4238bec | 267 | kDmaRequestMux0Reserved46 = 46|0x100U, /**< Reserved46 */ |
mbed_official | 121:7f86b4238bec | 268 | kDmaRequestMux0Reserved47 = 47|0x100U, /**< Reserved47 */ |
mbed_official | 121:7f86b4238bec | 269 | kDmaRequestMux0Reserved48 = 48|0x100U, /**< Reserved48 */ |
mbed_official | 121:7f86b4238bec | 270 | kDmaRequestMux0PortA = 49|0x100U, /**< PTA. */ |
mbed_official | 121:7f86b4238bec | 271 | kDmaRequestMux0PortB = 50|0x100U, /**< PTB. */ |
mbed_official | 121:7f86b4238bec | 272 | kDmaRequestMux0PortC = 51|0x100U, /**< PTC. */ |
mbed_official | 121:7f86b4238bec | 273 | kDmaRequestMux0PortD = 52|0x100U, /**< PTD. */ |
mbed_official | 121:7f86b4238bec | 274 | kDmaRequestMux0PortE = 53|0x100U, /**< PTE. */ |
mbed_official | 121:7f86b4238bec | 275 | kDmaRequestMux0TPM0Overflow = 54|0x100U, /**< TPM0. */ |
mbed_official | 121:7f86b4238bec | 276 | kDmaRequestMux0TPM1Overflow = 55|0x100U, /**< TPM1. */ |
mbed_official | 121:7f86b4238bec | 277 | kDmaRequestMux0TPM2Overflow = 56|0x100U, /**< TPM2. */ |
mbed_official | 121:7f86b4238bec | 278 | kDmaRequestMux0Reserved57 = 57|0x100U, /**< Reserved57 */ |
mbed_official | 121:7f86b4238bec | 279 | kDmaRequestMux0Reserved58 = 58|0x100U, /**< Reserved58 */ |
mbed_official | 121:7f86b4238bec | 280 | kDmaRequestMux0Reserved59 = 59|0x100U, /**< Reserved59 */ |
mbed_official | 121:7f86b4238bec | 281 | kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< DMAMUX Always Enabled slot. */ |
mbed_official | 121:7f86b4238bec | 282 | kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< DMAMUX Always Enabled slot. */ |
mbed_official | 121:7f86b4238bec | 283 | kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< DMAMUX Always Enabled slot. */ |
mbed_official | 121:7f86b4238bec | 284 | kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< DMAMUX Always Enabled slot. */ |
mbed_official | 121:7f86b4238bec | 285 | } dma_request_source_t; |
mbed_official | 121:7f86b4238bec | 286 | |
mbed_official | 121:7f86b4238bec | 287 | /* @} */ |
mbed_official | 121:7f86b4238bec | 288 | |
mbed_official | 121:7f86b4238bec | 289 | |
mbed_official | 121:7f86b4238bec | 290 | /*! |
mbed_official | 121:7f86b4238bec | 291 | * @} |
mbed_official | 121:7f86b4238bec | 292 | */ /* end of group Mapping_Information */ |
mbed_official | 121:7f86b4238bec | 293 | |
mbed_official | 121:7f86b4238bec | 294 | |
mbed_official | 121:7f86b4238bec | 295 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 296 | -- Device Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 297 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 298 | |
mbed_official | 121:7f86b4238bec | 299 | /*! |
mbed_official | 121:7f86b4238bec | 300 | * @addtogroup Peripheral_access_layer Device Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 301 | * @{ |
mbed_official | 121:7f86b4238bec | 302 | */ |
mbed_official | 121:7f86b4238bec | 303 | |
mbed_official | 121:7f86b4238bec | 304 | |
mbed_official | 121:7f86b4238bec | 305 | /* |
mbed_official | 121:7f86b4238bec | 306 | ** Start of section using anonymous unions |
mbed_official | 121:7f86b4238bec | 307 | */ |
mbed_official | 121:7f86b4238bec | 308 | |
mbed_official | 121:7f86b4238bec | 309 | #if defined(__ARMCC_VERSION) |
mbed_official | 121:7f86b4238bec | 310 | #pragma push |
mbed_official | 121:7f86b4238bec | 311 | #pragma anon_unions |
mbed_official | 121:7f86b4238bec | 312 | #elif defined(__CWCC__) |
mbed_official | 121:7f86b4238bec | 313 | #pragma push |
mbed_official | 121:7f86b4238bec | 314 | #pragma cpp_extensions on |
mbed_official | 121:7f86b4238bec | 315 | #elif defined(__GNUC__) |
mbed_official | 121:7f86b4238bec | 316 | /* anonymous unions are enabled by default */ |
mbed_official | 121:7f86b4238bec | 317 | #elif defined(__IAR_SYSTEMS_ICC__) |
mbed_official | 121:7f86b4238bec | 318 | #pragma language=extended |
mbed_official | 121:7f86b4238bec | 319 | #else |
mbed_official | 121:7f86b4238bec | 320 | #error Not supported compiler type |
mbed_official | 121:7f86b4238bec | 321 | #endif |
mbed_official | 121:7f86b4238bec | 322 | |
mbed_official | 121:7f86b4238bec | 323 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 324 | -- ADC Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 325 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 326 | |
mbed_official | 121:7f86b4238bec | 327 | /*! |
mbed_official | 121:7f86b4238bec | 328 | * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 329 | * @{ |
mbed_official | 121:7f86b4238bec | 330 | */ |
mbed_official | 121:7f86b4238bec | 331 | |
mbed_official | 121:7f86b4238bec | 332 | /** ADC - Register Layout Typedef */ |
mbed_official | 121:7f86b4238bec | 333 | typedef struct { |
mbed_official | 121:7f86b4238bec | 334 | __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */ |
mbed_official | 121:7f86b4238bec | 335 | __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */ |
mbed_official | 121:7f86b4238bec | 336 | __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */ |
mbed_official | 121:7f86b4238bec | 337 | __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */ |
mbed_official | 121:7f86b4238bec | 338 | __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */ |
mbed_official | 121:7f86b4238bec | 339 | __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */ |
mbed_official | 121:7f86b4238bec | 340 | __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */ |
mbed_official | 121:7f86b4238bec | 341 | __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */ |
mbed_official | 121:7f86b4238bec | 342 | __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */ |
mbed_official | 121:7f86b4238bec | 343 | __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */ |
mbed_official | 121:7f86b4238bec | 344 | __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */ |
mbed_official | 121:7f86b4238bec | 345 | __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */ |
mbed_official | 121:7f86b4238bec | 346 | __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */ |
mbed_official | 121:7f86b4238bec | 347 | __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */ |
mbed_official | 121:7f86b4238bec | 348 | __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */ |
mbed_official | 121:7f86b4238bec | 349 | __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */ |
mbed_official | 121:7f86b4238bec | 350 | __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */ |
mbed_official | 121:7f86b4238bec | 351 | __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */ |
mbed_official | 121:7f86b4238bec | 352 | uint8_t RESERVED_0[4]; |
mbed_official | 121:7f86b4238bec | 353 | __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */ |
mbed_official | 121:7f86b4238bec | 354 | __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */ |
mbed_official | 121:7f86b4238bec | 355 | __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */ |
mbed_official | 121:7f86b4238bec | 356 | __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */ |
mbed_official | 121:7f86b4238bec | 357 | __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */ |
mbed_official | 121:7f86b4238bec | 358 | __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */ |
mbed_official | 121:7f86b4238bec | 359 | __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */ |
mbed_official | 121:7f86b4238bec | 360 | } ADC_Type; |
mbed_official | 121:7f86b4238bec | 361 | |
mbed_official | 121:7f86b4238bec | 362 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 363 | -- ADC Register Masks |
mbed_official | 121:7f86b4238bec | 364 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 365 | |
mbed_official | 121:7f86b4238bec | 366 | /*! |
mbed_official | 121:7f86b4238bec | 367 | * @addtogroup ADC_Register_Masks ADC Register Masks |
mbed_official | 121:7f86b4238bec | 368 | * @{ |
mbed_official | 121:7f86b4238bec | 369 | */ |
mbed_official | 121:7f86b4238bec | 370 | |
mbed_official | 121:7f86b4238bec | 371 | /*! @name SC1 - ADC Status and Control Registers 1 */ |
mbed_official | 121:7f86b4238bec | 372 | #define ADC_SC1_ADCH_MASK (0x1FU) |
mbed_official | 121:7f86b4238bec | 373 | #define ADC_SC1_ADCH_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 374 | #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK) |
mbed_official | 121:7f86b4238bec | 375 | #define ADC_SC1_DIFF_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 376 | #define ADC_SC1_DIFF_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 377 | #define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK) |
mbed_official | 121:7f86b4238bec | 378 | #define ADC_SC1_AIEN_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 379 | #define ADC_SC1_AIEN_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 380 | #define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK) |
mbed_official | 121:7f86b4238bec | 381 | #define ADC_SC1_COCO_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 382 | #define ADC_SC1_COCO_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 383 | #define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK) |
mbed_official | 121:7f86b4238bec | 384 | |
mbed_official | 121:7f86b4238bec | 385 | /* The count of ADC_SC1 */ |
mbed_official | 121:7f86b4238bec | 386 | #define ADC_SC1_COUNT (2U) |
mbed_official | 121:7f86b4238bec | 387 | |
mbed_official | 121:7f86b4238bec | 388 | /*! @name CFG1 - ADC Configuration Register 1 */ |
mbed_official | 121:7f86b4238bec | 389 | #define ADC_CFG1_ADICLK_MASK (0x3U) |
mbed_official | 121:7f86b4238bec | 390 | #define ADC_CFG1_ADICLK_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 391 | #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK) |
mbed_official | 121:7f86b4238bec | 392 | #define ADC_CFG1_MODE_MASK (0xCU) |
mbed_official | 121:7f86b4238bec | 393 | #define ADC_CFG1_MODE_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 394 | #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK) |
mbed_official | 121:7f86b4238bec | 395 | #define ADC_CFG1_ADLSMP_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 396 | #define ADC_CFG1_ADLSMP_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 397 | #define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK) |
mbed_official | 121:7f86b4238bec | 398 | #define ADC_CFG1_ADIV_MASK (0x60U) |
mbed_official | 121:7f86b4238bec | 399 | #define ADC_CFG1_ADIV_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 400 | #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK) |
mbed_official | 121:7f86b4238bec | 401 | #define ADC_CFG1_ADLPC_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 402 | #define ADC_CFG1_ADLPC_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 403 | #define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK) |
mbed_official | 121:7f86b4238bec | 404 | |
mbed_official | 121:7f86b4238bec | 405 | /*! @name CFG2 - ADC Configuration Register 2 */ |
mbed_official | 121:7f86b4238bec | 406 | #define ADC_CFG2_ADLSTS_MASK (0x3U) |
mbed_official | 121:7f86b4238bec | 407 | #define ADC_CFG2_ADLSTS_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 408 | #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK) |
mbed_official | 121:7f86b4238bec | 409 | #define ADC_CFG2_ADHSC_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 410 | #define ADC_CFG2_ADHSC_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 411 | #define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK) |
mbed_official | 121:7f86b4238bec | 412 | #define ADC_CFG2_ADACKEN_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 413 | #define ADC_CFG2_ADACKEN_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 414 | #define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK) |
mbed_official | 121:7f86b4238bec | 415 | #define ADC_CFG2_MUXSEL_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 416 | #define ADC_CFG2_MUXSEL_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 417 | #define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK) |
mbed_official | 121:7f86b4238bec | 418 | |
mbed_official | 121:7f86b4238bec | 419 | /*! @name R - ADC Data Result Register */ |
mbed_official | 121:7f86b4238bec | 420 | #define ADC_R_D_MASK (0xFFFFU) |
mbed_official | 121:7f86b4238bec | 421 | #define ADC_R_D_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 422 | #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK) |
mbed_official | 121:7f86b4238bec | 423 | |
mbed_official | 121:7f86b4238bec | 424 | /* The count of ADC_R */ |
mbed_official | 121:7f86b4238bec | 425 | #define ADC_R_COUNT (2U) |
mbed_official | 121:7f86b4238bec | 426 | |
mbed_official | 121:7f86b4238bec | 427 | /*! @name CV1 - Compare Value Registers */ |
mbed_official | 121:7f86b4238bec | 428 | #define ADC_CV1_CV_MASK (0xFFFFU) |
mbed_official | 121:7f86b4238bec | 429 | #define ADC_CV1_CV_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 430 | #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK) |
mbed_official | 121:7f86b4238bec | 431 | |
mbed_official | 121:7f86b4238bec | 432 | /*! @name CV2 - Compare Value Registers */ |
mbed_official | 121:7f86b4238bec | 433 | #define ADC_CV2_CV_MASK (0xFFFFU) |
mbed_official | 121:7f86b4238bec | 434 | #define ADC_CV2_CV_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 435 | #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK) |
mbed_official | 121:7f86b4238bec | 436 | |
mbed_official | 121:7f86b4238bec | 437 | /*! @name SC2 - Status and Control Register 2 */ |
mbed_official | 121:7f86b4238bec | 438 | #define ADC_SC2_REFSEL_MASK (0x3U) |
mbed_official | 121:7f86b4238bec | 439 | #define ADC_SC2_REFSEL_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 440 | #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK) |
mbed_official | 121:7f86b4238bec | 441 | #define ADC_SC2_DMAEN_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 442 | #define ADC_SC2_DMAEN_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 443 | #define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK) |
mbed_official | 121:7f86b4238bec | 444 | #define ADC_SC2_ACREN_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 445 | #define ADC_SC2_ACREN_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 446 | #define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK) |
mbed_official | 121:7f86b4238bec | 447 | #define ADC_SC2_ACFGT_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 448 | #define ADC_SC2_ACFGT_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 449 | #define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK) |
mbed_official | 121:7f86b4238bec | 450 | #define ADC_SC2_ACFE_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 451 | #define ADC_SC2_ACFE_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 452 | #define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK) |
mbed_official | 121:7f86b4238bec | 453 | #define ADC_SC2_ADTRG_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 454 | #define ADC_SC2_ADTRG_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 455 | #define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK) |
mbed_official | 121:7f86b4238bec | 456 | #define ADC_SC2_ADACT_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 457 | #define ADC_SC2_ADACT_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 458 | #define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK) |
mbed_official | 121:7f86b4238bec | 459 | |
mbed_official | 121:7f86b4238bec | 460 | /*! @name SC3 - Status and Control Register 3 */ |
mbed_official | 121:7f86b4238bec | 461 | #define ADC_SC3_AVGS_MASK (0x3U) |
mbed_official | 121:7f86b4238bec | 462 | #define ADC_SC3_AVGS_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 463 | #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK) |
mbed_official | 121:7f86b4238bec | 464 | #define ADC_SC3_AVGE_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 465 | #define ADC_SC3_AVGE_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 466 | #define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK) |
mbed_official | 121:7f86b4238bec | 467 | #define ADC_SC3_ADCO_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 468 | #define ADC_SC3_ADCO_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 469 | #define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK) |
mbed_official | 121:7f86b4238bec | 470 | #define ADC_SC3_CALF_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 471 | #define ADC_SC3_CALF_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 472 | #define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK) |
mbed_official | 121:7f86b4238bec | 473 | #define ADC_SC3_CAL_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 474 | #define ADC_SC3_CAL_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 475 | #define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK) |
mbed_official | 121:7f86b4238bec | 476 | |
mbed_official | 121:7f86b4238bec | 477 | /*! @name OFS - ADC Offset Correction Register */ |
mbed_official | 121:7f86b4238bec | 478 | #define ADC_OFS_OFS_MASK (0xFFFFU) |
mbed_official | 121:7f86b4238bec | 479 | #define ADC_OFS_OFS_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 480 | #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK) |
mbed_official | 121:7f86b4238bec | 481 | |
mbed_official | 121:7f86b4238bec | 482 | /*! @name PG - ADC Plus-Side Gain Register */ |
mbed_official | 121:7f86b4238bec | 483 | #define ADC_PG_PG_MASK (0xFFFFU) |
mbed_official | 121:7f86b4238bec | 484 | #define ADC_PG_PG_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 485 | #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK) |
mbed_official | 121:7f86b4238bec | 486 | |
mbed_official | 121:7f86b4238bec | 487 | /*! @name MG - ADC Minus-Side Gain Register */ |
mbed_official | 121:7f86b4238bec | 488 | #define ADC_MG_MG_MASK (0xFFFFU) |
mbed_official | 121:7f86b4238bec | 489 | #define ADC_MG_MG_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 490 | #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK) |
mbed_official | 121:7f86b4238bec | 491 | |
mbed_official | 121:7f86b4238bec | 492 | /*! @name CLPD - ADC Plus-Side General Calibration Value Register */ |
mbed_official | 121:7f86b4238bec | 493 | #define ADC_CLPD_CLPD_MASK (0x3FU) |
mbed_official | 121:7f86b4238bec | 494 | #define ADC_CLPD_CLPD_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 495 | #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK) |
mbed_official | 121:7f86b4238bec | 496 | |
mbed_official | 121:7f86b4238bec | 497 | /*! @name CLPS - ADC Plus-Side General Calibration Value Register */ |
mbed_official | 121:7f86b4238bec | 498 | #define ADC_CLPS_CLPS_MASK (0x3FU) |
mbed_official | 121:7f86b4238bec | 499 | #define ADC_CLPS_CLPS_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 500 | #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK) |
mbed_official | 121:7f86b4238bec | 501 | |
mbed_official | 121:7f86b4238bec | 502 | /*! @name CLP4 - ADC Plus-Side General Calibration Value Register */ |
mbed_official | 121:7f86b4238bec | 503 | #define ADC_CLP4_CLP4_MASK (0x3FFU) |
mbed_official | 121:7f86b4238bec | 504 | #define ADC_CLP4_CLP4_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 505 | #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK) |
mbed_official | 121:7f86b4238bec | 506 | |
mbed_official | 121:7f86b4238bec | 507 | /*! @name CLP3 - ADC Plus-Side General Calibration Value Register */ |
mbed_official | 121:7f86b4238bec | 508 | #define ADC_CLP3_CLP3_MASK (0x1FFU) |
mbed_official | 121:7f86b4238bec | 509 | #define ADC_CLP3_CLP3_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 510 | #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK) |
mbed_official | 121:7f86b4238bec | 511 | |
mbed_official | 121:7f86b4238bec | 512 | /*! @name CLP2 - ADC Plus-Side General Calibration Value Register */ |
mbed_official | 121:7f86b4238bec | 513 | #define ADC_CLP2_CLP2_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 514 | #define ADC_CLP2_CLP2_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 515 | #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK) |
mbed_official | 121:7f86b4238bec | 516 | |
mbed_official | 121:7f86b4238bec | 517 | /*! @name CLP1 - ADC Plus-Side General Calibration Value Register */ |
mbed_official | 121:7f86b4238bec | 518 | #define ADC_CLP1_CLP1_MASK (0x7FU) |
mbed_official | 121:7f86b4238bec | 519 | #define ADC_CLP1_CLP1_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 520 | #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK) |
mbed_official | 121:7f86b4238bec | 521 | |
mbed_official | 121:7f86b4238bec | 522 | /*! @name CLP0 - ADC Plus-Side General Calibration Value Register */ |
mbed_official | 121:7f86b4238bec | 523 | #define ADC_CLP0_CLP0_MASK (0x3FU) |
mbed_official | 121:7f86b4238bec | 524 | #define ADC_CLP0_CLP0_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 525 | #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK) |
mbed_official | 121:7f86b4238bec | 526 | |
mbed_official | 121:7f86b4238bec | 527 | /*! @name CLMD - ADC Minus-Side General Calibration Value Register */ |
mbed_official | 121:7f86b4238bec | 528 | #define ADC_CLMD_CLMD_MASK (0x3FU) |
mbed_official | 121:7f86b4238bec | 529 | #define ADC_CLMD_CLMD_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 530 | #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK) |
mbed_official | 121:7f86b4238bec | 531 | |
mbed_official | 121:7f86b4238bec | 532 | /*! @name CLMS - ADC Minus-Side General Calibration Value Register */ |
mbed_official | 121:7f86b4238bec | 533 | #define ADC_CLMS_CLMS_MASK (0x3FU) |
mbed_official | 121:7f86b4238bec | 534 | #define ADC_CLMS_CLMS_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 535 | #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK) |
mbed_official | 121:7f86b4238bec | 536 | |
mbed_official | 121:7f86b4238bec | 537 | /*! @name CLM4 - ADC Minus-Side General Calibration Value Register */ |
mbed_official | 121:7f86b4238bec | 538 | #define ADC_CLM4_CLM4_MASK (0x3FFU) |
mbed_official | 121:7f86b4238bec | 539 | #define ADC_CLM4_CLM4_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 540 | #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK) |
mbed_official | 121:7f86b4238bec | 541 | |
mbed_official | 121:7f86b4238bec | 542 | /*! @name CLM3 - ADC Minus-Side General Calibration Value Register */ |
mbed_official | 121:7f86b4238bec | 543 | #define ADC_CLM3_CLM3_MASK (0x1FFU) |
mbed_official | 121:7f86b4238bec | 544 | #define ADC_CLM3_CLM3_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 545 | #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK) |
mbed_official | 121:7f86b4238bec | 546 | |
mbed_official | 121:7f86b4238bec | 547 | /*! @name CLM2 - ADC Minus-Side General Calibration Value Register */ |
mbed_official | 121:7f86b4238bec | 548 | #define ADC_CLM2_CLM2_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 549 | #define ADC_CLM2_CLM2_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 550 | #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK) |
mbed_official | 121:7f86b4238bec | 551 | |
mbed_official | 121:7f86b4238bec | 552 | /*! @name CLM1 - ADC Minus-Side General Calibration Value Register */ |
mbed_official | 121:7f86b4238bec | 553 | #define ADC_CLM1_CLM1_MASK (0x7FU) |
mbed_official | 121:7f86b4238bec | 554 | #define ADC_CLM1_CLM1_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 555 | #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK) |
mbed_official | 121:7f86b4238bec | 556 | |
mbed_official | 121:7f86b4238bec | 557 | /*! @name CLM0 - ADC Minus-Side General Calibration Value Register */ |
mbed_official | 121:7f86b4238bec | 558 | #define ADC_CLM0_CLM0_MASK (0x3FU) |
mbed_official | 121:7f86b4238bec | 559 | #define ADC_CLM0_CLM0_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 560 | #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK) |
mbed_official | 121:7f86b4238bec | 561 | |
mbed_official | 121:7f86b4238bec | 562 | |
mbed_official | 121:7f86b4238bec | 563 | /*! |
mbed_official | 121:7f86b4238bec | 564 | * @} |
mbed_official | 121:7f86b4238bec | 565 | */ /* end of group ADC_Register_Masks */ |
mbed_official | 121:7f86b4238bec | 566 | |
mbed_official | 121:7f86b4238bec | 567 | |
mbed_official | 121:7f86b4238bec | 568 | /* ADC - Peripheral instance base addresses */ |
mbed_official | 121:7f86b4238bec | 569 | /** Peripheral ADC0 base address */ |
mbed_official | 121:7f86b4238bec | 570 | #define ADC0_BASE (0x4003B000u) |
mbed_official | 121:7f86b4238bec | 571 | /** Peripheral ADC0 base pointer */ |
mbed_official | 121:7f86b4238bec | 572 | #define ADC0 ((ADC_Type *)ADC0_BASE) |
mbed_official | 121:7f86b4238bec | 573 | /** Array initializer of ADC peripheral base addresses */ |
mbed_official | 121:7f86b4238bec | 574 | #define ADC_BASE_ADDRS { ADC0_BASE } |
mbed_official | 121:7f86b4238bec | 575 | /** Array initializer of ADC peripheral base pointers */ |
mbed_official | 121:7f86b4238bec | 576 | #define ADC_BASE_PTRS { ADC0 } |
mbed_official | 121:7f86b4238bec | 577 | /** Interrupt vectors for the ADC peripheral type */ |
mbed_official | 121:7f86b4238bec | 578 | #define ADC_IRQS { ADC0_IRQn } |
mbed_official | 121:7f86b4238bec | 579 | |
mbed_official | 121:7f86b4238bec | 580 | /*! |
mbed_official | 121:7f86b4238bec | 581 | * @} |
mbed_official | 121:7f86b4238bec | 582 | */ /* end of group ADC_Peripheral_Access_Layer */ |
mbed_official | 121:7f86b4238bec | 583 | |
mbed_official | 121:7f86b4238bec | 584 | |
mbed_official | 121:7f86b4238bec | 585 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 586 | -- CMP Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 587 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 588 | |
mbed_official | 121:7f86b4238bec | 589 | /*! |
mbed_official | 121:7f86b4238bec | 590 | * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 591 | * @{ |
mbed_official | 121:7f86b4238bec | 592 | */ |
mbed_official | 121:7f86b4238bec | 593 | |
mbed_official | 121:7f86b4238bec | 594 | /** CMP - Register Layout Typedef */ |
mbed_official | 121:7f86b4238bec | 595 | typedef struct { |
mbed_official | 121:7f86b4238bec | 596 | __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ |
mbed_official | 121:7f86b4238bec | 597 | __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ |
mbed_official | 121:7f86b4238bec | 598 | __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */ |
mbed_official | 121:7f86b4238bec | 599 | __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */ |
mbed_official | 121:7f86b4238bec | 600 | __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */ |
mbed_official | 121:7f86b4238bec | 601 | __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ |
mbed_official | 121:7f86b4238bec | 602 | } CMP_Type; |
mbed_official | 121:7f86b4238bec | 603 | |
mbed_official | 121:7f86b4238bec | 604 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 605 | -- CMP Register Masks |
mbed_official | 121:7f86b4238bec | 606 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 607 | |
mbed_official | 121:7f86b4238bec | 608 | /*! |
mbed_official | 121:7f86b4238bec | 609 | * @addtogroup CMP_Register_Masks CMP Register Masks |
mbed_official | 121:7f86b4238bec | 610 | * @{ |
mbed_official | 121:7f86b4238bec | 611 | */ |
mbed_official | 121:7f86b4238bec | 612 | |
mbed_official | 121:7f86b4238bec | 613 | /*! @name CR0 - CMP Control Register 0 */ |
mbed_official | 121:7f86b4238bec | 614 | #define CMP_CR0_HYSTCTR_MASK (0x3U) |
mbed_official | 121:7f86b4238bec | 615 | #define CMP_CR0_HYSTCTR_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 616 | #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK) |
mbed_official | 121:7f86b4238bec | 617 | #define CMP_CR0_FILTER_CNT_MASK (0x70U) |
mbed_official | 121:7f86b4238bec | 618 | #define CMP_CR0_FILTER_CNT_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 619 | #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK) |
mbed_official | 121:7f86b4238bec | 620 | |
mbed_official | 121:7f86b4238bec | 621 | /*! @name CR1 - CMP Control Register 1 */ |
mbed_official | 121:7f86b4238bec | 622 | #define CMP_CR1_EN_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 623 | #define CMP_CR1_EN_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 624 | #define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK) |
mbed_official | 121:7f86b4238bec | 625 | #define CMP_CR1_OPE_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 626 | #define CMP_CR1_OPE_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 627 | #define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK) |
mbed_official | 121:7f86b4238bec | 628 | #define CMP_CR1_COS_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 629 | #define CMP_CR1_COS_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 630 | #define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK) |
mbed_official | 121:7f86b4238bec | 631 | #define CMP_CR1_INV_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 632 | #define CMP_CR1_INV_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 633 | #define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK) |
mbed_official | 121:7f86b4238bec | 634 | #define CMP_CR1_PMODE_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 635 | #define CMP_CR1_PMODE_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 636 | #define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK) |
mbed_official | 121:7f86b4238bec | 637 | #define CMP_CR1_TRIGM_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 638 | #define CMP_CR1_TRIGM_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 639 | #define CMP_CR1_TRIGM(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK) |
mbed_official | 121:7f86b4238bec | 640 | #define CMP_CR1_WE_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 641 | #define CMP_CR1_WE_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 642 | #define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK) |
mbed_official | 121:7f86b4238bec | 643 | #define CMP_CR1_SE_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 644 | #define CMP_CR1_SE_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 645 | #define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK) |
mbed_official | 121:7f86b4238bec | 646 | |
mbed_official | 121:7f86b4238bec | 647 | /*! @name FPR - CMP Filter Period Register */ |
mbed_official | 121:7f86b4238bec | 648 | #define CMP_FPR_FILT_PER_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 649 | #define CMP_FPR_FILT_PER_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 650 | #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK) |
mbed_official | 121:7f86b4238bec | 651 | |
mbed_official | 121:7f86b4238bec | 652 | /*! @name SCR - CMP Status and Control Register */ |
mbed_official | 121:7f86b4238bec | 653 | #define CMP_SCR_COUT_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 654 | #define CMP_SCR_COUT_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 655 | #define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK) |
mbed_official | 121:7f86b4238bec | 656 | #define CMP_SCR_CFF_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 657 | #define CMP_SCR_CFF_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 658 | #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK) |
mbed_official | 121:7f86b4238bec | 659 | #define CMP_SCR_CFR_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 660 | #define CMP_SCR_CFR_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 661 | #define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK) |
mbed_official | 121:7f86b4238bec | 662 | #define CMP_SCR_IEF_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 663 | #define CMP_SCR_IEF_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 664 | #define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK) |
mbed_official | 121:7f86b4238bec | 665 | #define CMP_SCR_IER_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 666 | #define CMP_SCR_IER_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 667 | #define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK) |
mbed_official | 121:7f86b4238bec | 668 | #define CMP_SCR_DMAEN_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 669 | #define CMP_SCR_DMAEN_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 670 | #define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK) |
mbed_official | 121:7f86b4238bec | 671 | |
mbed_official | 121:7f86b4238bec | 672 | /*! @name DACCR - DAC Control Register */ |
mbed_official | 121:7f86b4238bec | 673 | #define CMP_DACCR_VOSEL_MASK (0x3FU) |
mbed_official | 121:7f86b4238bec | 674 | #define CMP_DACCR_VOSEL_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 675 | #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK) |
mbed_official | 121:7f86b4238bec | 676 | #define CMP_DACCR_VRSEL_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 677 | #define CMP_DACCR_VRSEL_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 678 | #define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK) |
mbed_official | 121:7f86b4238bec | 679 | #define CMP_DACCR_DACEN_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 680 | #define CMP_DACCR_DACEN_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 681 | #define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK) |
mbed_official | 121:7f86b4238bec | 682 | |
mbed_official | 121:7f86b4238bec | 683 | /*! @name MUXCR - MUX Control Register */ |
mbed_official | 121:7f86b4238bec | 684 | #define CMP_MUXCR_MSEL_MASK (0x7U) |
mbed_official | 121:7f86b4238bec | 685 | #define CMP_MUXCR_MSEL_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 686 | #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK) |
mbed_official | 121:7f86b4238bec | 687 | #define CMP_MUXCR_PSEL_MASK (0x38U) |
mbed_official | 121:7f86b4238bec | 688 | #define CMP_MUXCR_PSEL_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 689 | #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK) |
mbed_official | 121:7f86b4238bec | 690 | #define CMP_MUXCR_PSTM_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 691 | #define CMP_MUXCR_PSTM_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 692 | #define CMP_MUXCR_PSTM(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK) |
mbed_official | 121:7f86b4238bec | 693 | |
mbed_official | 121:7f86b4238bec | 694 | |
mbed_official | 121:7f86b4238bec | 695 | /*! |
mbed_official | 121:7f86b4238bec | 696 | * @} |
mbed_official | 121:7f86b4238bec | 697 | */ /* end of group CMP_Register_Masks */ |
mbed_official | 121:7f86b4238bec | 698 | |
mbed_official | 121:7f86b4238bec | 699 | |
mbed_official | 121:7f86b4238bec | 700 | /* CMP - Peripheral instance base addresses */ |
mbed_official | 121:7f86b4238bec | 701 | /** Peripheral CMP0 base address */ |
mbed_official | 121:7f86b4238bec | 702 | #define CMP0_BASE (0x40073000u) |
mbed_official | 121:7f86b4238bec | 703 | /** Peripheral CMP0 base pointer */ |
mbed_official | 121:7f86b4238bec | 704 | #define CMP0 ((CMP_Type *)CMP0_BASE) |
mbed_official | 121:7f86b4238bec | 705 | /** Array initializer of CMP peripheral base addresses */ |
mbed_official | 121:7f86b4238bec | 706 | #define CMP_BASE_ADDRS { CMP0_BASE } |
mbed_official | 121:7f86b4238bec | 707 | /** Array initializer of CMP peripheral base pointers */ |
mbed_official | 121:7f86b4238bec | 708 | #define CMP_BASE_PTRS { CMP0 } |
mbed_official | 121:7f86b4238bec | 709 | /** Interrupt vectors for the CMP peripheral type */ |
mbed_official | 121:7f86b4238bec | 710 | #define CMP_IRQS { CMP0_IRQn } |
mbed_official | 121:7f86b4238bec | 711 | |
mbed_official | 121:7f86b4238bec | 712 | /*! |
mbed_official | 121:7f86b4238bec | 713 | * @} |
mbed_official | 121:7f86b4238bec | 714 | */ /* end of group CMP_Peripheral_Access_Layer */ |
mbed_official | 121:7f86b4238bec | 715 | |
mbed_official | 121:7f86b4238bec | 716 | |
mbed_official | 121:7f86b4238bec | 717 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 718 | -- CRC Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 719 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 720 | |
mbed_official | 121:7f86b4238bec | 721 | /*! |
mbed_official | 121:7f86b4238bec | 722 | * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 723 | * @{ |
mbed_official | 121:7f86b4238bec | 724 | */ |
mbed_official | 121:7f86b4238bec | 725 | |
mbed_official | 121:7f86b4238bec | 726 | /** CRC - Register Layout Typedef */ |
mbed_official | 121:7f86b4238bec | 727 | typedef struct { |
mbed_official | 121:7f86b4238bec | 728 | union { /* offset: 0x0 */ |
mbed_official | 121:7f86b4238bec | 729 | struct { /* offset: 0x0 */ |
mbed_official | 121:7f86b4238bec | 730 | __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */ |
mbed_official | 121:7f86b4238bec | 731 | __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */ |
mbed_official | 121:7f86b4238bec | 732 | } ACCESS16BIT; |
mbed_official | 121:7f86b4238bec | 733 | __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */ |
mbed_official | 121:7f86b4238bec | 734 | struct { /* offset: 0x0 */ |
mbed_official | 121:7f86b4238bec | 735 | __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */ |
mbed_official | 121:7f86b4238bec | 736 | __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */ |
mbed_official | 121:7f86b4238bec | 737 | __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */ |
mbed_official | 121:7f86b4238bec | 738 | __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */ |
mbed_official | 121:7f86b4238bec | 739 | } ACCESS8BIT; |
mbed_official | 121:7f86b4238bec | 740 | }; |
mbed_official | 121:7f86b4238bec | 741 | union { /* offset: 0x4 */ |
mbed_official | 121:7f86b4238bec | 742 | struct { /* offset: 0x4 */ |
mbed_official | 121:7f86b4238bec | 743 | __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */ |
mbed_official | 121:7f86b4238bec | 744 | __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */ |
mbed_official | 121:7f86b4238bec | 745 | } GPOLY_ACCESS16BIT; |
mbed_official | 121:7f86b4238bec | 746 | __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */ |
mbed_official | 121:7f86b4238bec | 747 | struct { /* offset: 0x4 */ |
mbed_official | 121:7f86b4238bec | 748 | __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */ |
mbed_official | 121:7f86b4238bec | 749 | __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */ |
mbed_official | 121:7f86b4238bec | 750 | __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */ |
mbed_official | 121:7f86b4238bec | 751 | __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */ |
mbed_official | 121:7f86b4238bec | 752 | } GPOLY_ACCESS8BIT; |
mbed_official | 121:7f86b4238bec | 753 | }; |
mbed_official | 121:7f86b4238bec | 754 | union { /* offset: 0x8 */ |
mbed_official | 121:7f86b4238bec | 755 | __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */ |
mbed_official | 121:7f86b4238bec | 756 | struct { /* offset: 0x8 */ |
mbed_official | 121:7f86b4238bec | 757 | uint8_t RESERVED_0[3]; |
mbed_official | 121:7f86b4238bec | 758 | __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */ |
mbed_official | 121:7f86b4238bec | 759 | } CTRL_ACCESS8BIT; |
mbed_official | 121:7f86b4238bec | 760 | }; |
mbed_official | 121:7f86b4238bec | 761 | } CRC_Type; |
mbed_official | 121:7f86b4238bec | 762 | |
mbed_official | 121:7f86b4238bec | 763 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 764 | -- CRC Register Masks |
mbed_official | 121:7f86b4238bec | 765 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 766 | |
mbed_official | 121:7f86b4238bec | 767 | /*! |
mbed_official | 121:7f86b4238bec | 768 | * @addtogroup CRC_Register_Masks CRC Register Masks |
mbed_official | 121:7f86b4238bec | 769 | * @{ |
mbed_official | 121:7f86b4238bec | 770 | */ |
mbed_official | 121:7f86b4238bec | 771 | |
mbed_official | 121:7f86b4238bec | 772 | /*! @name DATAL - CRC_DATAL register. */ |
mbed_official | 121:7f86b4238bec | 773 | #define CRC_DATAL_DATAL_MASK (0xFFFFU) |
mbed_official | 121:7f86b4238bec | 774 | #define CRC_DATAL_DATAL_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 775 | #define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK) |
mbed_official | 121:7f86b4238bec | 776 | |
mbed_official | 121:7f86b4238bec | 777 | /*! @name DATAH - CRC_DATAH register. */ |
mbed_official | 121:7f86b4238bec | 778 | #define CRC_DATAH_DATAH_MASK (0xFFFFU) |
mbed_official | 121:7f86b4238bec | 779 | #define CRC_DATAH_DATAH_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 780 | #define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK) |
mbed_official | 121:7f86b4238bec | 781 | |
mbed_official | 121:7f86b4238bec | 782 | /*! @name DATA - CRC Data register */ |
mbed_official | 121:7f86b4238bec | 783 | #define CRC_DATA_LL_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 784 | #define CRC_DATA_LL_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 785 | #define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK) |
mbed_official | 121:7f86b4238bec | 786 | #define CRC_DATA_LU_MASK (0xFF00U) |
mbed_official | 121:7f86b4238bec | 787 | #define CRC_DATA_LU_SHIFT (8U) |
mbed_official | 121:7f86b4238bec | 788 | #define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK) |
mbed_official | 121:7f86b4238bec | 789 | #define CRC_DATA_HL_MASK (0xFF0000U) |
mbed_official | 121:7f86b4238bec | 790 | #define CRC_DATA_HL_SHIFT (16U) |
mbed_official | 121:7f86b4238bec | 791 | #define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK) |
mbed_official | 121:7f86b4238bec | 792 | #define CRC_DATA_HU_MASK (0xFF000000U) |
mbed_official | 121:7f86b4238bec | 793 | #define CRC_DATA_HU_SHIFT (24U) |
mbed_official | 121:7f86b4238bec | 794 | #define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK) |
mbed_official | 121:7f86b4238bec | 795 | |
mbed_official | 121:7f86b4238bec | 796 | /*! @name DATALL - CRC_DATALL register. */ |
mbed_official | 121:7f86b4238bec | 797 | #define CRC_DATALL_DATALL_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 798 | #define CRC_DATALL_DATALL_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 799 | #define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK) |
mbed_official | 121:7f86b4238bec | 800 | |
mbed_official | 121:7f86b4238bec | 801 | /*! @name DATALU - CRC_DATALU register. */ |
mbed_official | 121:7f86b4238bec | 802 | #define CRC_DATALU_DATALU_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 803 | #define CRC_DATALU_DATALU_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 804 | #define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK) |
mbed_official | 121:7f86b4238bec | 805 | |
mbed_official | 121:7f86b4238bec | 806 | /*! @name DATAHL - CRC_DATAHL register. */ |
mbed_official | 121:7f86b4238bec | 807 | #define CRC_DATAHL_DATAHL_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 808 | #define CRC_DATAHL_DATAHL_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 809 | #define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK) |
mbed_official | 121:7f86b4238bec | 810 | |
mbed_official | 121:7f86b4238bec | 811 | /*! @name DATAHU - CRC_DATAHU register. */ |
mbed_official | 121:7f86b4238bec | 812 | #define CRC_DATAHU_DATAHU_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 813 | #define CRC_DATAHU_DATAHU_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 814 | #define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK) |
mbed_official | 121:7f86b4238bec | 815 | |
mbed_official | 121:7f86b4238bec | 816 | /*! @name GPOLYL - CRC_GPOLYL register. */ |
mbed_official | 121:7f86b4238bec | 817 | #define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU) |
mbed_official | 121:7f86b4238bec | 818 | #define CRC_GPOLYL_GPOLYL_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 819 | #define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK) |
mbed_official | 121:7f86b4238bec | 820 | |
mbed_official | 121:7f86b4238bec | 821 | /*! @name GPOLYH - CRC_GPOLYH register. */ |
mbed_official | 121:7f86b4238bec | 822 | #define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU) |
mbed_official | 121:7f86b4238bec | 823 | #define CRC_GPOLYH_GPOLYH_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 824 | #define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK) |
mbed_official | 121:7f86b4238bec | 825 | |
mbed_official | 121:7f86b4238bec | 826 | /*! @name GPOLY - CRC Polynomial register */ |
mbed_official | 121:7f86b4238bec | 827 | #define CRC_GPOLY_LOW_MASK (0xFFFFU) |
mbed_official | 121:7f86b4238bec | 828 | #define CRC_GPOLY_LOW_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 829 | #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK) |
mbed_official | 121:7f86b4238bec | 830 | #define CRC_GPOLY_HIGH_MASK (0xFFFF0000U) |
mbed_official | 121:7f86b4238bec | 831 | #define CRC_GPOLY_HIGH_SHIFT (16U) |
mbed_official | 121:7f86b4238bec | 832 | #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK) |
mbed_official | 121:7f86b4238bec | 833 | |
mbed_official | 121:7f86b4238bec | 834 | /*! @name GPOLYLL - CRC_GPOLYLL register. */ |
mbed_official | 121:7f86b4238bec | 835 | #define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 836 | #define CRC_GPOLYLL_GPOLYLL_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 837 | #define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK) |
mbed_official | 121:7f86b4238bec | 838 | |
mbed_official | 121:7f86b4238bec | 839 | /*! @name GPOLYLU - CRC_GPOLYLU register. */ |
mbed_official | 121:7f86b4238bec | 840 | #define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 841 | #define CRC_GPOLYLU_GPOLYLU_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 842 | #define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK) |
mbed_official | 121:7f86b4238bec | 843 | |
mbed_official | 121:7f86b4238bec | 844 | /*! @name GPOLYHL - CRC_GPOLYHL register. */ |
mbed_official | 121:7f86b4238bec | 845 | #define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 846 | #define CRC_GPOLYHL_GPOLYHL_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 847 | #define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK) |
mbed_official | 121:7f86b4238bec | 848 | |
mbed_official | 121:7f86b4238bec | 849 | /*! @name GPOLYHU - CRC_GPOLYHU register. */ |
mbed_official | 121:7f86b4238bec | 850 | #define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 851 | #define CRC_GPOLYHU_GPOLYHU_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 852 | #define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK) |
mbed_official | 121:7f86b4238bec | 853 | |
mbed_official | 121:7f86b4238bec | 854 | /*! @name CTRL - CRC Control register */ |
mbed_official | 121:7f86b4238bec | 855 | #define CRC_CTRL_TCRC_MASK (0x1000000U) |
mbed_official | 121:7f86b4238bec | 856 | #define CRC_CTRL_TCRC_SHIFT (24U) |
mbed_official | 121:7f86b4238bec | 857 | #define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK) |
mbed_official | 121:7f86b4238bec | 858 | #define CRC_CTRL_WAS_MASK (0x2000000U) |
mbed_official | 121:7f86b4238bec | 859 | #define CRC_CTRL_WAS_SHIFT (25U) |
mbed_official | 121:7f86b4238bec | 860 | #define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK) |
mbed_official | 121:7f86b4238bec | 861 | #define CRC_CTRL_FXOR_MASK (0x4000000U) |
mbed_official | 121:7f86b4238bec | 862 | #define CRC_CTRL_FXOR_SHIFT (26U) |
mbed_official | 121:7f86b4238bec | 863 | #define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK) |
mbed_official | 121:7f86b4238bec | 864 | #define CRC_CTRL_TOTR_MASK (0x30000000U) |
mbed_official | 121:7f86b4238bec | 865 | #define CRC_CTRL_TOTR_SHIFT (28U) |
mbed_official | 121:7f86b4238bec | 866 | #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK) |
mbed_official | 121:7f86b4238bec | 867 | #define CRC_CTRL_TOT_MASK (0xC0000000U) |
mbed_official | 121:7f86b4238bec | 868 | #define CRC_CTRL_TOT_SHIFT (30U) |
mbed_official | 121:7f86b4238bec | 869 | #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK) |
mbed_official | 121:7f86b4238bec | 870 | |
mbed_official | 121:7f86b4238bec | 871 | /*! @name CTRLHU - CRC_CTRLHU register. */ |
mbed_official | 121:7f86b4238bec | 872 | #define CRC_CTRLHU_TCRC_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 873 | #define CRC_CTRLHU_TCRC_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 874 | #define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK) |
mbed_official | 121:7f86b4238bec | 875 | #define CRC_CTRLHU_WAS_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 876 | #define CRC_CTRLHU_WAS_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 877 | #define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK) |
mbed_official | 121:7f86b4238bec | 878 | #define CRC_CTRLHU_FXOR_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 879 | #define CRC_CTRLHU_FXOR_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 880 | #define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK) |
mbed_official | 121:7f86b4238bec | 881 | #define CRC_CTRLHU_TOTR_MASK (0x30U) |
mbed_official | 121:7f86b4238bec | 882 | #define CRC_CTRLHU_TOTR_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 883 | #define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK) |
mbed_official | 121:7f86b4238bec | 884 | #define CRC_CTRLHU_TOT_MASK (0xC0U) |
mbed_official | 121:7f86b4238bec | 885 | #define CRC_CTRLHU_TOT_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 886 | #define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK) |
mbed_official | 121:7f86b4238bec | 887 | |
mbed_official | 121:7f86b4238bec | 888 | |
mbed_official | 121:7f86b4238bec | 889 | /*! |
mbed_official | 121:7f86b4238bec | 890 | * @} |
mbed_official | 121:7f86b4238bec | 891 | */ /* end of group CRC_Register_Masks */ |
mbed_official | 121:7f86b4238bec | 892 | |
mbed_official | 121:7f86b4238bec | 893 | |
mbed_official | 121:7f86b4238bec | 894 | /* CRC - Peripheral instance base addresses */ |
mbed_official | 121:7f86b4238bec | 895 | /** Peripheral CRC base address */ |
mbed_official | 121:7f86b4238bec | 896 | #define CRC_BASE (0x40032000u) |
mbed_official | 121:7f86b4238bec | 897 | /** Peripheral CRC base pointer */ |
mbed_official | 121:7f86b4238bec | 898 | #define CRC0 ((CRC_Type *)CRC_BASE) |
mbed_official | 121:7f86b4238bec | 899 | /** Array initializer of CRC peripheral base addresses */ |
mbed_official | 121:7f86b4238bec | 900 | #define CRC_BASE_ADDRS { CRC_BASE } |
mbed_official | 121:7f86b4238bec | 901 | /** Array initializer of CRC peripheral base pointers */ |
mbed_official | 121:7f86b4238bec | 902 | #define CRC_BASE_PTRS { CRC0 } |
mbed_official | 121:7f86b4238bec | 903 | |
mbed_official | 121:7f86b4238bec | 904 | /*! |
mbed_official | 121:7f86b4238bec | 905 | * @} |
mbed_official | 121:7f86b4238bec | 906 | */ /* end of group CRC_Peripheral_Access_Layer */ |
mbed_official | 121:7f86b4238bec | 907 | |
mbed_official | 121:7f86b4238bec | 908 | |
mbed_official | 121:7f86b4238bec | 909 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 910 | -- DMA Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 911 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 912 | |
mbed_official | 121:7f86b4238bec | 913 | /*! |
mbed_official | 121:7f86b4238bec | 914 | * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 915 | * @{ |
mbed_official | 121:7f86b4238bec | 916 | */ |
mbed_official | 121:7f86b4238bec | 917 | |
mbed_official | 121:7f86b4238bec | 918 | /** DMA - Register Layout Typedef */ |
mbed_official | 121:7f86b4238bec | 919 | typedef struct { |
mbed_official | 121:7f86b4238bec | 920 | uint8_t RESERVED_0[256]; |
mbed_official | 121:7f86b4238bec | 921 | struct { /* offset: 0x100, array step: 0x10 */ |
mbed_official | 121:7f86b4238bec | 922 | __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */ |
mbed_official | 121:7f86b4238bec | 923 | __IO uint32_t DAR; /**< Destination Address Register, array offset: 0x104, array step: 0x10 */ |
mbed_official | 121:7f86b4238bec | 924 | union { /* offset: 0x108, array step: 0x10 */ |
mbed_official | 121:7f86b4238bec | 925 | __IO uint32_t DSR_BCR; /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */ |
mbed_official | 121:7f86b4238bec | 926 | struct { /* offset: 0x108, array step: 0x10 */ |
mbed_official | 121:7f86b4238bec | 927 | uint8_t RESERVED_0[3]; |
mbed_official | 121:7f86b4238bec | 928 | __IO uint8_t DSR; /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */ |
mbed_official | 121:7f86b4238bec | 929 | } DMA_DSR_ACCESS8BIT; |
mbed_official | 121:7f86b4238bec | 930 | }; |
mbed_official | 121:7f86b4238bec | 931 | __IO uint32_t DCR; /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */ |
mbed_official | 121:7f86b4238bec | 932 | } DMA[4]; |
mbed_official | 121:7f86b4238bec | 933 | } DMA_Type; |
mbed_official | 121:7f86b4238bec | 934 | |
mbed_official | 121:7f86b4238bec | 935 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 936 | -- DMA Register Masks |
mbed_official | 121:7f86b4238bec | 937 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 938 | |
mbed_official | 121:7f86b4238bec | 939 | /*! |
mbed_official | 121:7f86b4238bec | 940 | * @addtogroup DMA_Register_Masks DMA Register Masks |
mbed_official | 121:7f86b4238bec | 941 | * @{ |
mbed_official | 121:7f86b4238bec | 942 | */ |
mbed_official | 121:7f86b4238bec | 943 | |
mbed_official | 121:7f86b4238bec | 944 | /*! @name SAR - Source Address Register */ |
mbed_official | 121:7f86b4238bec | 945 | #define DMA_SAR_SAR_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 946 | #define DMA_SAR_SAR_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 947 | #define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SAR_SAR_SHIFT)) & DMA_SAR_SAR_MASK) |
mbed_official | 121:7f86b4238bec | 948 | |
mbed_official | 121:7f86b4238bec | 949 | /* The count of DMA_SAR */ |
mbed_official | 121:7f86b4238bec | 950 | #define DMA_SAR_COUNT (4U) |
mbed_official | 121:7f86b4238bec | 951 | |
mbed_official | 121:7f86b4238bec | 952 | /*! @name DAR - Destination Address Register */ |
mbed_official | 121:7f86b4238bec | 953 | #define DMA_DAR_DAR_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 954 | #define DMA_DAR_DAR_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 955 | #define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DAR_DAR_SHIFT)) & DMA_DAR_DAR_MASK) |
mbed_official | 121:7f86b4238bec | 956 | |
mbed_official | 121:7f86b4238bec | 957 | /* The count of DMA_DAR */ |
mbed_official | 121:7f86b4238bec | 958 | #define DMA_DAR_COUNT (4U) |
mbed_official | 121:7f86b4238bec | 959 | |
mbed_official | 121:7f86b4238bec | 960 | /*! @name DSR_BCR - DMA Status Register / Byte Count Register */ |
mbed_official | 121:7f86b4238bec | 961 | #define DMA_DSR_BCR_BCR_MASK (0xFFFFFFU) |
mbed_official | 121:7f86b4238bec | 962 | #define DMA_DSR_BCR_BCR_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 963 | #define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BCR_SHIFT)) & DMA_DSR_BCR_BCR_MASK) |
mbed_official | 121:7f86b4238bec | 964 | #define DMA_DSR_BCR_DONE_MASK (0x1000000U) |
mbed_official | 121:7f86b4238bec | 965 | #define DMA_DSR_BCR_DONE_SHIFT (24U) |
mbed_official | 121:7f86b4238bec | 966 | #define DMA_DSR_BCR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_DONE_SHIFT)) & DMA_DSR_BCR_DONE_MASK) |
mbed_official | 121:7f86b4238bec | 967 | #define DMA_DSR_BCR_BSY_MASK (0x2000000U) |
mbed_official | 121:7f86b4238bec | 968 | #define DMA_DSR_BCR_BSY_SHIFT (25U) |
mbed_official | 121:7f86b4238bec | 969 | #define DMA_DSR_BCR_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BSY_SHIFT)) & DMA_DSR_BCR_BSY_MASK) |
mbed_official | 121:7f86b4238bec | 970 | #define DMA_DSR_BCR_REQ_MASK (0x4000000U) |
mbed_official | 121:7f86b4238bec | 971 | #define DMA_DSR_BCR_REQ_SHIFT (26U) |
mbed_official | 121:7f86b4238bec | 972 | #define DMA_DSR_BCR_REQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_REQ_SHIFT)) & DMA_DSR_BCR_REQ_MASK) |
mbed_official | 121:7f86b4238bec | 973 | #define DMA_DSR_BCR_BED_MASK (0x10000000U) |
mbed_official | 121:7f86b4238bec | 974 | #define DMA_DSR_BCR_BED_SHIFT (28U) |
mbed_official | 121:7f86b4238bec | 975 | #define DMA_DSR_BCR_BED(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BED_SHIFT)) & DMA_DSR_BCR_BED_MASK) |
mbed_official | 121:7f86b4238bec | 976 | #define DMA_DSR_BCR_BES_MASK (0x20000000U) |
mbed_official | 121:7f86b4238bec | 977 | #define DMA_DSR_BCR_BES_SHIFT (29U) |
mbed_official | 121:7f86b4238bec | 978 | #define DMA_DSR_BCR_BES(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BES_SHIFT)) & DMA_DSR_BCR_BES_MASK) |
mbed_official | 121:7f86b4238bec | 979 | #define DMA_DSR_BCR_CE_MASK (0x40000000U) |
mbed_official | 121:7f86b4238bec | 980 | #define DMA_DSR_BCR_CE_SHIFT (30U) |
mbed_official | 121:7f86b4238bec | 981 | #define DMA_DSR_BCR_CE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_CE_SHIFT)) & DMA_DSR_BCR_CE_MASK) |
mbed_official | 121:7f86b4238bec | 982 | |
mbed_official | 121:7f86b4238bec | 983 | /* The count of DMA_DSR_BCR */ |
mbed_official | 121:7f86b4238bec | 984 | #define DMA_DSR_BCR_COUNT (4U) |
mbed_official | 121:7f86b4238bec | 985 | |
mbed_official | 121:7f86b4238bec | 986 | /* The count of DMA_DSR */ |
mbed_official | 121:7f86b4238bec | 987 | #define DMA_DSR_COUNT (4U) |
mbed_official | 121:7f86b4238bec | 988 | |
mbed_official | 121:7f86b4238bec | 989 | /*! @name DCR - DMA Control Register */ |
mbed_official | 121:7f86b4238bec | 990 | #define DMA_DCR_LCH2_MASK (0x3U) |
mbed_official | 121:7f86b4238bec | 991 | #define DMA_DCR_LCH2_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 992 | #define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_LCH2_SHIFT)) & DMA_DCR_LCH2_MASK) |
mbed_official | 121:7f86b4238bec | 993 | #define DMA_DCR_LCH1_MASK (0xCU) |
mbed_official | 121:7f86b4238bec | 994 | #define DMA_DCR_LCH1_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 995 | #define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_LCH1_SHIFT)) & DMA_DCR_LCH1_MASK) |
mbed_official | 121:7f86b4238bec | 996 | #define DMA_DCR_LINKCC_MASK (0x30U) |
mbed_official | 121:7f86b4238bec | 997 | #define DMA_DCR_LINKCC_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 998 | #define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_LINKCC_SHIFT)) & DMA_DCR_LINKCC_MASK) |
mbed_official | 121:7f86b4238bec | 999 | #define DMA_DCR_D_REQ_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 1000 | #define DMA_DCR_D_REQ_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 1001 | #define DMA_DCR_D_REQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_D_REQ_SHIFT)) & DMA_DCR_D_REQ_MASK) |
mbed_official | 121:7f86b4238bec | 1002 | #define DMA_DCR_DMOD_MASK (0xF00U) |
mbed_official | 121:7f86b4238bec | 1003 | #define DMA_DCR_DMOD_SHIFT (8U) |
mbed_official | 121:7f86b4238bec | 1004 | #define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_DMOD_SHIFT)) & DMA_DCR_DMOD_MASK) |
mbed_official | 121:7f86b4238bec | 1005 | #define DMA_DCR_SMOD_MASK (0xF000U) |
mbed_official | 121:7f86b4238bec | 1006 | #define DMA_DCR_SMOD_SHIFT (12U) |
mbed_official | 121:7f86b4238bec | 1007 | #define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_SMOD_SHIFT)) & DMA_DCR_SMOD_MASK) |
mbed_official | 121:7f86b4238bec | 1008 | #define DMA_DCR_START_MASK (0x10000U) |
mbed_official | 121:7f86b4238bec | 1009 | #define DMA_DCR_START_SHIFT (16U) |
mbed_official | 121:7f86b4238bec | 1010 | #define DMA_DCR_START(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_START_SHIFT)) & DMA_DCR_START_MASK) |
mbed_official | 121:7f86b4238bec | 1011 | #define DMA_DCR_DSIZE_MASK (0x60000U) |
mbed_official | 121:7f86b4238bec | 1012 | #define DMA_DCR_DSIZE_SHIFT (17U) |
mbed_official | 121:7f86b4238bec | 1013 | #define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_DSIZE_SHIFT)) & DMA_DCR_DSIZE_MASK) |
mbed_official | 121:7f86b4238bec | 1014 | #define DMA_DCR_DINC_MASK (0x80000U) |
mbed_official | 121:7f86b4238bec | 1015 | #define DMA_DCR_DINC_SHIFT (19U) |
mbed_official | 121:7f86b4238bec | 1016 | #define DMA_DCR_DINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_DINC_SHIFT)) & DMA_DCR_DINC_MASK) |
mbed_official | 121:7f86b4238bec | 1017 | #define DMA_DCR_SSIZE_MASK (0x300000U) |
mbed_official | 121:7f86b4238bec | 1018 | #define DMA_DCR_SSIZE_SHIFT (20U) |
mbed_official | 121:7f86b4238bec | 1019 | #define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_SSIZE_SHIFT)) & DMA_DCR_SSIZE_MASK) |
mbed_official | 121:7f86b4238bec | 1020 | #define DMA_DCR_SINC_MASK (0x400000U) |
mbed_official | 121:7f86b4238bec | 1021 | #define DMA_DCR_SINC_SHIFT (22U) |
mbed_official | 121:7f86b4238bec | 1022 | #define DMA_DCR_SINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_SINC_SHIFT)) & DMA_DCR_SINC_MASK) |
mbed_official | 121:7f86b4238bec | 1023 | #define DMA_DCR_EADREQ_MASK (0x800000U) |
mbed_official | 121:7f86b4238bec | 1024 | #define DMA_DCR_EADREQ_SHIFT (23U) |
mbed_official | 121:7f86b4238bec | 1025 | #define DMA_DCR_EADREQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_EADREQ_SHIFT)) & DMA_DCR_EADREQ_MASK) |
mbed_official | 121:7f86b4238bec | 1026 | #define DMA_DCR_AA_MASK (0x10000000U) |
mbed_official | 121:7f86b4238bec | 1027 | #define DMA_DCR_AA_SHIFT (28U) |
mbed_official | 121:7f86b4238bec | 1028 | #define DMA_DCR_AA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_AA_SHIFT)) & DMA_DCR_AA_MASK) |
mbed_official | 121:7f86b4238bec | 1029 | #define DMA_DCR_CS_MASK (0x20000000U) |
mbed_official | 121:7f86b4238bec | 1030 | #define DMA_DCR_CS_SHIFT (29U) |
mbed_official | 121:7f86b4238bec | 1031 | #define DMA_DCR_CS(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_CS_SHIFT)) & DMA_DCR_CS_MASK) |
mbed_official | 121:7f86b4238bec | 1032 | #define DMA_DCR_ERQ_MASK (0x40000000U) |
mbed_official | 121:7f86b4238bec | 1033 | #define DMA_DCR_ERQ_SHIFT (30U) |
mbed_official | 121:7f86b4238bec | 1034 | #define DMA_DCR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_ERQ_SHIFT)) & DMA_DCR_ERQ_MASK) |
mbed_official | 121:7f86b4238bec | 1035 | #define DMA_DCR_EINT_MASK (0x80000000U) |
mbed_official | 121:7f86b4238bec | 1036 | #define DMA_DCR_EINT_SHIFT (31U) |
mbed_official | 121:7f86b4238bec | 1037 | #define DMA_DCR_EINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_EINT_SHIFT)) & DMA_DCR_EINT_MASK) |
mbed_official | 121:7f86b4238bec | 1038 | |
mbed_official | 121:7f86b4238bec | 1039 | /* The count of DMA_DCR */ |
mbed_official | 121:7f86b4238bec | 1040 | #define DMA_DCR_COUNT (4U) |
mbed_official | 121:7f86b4238bec | 1041 | |
mbed_official | 121:7f86b4238bec | 1042 | |
mbed_official | 121:7f86b4238bec | 1043 | /*! |
mbed_official | 121:7f86b4238bec | 1044 | * @} |
mbed_official | 121:7f86b4238bec | 1045 | */ /* end of group DMA_Register_Masks */ |
mbed_official | 121:7f86b4238bec | 1046 | |
mbed_official | 121:7f86b4238bec | 1047 | |
mbed_official | 121:7f86b4238bec | 1048 | /* DMA - Peripheral instance base addresses */ |
mbed_official | 121:7f86b4238bec | 1049 | /** Peripheral DMA base address */ |
mbed_official | 121:7f86b4238bec | 1050 | #define DMA_BASE (0x40008000u) |
mbed_official | 121:7f86b4238bec | 1051 | /** Peripheral DMA base pointer */ |
mbed_official | 121:7f86b4238bec | 1052 | #define DMA0 ((DMA_Type *)DMA_BASE) |
mbed_official | 121:7f86b4238bec | 1053 | /** Array initializer of DMA peripheral base addresses */ |
mbed_official | 121:7f86b4238bec | 1054 | #define DMA_BASE_ADDRS { DMA_BASE } |
mbed_official | 121:7f86b4238bec | 1055 | /** Array initializer of DMA peripheral base pointers */ |
mbed_official | 121:7f86b4238bec | 1056 | #define DMA_BASE_PTRS { DMA0 } |
mbed_official | 121:7f86b4238bec | 1057 | /** Interrupt vectors for the DMA peripheral type */ |
mbed_official | 121:7f86b4238bec | 1058 | #define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn } |
mbed_official | 121:7f86b4238bec | 1059 | |
mbed_official | 121:7f86b4238bec | 1060 | /*! |
mbed_official | 121:7f86b4238bec | 1061 | * @} |
mbed_official | 121:7f86b4238bec | 1062 | */ /* end of group DMA_Peripheral_Access_Layer */ |
mbed_official | 121:7f86b4238bec | 1063 | |
mbed_official | 121:7f86b4238bec | 1064 | |
mbed_official | 121:7f86b4238bec | 1065 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 1066 | -- DMAMUX Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 1067 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 1068 | |
mbed_official | 121:7f86b4238bec | 1069 | /*! |
mbed_official | 121:7f86b4238bec | 1070 | * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 1071 | * @{ |
mbed_official | 121:7f86b4238bec | 1072 | */ |
mbed_official | 121:7f86b4238bec | 1073 | |
mbed_official | 121:7f86b4238bec | 1074 | /** DMAMUX - Register Layout Typedef */ |
mbed_official | 121:7f86b4238bec | 1075 | typedef struct { |
mbed_official | 121:7f86b4238bec | 1076 | __IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */ |
mbed_official | 121:7f86b4238bec | 1077 | } DMAMUX_Type; |
mbed_official | 121:7f86b4238bec | 1078 | |
mbed_official | 121:7f86b4238bec | 1079 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 1080 | -- DMAMUX Register Masks |
mbed_official | 121:7f86b4238bec | 1081 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 1082 | |
mbed_official | 121:7f86b4238bec | 1083 | /*! |
mbed_official | 121:7f86b4238bec | 1084 | * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks |
mbed_official | 121:7f86b4238bec | 1085 | * @{ |
mbed_official | 121:7f86b4238bec | 1086 | */ |
mbed_official | 121:7f86b4238bec | 1087 | |
mbed_official | 121:7f86b4238bec | 1088 | /*! @name CHCFG - Channel Configuration register */ |
mbed_official | 121:7f86b4238bec | 1089 | #define DMAMUX_CHCFG_SOURCE_MASK (0x3FU) |
mbed_official | 121:7f86b4238bec | 1090 | #define DMAMUX_CHCFG_SOURCE_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1091 | #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) |
mbed_official | 121:7f86b4238bec | 1092 | #define DMAMUX_CHCFG_TRIG_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 1093 | #define DMAMUX_CHCFG_TRIG_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 1094 | #define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK) |
mbed_official | 121:7f86b4238bec | 1095 | #define DMAMUX_CHCFG_ENBL_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 1096 | #define DMAMUX_CHCFG_ENBL_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 1097 | #define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK) |
mbed_official | 121:7f86b4238bec | 1098 | |
mbed_official | 121:7f86b4238bec | 1099 | /* The count of DMAMUX_CHCFG */ |
mbed_official | 121:7f86b4238bec | 1100 | #define DMAMUX_CHCFG_COUNT (4U) |
mbed_official | 121:7f86b4238bec | 1101 | |
mbed_official | 121:7f86b4238bec | 1102 | |
mbed_official | 121:7f86b4238bec | 1103 | /*! |
mbed_official | 121:7f86b4238bec | 1104 | * @} |
mbed_official | 121:7f86b4238bec | 1105 | */ /* end of group DMAMUX_Register_Masks */ |
mbed_official | 121:7f86b4238bec | 1106 | |
mbed_official | 121:7f86b4238bec | 1107 | |
mbed_official | 121:7f86b4238bec | 1108 | /* DMAMUX - Peripheral instance base addresses */ |
mbed_official | 121:7f86b4238bec | 1109 | /** Peripheral DMAMUX0 base address */ |
mbed_official | 121:7f86b4238bec | 1110 | #define DMAMUX0_BASE (0x40021000u) |
mbed_official | 121:7f86b4238bec | 1111 | /** Peripheral DMAMUX0 base pointer */ |
mbed_official | 121:7f86b4238bec | 1112 | #define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE) |
mbed_official | 121:7f86b4238bec | 1113 | /** Array initializer of DMAMUX peripheral base addresses */ |
mbed_official | 121:7f86b4238bec | 1114 | #define DMAMUX_BASE_ADDRS { DMAMUX0_BASE } |
mbed_official | 121:7f86b4238bec | 1115 | /** Array initializer of DMAMUX peripheral base pointers */ |
mbed_official | 121:7f86b4238bec | 1116 | #define DMAMUX_BASE_PTRS { DMAMUX0 } |
mbed_official | 121:7f86b4238bec | 1117 | |
mbed_official | 121:7f86b4238bec | 1118 | /*! |
mbed_official | 121:7f86b4238bec | 1119 | * @} |
mbed_official | 121:7f86b4238bec | 1120 | */ /* end of group DMAMUX_Peripheral_Access_Layer */ |
mbed_official | 121:7f86b4238bec | 1121 | |
mbed_official | 121:7f86b4238bec | 1122 | |
mbed_official | 121:7f86b4238bec | 1123 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 1124 | -- FLEXIO Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 1125 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 1126 | |
mbed_official | 121:7f86b4238bec | 1127 | /*! |
mbed_official | 121:7f86b4238bec | 1128 | * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 1129 | * @{ |
mbed_official | 121:7f86b4238bec | 1130 | */ |
mbed_official | 121:7f86b4238bec | 1131 | |
mbed_official | 121:7f86b4238bec | 1132 | /** FLEXIO - Register Layout Typedef */ |
mbed_official | 121:7f86b4238bec | 1133 | typedef struct { |
mbed_official | 121:7f86b4238bec | 1134 | __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ |
mbed_official | 121:7f86b4238bec | 1135 | __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ |
mbed_official | 121:7f86b4238bec | 1136 | __IO uint32_t CTRL; /**< FlexIO Control Register, offset: 0x8 */ |
mbed_official | 121:7f86b4238bec | 1137 | uint8_t RESERVED_0[4]; |
mbed_official | 121:7f86b4238bec | 1138 | __IO uint32_t SHIFTSTAT; /**< Shifter Status Register, offset: 0x10 */ |
mbed_official | 121:7f86b4238bec | 1139 | __IO uint32_t SHIFTERR; /**< Shifter Error Register, offset: 0x14 */ |
mbed_official | 121:7f86b4238bec | 1140 | __IO uint32_t TIMSTAT; /**< Timer Status Register, offset: 0x18 */ |
mbed_official | 121:7f86b4238bec | 1141 | uint8_t RESERVED_1[4]; |
mbed_official | 121:7f86b4238bec | 1142 | __IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */ |
mbed_official | 121:7f86b4238bec | 1143 | __IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */ |
mbed_official | 121:7f86b4238bec | 1144 | __IO uint32_t TIMIEN; /**< Timer Interrupt Enable Register, offset: 0x28 */ |
mbed_official | 121:7f86b4238bec | 1145 | uint8_t RESERVED_2[4]; |
mbed_official | 121:7f86b4238bec | 1146 | __IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */ |
mbed_official | 121:7f86b4238bec | 1147 | uint8_t RESERVED_3[76]; |
mbed_official | 121:7f86b4238bec | 1148 | __IO uint32_t SHIFTCTL[4]; /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */ |
mbed_official | 121:7f86b4238bec | 1149 | uint8_t RESERVED_4[112]; |
mbed_official | 121:7f86b4238bec | 1150 | __IO uint32_t SHIFTCFG[4]; /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */ |
mbed_official | 121:7f86b4238bec | 1151 | uint8_t RESERVED_5[240]; |
mbed_official | 121:7f86b4238bec | 1152 | __IO uint32_t SHIFTBUF[4]; /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */ |
mbed_official | 121:7f86b4238bec | 1153 | uint8_t RESERVED_6[112]; |
mbed_official | 121:7f86b4238bec | 1154 | __IO uint32_t SHIFTBUFBIS[4]; /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */ |
mbed_official | 121:7f86b4238bec | 1155 | uint8_t RESERVED_7[112]; |
mbed_official | 121:7f86b4238bec | 1156 | __IO uint32_t SHIFTBUFBYS[4]; /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */ |
mbed_official | 121:7f86b4238bec | 1157 | uint8_t RESERVED_8[112]; |
mbed_official | 121:7f86b4238bec | 1158 | __IO uint32_t SHIFTBUFBBS[4]; /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */ |
mbed_official | 121:7f86b4238bec | 1159 | uint8_t RESERVED_9[112]; |
mbed_official | 121:7f86b4238bec | 1160 | __IO uint32_t TIMCTL[4]; /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */ |
mbed_official | 121:7f86b4238bec | 1161 | uint8_t RESERVED_10[112]; |
mbed_official | 121:7f86b4238bec | 1162 | __IO uint32_t TIMCFG[4]; /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */ |
mbed_official | 121:7f86b4238bec | 1163 | uint8_t RESERVED_11[112]; |
mbed_official | 121:7f86b4238bec | 1164 | __IO uint32_t TIMCMP[4]; /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */ |
mbed_official | 121:7f86b4238bec | 1165 | } FLEXIO_Type; |
mbed_official | 121:7f86b4238bec | 1166 | |
mbed_official | 121:7f86b4238bec | 1167 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 1168 | -- FLEXIO Register Masks |
mbed_official | 121:7f86b4238bec | 1169 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 1170 | |
mbed_official | 121:7f86b4238bec | 1171 | /*! |
mbed_official | 121:7f86b4238bec | 1172 | * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks |
mbed_official | 121:7f86b4238bec | 1173 | * @{ |
mbed_official | 121:7f86b4238bec | 1174 | */ |
mbed_official | 121:7f86b4238bec | 1175 | |
mbed_official | 121:7f86b4238bec | 1176 | /*! @name VERID - Version ID Register */ |
mbed_official | 121:7f86b4238bec | 1177 | #define FLEXIO_VERID_FEATURE_MASK (0xFFFFU) |
mbed_official | 121:7f86b4238bec | 1178 | #define FLEXIO_VERID_FEATURE_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1179 | #define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK) |
mbed_official | 121:7f86b4238bec | 1180 | #define FLEXIO_VERID_MINOR_MASK (0xFF0000U) |
mbed_official | 121:7f86b4238bec | 1181 | #define FLEXIO_VERID_MINOR_SHIFT (16U) |
mbed_official | 121:7f86b4238bec | 1182 | #define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK) |
mbed_official | 121:7f86b4238bec | 1183 | #define FLEXIO_VERID_MAJOR_MASK (0xFF000000U) |
mbed_official | 121:7f86b4238bec | 1184 | #define FLEXIO_VERID_MAJOR_SHIFT (24U) |
mbed_official | 121:7f86b4238bec | 1185 | #define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK) |
mbed_official | 121:7f86b4238bec | 1186 | |
mbed_official | 121:7f86b4238bec | 1187 | /*! @name PARAM - Parameter Register */ |
mbed_official | 121:7f86b4238bec | 1188 | #define FLEXIO_PARAM_SHIFTER_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 1189 | #define FLEXIO_PARAM_SHIFTER_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1190 | #define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK) |
mbed_official | 121:7f86b4238bec | 1191 | #define FLEXIO_PARAM_TIMER_MASK (0xFF00U) |
mbed_official | 121:7f86b4238bec | 1192 | #define FLEXIO_PARAM_TIMER_SHIFT (8U) |
mbed_official | 121:7f86b4238bec | 1193 | #define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK) |
mbed_official | 121:7f86b4238bec | 1194 | #define FLEXIO_PARAM_PIN_MASK (0xFF0000U) |
mbed_official | 121:7f86b4238bec | 1195 | #define FLEXIO_PARAM_PIN_SHIFT (16U) |
mbed_official | 121:7f86b4238bec | 1196 | #define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK) |
mbed_official | 121:7f86b4238bec | 1197 | #define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U) |
mbed_official | 121:7f86b4238bec | 1198 | #define FLEXIO_PARAM_TRIGGER_SHIFT (24U) |
mbed_official | 121:7f86b4238bec | 1199 | #define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK) |
mbed_official | 121:7f86b4238bec | 1200 | |
mbed_official | 121:7f86b4238bec | 1201 | /*! @name CTRL - FlexIO Control Register */ |
mbed_official | 121:7f86b4238bec | 1202 | #define FLEXIO_CTRL_FLEXEN_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 1203 | #define FLEXIO_CTRL_FLEXEN_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1204 | #define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK) |
mbed_official | 121:7f86b4238bec | 1205 | #define FLEXIO_CTRL_SWRST_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 1206 | #define FLEXIO_CTRL_SWRST_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 1207 | #define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK) |
mbed_official | 121:7f86b4238bec | 1208 | #define FLEXIO_CTRL_FASTACC_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 1209 | #define FLEXIO_CTRL_FASTACC_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 1210 | #define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK) |
mbed_official | 121:7f86b4238bec | 1211 | #define FLEXIO_CTRL_DBGE_MASK (0x40000000U) |
mbed_official | 121:7f86b4238bec | 1212 | #define FLEXIO_CTRL_DBGE_SHIFT (30U) |
mbed_official | 121:7f86b4238bec | 1213 | #define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK) |
mbed_official | 121:7f86b4238bec | 1214 | #define FLEXIO_CTRL_DOZEN_MASK (0x80000000U) |
mbed_official | 121:7f86b4238bec | 1215 | #define FLEXIO_CTRL_DOZEN_SHIFT (31U) |
mbed_official | 121:7f86b4238bec | 1216 | #define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK) |
mbed_official | 121:7f86b4238bec | 1217 | |
mbed_official | 121:7f86b4238bec | 1218 | /*! @name SHIFTSTAT - Shifter Status Register */ |
mbed_official | 121:7f86b4238bec | 1219 | #define FLEXIO_SHIFTSTAT_SSF_MASK (0xFU) |
mbed_official | 121:7f86b4238bec | 1220 | #define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1221 | #define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK) |
mbed_official | 121:7f86b4238bec | 1222 | |
mbed_official | 121:7f86b4238bec | 1223 | /*! @name SHIFTERR - Shifter Error Register */ |
mbed_official | 121:7f86b4238bec | 1224 | #define FLEXIO_SHIFTERR_SEF_MASK (0xFU) |
mbed_official | 121:7f86b4238bec | 1225 | #define FLEXIO_SHIFTERR_SEF_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1226 | #define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK) |
mbed_official | 121:7f86b4238bec | 1227 | |
mbed_official | 121:7f86b4238bec | 1228 | /*! @name TIMSTAT - Timer Status Register */ |
mbed_official | 121:7f86b4238bec | 1229 | #define FLEXIO_TIMSTAT_TSF_MASK (0xFU) |
mbed_official | 121:7f86b4238bec | 1230 | #define FLEXIO_TIMSTAT_TSF_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1231 | #define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK) |
mbed_official | 121:7f86b4238bec | 1232 | |
mbed_official | 121:7f86b4238bec | 1233 | /*! @name SHIFTSIEN - Shifter Status Interrupt Enable */ |
mbed_official | 121:7f86b4238bec | 1234 | #define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFU) |
mbed_official | 121:7f86b4238bec | 1235 | #define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1236 | #define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK) |
mbed_official | 121:7f86b4238bec | 1237 | |
mbed_official | 121:7f86b4238bec | 1238 | /*! @name SHIFTEIEN - Shifter Error Interrupt Enable */ |
mbed_official | 121:7f86b4238bec | 1239 | #define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFU) |
mbed_official | 121:7f86b4238bec | 1240 | #define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1241 | #define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK) |
mbed_official | 121:7f86b4238bec | 1242 | |
mbed_official | 121:7f86b4238bec | 1243 | /*! @name TIMIEN - Timer Interrupt Enable Register */ |
mbed_official | 121:7f86b4238bec | 1244 | #define FLEXIO_TIMIEN_TEIE_MASK (0xFU) |
mbed_official | 121:7f86b4238bec | 1245 | #define FLEXIO_TIMIEN_TEIE_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1246 | #define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK) |
mbed_official | 121:7f86b4238bec | 1247 | |
mbed_official | 121:7f86b4238bec | 1248 | /*! @name SHIFTSDEN - Shifter Status DMA Enable */ |
mbed_official | 121:7f86b4238bec | 1249 | #define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFU) |
mbed_official | 121:7f86b4238bec | 1250 | #define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1251 | #define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK) |
mbed_official | 121:7f86b4238bec | 1252 | |
mbed_official | 121:7f86b4238bec | 1253 | /*! @name SHIFTCTL - Shifter Control N Register */ |
mbed_official | 121:7f86b4238bec | 1254 | #define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U) |
mbed_official | 121:7f86b4238bec | 1255 | #define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1256 | #define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK) |
mbed_official | 121:7f86b4238bec | 1257 | #define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 1258 | #define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 1259 | #define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK) |
mbed_official | 121:7f86b4238bec | 1260 | #define FLEXIO_SHIFTCTL_PINSEL_MASK (0x700U) |
mbed_official | 121:7f86b4238bec | 1261 | #define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U) |
mbed_official | 121:7f86b4238bec | 1262 | #define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK) |
mbed_official | 121:7f86b4238bec | 1263 | #define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U) |
mbed_official | 121:7f86b4238bec | 1264 | #define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U) |
mbed_official | 121:7f86b4238bec | 1265 | #define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK) |
mbed_official | 121:7f86b4238bec | 1266 | #define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U) |
mbed_official | 121:7f86b4238bec | 1267 | #define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U) |
mbed_official | 121:7f86b4238bec | 1268 | #define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK) |
mbed_official | 121:7f86b4238bec | 1269 | #define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x3000000U) |
mbed_official | 121:7f86b4238bec | 1270 | #define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U) |
mbed_official | 121:7f86b4238bec | 1271 | #define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK) |
mbed_official | 121:7f86b4238bec | 1272 | |
mbed_official | 121:7f86b4238bec | 1273 | /* The count of FLEXIO_SHIFTCTL */ |
mbed_official | 121:7f86b4238bec | 1274 | #define FLEXIO_SHIFTCTL_COUNT (4U) |
mbed_official | 121:7f86b4238bec | 1275 | |
mbed_official | 121:7f86b4238bec | 1276 | /*! @name SHIFTCFG - Shifter Configuration N Register */ |
mbed_official | 121:7f86b4238bec | 1277 | #define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U) |
mbed_official | 121:7f86b4238bec | 1278 | #define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1279 | #define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK) |
mbed_official | 121:7f86b4238bec | 1280 | #define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U) |
mbed_official | 121:7f86b4238bec | 1281 | #define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 1282 | #define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK) |
mbed_official | 121:7f86b4238bec | 1283 | #define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U) |
mbed_official | 121:7f86b4238bec | 1284 | #define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U) |
mbed_official | 121:7f86b4238bec | 1285 | #define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK) |
mbed_official | 121:7f86b4238bec | 1286 | |
mbed_official | 121:7f86b4238bec | 1287 | /* The count of FLEXIO_SHIFTCFG */ |
mbed_official | 121:7f86b4238bec | 1288 | #define FLEXIO_SHIFTCFG_COUNT (4U) |
mbed_official | 121:7f86b4238bec | 1289 | |
mbed_official | 121:7f86b4238bec | 1290 | /*! @name SHIFTBUF - Shifter Buffer N Register */ |
mbed_official | 121:7f86b4238bec | 1291 | #define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 1292 | #define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1293 | #define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK) |
mbed_official | 121:7f86b4238bec | 1294 | |
mbed_official | 121:7f86b4238bec | 1295 | /* The count of FLEXIO_SHIFTBUF */ |
mbed_official | 121:7f86b4238bec | 1296 | #define FLEXIO_SHIFTBUF_COUNT (4U) |
mbed_official | 121:7f86b4238bec | 1297 | |
mbed_official | 121:7f86b4238bec | 1298 | /*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */ |
mbed_official | 121:7f86b4238bec | 1299 | #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 1300 | #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1301 | #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK) |
mbed_official | 121:7f86b4238bec | 1302 | |
mbed_official | 121:7f86b4238bec | 1303 | /* The count of FLEXIO_SHIFTBUFBIS */ |
mbed_official | 121:7f86b4238bec | 1304 | #define FLEXIO_SHIFTBUFBIS_COUNT (4U) |
mbed_official | 121:7f86b4238bec | 1305 | |
mbed_official | 121:7f86b4238bec | 1306 | /*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */ |
mbed_official | 121:7f86b4238bec | 1307 | #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 1308 | #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1309 | #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK) |
mbed_official | 121:7f86b4238bec | 1310 | |
mbed_official | 121:7f86b4238bec | 1311 | /* The count of FLEXIO_SHIFTBUFBYS */ |
mbed_official | 121:7f86b4238bec | 1312 | #define FLEXIO_SHIFTBUFBYS_COUNT (4U) |
mbed_official | 121:7f86b4238bec | 1313 | |
mbed_official | 121:7f86b4238bec | 1314 | /*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */ |
mbed_official | 121:7f86b4238bec | 1315 | #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 1316 | #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1317 | #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK) |
mbed_official | 121:7f86b4238bec | 1318 | |
mbed_official | 121:7f86b4238bec | 1319 | /* The count of FLEXIO_SHIFTBUFBBS */ |
mbed_official | 121:7f86b4238bec | 1320 | #define FLEXIO_SHIFTBUFBBS_COUNT (4U) |
mbed_official | 121:7f86b4238bec | 1321 | |
mbed_official | 121:7f86b4238bec | 1322 | /*! @name TIMCTL - Timer Control N Register */ |
mbed_official | 121:7f86b4238bec | 1323 | #define FLEXIO_TIMCTL_TIMOD_MASK (0x3U) |
mbed_official | 121:7f86b4238bec | 1324 | #define FLEXIO_TIMCTL_TIMOD_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1325 | #define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK) |
mbed_official | 121:7f86b4238bec | 1326 | #define FLEXIO_TIMCTL_PINPOL_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 1327 | #define FLEXIO_TIMCTL_PINPOL_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 1328 | #define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK) |
mbed_official | 121:7f86b4238bec | 1329 | #define FLEXIO_TIMCTL_PINSEL_MASK (0x700U) |
mbed_official | 121:7f86b4238bec | 1330 | #define FLEXIO_TIMCTL_PINSEL_SHIFT (8U) |
mbed_official | 121:7f86b4238bec | 1331 | #define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK) |
mbed_official | 121:7f86b4238bec | 1332 | #define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U) |
mbed_official | 121:7f86b4238bec | 1333 | #define FLEXIO_TIMCTL_PINCFG_SHIFT (16U) |
mbed_official | 121:7f86b4238bec | 1334 | #define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK) |
mbed_official | 121:7f86b4238bec | 1335 | #define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U) |
mbed_official | 121:7f86b4238bec | 1336 | #define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U) |
mbed_official | 121:7f86b4238bec | 1337 | #define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK) |
mbed_official | 121:7f86b4238bec | 1338 | #define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U) |
mbed_official | 121:7f86b4238bec | 1339 | #define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U) |
mbed_official | 121:7f86b4238bec | 1340 | #define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK) |
mbed_official | 121:7f86b4238bec | 1341 | #define FLEXIO_TIMCTL_TRGSEL_MASK (0xF000000U) |
mbed_official | 121:7f86b4238bec | 1342 | #define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U) |
mbed_official | 121:7f86b4238bec | 1343 | #define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK) |
mbed_official | 121:7f86b4238bec | 1344 | |
mbed_official | 121:7f86b4238bec | 1345 | /* The count of FLEXIO_TIMCTL */ |
mbed_official | 121:7f86b4238bec | 1346 | #define FLEXIO_TIMCTL_COUNT (4U) |
mbed_official | 121:7f86b4238bec | 1347 | |
mbed_official | 121:7f86b4238bec | 1348 | /*! @name TIMCFG - Timer Configuration N Register */ |
mbed_official | 121:7f86b4238bec | 1349 | #define FLEXIO_TIMCFG_TSTART_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 1350 | #define FLEXIO_TIMCFG_TSTART_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 1351 | #define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK) |
mbed_official | 121:7f86b4238bec | 1352 | #define FLEXIO_TIMCFG_TSTOP_MASK (0x30U) |
mbed_official | 121:7f86b4238bec | 1353 | #define FLEXIO_TIMCFG_TSTOP_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 1354 | #define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK) |
mbed_official | 121:7f86b4238bec | 1355 | #define FLEXIO_TIMCFG_TIMENA_MASK (0x700U) |
mbed_official | 121:7f86b4238bec | 1356 | #define FLEXIO_TIMCFG_TIMENA_SHIFT (8U) |
mbed_official | 121:7f86b4238bec | 1357 | #define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK) |
mbed_official | 121:7f86b4238bec | 1358 | #define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U) |
mbed_official | 121:7f86b4238bec | 1359 | #define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U) |
mbed_official | 121:7f86b4238bec | 1360 | #define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK) |
mbed_official | 121:7f86b4238bec | 1361 | #define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U) |
mbed_official | 121:7f86b4238bec | 1362 | #define FLEXIO_TIMCFG_TIMRST_SHIFT (16U) |
mbed_official | 121:7f86b4238bec | 1363 | #define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK) |
mbed_official | 121:7f86b4238bec | 1364 | #define FLEXIO_TIMCFG_TIMDEC_MASK (0x300000U) |
mbed_official | 121:7f86b4238bec | 1365 | #define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U) |
mbed_official | 121:7f86b4238bec | 1366 | #define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK) |
mbed_official | 121:7f86b4238bec | 1367 | #define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U) |
mbed_official | 121:7f86b4238bec | 1368 | #define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U) |
mbed_official | 121:7f86b4238bec | 1369 | #define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK) |
mbed_official | 121:7f86b4238bec | 1370 | |
mbed_official | 121:7f86b4238bec | 1371 | /* The count of FLEXIO_TIMCFG */ |
mbed_official | 121:7f86b4238bec | 1372 | #define FLEXIO_TIMCFG_COUNT (4U) |
mbed_official | 121:7f86b4238bec | 1373 | |
mbed_official | 121:7f86b4238bec | 1374 | /*! @name TIMCMP - Timer Compare N Register */ |
mbed_official | 121:7f86b4238bec | 1375 | #define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU) |
mbed_official | 121:7f86b4238bec | 1376 | #define FLEXIO_TIMCMP_CMP_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1377 | #define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK) |
mbed_official | 121:7f86b4238bec | 1378 | |
mbed_official | 121:7f86b4238bec | 1379 | /* The count of FLEXIO_TIMCMP */ |
mbed_official | 121:7f86b4238bec | 1380 | #define FLEXIO_TIMCMP_COUNT (4U) |
mbed_official | 121:7f86b4238bec | 1381 | |
mbed_official | 121:7f86b4238bec | 1382 | |
mbed_official | 121:7f86b4238bec | 1383 | /*! |
mbed_official | 121:7f86b4238bec | 1384 | * @} |
mbed_official | 121:7f86b4238bec | 1385 | */ /* end of group FLEXIO_Register_Masks */ |
mbed_official | 121:7f86b4238bec | 1386 | |
mbed_official | 121:7f86b4238bec | 1387 | |
mbed_official | 121:7f86b4238bec | 1388 | /* FLEXIO - Peripheral instance base addresses */ |
mbed_official | 121:7f86b4238bec | 1389 | /** Peripheral FLEXIO base address */ |
mbed_official | 121:7f86b4238bec | 1390 | #define FLEXIO_BASE (0x4005F000u) |
mbed_official | 121:7f86b4238bec | 1391 | /** Peripheral FLEXIO base pointer */ |
mbed_official | 121:7f86b4238bec | 1392 | #define FLEXIO ((FLEXIO_Type *)FLEXIO_BASE) |
mbed_official | 121:7f86b4238bec | 1393 | /** Array initializer of FLEXIO peripheral base addresses */ |
mbed_official | 121:7f86b4238bec | 1394 | #define FLEXIO_BASE_ADDRS { FLEXIO_BASE } |
mbed_official | 121:7f86b4238bec | 1395 | /** Array initializer of FLEXIO peripheral base pointers */ |
mbed_official | 121:7f86b4238bec | 1396 | #define FLEXIO_BASE_PTRS { FLEXIO } |
mbed_official | 121:7f86b4238bec | 1397 | /** Interrupt vectors for the FLEXIO peripheral type */ |
mbed_official | 121:7f86b4238bec | 1398 | #define FLEXIO_IRQS { UART2_FLEXIO_IRQn } |
mbed_official | 121:7f86b4238bec | 1399 | |
mbed_official | 121:7f86b4238bec | 1400 | /*! |
mbed_official | 121:7f86b4238bec | 1401 | * @} |
mbed_official | 121:7f86b4238bec | 1402 | */ /* end of group FLEXIO_Peripheral_Access_Layer */ |
mbed_official | 121:7f86b4238bec | 1403 | |
mbed_official | 121:7f86b4238bec | 1404 | |
mbed_official | 121:7f86b4238bec | 1405 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 1406 | -- FTFA Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 1407 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 1408 | |
mbed_official | 121:7f86b4238bec | 1409 | /*! |
mbed_official | 121:7f86b4238bec | 1410 | * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 1411 | * @{ |
mbed_official | 121:7f86b4238bec | 1412 | */ |
mbed_official | 121:7f86b4238bec | 1413 | |
mbed_official | 121:7f86b4238bec | 1414 | /** FTFA - Register Layout Typedef */ |
mbed_official | 121:7f86b4238bec | 1415 | typedef struct { |
mbed_official | 121:7f86b4238bec | 1416 | __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */ |
mbed_official | 121:7f86b4238bec | 1417 | __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */ |
mbed_official | 121:7f86b4238bec | 1418 | __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */ |
mbed_official | 121:7f86b4238bec | 1419 | __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */ |
mbed_official | 121:7f86b4238bec | 1420 | __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */ |
mbed_official | 121:7f86b4238bec | 1421 | __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */ |
mbed_official | 121:7f86b4238bec | 1422 | __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */ |
mbed_official | 121:7f86b4238bec | 1423 | __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */ |
mbed_official | 121:7f86b4238bec | 1424 | __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */ |
mbed_official | 121:7f86b4238bec | 1425 | __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */ |
mbed_official | 121:7f86b4238bec | 1426 | __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */ |
mbed_official | 121:7f86b4238bec | 1427 | __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */ |
mbed_official | 121:7f86b4238bec | 1428 | __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */ |
mbed_official | 121:7f86b4238bec | 1429 | __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */ |
mbed_official | 121:7f86b4238bec | 1430 | __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */ |
mbed_official | 121:7f86b4238bec | 1431 | __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */ |
mbed_official | 121:7f86b4238bec | 1432 | __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */ |
mbed_official | 121:7f86b4238bec | 1433 | __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */ |
mbed_official | 121:7f86b4238bec | 1434 | __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */ |
mbed_official | 121:7f86b4238bec | 1435 | __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */ |
mbed_official | 121:7f86b4238bec | 1436 | } FTFA_Type; |
mbed_official | 121:7f86b4238bec | 1437 | |
mbed_official | 121:7f86b4238bec | 1438 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 1439 | -- FTFA Register Masks |
mbed_official | 121:7f86b4238bec | 1440 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 1441 | |
mbed_official | 121:7f86b4238bec | 1442 | /*! |
mbed_official | 121:7f86b4238bec | 1443 | * @addtogroup FTFA_Register_Masks FTFA Register Masks |
mbed_official | 121:7f86b4238bec | 1444 | * @{ |
mbed_official | 121:7f86b4238bec | 1445 | */ |
mbed_official | 121:7f86b4238bec | 1446 | |
mbed_official | 121:7f86b4238bec | 1447 | /*! @name FSTAT - Flash Status Register */ |
mbed_official | 121:7f86b4238bec | 1448 | #define FTFA_FSTAT_MGSTAT0_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 1449 | #define FTFA_FSTAT_MGSTAT0_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1450 | #define FTFA_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_MGSTAT0_SHIFT)) & FTFA_FSTAT_MGSTAT0_MASK) |
mbed_official | 121:7f86b4238bec | 1451 | #define FTFA_FSTAT_FPVIOL_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 1452 | #define FTFA_FSTAT_FPVIOL_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 1453 | #define FTFA_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_FPVIOL_SHIFT)) & FTFA_FSTAT_FPVIOL_MASK) |
mbed_official | 121:7f86b4238bec | 1454 | #define FTFA_FSTAT_ACCERR_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 1455 | #define FTFA_FSTAT_ACCERR_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 1456 | #define FTFA_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_ACCERR_SHIFT)) & FTFA_FSTAT_ACCERR_MASK) |
mbed_official | 121:7f86b4238bec | 1457 | #define FTFA_FSTAT_RDCOLERR_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 1458 | #define FTFA_FSTAT_RDCOLERR_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 1459 | #define FTFA_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_RDCOLERR_SHIFT)) & FTFA_FSTAT_RDCOLERR_MASK) |
mbed_official | 121:7f86b4238bec | 1460 | #define FTFA_FSTAT_CCIF_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 1461 | #define FTFA_FSTAT_CCIF_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 1462 | #define FTFA_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_CCIF_SHIFT)) & FTFA_FSTAT_CCIF_MASK) |
mbed_official | 121:7f86b4238bec | 1463 | |
mbed_official | 121:7f86b4238bec | 1464 | /*! @name FCNFG - Flash Configuration Register */ |
mbed_official | 121:7f86b4238bec | 1465 | #define FTFA_FCNFG_ERSSUSP_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 1466 | #define FTFA_FCNFG_ERSSUSP_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 1467 | #define FTFA_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSSUSP_SHIFT)) & FTFA_FCNFG_ERSSUSP_MASK) |
mbed_official | 121:7f86b4238bec | 1468 | #define FTFA_FCNFG_ERSAREQ_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 1469 | #define FTFA_FCNFG_ERSAREQ_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 1470 | #define FTFA_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSAREQ_SHIFT)) & FTFA_FCNFG_ERSAREQ_MASK) |
mbed_official | 121:7f86b4238bec | 1471 | #define FTFA_FCNFG_RDCOLLIE_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 1472 | #define FTFA_FCNFG_RDCOLLIE_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 1473 | #define FTFA_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_RDCOLLIE_SHIFT)) & FTFA_FCNFG_RDCOLLIE_MASK) |
mbed_official | 121:7f86b4238bec | 1474 | #define FTFA_FCNFG_CCIE_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 1475 | #define FTFA_FCNFG_CCIE_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 1476 | #define FTFA_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_CCIE_SHIFT)) & FTFA_FCNFG_CCIE_MASK) |
mbed_official | 121:7f86b4238bec | 1477 | |
mbed_official | 121:7f86b4238bec | 1478 | /*! @name FSEC - Flash Security Register */ |
mbed_official | 121:7f86b4238bec | 1479 | #define FTFA_FSEC_SEC_MASK (0x3U) |
mbed_official | 121:7f86b4238bec | 1480 | #define FTFA_FSEC_SEC_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1481 | #define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_SEC_SHIFT)) & FTFA_FSEC_SEC_MASK) |
mbed_official | 121:7f86b4238bec | 1482 | #define FTFA_FSEC_FSLACC_MASK (0xCU) |
mbed_official | 121:7f86b4238bec | 1483 | #define FTFA_FSEC_FSLACC_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 1484 | #define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_FSLACC_SHIFT)) & FTFA_FSEC_FSLACC_MASK) |
mbed_official | 121:7f86b4238bec | 1485 | #define FTFA_FSEC_MEEN_MASK (0x30U) |
mbed_official | 121:7f86b4238bec | 1486 | #define FTFA_FSEC_MEEN_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 1487 | #define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_MEEN_SHIFT)) & FTFA_FSEC_MEEN_MASK) |
mbed_official | 121:7f86b4238bec | 1488 | #define FTFA_FSEC_KEYEN_MASK (0xC0U) |
mbed_official | 121:7f86b4238bec | 1489 | #define FTFA_FSEC_KEYEN_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 1490 | #define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_KEYEN_SHIFT)) & FTFA_FSEC_KEYEN_MASK) |
mbed_official | 121:7f86b4238bec | 1491 | |
mbed_official | 121:7f86b4238bec | 1492 | /*! @name FOPT - Flash Option Register */ |
mbed_official | 121:7f86b4238bec | 1493 | #define FTFA_FOPT_OPT_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 1494 | #define FTFA_FOPT_OPT_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1495 | #define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FOPT_OPT_SHIFT)) & FTFA_FOPT_OPT_MASK) |
mbed_official | 121:7f86b4238bec | 1496 | |
mbed_official | 121:7f86b4238bec | 1497 | /*! @name FCCOB3 - Flash Common Command Object Registers */ |
mbed_official | 121:7f86b4238bec | 1498 | #define FTFA_FCCOB3_CCOBn_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 1499 | #define FTFA_FCCOB3_CCOBn_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1500 | #define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB3_CCOBn_SHIFT)) & FTFA_FCCOB3_CCOBn_MASK) |
mbed_official | 121:7f86b4238bec | 1501 | |
mbed_official | 121:7f86b4238bec | 1502 | /*! @name FCCOB2 - Flash Common Command Object Registers */ |
mbed_official | 121:7f86b4238bec | 1503 | #define FTFA_FCCOB2_CCOBn_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 1504 | #define FTFA_FCCOB2_CCOBn_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1505 | #define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB2_CCOBn_SHIFT)) & FTFA_FCCOB2_CCOBn_MASK) |
mbed_official | 121:7f86b4238bec | 1506 | |
mbed_official | 121:7f86b4238bec | 1507 | /*! @name FCCOB1 - Flash Common Command Object Registers */ |
mbed_official | 121:7f86b4238bec | 1508 | #define FTFA_FCCOB1_CCOBn_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 1509 | #define FTFA_FCCOB1_CCOBn_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1510 | #define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB1_CCOBn_SHIFT)) & FTFA_FCCOB1_CCOBn_MASK) |
mbed_official | 121:7f86b4238bec | 1511 | |
mbed_official | 121:7f86b4238bec | 1512 | /*! @name FCCOB0 - Flash Common Command Object Registers */ |
mbed_official | 121:7f86b4238bec | 1513 | #define FTFA_FCCOB0_CCOBn_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 1514 | #define FTFA_FCCOB0_CCOBn_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1515 | #define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB0_CCOBn_SHIFT)) & FTFA_FCCOB0_CCOBn_MASK) |
mbed_official | 121:7f86b4238bec | 1516 | |
mbed_official | 121:7f86b4238bec | 1517 | /*! @name FCCOB7 - Flash Common Command Object Registers */ |
mbed_official | 121:7f86b4238bec | 1518 | #define FTFA_FCCOB7_CCOBn_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 1519 | #define FTFA_FCCOB7_CCOBn_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1520 | #define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB7_CCOBn_SHIFT)) & FTFA_FCCOB7_CCOBn_MASK) |
mbed_official | 121:7f86b4238bec | 1521 | |
mbed_official | 121:7f86b4238bec | 1522 | /*! @name FCCOB6 - Flash Common Command Object Registers */ |
mbed_official | 121:7f86b4238bec | 1523 | #define FTFA_FCCOB6_CCOBn_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 1524 | #define FTFA_FCCOB6_CCOBn_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1525 | #define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB6_CCOBn_SHIFT)) & FTFA_FCCOB6_CCOBn_MASK) |
mbed_official | 121:7f86b4238bec | 1526 | |
mbed_official | 121:7f86b4238bec | 1527 | /*! @name FCCOB5 - Flash Common Command Object Registers */ |
mbed_official | 121:7f86b4238bec | 1528 | #define FTFA_FCCOB5_CCOBn_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 1529 | #define FTFA_FCCOB5_CCOBn_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1530 | #define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB5_CCOBn_SHIFT)) & FTFA_FCCOB5_CCOBn_MASK) |
mbed_official | 121:7f86b4238bec | 1531 | |
mbed_official | 121:7f86b4238bec | 1532 | /*! @name FCCOB4 - Flash Common Command Object Registers */ |
mbed_official | 121:7f86b4238bec | 1533 | #define FTFA_FCCOB4_CCOBn_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 1534 | #define FTFA_FCCOB4_CCOBn_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1535 | #define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB4_CCOBn_SHIFT)) & FTFA_FCCOB4_CCOBn_MASK) |
mbed_official | 121:7f86b4238bec | 1536 | |
mbed_official | 121:7f86b4238bec | 1537 | /*! @name FCCOBB - Flash Common Command Object Registers */ |
mbed_official | 121:7f86b4238bec | 1538 | #define FTFA_FCCOBB_CCOBn_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 1539 | #define FTFA_FCCOBB_CCOBn_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1540 | #define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBB_CCOBn_SHIFT)) & FTFA_FCCOBB_CCOBn_MASK) |
mbed_official | 121:7f86b4238bec | 1541 | |
mbed_official | 121:7f86b4238bec | 1542 | /*! @name FCCOBA - Flash Common Command Object Registers */ |
mbed_official | 121:7f86b4238bec | 1543 | #define FTFA_FCCOBA_CCOBn_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 1544 | #define FTFA_FCCOBA_CCOBn_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1545 | #define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBA_CCOBn_SHIFT)) & FTFA_FCCOBA_CCOBn_MASK) |
mbed_official | 121:7f86b4238bec | 1546 | |
mbed_official | 121:7f86b4238bec | 1547 | /*! @name FCCOB9 - Flash Common Command Object Registers */ |
mbed_official | 121:7f86b4238bec | 1548 | #define FTFA_FCCOB9_CCOBn_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 1549 | #define FTFA_FCCOB9_CCOBn_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1550 | #define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB9_CCOBn_SHIFT)) & FTFA_FCCOB9_CCOBn_MASK) |
mbed_official | 121:7f86b4238bec | 1551 | |
mbed_official | 121:7f86b4238bec | 1552 | /*! @name FCCOB8 - Flash Common Command Object Registers */ |
mbed_official | 121:7f86b4238bec | 1553 | #define FTFA_FCCOB8_CCOBn_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 1554 | #define FTFA_FCCOB8_CCOBn_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1555 | #define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB8_CCOBn_SHIFT)) & FTFA_FCCOB8_CCOBn_MASK) |
mbed_official | 121:7f86b4238bec | 1556 | |
mbed_official | 121:7f86b4238bec | 1557 | /*! @name FPROT3 - Program Flash Protection Registers */ |
mbed_official | 121:7f86b4238bec | 1558 | #define FTFA_FPROT3_PROT_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 1559 | #define FTFA_FPROT3_PROT_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1560 | #define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT3_PROT_SHIFT)) & FTFA_FPROT3_PROT_MASK) |
mbed_official | 121:7f86b4238bec | 1561 | |
mbed_official | 121:7f86b4238bec | 1562 | /*! @name FPROT2 - Program Flash Protection Registers */ |
mbed_official | 121:7f86b4238bec | 1563 | #define FTFA_FPROT2_PROT_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 1564 | #define FTFA_FPROT2_PROT_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1565 | #define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT2_PROT_SHIFT)) & FTFA_FPROT2_PROT_MASK) |
mbed_official | 121:7f86b4238bec | 1566 | |
mbed_official | 121:7f86b4238bec | 1567 | /*! @name FPROT1 - Program Flash Protection Registers */ |
mbed_official | 121:7f86b4238bec | 1568 | #define FTFA_FPROT1_PROT_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 1569 | #define FTFA_FPROT1_PROT_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1570 | #define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT1_PROT_SHIFT)) & FTFA_FPROT1_PROT_MASK) |
mbed_official | 121:7f86b4238bec | 1571 | |
mbed_official | 121:7f86b4238bec | 1572 | /*! @name FPROT0 - Program Flash Protection Registers */ |
mbed_official | 121:7f86b4238bec | 1573 | #define FTFA_FPROT0_PROT_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 1574 | #define FTFA_FPROT0_PROT_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1575 | #define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT0_PROT_SHIFT)) & FTFA_FPROT0_PROT_MASK) |
mbed_official | 121:7f86b4238bec | 1576 | |
mbed_official | 121:7f86b4238bec | 1577 | |
mbed_official | 121:7f86b4238bec | 1578 | /*! |
mbed_official | 121:7f86b4238bec | 1579 | * @} |
mbed_official | 121:7f86b4238bec | 1580 | */ /* end of group FTFA_Register_Masks */ |
mbed_official | 121:7f86b4238bec | 1581 | |
mbed_official | 121:7f86b4238bec | 1582 | |
mbed_official | 121:7f86b4238bec | 1583 | /* FTFA - Peripheral instance base addresses */ |
mbed_official | 121:7f86b4238bec | 1584 | /** Peripheral FTFA base address */ |
mbed_official | 121:7f86b4238bec | 1585 | #define FTFA_BASE (0x40020000u) |
mbed_official | 121:7f86b4238bec | 1586 | /** Peripheral FTFA base pointer */ |
mbed_official | 121:7f86b4238bec | 1587 | #define FTFA ((FTFA_Type *)FTFA_BASE) |
mbed_official | 121:7f86b4238bec | 1588 | /** Array initializer of FTFA peripheral base addresses */ |
mbed_official | 121:7f86b4238bec | 1589 | #define FTFA_BASE_ADDRS { FTFA_BASE } |
mbed_official | 121:7f86b4238bec | 1590 | /** Array initializer of FTFA peripheral base pointers */ |
mbed_official | 121:7f86b4238bec | 1591 | #define FTFA_BASE_PTRS { FTFA } |
mbed_official | 121:7f86b4238bec | 1592 | /** Interrupt vectors for the FTFA peripheral type */ |
mbed_official | 121:7f86b4238bec | 1593 | #define FTFA_COMMAND_COMPLETE_IRQS { FTFA_IRQn } |
mbed_official | 121:7f86b4238bec | 1594 | |
mbed_official | 121:7f86b4238bec | 1595 | /*! |
mbed_official | 121:7f86b4238bec | 1596 | * @} |
mbed_official | 121:7f86b4238bec | 1597 | */ /* end of group FTFA_Peripheral_Access_Layer */ |
mbed_official | 121:7f86b4238bec | 1598 | |
mbed_official | 121:7f86b4238bec | 1599 | |
mbed_official | 121:7f86b4238bec | 1600 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 1601 | -- GPIO Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 1602 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 1603 | |
mbed_official | 121:7f86b4238bec | 1604 | /*! |
mbed_official | 121:7f86b4238bec | 1605 | * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 1606 | * @{ |
mbed_official | 121:7f86b4238bec | 1607 | */ |
mbed_official | 121:7f86b4238bec | 1608 | |
mbed_official | 121:7f86b4238bec | 1609 | /** GPIO - Register Layout Typedef */ |
mbed_official | 121:7f86b4238bec | 1610 | typedef struct { |
mbed_official | 121:7f86b4238bec | 1611 | __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ |
mbed_official | 121:7f86b4238bec | 1612 | __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ |
mbed_official | 121:7f86b4238bec | 1613 | __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ |
mbed_official | 121:7f86b4238bec | 1614 | __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ |
mbed_official | 121:7f86b4238bec | 1615 | __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ |
mbed_official | 121:7f86b4238bec | 1616 | __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ |
mbed_official | 121:7f86b4238bec | 1617 | } GPIO_Type; |
mbed_official | 121:7f86b4238bec | 1618 | |
mbed_official | 121:7f86b4238bec | 1619 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 1620 | -- GPIO Register Masks |
mbed_official | 121:7f86b4238bec | 1621 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 1622 | |
mbed_official | 121:7f86b4238bec | 1623 | /*! |
mbed_official | 121:7f86b4238bec | 1624 | * @addtogroup GPIO_Register_Masks GPIO Register Masks |
mbed_official | 121:7f86b4238bec | 1625 | * @{ |
mbed_official | 121:7f86b4238bec | 1626 | */ |
mbed_official | 121:7f86b4238bec | 1627 | |
mbed_official | 121:7f86b4238bec | 1628 | /*! @name PDOR - Port Data Output Register */ |
mbed_official | 121:7f86b4238bec | 1629 | #define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 1630 | #define GPIO_PDOR_PDO_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1631 | #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK) |
mbed_official | 121:7f86b4238bec | 1632 | |
mbed_official | 121:7f86b4238bec | 1633 | /*! @name PSOR - Port Set Output Register */ |
mbed_official | 121:7f86b4238bec | 1634 | #define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 1635 | #define GPIO_PSOR_PTSO_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1636 | #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK) |
mbed_official | 121:7f86b4238bec | 1637 | |
mbed_official | 121:7f86b4238bec | 1638 | /*! @name PCOR - Port Clear Output Register */ |
mbed_official | 121:7f86b4238bec | 1639 | #define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 1640 | #define GPIO_PCOR_PTCO_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1641 | #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK) |
mbed_official | 121:7f86b4238bec | 1642 | |
mbed_official | 121:7f86b4238bec | 1643 | /*! @name PTOR - Port Toggle Output Register */ |
mbed_official | 121:7f86b4238bec | 1644 | #define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 1645 | #define GPIO_PTOR_PTTO_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1646 | #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK) |
mbed_official | 121:7f86b4238bec | 1647 | |
mbed_official | 121:7f86b4238bec | 1648 | /*! @name PDIR - Port Data Input Register */ |
mbed_official | 121:7f86b4238bec | 1649 | #define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 1650 | #define GPIO_PDIR_PDI_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1651 | #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK) |
mbed_official | 121:7f86b4238bec | 1652 | |
mbed_official | 121:7f86b4238bec | 1653 | /*! @name PDDR - Port Data Direction Register */ |
mbed_official | 121:7f86b4238bec | 1654 | #define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 1655 | #define GPIO_PDDR_PDD_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1656 | #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK) |
mbed_official | 121:7f86b4238bec | 1657 | |
mbed_official | 121:7f86b4238bec | 1658 | |
mbed_official | 121:7f86b4238bec | 1659 | /*! |
mbed_official | 121:7f86b4238bec | 1660 | * @} |
mbed_official | 121:7f86b4238bec | 1661 | */ /* end of group GPIO_Register_Masks */ |
mbed_official | 121:7f86b4238bec | 1662 | |
mbed_official | 121:7f86b4238bec | 1663 | |
mbed_official | 121:7f86b4238bec | 1664 | /* GPIO - Peripheral instance base addresses */ |
mbed_official | 121:7f86b4238bec | 1665 | /** Peripheral GPIOA base address */ |
mbed_official | 121:7f86b4238bec | 1666 | #define GPIOA_BASE (0x400FF000u) |
mbed_official | 121:7f86b4238bec | 1667 | /** Peripheral GPIOA base pointer */ |
mbed_official | 121:7f86b4238bec | 1668 | #define GPIOA ((GPIO_Type *)GPIOA_BASE) |
mbed_official | 121:7f86b4238bec | 1669 | /** Peripheral GPIOB base address */ |
mbed_official | 121:7f86b4238bec | 1670 | #define GPIOB_BASE (0x400FF040u) |
mbed_official | 121:7f86b4238bec | 1671 | /** Peripheral GPIOB base pointer */ |
mbed_official | 121:7f86b4238bec | 1672 | #define GPIOB ((GPIO_Type *)GPIOB_BASE) |
mbed_official | 121:7f86b4238bec | 1673 | /** Peripheral GPIOC base address */ |
mbed_official | 121:7f86b4238bec | 1674 | #define GPIOC_BASE (0x400FF080u) |
mbed_official | 121:7f86b4238bec | 1675 | /** Peripheral GPIOC base pointer */ |
mbed_official | 121:7f86b4238bec | 1676 | #define GPIOC ((GPIO_Type *)GPIOC_BASE) |
mbed_official | 121:7f86b4238bec | 1677 | /** Peripheral GPIOD base address */ |
mbed_official | 121:7f86b4238bec | 1678 | #define GPIOD_BASE (0x400FF0C0u) |
mbed_official | 121:7f86b4238bec | 1679 | /** Peripheral GPIOD base pointer */ |
mbed_official | 121:7f86b4238bec | 1680 | #define GPIOD ((GPIO_Type *)GPIOD_BASE) |
mbed_official | 121:7f86b4238bec | 1681 | /** Peripheral GPIOE base address */ |
mbed_official | 121:7f86b4238bec | 1682 | #define GPIOE_BASE (0x400FF100u) |
mbed_official | 121:7f86b4238bec | 1683 | /** Peripheral GPIOE base pointer */ |
mbed_official | 121:7f86b4238bec | 1684 | #define GPIOE ((GPIO_Type *)GPIOE_BASE) |
mbed_official | 121:7f86b4238bec | 1685 | /** Array initializer of GPIO peripheral base addresses */ |
mbed_official | 121:7f86b4238bec | 1686 | #define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE } |
mbed_official | 121:7f86b4238bec | 1687 | /** Array initializer of GPIO peripheral base pointers */ |
mbed_official | 121:7f86b4238bec | 1688 | #define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE } |
mbed_official | 121:7f86b4238bec | 1689 | |
mbed_official | 121:7f86b4238bec | 1690 | /*! |
mbed_official | 121:7f86b4238bec | 1691 | * @} |
mbed_official | 121:7f86b4238bec | 1692 | */ /* end of group GPIO_Peripheral_Access_Layer */ |
mbed_official | 121:7f86b4238bec | 1693 | |
mbed_official | 121:7f86b4238bec | 1694 | |
mbed_official | 121:7f86b4238bec | 1695 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 1696 | -- I2C Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 1697 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 1698 | |
mbed_official | 121:7f86b4238bec | 1699 | /*! |
mbed_official | 121:7f86b4238bec | 1700 | * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 1701 | * @{ |
mbed_official | 121:7f86b4238bec | 1702 | */ |
mbed_official | 121:7f86b4238bec | 1703 | |
mbed_official | 121:7f86b4238bec | 1704 | /** I2C - Register Layout Typedef */ |
mbed_official | 121:7f86b4238bec | 1705 | typedef struct { |
mbed_official | 121:7f86b4238bec | 1706 | __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */ |
mbed_official | 121:7f86b4238bec | 1707 | __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */ |
mbed_official | 121:7f86b4238bec | 1708 | __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */ |
mbed_official | 121:7f86b4238bec | 1709 | __IO uint8_t S; /**< I2C Status register, offset: 0x3 */ |
mbed_official | 121:7f86b4238bec | 1710 | __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */ |
mbed_official | 121:7f86b4238bec | 1711 | __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */ |
mbed_official | 121:7f86b4238bec | 1712 | __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter Register, offset: 0x6 */ |
mbed_official | 121:7f86b4238bec | 1713 | __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */ |
mbed_official | 121:7f86b4238bec | 1714 | __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */ |
mbed_official | 121:7f86b4238bec | 1715 | __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */ |
mbed_official | 121:7f86b4238bec | 1716 | __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */ |
mbed_official | 121:7f86b4238bec | 1717 | __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */ |
mbed_official | 121:7f86b4238bec | 1718 | __IO uint8_t S2; /**< I2C Status register 2, offset: 0xC */ |
mbed_official | 121:7f86b4238bec | 1719 | } I2C_Type; |
mbed_official | 121:7f86b4238bec | 1720 | |
mbed_official | 121:7f86b4238bec | 1721 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 1722 | -- I2C Register Masks |
mbed_official | 121:7f86b4238bec | 1723 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 1724 | |
mbed_official | 121:7f86b4238bec | 1725 | /*! |
mbed_official | 121:7f86b4238bec | 1726 | * @addtogroup I2C_Register_Masks I2C Register Masks |
mbed_official | 121:7f86b4238bec | 1727 | * @{ |
mbed_official | 121:7f86b4238bec | 1728 | */ |
mbed_official | 121:7f86b4238bec | 1729 | |
mbed_official | 121:7f86b4238bec | 1730 | /*! @name A1 - I2C Address Register 1 */ |
mbed_official | 121:7f86b4238bec | 1731 | #define I2C_A1_AD_MASK (0xFEU) |
mbed_official | 121:7f86b4238bec | 1732 | #define I2C_A1_AD_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 1733 | #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK) |
mbed_official | 121:7f86b4238bec | 1734 | |
mbed_official | 121:7f86b4238bec | 1735 | /*! @name F - I2C Frequency Divider register */ |
mbed_official | 121:7f86b4238bec | 1736 | #define I2C_F_ICR_MASK (0x3FU) |
mbed_official | 121:7f86b4238bec | 1737 | #define I2C_F_ICR_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1738 | #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK) |
mbed_official | 121:7f86b4238bec | 1739 | #define I2C_F_MULT_MASK (0xC0U) |
mbed_official | 121:7f86b4238bec | 1740 | #define I2C_F_MULT_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 1741 | #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK) |
mbed_official | 121:7f86b4238bec | 1742 | |
mbed_official | 121:7f86b4238bec | 1743 | /*! @name C1 - I2C Control Register 1 */ |
mbed_official | 121:7f86b4238bec | 1744 | #define I2C_C1_DMAEN_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 1745 | #define I2C_C1_DMAEN_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1746 | #define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK) |
mbed_official | 121:7f86b4238bec | 1747 | #define I2C_C1_WUEN_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 1748 | #define I2C_C1_WUEN_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 1749 | #define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK) |
mbed_official | 121:7f86b4238bec | 1750 | #define I2C_C1_RSTA_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 1751 | #define I2C_C1_RSTA_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 1752 | #define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK) |
mbed_official | 121:7f86b4238bec | 1753 | #define I2C_C1_TXAK_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 1754 | #define I2C_C1_TXAK_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 1755 | #define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK) |
mbed_official | 121:7f86b4238bec | 1756 | #define I2C_C1_TX_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 1757 | #define I2C_C1_TX_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 1758 | #define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK) |
mbed_official | 121:7f86b4238bec | 1759 | #define I2C_C1_MST_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 1760 | #define I2C_C1_MST_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 1761 | #define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK) |
mbed_official | 121:7f86b4238bec | 1762 | #define I2C_C1_IICIE_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 1763 | #define I2C_C1_IICIE_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 1764 | #define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK) |
mbed_official | 121:7f86b4238bec | 1765 | #define I2C_C1_IICEN_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 1766 | #define I2C_C1_IICEN_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 1767 | #define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK) |
mbed_official | 121:7f86b4238bec | 1768 | |
mbed_official | 121:7f86b4238bec | 1769 | /*! @name S - I2C Status register */ |
mbed_official | 121:7f86b4238bec | 1770 | #define I2C_S_RXAK_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 1771 | #define I2C_S_RXAK_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1772 | #define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK) |
mbed_official | 121:7f86b4238bec | 1773 | #define I2C_S_IICIF_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 1774 | #define I2C_S_IICIF_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 1775 | #define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK) |
mbed_official | 121:7f86b4238bec | 1776 | #define I2C_S_SRW_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 1777 | #define I2C_S_SRW_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 1778 | #define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK) |
mbed_official | 121:7f86b4238bec | 1779 | #define I2C_S_RAM_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 1780 | #define I2C_S_RAM_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 1781 | #define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK) |
mbed_official | 121:7f86b4238bec | 1782 | #define I2C_S_ARBL_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 1783 | #define I2C_S_ARBL_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 1784 | #define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK) |
mbed_official | 121:7f86b4238bec | 1785 | #define I2C_S_BUSY_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 1786 | #define I2C_S_BUSY_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 1787 | #define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK) |
mbed_official | 121:7f86b4238bec | 1788 | #define I2C_S_IAAS_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 1789 | #define I2C_S_IAAS_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 1790 | #define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK) |
mbed_official | 121:7f86b4238bec | 1791 | #define I2C_S_TCF_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 1792 | #define I2C_S_TCF_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 1793 | #define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK) |
mbed_official | 121:7f86b4238bec | 1794 | |
mbed_official | 121:7f86b4238bec | 1795 | /*! @name D - I2C Data I/O register */ |
mbed_official | 121:7f86b4238bec | 1796 | #define I2C_D_DATA_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 1797 | #define I2C_D_DATA_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1798 | #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK) |
mbed_official | 121:7f86b4238bec | 1799 | |
mbed_official | 121:7f86b4238bec | 1800 | /*! @name C2 - I2C Control Register 2 */ |
mbed_official | 121:7f86b4238bec | 1801 | #define I2C_C2_AD_MASK (0x7U) |
mbed_official | 121:7f86b4238bec | 1802 | #define I2C_C2_AD_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1803 | #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK) |
mbed_official | 121:7f86b4238bec | 1804 | #define I2C_C2_RMEN_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 1805 | #define I2C_C2_RMEN_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 1806 | #define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK) |
mbed_official | 121:7f86b4238bec | 1807 | #define I2C_C2_SBRC_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 1808 | #define I2C_C2_SBRC_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 1809 | #define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK) |
mbed_official | 121:7f86b4238bec | 1810 | #define I2C_C2_HDRS_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 1811 | #define I2C_C2_HDRS_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 1812 | #define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK) |
mbed_official | 121:7f86b4238bec | 1813 | #define I2C_C2_ADEXT_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 1814 | #define I2C_C2_ADEXT_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 1815 | #define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK) |
mbed_official | 121:7f86b4238bec | 1816 | #define I2C_C2_GCAEN_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 1817 | #define I2C_C2_GCAEN_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 1818 | #define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK) |
mbed_official | 121:7f86b4238bec | 1819 | |
mbed_official | 121:7f86b4238bec | 1820 | /*! @name FLT - I2C Programmable Input Glitch Filter Register */ |
mbed_official | 121:7f86b4238bec | 1821 | #define I2C_FLT_FLT_MASK (0xFU) |
mbed_official | 121:7f86b4238bec | 1822 | #define I2C_FLT_FLT_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1823 | #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK) |
mbed_official | 121:7f86b4238bec | 1824 | #define I2C_FLT_STARTF_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 1825 | #define I2C_FLT_STARTF_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 1826 | #define I2C_FLT_STARTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK) |
mbed_official | 121:7f86b4238bec | 1827 | #define I2C_FLT_SSIE_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 1828 | #define I2C_FLT_SSIE_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 1829 | #define I2C_FLT_SSIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK) |
mbed_official | 121:7f86b4238bec | 1830 | #define I2C_FLT_STOPF_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 1831 | #define I2C_FLT_STOPF_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 1832 | #define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK) |
mbed_official | 121:7f86b4238bec | 1833 | #define I2C_FLT_SHEN_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 1834 | #define I2C_FLT_SHEN_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 1835 | #define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK) |
mbed_official | 121:7f86b4238bec | 1836 | |
mbed_official | 121:7f86b4238bec | 1837 | /*! @name RA - I2C Range Address register */ |
mbed_official | 121:7f86b4238bec | 1838 | #define I2C_RA_RAD_MASK (0xFEU) |
mbed_official | 121:7f86b4238bec | 1839 | #define I2C_RA_RAD_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 1840 | #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK) |
mbed_official | 121:7f86b4238bec | 1841 | |
mbed_official | 121:7f86b4238bec | 1842 | /*! @name SMB - I2C SMBus Control and Status register */ |
mbed_official | 121:7f86b4238bec | 1843 | #define I2C_SMB_SHTF2IE_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 1844 | #define I2C_SMB_SHTF2IE_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1845 | #define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK) |
mbed_official | 121:7f86b4238bec | 1846 | #define I2C_SMB_SHTF2_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 1847 | #define I2C_SMB_SHTF2_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 1848 | #define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK) |
mbed_official | 121:7f86b4238bec | 1849 | #define I2C_SMB_SHTF1_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 1850 | #define I2C_SMB_SHTF1_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 1851 | #define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK) |
mbed_official | 121:7f86b4238bec | 1852 | #define I2C_SMB_SLTF_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 1853 | #define I2C_SMB_SLTF_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 1854 | #define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK) |
mbed_official | 121:7f86b4238bec | 1855 | #define I2C_SMB_TCKSEL_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 1856 | #define I2C_SMB_TCKSEL_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 1857 | #define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK) |
mbed_official | 121:7f86b4238bec | 1858 | #define I2C_SMB_SIICAEN_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 1859 | #define I2C_SMB_SIICAEN_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 1860 | #define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK) |
mbed_official | 121:7f86b4238bec | 1861 | #define I2C_SMB_ALERTEN_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 1862 | #define I2C_SMB_ALERTEN_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 1863 | #define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK) |
mbed_official | 121:7f86b4238bec | 1864 | #define I2C_SMB_FACK_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 1865 | #define I2C_SMB_FACK_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 1866 | #define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK) |
mbed_official | 121:7f86b4238bec | 1867 | |
mbed_official | 121:7f86b4238bec | 1868 | /*! @name A2 - I2C Address Register 2 */ |
mbed_official | 121:7f86b4238bec | 1869 | #define I2C_A2_SAD_MASK (0xFEU) |
mbed_official | 121:7f86b4238bec | 1870 | #define I2C_A2_SAD_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 1871 | #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK) |
mbed_official | 121:7f86b4238bec | 1872 | |
mbed_official | 121:7f86b4238bec | 1873 | /*! @name SLTH - I2C SCL Low Timeout Register High */ |
mbed_official | 121:7f86b4238bec | 1874 | #define I2C_SLTH_SSLT_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 1875 | #define I2C_SLTH_SSLT_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1876 | #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK) |
mbed_official | 121:7f86b4238bec | 1877 | |
mbed_official | 121:7f86b4238bec | 1878 | /*! @name SLTL - I2C SCL Low Timeout Register Low */ |
mbed_official | 121:7f86b4238bec | 1879 | #define I2C_SLTL_SSLT_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 1880 | #define I2C_SLTL_SSLT_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1881 | #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK) |
mbed_official | 121:7f86b4238bec | 1882 | |
mbed_official | 121:7f86b4238bec | 1883 | /*! @name S2 - I2C Status register 2 */ |
mbed_official | 121:7f86b4238bec | 1884 | #define I2C_S2_EMPTY_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 1885 | #define I2C_S2_EMPTY_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1886 | #define I2C_S2_EMPTY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S2_EMPTY_SHIFT)) & I2C_S2_EMPTY_MASK) |
mbed_official | 121:7f86b4238bec | 1887 | #define I2C_S2_ERROR_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 1888 | #define I2C_S2_ERROR_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 1889 | #define I2C_S2_ERROR(x) (((uint8_t)(((uint8_t)(x)) << I2C_S2_ERROR_SHIFT)) & I2C_S2_ERROR_MASK) |
mbed_official | 121:7f86b4238bec | 1890 | |
mbed_official | 121:7f86b4238bec | 1891 | |
mbed_official | 121:7f86b4238bec | 1892 | /*! |
mbed_official | 121:7f86b4238bec | 1893 | * @} |
mbed_official | 121:7f86b4238bec | 1894 | */ /* end of group I2C_Register_Masks */ |
mbed_official | 121:7f86b4238bec | 1895 | |
mbed_official | 121:7f86b4238bec | 1896 | |
mbed_official | 121:7f86b4238bec | 1897 | /* I2C - Peripheral instance base addresses */ |
mbed_official | 121:7f86b4238bec | 1898 | /** Peripheral I2C0 base address */ |
mbed_official | 121:7f86b4238bec | 1899 | #define I2C0_BASE (0x40066000u) |
mbed_official | 121:7f86b4238bec | 1900 | /** Peripheral I2C0 base pointer */ |
mbed_official | 121:7f86b4238bec | 1901 | #define I2C0 ((I2C_Type *)I2C0_BASE) |
mbed_official | 121:7f86b4238bec | 1902 | /** Peripheral I2C1 base address */ |
mbed_official | 121:7f86b4238bec | 1903 | #define I2C1_BASE (0x40067000u) |
mbed_official | 121:7f86b4238bec | 1904 | /** Peripheral I2C1 base pointer */ |
mbed_official | 121:7f86b4238bec | 1905 | #define I2C1 ((I2C_Type *)I2C1_BASE) |
mbed_official | 121:7f86b4238bec | 1906 | /** Array initializer of I2C peripheral base addresses */ |
mbed_official | 121:7f86b4238bec | 1907 | #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE } |
mbed_official | 121:7f86b4238bec | 1908 | /** Array initializer of I2C peripheral base pointers */ |
mbed_official | 121:7f86b4238bec | 1909 | #define I2C_BASE_PTRS { I2C0, I2C1 } |
mbed_official | 121:7f86b4238bec | 1910 | /** Interrupt vectors for the I2C peripheral type */ |
mbed_official | 121:7f86b4238bec | 1911 | #define I2C_IRQS { I2C0_IRQn, I2C1_IRQn } |
mbed_official | 121:7f86b4238bec | 1912 | |
mbed_official | 121:7f86b4238bec | 1913 | /*! |
mbed_official | 121:7f86b4238bec | 1914 | * @} |
mbed_official | 121:7f86b4238bec | 1915 | */ /* end of group I2C_Peripheral_Access_Layer */ |
mbed_official | 121:7f86b4238bec | 1916 | |
mbed_official | 121:7f86b4238bec | 1917 | |
mbed_official | 121:7f86b4238bec | 1918 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 1919 | -- LLWU Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 1920 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 1921 | |
mbed_official | 121:7f86b4238bec | 1922 | /*! |
mbed_official | 121:7f86b4238bec | 1923 | * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 1924 | * @{ |
mbed_official | 121:7f86b4238bec | 1925 | */ |
mbed_official | 121:7f86b4238bec | 1926 | |
mbed_official | 121:7f86b4238bec | 1927 | /** LLWU - Register Layout Typedef */ |
mbed_official | 121:7f86b4238bec | 1928 | typedef struct { |
mbed_official | 121:7f86b4238bec | 1929 | __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */ |
mbed_official | 121:7f86b4238bec | 1930 | __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */ |
mbed_official | 121:7f86b4238bec | 1931 | __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */ |
mbed_official | 121:7f86b4238bec | 1932 | __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */ |
mbed_official | 121:7f86b4238bec | 1933 | __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */ |
mbed_official | 121:7f86b4238bec | 1934 | __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */ |
mbed_official | 121:7f86b4238bec | 1935 | __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */ |
mbed_official | 121:7f86b4238bec | 1936 | __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */ |
mbed_official | 121:7f86b4238bec | 1937 | __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */ |
mbed_official | 121:7f86b4238bec | 1938 | __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */ |
mbed_official | 121:7f86b4238bec | 1939 | } LLWU_Type; |
mbed_official | 121:7f86b4238bec | 1940 | |
mbed_official | 121:7f86b4238bec | 1941 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 1942 | -- LLWU Register Masks |
mbed_official | 121:7f86b4238bec | 1943 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 1944 | |
mbed_official | 121:7f86b4238bec | 1945 | /*! |
mbed_official | 121:7f86b4238bec | 1946 | * @addtogroup LLWU_Register_Masks LLWU Register Masks |
mbed_official | 121:7f86b4238bec | 1947 | * @{ |
mbed_official | 121:7f86b4238bec | 1948 | */ |
mbed_official | 121:7f86b4238bec | 1949 | |
mbed_official | 121:7f86b4238bec | 1950 | /*! @name PE1 - LLWU Pin Enable 1 register */ |
mbed_official | 121:7f86b4238bec | 1951 | #define LLWU_PE1_WUPE0_MASK (0x3U) |
mbed_official | 121:7f86b4238bec | 1952 | #define LLWU_PE1_WUPE0_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1953 | #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK) |
mbed_official | 121:7f86b4238bec | 1954 | #define LLWU_PE1_WUPE1_MASK (0xCU) |
mbed_official | 121:7f86b4238bec | 1955 | #define LLWU_PE1_WUPE1_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 1956 | #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK) |
mbed_official | 121:7f86b4238bec | 1957 | #define LLWU_PE1_WUPE2_MASK (0x30U) |
mbed_official | 121:7f86b4238bec | 1958 | #define LLWU_PE1_WUPE2_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 1959 | #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK) |
mbed_official | 121:7f86b4238bec | 1960 | #define LLWU_PE1_WUPE3_MASK (0xC0U) |
mbed_official | 121:7f86b4238bec | 1961 | #define LLWU_PE1_WUPE3_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 1962 | #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK) |
mbed_official | 121:7f86b4238bec | 1963 | |
mbed_official | 121:7f86b4238bec | 1964 | /*! @name PE2 - LLWU Pin Enable 2 register */ |
mbed_official | 121:7f86b4238bec | 1965 | #define LLWU_PE2_WUPE4_MASK (0x3U) |
mbed_official | 121:7f86b4238bec | 1966 | #define LLWU_PE2_WUPE4_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1967 | #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK) |
mbed_official | 121:7f86b4238bec | 1968 | #define LLWU_PE2_WUPE5_MASK (0xCU) |
mbed_official | 121:7f86b4238bec | 1969 | #define LLWU_PE2_WUPE5_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 1970 | #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK) |
mbed_official | 121:7f86b4238bec | 1971 | #define LLWU_PE2_WUPE6_MASK (0x30U) |
mbed_official | 121:7f86b4238bec | 1972 | #define LLWU_PE2_WUPE6_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 1973 | #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK) |
mbed_official | 121:7f86b4238bec | 1974 | #define LLWU_PE2_WUPE7_MASK (0xC0U) |
mbed_official | 121:7f86b4238bec | 1975 | #define LLWU_PE2_WUPE7_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 1976 | #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK) |
mbed_official | 121:7f86b4238bec | 1977 | |
mbed_official | 121:7f86b4238bec | 1978 | /*! @name PE3 - LLWU Pin Enable 3 register */ |
mbed_official | 121:7f86b4238bec | 1979 | #define LLWU_PE3_WUPE8_MASK (0x3U) |
mbed_official | 121:7f86b4238bec | 1980 | #define LLWU_PE3_WUPE8_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1981 | #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK) |
mbed_official | 121:7f86b4238bec | 1982 | #define LLWU_PE3_WUPE9_MASK (0xCU) |
mbed_official | 121:7f86b4238bec | 1983 | #define LLWU_PE3_WUPE9_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 1984 | #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK) |
mbed_official | 121:7f86b4238bec | 1985 | #define LLWU_PE3_WUPE10_MASK (0x30U) |
mbed_official | 121:7f86b4238bec | 1986 | #define LLWU_PE3_WUPE10_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 1987 | #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK) |
mbed_official | 121:7f86b4238bec | 1988 | #define LLWU_PE3_WUPE11_MASK (0xC0U) |
mbed_official | 121:7f86b4238bec | 1989 | #define LLWU_PE3_WUPE11_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 1990 | #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK) |
mbed_official | 121:7f86b4238bec | 1991 | |
mbed_official | 121:7f86b4238bec | 1992 | /*! @name PE4 - LLWU Pin Enable 4 register */ |
mbed_official | 121:7f86b4238bec | 1993 | #define LLWU_PE4_WUPE12_MASK (0x3U) |
mbed_official | 121:7f86b4238bec | 1994 | #define LLWU_PE4_WUPE12_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 1995 | #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK) |
mbed_official | 121:7f86b4238bec | 1996 | #define LLWU_PE4_WUPE13_MASK (0xCU) |
mbed_official | 121:7f86b4238bec | 1997 | #define LLWU_PE4_WUPE13_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 1998 | #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK) |
mbed_official | 121:7f86b4238bec | 1999 | #define LLWU_PE4_WUPE14_MASK (0x30U) |
mbed_official | 121:7f86b4238bec | 2000 | #define LLWU_PE4_WUPE14_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 2001 | #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK) |
mbed_official | 121:7f86b4238bec | 2002 | #define LLWU_PE4_WUPE15_MASK (0xC0U) |
mbed_official | 121:7f86b4238bec | 2003 | #define LLWU_PE4_WUPE15_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 2004 | #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK) |
mbed_official | 121:7f86b4238bec | 2005 | |
mbed_official | 121:7f86b4238bec | 2006 | /*! @name ME - LLWU Module Enable register */ |
mbed_official | 121:7f86b4238bec | 2007 | #define LLWU_ME_WUME0_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 2008 | #define LLWU_ME_WUME0_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 2009 | #define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK) |
mbed_official | 121:7f86b4238bec | 2010 | #define LLWU_ME_WUME1_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 2011 | #define LLWU_ME_WUME1_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 2012 | #define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK) |
mbed_official | 121:7f86b4238bec | 2013 | #define LLWU_ME_WUME2_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 2014 | #define LLWU_ME_WUME2_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 2015 | #define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK) |
mbed_official | 121:7f86b4238bec | 2016 | #define LLWU_ME_WUME3_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 2017 | #define LLWU_ME_WUME3_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 2018 | #define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK) |
mbed_official | 121:7f86b4238bec | 2019 | #define LLWU_ME_WUME4_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 2020 | #define LLWU_ME_WUME4_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 2021 | #define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK) |
mbed_official | 121:7f86b4238bec | 2022 | #define LLWU_ME_WUME5_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 2023 | #define LLWU_ME_WUME5_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 2024 | #define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK) |
mbed_official | 121:7f86b4238bec | 2025 | #define LLWU_ME_WUME6_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 2026 | #define LLWU_ME_WUME6_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 2027 | #define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK) |
mbed_official | 121:7f86b4238bec | 2028 | #define LLWU_ME_WUME7_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 2029 | #define LLWU_ME_WUME7_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 2030 | #define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK) |
mbed_official | 121:7f86b4238bec | 2031 | |
mbed_official | 121:7f86b4238bec | 2032 | /*! @name F1 - LLWU Flag 1 register */ |
mbed_official | 121:7f86b4238bec | 2033 | #define LLWU_F1_WUF0_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 2034 | #define LLWU_F1_WUF0_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 2035 | #define LLWU_F1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF0_SHIFT)) & LLWU_F1_WUF0_MASK) |
mbed_official | 121:7f86b4238bec | 2036 | #define LLWU_F1_WUF1_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 2037 | #define LLWU_F1_WUF1_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 2038 | #define LLWU_F1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF1_SHIFT)) & LLWU_F1_WUF1_MASK) |
mbed_official | 121:7f86b4238bec | 2039 | #define LLWU_F1_WUF2_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 2040 | #define LLWU_F1_WUF2_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 2041 | #define LLWU_F1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF2_SHIFT)) & LLWU_F1_WUF2_MASK) |
mbed_official | 121:7f86b4238bec | 2042 | #define LLWU_F1_WUF3_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 2043 | #define LLWU_F1_WUF3_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 2044 | #define LLWU_F1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF3_SHIFT)) & LLWU_F1_WUF3_MASK) |
mbed_official | 121:7f86b4238bec | 2045 | #define LLWU_F1_WUF4_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 2046 | #define LLWU_F1_WUF4_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 2047 | #define LLWU_F1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF4_SHIFT)) & LLWU_F1_WUF4_MASK) |
mbed_official | 121:7f86b4238bec | 2048 | #define LLWU_F1_WUF5_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 2049 | #define LLWU_F1_WUF5_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 2050 | #define LLWU_F1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF5_SHIFT)) & LLWU_F1_WUF5_MASK) |
mbed_official | 121:7f86b4238bec | 2051 | #define LLWU_F1_WUF6_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 2052 | #define LLWU_F1_WUF6_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 2053 | #define LLWU_F1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF6_SHIFT)) & LLWU_F1_WUF6_MASK) |
mbed_official | 121:7f86b4238bec | 2054 | #define LLWU_F1_WUF7_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 2055 | #define LLWU_F1_WUF7_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 2056 | #define LLWU_F1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF7_SHIFT)) & LLWU_F1_WUF7_MASK) |
mbed_official | 121:7f86b4238bec | 2057 | |
mbed_official | 121:7f86b4238bec | 2058 | /*! @name F2 - LLWU Flag 2 register */ |
mbed_official | 121:7f86b4238bec | 2059 | #define LLWU_F2_WUF8_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 2060 | #define LLWU_F2_WUF8_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 2061 | #define LLWU_F2_WUF8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF8_SHIFT)) & LLWU_F2_WUF8_MASK) |
mbed_official | 121:7f86b4238bec | 2062 | #define LLWU_F2_WUF9_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 2063 | #define LLWU_F2_WUF9_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 2064 | #define LLWU_F2_WUF9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF9_SHIFT)) & LLWU_F2_WUF9_MASK) |
mbed_official | 121:7f86b4238bec | 2065 | #define LLWU_F2_WUF10_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 2066 | #define LLWU_F2_WUF10_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 2067 | #define LLWU_F2_WUF10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF10_SHIFT)) & LLWU_F2_WUF10_MASK) |
mbed_official | 121:7f86b4238bec | 2068 | #define LLWU_F2_WUF11_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 2069 | #define LLWU_F2_WUF11_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 2070 | #define LLWU_F2_WUF11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF11_SHIFT)) & LLWU_F2_WUF11_MASK) |
mbed_official | 121:7f86b4238bec | 2071 | #define LLWU_F2_WUF12_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 2072 | #define LLWU_F2_WUF12_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 2073 | #define LLWU_F2_WUF12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF12_SHIFT)) & LLWU_F2_WUF12_MASK) |
mbed_official | 121:7f86b4238bec | 2074 | #define LLWU_F2_WUF13_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 2075 | #define LLWU_F2_WUF13_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 2076 | #define LLWU_F2_WUF13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF13_SHIFT)) & LLWU_F2_WUF13_MASK) |
mbed_official | 121:7f86b4238bec | 2077 | #define LLWU_F2_WUF14_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 2078 | #define LLWU_F2_WUF14_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 2079 | #define LLWU_F2_WUF14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF14_SHIFT)) & LLWU_F2_WUF14_MASK) |
mbed_official | 121:7f86b4238bec | 2080 | #define LLWU_F2_WUF15_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 2081 | #define LLWU_F2_WUF15_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 2082 | #define LLWU_F2_WUF15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF15_SHIFT)) & LLWU_F2_WUF15_MASK) |
mbed_official | 121:7f86b4238bec | 2083 | |
mbed_official | 121:7f86b4238bec | 2084 | /*! @name F3 - LLWU Flag 3 register */ |
mbed_official | 121:7f86b4238bec | 2085 | #define LLWU_F3_MWUF0_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 2086 | #define LLWU_F3_MWUF0_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 2087 | #define LLWU_F3_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF0_SHIFT)) & LLWU_F3_MWUF0_MASK) |
mbed_official | 121:7f86b4238bec | 2088 | #define LLWU_F3_MWUF1_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 2089 | #define LLWU_F3_MWUF1_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 2090 | #define LLWU_F3_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF1_SHIFT)) & LLWU_F3_MWUF1_MASK) |
mbed_official | 121:7f86b4238bec | 2091 | #define LLWU_F3_MWUF2_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 2092 | #define LLWU_F3_MWUF2_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 2093 | #define LLWU_F3_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF2_SHIFT)) & LLWU_F3_MWUF2_MASK) |
mbed_official | 121:7f86b4238bec | 2094 | #define LLWU_F3_MWUF3_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 2095 | #define LLWU_F3_MWUF3_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 2096 | #define LLWU_F3_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF3_SHIFT)) & LLWU_F3_MWUF3_MASK) |
mbed_official | 121:7f86b4238bec | 2097 | #define LLWU_F3_MWUF4_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 2098 | #define LLWU_F3_MWUF4_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 2099 | #define LLWU_F3_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF4_SHIFT)) & LLWU_F3_MWUF4_MASK) |
mbed_official | 121:7f86b4238bec | 2100 | #define LLWU_F3_MWUF5_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 2101 | #define LLWU_F3_MWUF5_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 2102 | #define LLWU_F3_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF5_SHIFT)) & LLWU_F3_MWUF5_MASK) |
mbed_official | 121:7f86b4238bec | 2103 | #define LLWU_F3_MWUF6_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 2104 | #define LLWU_F3_MWUF6_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 2105 | #define LLWU_F3_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF6_SHIFT)) & LLWU_F3_MWUF6_MASK) |
mbed_official | 121:7f86b4238bec | 2106 | #define LLWU_F3_MWUF7_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 2107 | #define LLWU_F3_MWUF7_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 2108 | #define LLWU_F3_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF7_SHIFT)) & LLWU_F3_MWUF7_MASK) |
mbed_official | 121:7f86b4238bec | 2109 | |
mbed_official | 121:7f86b4238bec | 2110 | /*! @name FILT1 - LLWU Pin Filter 1 register */ |
mbed_official | 121:7f86b4238bec | 2111 | #define LLWU_FILT1_FILTSEL_MASK (0xFU) |
mbed_official | 121:7f86b4238bec | 2112 | #define LLWU_FILT1_FILTSEL_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 2113 | #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK) |
mbed_official | 121:7f86b4238bec | 2114 | #define LLWU_FILT1_FILTE_MASK (0x60U) |
mbed_official | 121:7f86b4238bec | 2115 | #define LLWU_FILT1_FILTE_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 2116 | #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK) |
mbed_official | 121:7f86b4238bec | 2117 | #define LLWU_FILT1_FILTF_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 2118 | #define LLWU_FILT1_FILTF_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 2119 | #define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK) |
mbed_official | 121:7f86b4238bec | 2120 | |
mbed_official | 121:7f86b4238bec | 2121 | /*! @name FILT2 - LLWU Pin Filter 2 register */ |
mbed_official | 121:7f86b4238bec | 2122 | #define LLWU_FILT2_FILTSEL_MASK (0xFU) |
mbed_official | 121:7f86b4238bec | 2123 | #define LLWU_FILT2_FILTSEL_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 2124 | #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK) |
mbed_official | 121:7f86b4238bec | 2125 | #define LLWU_FILT2_FILTE_MASK (0x60U) |
mbed_official | 121:7f86b4238bec | 2126 | #define LLWU_FILT2_FILTE_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 2127 | #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK) |
mbed_official | 121:7f86b4238bec | 2128 | #define LLWU_FILT2_FILTF_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 2129 | #define LLWU_FILT2_FILTF_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 2130 | #define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK) |
mbed_official | 121:7f86b4238bec | 2131 | |
mbed_official | 121:7f86b4238bec | 2132 | |
mbed_official | 121:7f86b4238bec | 2133 | /*! |
mbed_official | 121:7f86b4238bec | 2134 | * @} |
mbed_official | 121:7f86b4238bec | 2135 | */ /* end of group LLWU_Register_Masks */ |
mbed_official | 121:7f86b4238bec | 2136 | |
mbed_official | 121:7f86b4238bec | 2137 | |
mbed_official | 121:7f86b4238bec | 2138 | /* LLWU - Peripheral instance base addresses */ |
mbed_official | 121:7f86b4238bec | 2139 | /** Peripheral LLWU base address */ |
mbed_official | 121:7f86b4238bec | 2140 | #define LLWU_BASE (0x4007C000u) |
mbed_official | 121:7f86b4238bec | 2141 | /** Peripheral LLWU base pointer */ |
mbed_official | 121:7f86b4238bec | 2142 | #define LLWU ((LLWU_Type *)LLWU_BASE) |
mbed_official | 121:7f86b4238bec | 2143 | /** Array initializer of LLWU peripheral base addresses */ |
mbed_official | 121:7f86b4238bec | 2144 | #define LLWU_BASE_ADDRS { LLWU_BASE } |
mbed_official | 121:7f86b4238bec | 2145 | /** Array initializer of LLWU peripheral base pointers */ |
mbed_official | 121:7f86b4238bec | 2146 | #define LLWU_BASE_PTRS { LLWU } |
mbed_official | 121:7f86b4238bec | 2147 | /** Interrupt vectors for the LLWU peripheral type */ |
mbed_official | 121:7f86b4238bec | 2148 | #define LLWU_IRQS { LLWU_IRQn } |
mbed_official | 121:7f86b4238bec | 2149 | |
mbed_official | 121:7f86b4238bec | 2150 | /*! |
mbed_official | 121:7f86b4238bec | 2151 | * @} |
mbed_official | 121:7f86b4238bec | 2152 | */ /* end of group LLWU_Peripheral_Access_Layer */ |
mbed_official | 121:7f86b4238bec | 2153 | |
mbed_official | 121:7f86b4238bec | 2154 | |
mbed_official | 121:7f86b4238bec | 2155 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 2156 | -- LPTMR Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 2157 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 2158 | |
mbed_official | 121:7f86b4238bec | 2159 | /*! |
mbed_official | 121:7f86b4238bec | 2160 | * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 2161 | * @{ |
mbed_official | 121:7f86b4238bec | 2162 | */ |
mbed_official | 121:7f86b4238bec | 2163 | |
mbed_official | 121:7f86b4238bec | 2164 | /** LPTMR - Register Layout Typedef */ |
mbed_official | 121:7f86b4238bec | 2165 | typedef struct { |
mbed_official | 121:7f86b4238bec | 2166 | __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */ |
mbed_official | 121:7f86b4238bec | 2167 | __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */ |
mbed_official | 121:7f86b4238bec | 2168 | __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */ |
mbed_official | 121:7f86b4238bec | 2169 | __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */ |
mbed_official | 121:7f86b4238bec | 2170 | } LPTMR_Type; |
mbed_official | 121:7f86b4238bec | 2171 | |
mbed_official | 121:7f86b4238bec | 2172 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 2173 | -- LPTMR Register Masks |
mbed_official | 121:7f86b4238bec | 2174 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 2175 | |
mbed_official | 121:7f86b4238bec | 2176 | /*! |
mbed_official | 121:7f86b4238bec | 2177 | * @addtogroup LPTMR_Register_Masks LPTMR Register Masks |
mbed_official | 121:7f86b4238bec | 2178 | * @{ |
mbed_official | 121:7f86b4238bec | 2179 | */ |
mbed_official | 121:7f86b4238bec | 2180 | |
mbed_official | 121:7f86b4238bec | 2181 | /*! @name CSR - Low Power Timer Control Status Register */ |
mbed_official | 121:7f86b4238bec | 2182 | #define LPTMR_CSR_TEN_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 2183 | #define LPTMR_CSR_TEN_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 2184 | #define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK) |
mbed_official | 121:7f86b4238bec | 2185 | #define LPTMR_CSR_TMS_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 2186 | #define LPTMR_CSR_TMS_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 2187 | #define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK) |
mbed_official | 121:7f86b4238bec | 2188 | #define LPTMR_CSR_TFC_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 2189 | #define LPTMR_CSR_TFC_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 2190 | #define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK) |
mbed_official | 121:7f86b4238bec | 2191 | #define LPTMR_CSR_TPP_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 2192 | #define LPTMR_CSR_TPP_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 2193 | #define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK) |
mbed_official | 121:7f86b4238bec | 2194 | #define LPTMR_CSR_TPS_MASK (0x30U) |
mbed_official | 121:7f86b4238bec | 2195 | #define LPTMR_CSR_TPS_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 2196 | #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK) |
mbed_official | 121:7f86b4238bec | 2197 | #define LPTMR_CSR_TIE_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 2198 | #define LPTMR_CSR_TIE_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 2199 | #define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK) |
mbed_official | 121:7f86b4238bec | 2200 | #define LPTMR_CSR_TCF_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 2201 | #define LPTMR_CSR_TCF_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 2202 | #define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK) |
mbed_official | 121:7f86b4238bec | 2203 | |
mbed_official | 121:7f86b4238bec | 2204 | /*! @name PSR - Low Power Timer Prescale Register */ |
mbed_official | 121:7f86b4238bec | 2205 | #define LPTMR_PSR_PCS_MASK (0x3U) |
mbed_official | 121:7f86b4238bec | 2206 | #define LPTMR_PSR_PCS_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 2207 | #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK) |
mbed_official | 121:7f86b4238bec | 2208 | #define LPTMR_PSR_PBYP_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 2209 | #define LPTMR_PSR_PBYP_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 2210 | #define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK) |
mbed_official | 121:7f86b4238bec | 2211 | #define LPTMR_PSR_PRESCALE_MASK (0x78U) |
mbed_official | 121:7f86b4238bec | 2212 | #define LPTMR_PSR_PRESCALE_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 2213 | #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK) |
mbed_official | 121:7f86b4238bec | 2214 | |
mbed_official | 121:7f86b4238bec | 2215 | /*! @name CMR - Low Power Timer Compare Register */ |
mbed_official | 121:7f86b4238bec | 2216 | #define LPTMR_CMR_COMPARE_MASK (0xFFFFU) |
mbed_official | 121:7f86b4238bec | 2217 | #define LPTMR_CMR_COMPARE_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 2218 | #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK) |
mbed_official | 121:7f86b4238bec | 2219 | |
mbed_official | 121:7f86b4238bec | 2220 | /*! @name CNR - Low Power Timer Counter Register */ |
mbed_official | 121:7f86b4238bec | 2221 | #define LPTMR_CNR_COUNTER_MASK (0xFFFFU) |
mbed_official | 121:7f86b4238bec | 2222 | #define LPTMR_CNR_COUNTER_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 2223 | #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK) |
mbed_official | 121:7f86b4238bec | 2224 | |
mbed_official | 121:7f86b4238bec | 2225 | |
mbed_official | 121:7f86b4238bec | 2226 | /*! |
mbed_official | 121:7f86b4238bec | 2227 | * @} |
mbed_official | 121:7f86b4238bec | 2228 | */ /* end of group LPTMR_Register_Masks */ |
mbed_official | 121:7f86b4238bec | 2229 | |
mbed_official | 121:7f86b4238bec | 2230 | |
mbed_official | 121:7f86b4238bec | 2231 | /* LPTMR - Peripheral instance base addresses */ |
mbed_official | 121:7f86b4238bec | 2232 | /** Peripheral LPTMR0 base address */ |
mbed_official | 121:7f86b4238bec | 2233 | #define LPTMR0_BASE (0x40040000u) |
mbed_official | 121:7f86b4238bec | 2234 | /** Peripheral LPTMR0 base pointer */ |
mbed_official | 121:7f86b4238bec | 2235 | #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) |
mbed_official | 121:7f86b4238bec | 2236 | /** Array initializer of LPTMR peripheral base addresses */ |
mbed_official | 121:7f86b4238bec | 2237 | #define LPTMR_BASE_ADDRS { LPTMR0_BASE } |
mbed_official | 121:7f86b4238bec | 2238 | /** Array initializer of LPTMR peripheral base pointers */ |
mbed_official | 121:7f86b4238bec | 2239 | #define LPTMR_BASE_PTRS { LPTMR0 } |
mbed_official | 121:7f86b4238bec | 2240 | /** Interrupt vectors for the LPTMR peripheral type */ |
mbed_official | 121:7f86b4238bec | 2241 | #define LPTMR_IRQS { LPTMR0_IRQn } |
mbed_official | 121:7f86b4238bec | 2242 | |
mbed_official | 121:7f86b4238bec | 2243 | /*! |
mbed_official | 121:7f86b4238bec | 2244 | * @} |
mbed_official | 121:7f86b4238bec | 2245 | */ /* end of group LPTMR_Peripheral_Access_Layer */ |
mbed_official | 121:7f86b4238bec | 2246 | |
mbed_official | 121:7f86b4238bec | 2247 | |
mbed_official | 121:7f86b4238bec | 2248 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 2249 | -- LPUART Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 2250 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 2251 | |
mbed_official | 121:7f86b4238bec | 2252 | /*! |
mbed_official | 121:7f86b4238bec | 2253 | * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 2254 | * @{ |
mbed_official | 121:7f86b4238bec | 2255 | */ |
mbed_official | 121:7f86b4238bec | 2256 | |
mbed_official | 121:7f86b4238bec | 2257 | /** LPUART - Register Layout Typedef */ |
mbed_official | 121:7f86b4238bec | 2258 | typedef struct { |
mbed_official | 121:7f86b4238bec | 2259 | __IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x0 */ |
mbed_official | 121:7f86b4238bec | 2260 | __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x4 */ |
mbed_official | 121:7f86b4238bec | 2261 | __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x8 */ |
mbed_official | 121:7f86b4238bec | 2262 | __IO uint32_t DATA; /**< LPUART Data Register, offset: 0xC */ |
mbed_official | 121:7f86b4238bec | 2263 | __IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x10 */ |
mbed_official | 121:7f86b4238bec | 2264 | } LPUART_Type; |
mbed_official | 121:7f86b4238bec | 2265 | |
mbed_official | 121:7f86b4238bec | 2266 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 2267 | -- LPUART Register Masks |
mbed_official | 121:7f86b4238bec | 2268 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 2269 | |
mbed_official | 121:7f86b4238bec | 2270 | /*! |
mbed_official | 121:7f86b4238bec | 2271 | * @addtogroup LPUART_Register_Masks LPUART Register Masks |
mbed_official | 121:7f86b4238bec | 2272 | * @{ |
mbed_official | 121:7f86b4238bec | 2273 | */ |
mbed_official | 121:7f86b4238bec | 2274 | |
mbed_official | 121:7f86b4238bec | 2275 | /*! @name BAUD - LPUART Baud Rate Register */ |
mbed_official | 121:7f86b4238bec | 2276 | #define LPUART_BAUD_SBR_MASK (0x1FFFU) |
mbed_official | 121:7f86b4238bec | 2277 | #define LPUART_BAUD_SBR_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 2278 | #define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK) |
mbed_official | 121:7f86b4238bec | 2279 | #define LPUART_BAUD_SBNS_MASK (0x2000U) |
mbed_official | 121:7f86b4238bec | 2280 | #define LPUART_BAUD_SBNS_SHIFT (13U) |
mbed_official | 121:7f86b4238bec | 2281 | #define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK) |
mbed_official | 121:7f86b4238bec | 2282 | #define LPUART_BAUD_RXEDGIE_MASK (0x4000U) |
mbed_official | 121:7f86b4238bec | 2283 | #define LPUART_BAUD_RXEDGIE_SHIFT (14U) |
mbed_official | 121:7f86b4238bec | 2284 | #define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK) |
mbed_official | 121:7f86b4238bec | 2285 | #define LPUART_BAUD_LBKDIE_MASK (0x8000U) |
mbed_official | 121:7f86b4238bec | 2286 | #define LPUART_BAUD_LBKDIE_SHIFT (15U) |
mbed_official | 121:7f86b4238bec | 2287 | #define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK) |
mbed_official | 121:7f86b4238bec | 2288 | #define LPUART_BAUD_RESYNCDIS_MASK (0x10000U) |
mbed_official | 121:7f86b4238bec | 2289 | #define LPUART_BAUD_RESYNCDIS_SHIFT (16U) |
mbed_official | 121:7f86b4238bec | 2290 | #define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK) |
mbed_official | 121:7f86b4238bec | 2291 | #define LPUART_BAUD_BOTHEDGE_MASK (0x20000U) |
mbed_official | 121:7f86b4238bec | 2292 | #define LPUART_BAUD_BOTHEDGE_SHIFT (17U) |
mbed_official | 121:7f86b4238bec | 2293 | #define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK) |
mbed_official | 121:7f86b4238bec | 2294 | #define LPUART_BAUD_MATCFG_MASK (0xC0000U) |
mbed_official | 121:7f86b4238bec | 2295 | #define LPUART_BAUD_MATCFG_SHIFT (18U) |
mbed_official | 121:7f86b4238bec | 2296 | #define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK) |
mbed_official | 121:7f86b4238bec | 2297 | #define LPUART_BAUD_RDMAE_MASK (0x200000U) |
mbed_official | 121:7f86b4238bec | 2298 | #define LPUART_BAUD_RDMAE_SHIFT (21U) |
mbed_official | 121:7f86b4238bec | 2299 | #define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK) |
mbed_official | 121:7f86b4238bec | 2300 | #define LPUART_BAUD_TDMAE_MASK (0x800000U) |
mbed_official | 121:7f86b4238bec | 2301 | #define LPUART_BAUD_TDMAE_SHIFT (23U) |
mbed_official | 121:7f86b4238bec | 2302 | #define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK) |
mbed_official | 121:7f86b4238bec | 2303 | #define LPUART_BAUD_OSR_MASK (0x1F000000U) |
mbed_official | 121:7f86b4238bec | 2304 | #define LPUART_BAUD_OSR_SHIFT (24U) |
mbed_official | 121:7f86b4238bec | 2305 | #define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK) |
mbed_official | 121:7f86b4238bec | 2306 | #define LPUART_BAUD_M10_MASK (0x20000000U) |
mbed_official | 121:7f86b4238bec | 2307 | #define LPUART_BAUD_M10_SHIFT (29U) |
mbed_official | 121:7f86b4238bec | 2308 | #define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK) |
mbed_official | 121:7f86b4238bec | 2309 | #define LPUART_BAUD_MAEN2_MASK (0x40000000U) |
mbed_official | 121:7f86b4238bec | 2310 | #define LPUART_BAUD_MAEN2_SHIFT (30U) |
mbed_official | 121:7f86b4238bec | 2311 | #define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK) |
mbed_official | 121:7f86b4238bec | 2312 | #define LPUART_BAUD_MAEN1_MASK (0x80000000U) |
mbed_official | 121:7f86b4238bec | 2313 | #define LPUART_BAUD_MAEN1_SHIFT (31U) |
mbed_official | 121:7f86b4238bec | 2314 | #define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK) |
mbed_official | 121:7f86b4238bec | 2315 | |
mbed_official | 121:7f86b4238bec | 2316 | /*! @name STAT - LPUART Status Register */ |
mbed_official | 121:7f86b4238bec | 2317 | #define LPUART_STAT_MA2F_MASK (0x4000U) |
mbed_official | 121:7f86b4238bec | 2318 | #define LPUART_STAT_MA2F_SHIFT (14U) |
mbed_official | 121:7f86b4238bec | 2319 | #define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK) |
mbed_official | 121:7f86b4238bec | 2320 | #define LPUART_STAT_MA1F_MASK (0x8000U) |
mbed_official | 121:7f86b4238bec | 2321 | #define LPUART_STAT_MA1F_SHIFT (15U) |
mbed_official | 121:7f86b4238bec | 2322 | #define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK) |
mbed_official | 121:7f86b4238bec | 2323 | #define LPUART_STAT_PF_MASK (0x10000U) |
mbed_official | 121:7f86b4238bec | 2324 | #define LPUART_STAT_PF_SHIFT (16U) |
mbed_official | 121:7f86b4238bec | 2325 | #define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK) |
mbed_official | 121:7f86b4238bec | 2326 | #define LPUART_STAT_FE_MASK (0x20000U) |
mbed_official | 121:7f86b4238bec | 2327 | #define LPUART_STAT_FE_SHIFT (17U) |
mbed_official | 121:7f86b4238bec | 2328 | #define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK) |
mbed_official | 121:7f86b4238bec | 2329 | #define LPUART_STAT_NF_MASK (0x40000U) |
mbed_official | 121:7f86b4238bec | 2330 | #define LPUART_STAT_NF_SHIFT (18U) |
mbed_official | 121:7f86b4238bec | 2331 | #define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK) |
mbed_official | 121:7f86b4238bec | 2332 | #define LPUART_STAT_OR_MASK (0x80000U) |
mbed_official | 121:7f86b4238bec | 2333 | #define LPUART_STAT_OR_SHIFT (19U) |
mbed_official | 121:7f86b4238bec | 2334 | #define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK) |
mbed_official | 121:7f86b4238bec | 2335 | #define LPUART_STAT_IDLE_MASK (0x100000U) |
mbed_official | 121:7f86b4238bec | 2336 | #define LPUART_STAT_IDLE_SHIFT (20U) |
mbed_official | 121:7f86b4238bec | 2337 | #define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK) |
mbed_official | 121:7f86b4238bec | 2338 | #define LPUART_STAT_RDRF_MASK (0x200000U) |
mbed_official | 121:7f86b4238bec | 2339 | #define LPUART_STAT_RDRF_SHIFT (21U) |
mbed_official | 121:7f86b4238bec | 2340 | #define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK) |
mbed_official | 121:7f86b4238bec | 2341 | #define LPUART_STAT_TC_MASK (0x400000U) |
mbed_official | 121:7f86b4238bec | 2342 | #define LPUART_STAT_TC_SHIFT (22U) |
mbed_official | 121:7f86b4238bec | 2343 | #define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK) |
mbed_official | 121:7f86b4238bec | 2344 | #define LPUART_STAT_TDRE_MASK (0x800000U) |
mbed_official | 121:7f86b4238bec | 2345 | #define LPUART_STAT_TDRE_SHIFT (23U) |
mbed_official | 121:7f86b4238bec | 2346 | #define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK) |
mbed_official | 121:7f86b4238bec | 2347 | #define LPUART_STAT_RAF_MASK (0x1000000U) |
mbed_official | 121:7f86b4238bec | 2348 | #define LPUART_STAT_RAF_SHIFT (24U) |
mbed_official | 121:7f86b4238bec | 2349 | #define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK) |
mbed_official | 121:7f86b4238bec | 2350 | #define LPUART_STAT_LBKDE_MASK (0x2000000U) |
mbed_official | 121:7f86b4238bec | 2351 | #define LPUART_STAT_LBKDE_SHIFT (25U) |
mbed_official | 121:7f86b4238bec | 2352 | #define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK) |
mbed_official | 121:7f86b4238bec | 2353 | #define LPUART_STAT_BRK13_MASK (0x4000000U) |
mbed_official | 121:7f86b4238bec | 2354 | #define LPUART_STAT_BRK13_SHIFT (26U) |
mbed_official | 121:7f86b4238bec | 2355 | #define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK) |
mbed_official | 121:7f86b4238bec | 2356 | #define LPUART_STAT_RWUID_MASK (0x8000000U) |
mbed_official | 121:7f86b4238bec | 2357 | #define LPUART_STAT_RWUID_SHIFT (27U) |
mbed_official | 121:7f86b4238bec | 2358 | #define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK) |
mbed_official | 121:7f86b4238bec | 2359 | #define LPUART_STAT_RXINV_MASK (0x10000000U) |
mbed_official | 121:7f86b4238bec | 2360 | #define LPUART_STAT_RXINV_SHIFT (28U) |
mbed_official | 121:7f86b4238bec | 2361 | #define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK) |
mbed_official | 121:7f86b4238bec | 2362 | #define LPUART_STAT_MSBF_MASK (0x20000000U) |
mbed_official | 121:7f86b4238bec | 2363 | #define LPUART_STAT_MSBF_SHIFT (29U) |
mbed_official | 121:7f86b4238bec | 2364 | #define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK) |
mbed_official | 121:7f86b4238bec | 2365 | #define LPUART_STAT_RXEDGIF_MASK (0x40000000U) |
mbed_official | 121:7f86b4238bec | 2366 | #define LPUART_STAT_RXEDGIF_SHIFT (30U) |
mbed_official | 121:7f86b4238bec | 2367 | #define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK) |
mbed_official | 121:7f86b4238bec | 2368 | #define LPUART_STAT_LBKDIF_MASK (0x80000000U) |
mbed_official | 121:7f86b4238bec | 2369 | #define LPUART_STAT_LBKDIF_SHIFT (31U) |
mbed_official | 121:7f86b4238bec | 2370 | #define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK) |
mbed_official | 121:7f86b4238bec | 2371 | |
mbed_official | 121:7f86b4238bec | 2372 | /*! @name CTRL - LPUART Control Register */ |
mbed_official | 121:7f86b4238bec | 2373 | #define LPUART_CTRL_PT_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 2374 | #define LPUART_CTRL_PT_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 2375 | #define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK) |
mbed_official | 121:7f86b4238bec | 2376 | #define LPUART_CTRL_PE_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 2377 | #define LPUART_CTRL_PE_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 2378 | #define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK) |
mbed_official | 121:7f86b4238bec | 2379 | #define LPUART_CTRL_ILT_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 2380 | #define LPUART_CTRL_ILT_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 2381 | #define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK) |
mbed_official | 121:7f86b4238bec | 2382 | #define LPUART_CTRL_WAKE_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 2383 | #define LPUART_CTRL_WAKE_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 2384 | #define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK) |
mbed_official | 121:7f86b4238bec | 2385 | #define LPUART_CTRL_M_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 2386 | #define LPUART_CTRL_M_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 2387 | #define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK) |
mbed_official | 121:7f86b4238bec | 2388 | #define LPUART_CTRL_RSRC_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 2389 | #define LPUART_CTRL_RSRC_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 2390 | #define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK) |
mbed_official | 121:7f86b4238bec | 2391 | #define LPUART_CTRL_DOZEEN_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 2392 | #define LPUART_CTRL_DOZEEN_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 2393 | #define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK) |
mbed_official | 121:7f86b4238bec | 2394 | #define LPUART_CTRL_LOOPS_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 2395 | #define LPUART_CTRL_LOOPS_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 2396 | #define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK) |
mbed_official | 121:7f86b4238bec | 2397 | #define LPUART_CTRL_IDLECFG_MASK (0x700U) |
mbed_official | 121:7f86b4238bec | 2398 | #define LPUART_CTRL_IDLECFG_SHIFT (8U) |
mbed_official | 121:7f86b4238bec | 2399 | #define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK) |
mbed_official | 121:7f86b4238bec | 2400 | #define LPUART_CTRL_MA2IE_MASK (0x4000U) |
mbed_official | 121:7f86b4238bec | 2401 | #define LPUART_CTRL_MA2IE_SHIFT (14U) |
mbed_official | 121:7f86b4238bec | 2402 | #define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK) |
mbed_official | 121:7f86b4238bec | 2403 | #define LPUART_CTRL_MA1IE_MASK (0x8000U) |
mbed_official | 121:7f86b4238bec | 2404 | #define LPUART_CTRL_MA1IE_SHIFT (15U) |
mbed_official | 121:7f86b4238bec | 2405 | #define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK) |
mbed_official | 121:7f86b4238bec | 2406 | #define LPUART_CTRL_SBK_MASK (0x10000U) |
mbed_official | 121:7f86b4238bec | 2407 | #define LPUART_CTRL_SBK_SHIFT (16U) |
mbed_official | 121:7f86b4238bec | 2408 | #define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK) |
mbed_official | 121:7f86b4238bec | 2409 | #define LPUART_CTRL_RWU_MASK (0x20000U) |
mbed_official | 121:7f86b4238bec | 2410 | #define LPUART_CTRL_RWU_SHIFT (17U) |
mbed_official | 121:7f86b4238bec | 2411 | #define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK) |
mbed_official | 121:7f86b4238bec | 2412 | #define LPUART_CTRL_RE_MASK (0x40000U) |
mbed_official | 121:7f86b4238bec | 2413 | #define LPUART_CTRL_RE_SHIFT (18U) |
mbed_official | 121:7f86b4238bec | 2414 | #define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK) |
mbed_official | 121:7f86b4238bec | 2415 | #define LPUART_CTRL_TE_MASK (0x80000U) |
mbed_official | 121:7f86b4238bec | 2416 | #define LPUART_CTRL_TE_SHIFT (19U) |
mbed_official | 121:7f86b4238bec | 2417 | #define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK) |
mbed_official | 121:7f86b4238bec | 2418 | #define LPUART_CTRL_ILIE_MASK (0x100000U) |
mbed_official | 121:7f86b4238bec | 2419 | #define LPUART_CTRL_ILIE_SHIFT (20U) |
mbed_official | 121:7f86b4238bec | 2420 | #define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK) |
mbed_official | 121:7f86b4238bec | 2421 | #define LPUART_CTRL_RIE_MASK (0x200000U) |
mbed_official | 121:7f86b4238bec | 2422 | #define LPUART_CTRL_RIE_SHIFT (21U) |
mbed_official | 121:7f86b4238bec | 2423 | #define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK) |
mbed_official | 121:7f86b4238bec | 2424 | #define LPUART_CTRL_TCIE_MASK (0x400000U) |
mbed_official | 121:7f86b4238bec | 2425 | #define LPUART_CTRL_TCIE_SHIFT (22U) |
mbed_official | 121:7f86b4238bec | 2426 | #define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK) |
mbed_official | 121:7f86b4238bec | 2427 | #define LPUART_CTRL_TIE_MASK (0x800000U) |
mbed_official | 121:7f86b4238bec | 2428 | #define LPUART_CTRL_TIE_SHIFT (23U) |
mbed_official | 121:7f86b4238bec | 2429 | #define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK) |
mbed_official | 121:7f86b4238bec | 2430 | #define LPUART_CTRL_PEIE_MASK (0x1000000U) |
mbed_official | 121:7f86b4238bec | 2431 | #define LPUART_CTRL_PEIE_SHIFT (24U) |
mbed_official | 121:7f86b4238bec | 2432 | #define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK) |
mbed_official | 121:7f86b4238bec | 2433 | #define LPUART_CTRL_FEIE_MASK (0x2000000U) |
mbed_official | 121:7f86b4238bec | 2434 | #define LPUART_CTRL_FEIE_SHIFT (25U) |
mbed_official | 121:7f86b4238bec | 2435 | #define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK) |
mbed_official | 121:7f86b4238bec | 2436 | #define LPUART_CTRL_NEIE_MASK (0x4000000U) |
mbed_official | 121:7f86b4238bec | 2437 | #define LPUART_CTRL_NEIE_SHIFT (26U) |
mbed_official | 121:7f86b4238bec | 2438 | #define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK) |
mbed_official | 121:7f86b4238bec | 2439 | #define LPUART_CTRL_ORIE_MASK (0x8000000U) |
mbed_official | 121:7f86b4238bec | 2440 | #define LPUART_CTRL_ORIE_SHIFT (27U) |
mbed_official | 121:7f86b4238bec | 2441 | #define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK) |
mbed_official | 121:7f86b4238bec | 2442 | #define LPUART_CTRL_TXINV_MASK (0x10000000U) |
mbed_official | 121:7f86b4238bec | 2443 | #define LPUART_CTRL_TXINV_SHIFT (28U) |
mbed_official | 121:7f86b4238bec | 2444 | #define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK) |
mbed_official | 121:7f86b4238bec | 2445 | #define LPUART_CTRL_TXDIR_MASK (0x20000000U) |
mbed_official | 121:7f86b4238bec | 2446 | #define LPUART_CTRL_TXDIR_SHIFT (29U) |
mbed_official | 121:7f86b4238bec | 2447 | #define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK) |
mbed_official | 121:7f86b4238bec | 2448 | #define LPUART_CTRL_R9T8_MASK (0x40000000U) |
mbed_official | 121:7f86b4238bec | 2449 | #define LPUART_CTRL_R9T8_SHIFT (30U) |
mbed_official | 121:7f86b4238bec | 2450 | #define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK) |
mbed_official | 121:7f86b4238bec | 2451 | #define LPUART_CTRL_R8T9_MASK (0x80000000U) |
mbed_official | 121:7f86b4238bec | 2452 | #define LPUART_CTRL_R8T9_SHIFT (31U) |
mbed_official | 121:7f86b4238bec | 2453 | #define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK) |
mbed_official | 121:7f86b4238bec | 2454 | |
mbed_official | 121:7f86b4238bec | 2455 | /*! @name DATA - LPUART Data Register */ |
mbed_official | 121:7f86b4238bec | 2456 | #define LPUART_DATA_R0T0_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 2457 | #define LPUART_DATA_R0T0_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 2458 | #define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK) |
mbed_official | 121:7f86b4238bec | 2459 | #define LPUART_DATA_R1T1_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 2460 | #define LPUART_DATA_R1T1_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 2461 | #define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK) |
mbed_official | 121:7f86b4238bec | 2462 | #define LPUART_DATA_R2T2_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 2463 | #define LPUART_DATA_R2T2_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 2464 | #define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK) |
mbed_official | 121:7f86b4238bec | 2465 | #define LPUART_DATA_R3T3_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 2466 | #define LPUART_DATA_R3T3_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 2467 | #define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK) |
mbed_official | 121:7f86b4238bec | 2468 | #define LPUART_DATA_R4T4_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 2469 | #define LPUART_DATA_R4T4_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 2470 | #define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK) |
mbed_official | 121:7f86b4238bec | 2471 | #define LPUART_DATA_R5T5_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 2472 | #define LPUART_DATA_R5T5_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 2473 | #define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK) |
mbed_official | 121:7f86b4238bec | 2474 | #define LPUART_DATA_R6T6_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 2475 | #define LPUART_DATA_R6T6_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 2476 | #define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK) |
mbed_official | 121:7f86b4238bec | 2477 | #define LPUART_DATA_R7T7_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 2478 | #define LPUART_DATA_R7T7_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 2479 | #define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK) |
mbed_official | 121:7f86b4238bec | 2480 | #define LPUART_DATA_R8T8_MASK (0x100U) |
mbed_official | 121:7f86b4238bec | 2481 | #define LPUART_DATA_R8T8_SHIFT (8U) |
mbed_official | 121:7f86b4238bec | 2482 | #define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK) |
mbed_official | 121:7f86b4238bec | 2483 | #define LPUART_DATA_R9T9_MASK (0x200U) |
mbed_official | 121:7f86b4238bec | 2484 | #define LPUART_DATA_R9T9_SHIFT (9U) |
mbed_official | 121:7f86b4238bec | 2485 | #define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK) |
mbed_official | 121:7f86b4238bec | 2486 | #define LPUART_DATA_IDLINE_MASK (0x800U) |
mbed_official | 121:7f86b4238bec | 2487 | #define LPUART_DATA_IDLINE_SHIFT (11U) |
mbed_official | 121:7f86b4238bec | 2488 | #define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK) |
mbed_official | 121:7f86b4238bec | 2489 | #define LPUART_DATA_RXEMPT_MASK (0x1000U) |
mbed_official | 121:7f86b4238bec | 2490 | #define LPUART_DATA_RXEMPT_SHIFT (12U) |
mbed_official | 121:7f86b4238bec | 2491 | #define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK) |
mbed_official | 121:7f86b4238bec | 2492 | #define LPUART_DATA_FRETSC_MASK (0x2000U) |
mbed_official | 121:7f86b4238bec | 2493 | #define LPUART_DATA_FRETSC_SHIFT (13U) |
mbed_official | 121:7f86b4238bec | 2494 | #define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK) |
mbed_official | 121:7f86b4238bec | 2495 | #define LPUART_DATA_PARITYE_MASK (0x4000U) |
mbed_official | 121:7f86b4238bec | 2496 | #define LPUART_DATA_PARITYE_SHIFT (14U) |
mbed_official | 121:7f86b4238bec | 2497 | #define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK) |
mbed_official | 121:7f86b4238bec | 2498 | #define LPUART_DATA_NOISY_MASK (0x8000U) |
mbed_official | 121:7f86b4238bec | 2499 | #define LPUART_DATA_NOISY_SHIFT (15U) |
mbed_official | 121:7f86b4238bec | 2500 | #define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK) |
mbed_official | 121:7f86b4238bec | 2501 | |
mbed_official | 121:7f86b4238bec | 2502 | /*! @name MATCH - LPUART Match Address Register */ |
mbed_official | 121:7f86b4238bec | 2503 | #define LPUART_MATCH_MA1_MASK (0x3FFU) |
mbed_official | 121:7f86b4238bec | 2504 | #define LPUART_MATCH_MA1_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 2505 | #define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK) |
mbed_official | 121:7f86b4238bec | 2506 | #define LPUART_MATCH_MA2_MASK (0x3FF0000U) |
mbed_official | 121:7f86b4238bec | 2507 | #define LPUART_MATCH_MA2_SHIFT (16U) |
mbed_official | 121:7f86b4238bec | 2508 | #define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK) |
mbed_official | 121:7f86b4238bec | 2509 | |
mbed_official | 121:7f86b4238bec | 2510 | |
mbed_official | 121:7f86b4238bec | 2511 | /*! |
mbed_official | 121:7f86b4238bec | 2512 | * @} |
mbed_official | 121:7f86b4238bec | 2513 | */ /* end of group LPUART_Register_Masks */ |
mbed_official | 121:7f86b4238bec | 2514 | |
mbed_official | 121:7f86b4238bec | 2515 | |
mbed_official | 121:7f86b4238bec | 2516 | /* LPUART - Peripheral instance base addresses */ |
mbed_official | 121:7f86b4238bec | 2517 | /** Peripheral LPUART0 base address */ |
mbed_official | 121:7f86b4238bec | 2518 | #define LPUART0_BASE (0x40054000u) |
mbed_official | 121:7f86b4238bec | 2519 | /** Peripheral LPUART0 base pointer */ |
mbed_official | 121:7f86b4238bec | 2520 | #define LPUART0 ((LPUART_Type *)LPUART0_BASE) |
mbed_official | 121:7f86b4238bec | 2521 | /** Peripheral LPUART1 base address */ |
mbed_official | 121:7f86b4238bec | 2522 | #define LPUART1_BASE (0x40055000u) |
mbed_official | 121:7f86b4238bec | 2523 | /** Peripheral LPUART1 base pointer */ |
mbed_official | 121:7f86b4238bec | 2524 | #define LPUART1 ((LPUART_Type *)LPUART1_BASE) |
mbed_official | 121:7f86b4238bec | 2525 | /** Array initializer of LPUART peripheral base addresses */ |
mbed_official | 121:7f86b4238bec | 2526 | #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE } |
mbed_official | 121:7f86b4238bec | 2527 | /** Array initializer of LPUART peripheral base pointers */ |
mbed_official | 121:7f86b4238bec | 2528 | #define LPUART_BASE_PTRS { LPUART0, LPUART1 } |
mbed_official | 121:7f86b4238bec | 2529 | /** Interrupt vectors for the LPUART peripheral type */ |
mbed_official | 121:7f86b4238bec | 2530 | #define LPUART_RX_TX_IRQS { LPUART0_IRQn, LPUART1_IRQn } |
mbed_official | 121:7f86b4238bec | 2531 | #define LPUART_ERR_IRQS { LPUART0_IRQn, LPUART1_IRQn } |
mbed_official | 121:7f86b4238bec | 2532 | |
mbed_official | 121:7f86b4238bec | 2533 | /*! |
mbed_official | 121:7f86b4238bec | 2534 | * @} |
mbed_official | 121:7f86b4238bec | 2535 | */ /* end of group LPUART_Peripheral_Access_Layer */ |
mbed_official | 121:7f86b4238bec | 2536 | |
mbed_official | 121:7f86b4238bec | 2537 | |
mbed_official | 121:7f86b4238bec | 2538 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 2539 | -- MCG Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 2540 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 2541 | |
mbed_official | 121:7f86b4238bec | 2542 | /*! |
mbed_official | 121:7f86b4238bec | 2543 | * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 2544 | * @{ |
mbed_official | 121:7f86b4238bec | 2545 | */ |
mbed_official | 121:7f86b4238bec | 2546 | |
mbed_official | 121:7f86b4238bec | 2547 | /** MCG - Register Layout Typedef */ |
mbed_official | 121:7f86b4238bec | 2548 | typedef struct { |
mbed_official | 121:7f86b4238bec | 2549 | __IO uint8_t C1; /**< MCG Control Register 1, offset: 0x0 */ |
mbed_official | 121:7f86b4238bec | 2550 | __IO uint8_t C2; /**< MCG Control Register 2, offset: 0x1 */ |
mbed_official | 121:7f86b4238bec | 2551 | uint8_t RESERVED_0[4]; |
mbed_official | 121:7f86b4238bec | 2552 | __I uint8_t S; /**< MCG Status Register, offset: 0x6 */ |
mbed_official | 121:7f86b4238bec | 2553 | uint8_t RESERVED_1[1]; |
mbed_official | 121:7f86b4238bec | 2554 | __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */ |
mbed_official | 121:7f86b4238bec | 2555 | uint8_t RESERVED_2[15]; |
mbed_official | 121:7f86b4238bec | 2556 | __IO uint8_t MC; /**< MCG Miscellaneous Control Register, offset: 0x18 */ |
mbed_official | 121:7f86b4238bec | 2557 | } MCG_Type; |
mbed_official | 121:7f86b4238bec | 2558 | |
mbed_official | 121:7f86b4238bec | 2559 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 2560 | -- MCG Register Masks |
mbed_official | 121:7f86b4238bec | 2561 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 2562 | |
mbed_official | 121:7f86b4238bec | 2563 | /*! |
mbed_official | 121:7f86b4238bec | 2564 | * @addtogroup MCG_Register_Masks MCG Register Masks |
mbed_official | 121:7f86b4238bec | 2565 | * @{ |
mbed_official | 121:7f86b4238bec | 2566 | */ |
mbed_official | 121:7f86b4238bec | 2567 | |
mbed_official | 121:7f86b4238bec | 2568 | /*! @name C1 - MCG Control Register 1 */ |
mbed_official | 121:7f86b4238bec | 2569 | #define MCG_C1_IREFSTEN_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 2570 | #define MCG_C1_IREFSTEN_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 2571 | #define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK) |
mbed_official | 121:7f86b4238bec | 2572 | #define MCG_C1_IRCLKEN_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 2573 | #define MCG_C1_IRCLKEN_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 2574 | #define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK) |
mbed_official | 121:7f86b4238bec | 2575 | #define MCG_C1_CLKS_MASK (0xC0U) |
mbed_official | 121:7f86b4238bec | 2576 | #define MCG_C1_CLKS_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 2577 | #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK) |
mbed_official | 121:7f86b4238bec | 2578 | |
mbed_official | 121:7f86b4238bec | 2579 | /*! @name C2 - MCG Control Register 2 */ |
mbed_official | 121:7f86b4238bec | 2580 | #define MCG_C2_IRCS_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 2581 | #define MCG_C2_IRCS_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 2582 | #define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK) |
mbed_official | 121:7f86b4238bec | 2583 | #define MCG_C2_EREFS0_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 2584 | #define MCG_C2_EREFS0_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 2585 | #define MCG_C2_EREFS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS0_SHIFT)) & MCG_C2_EREFS0_MASK) |
mbed_official | 121:7f86b4238bec | 2586 | #define MCG_C2_HGO0_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 2587 | #define MCG_C2_HGO0_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 2588 | #define MCG_C2_HGO0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO0_SHIFT)) & MCG_C2_HGO0_MASK) |
mbed_official | 121:7f86b4238bec | 2589 | #define MCG_C2_RANGE0_MASK (0x30U) |
mbed_official | 121:7f86b4238bec | 2590 | #define MCG_C2_RANGE0_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 2591 | #define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE0_SHIFT)) & MCG_C2_RANGE0_MASK) |
mbed_official | 121:7f86b4238bec | 2592 | |
mbed_official | 121:7f86b4238bec | 2593 | /*! @name S - MCG Status Register */ |
mbed_official | 121:7f86b4238bec | 2594 | #define MCG_S_OSCINIT0_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 2595 | #define MCG_S_OSCINIT0_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 2596 | #define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK) |
mbed_official | 121:7f86b4238bec | 2597 | #define MCG_S_CLKST_MASK (0xCU) |
mbed_official | 121:7f86b4238bec | 2598 | #define MCG_S_CLKST_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 2599 | #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK) |
mbed_official | 121:7f86b4238bec | 2600 | |
mbed_official | 121:7f86b4238bec | 2601 | /*! @name SC - MCG Status and Control Register */ |
mbed_official | 121:7f86b4238bec | 2602 | #define MCG_SC_FCRDIV_MASK (0xEU) |
mbed_official | 121:7f86b4238bec | 2603 | #define MCG_SC_FCRDIV_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 2604 | #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK) |
mbed_official | 121:7f86b4238bec | 2605 | |
mbed_official | 121:7f86b4238bec | 2606 | /*! @name MC - MCG Miscellaneous Control Register */ |
mbed_official | 121:7f86b4238bec | 2607 | #define MCG_MC_LIRC_DIV2_MASK (0x7U) |
mbed_official | 121:7f86b4238bec | 2608 | #define MCG_MC_LIRC_DIV2_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 2609 | #define MCG_MC_LIRC_DIV2(x) (((uint8_t)(((uint8_t)(x)) << MCG_MC_LIRC_DIV2_SHIFT)) & MCG_MC_LIRC_DIV2_MASK) |
mbed_official | 121:7f86b4238bec | 2610 | #define MCG_MC_HIRCLPEN_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 2611 | #define MCG_MC_HIRCLPEN_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 2612 | #define MCG_MC_HIRCLPEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_MC_HIRCLPEN_SHIFT)) & MCG_MC_HIRCLPEN_MASK) |
mbed_official | 121:7f86b4238bec | 2613 | #define MCG_MC_HIRCEN_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 2614 | #define MCG_MC_HIRCEN_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 2615 | #define MCG_MC_HIRCEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_MC_HIRCEN_SHIFT)) & MCG_MC_HIRCEN_MASK) |
mbed_official | 121:7f86b4238bec | 2616 | |
mbed_official | 121:7f86b4238bec | 2617 | |
mbed_official | 121:7f86b4238bec | 2618 | /*! |
mbed_official | 121:7f86b4238bec | 2619 | * @} |
mbed_official | 121:7f86b4238bec | 2620 | */ /* end of group MCG_Register_Masks */ |
mbed_official | 121:7f86b4238bec | 2621 | |
mbed_official | 121:7f86b4238bec | 2622 | |
mbed_official | 121:7f86b4238bec | 2623 | /* MCG - Peripheral instance base addresses */ |
mbed_official | 121:7f86b4238bec | 2624 | /** Peripheral MCG base address */ |
mbed_official | 121:7f86b4238bec | 2625 | #define MCG_BASE (0x40064000u) |
mbed_official | 121:7f86b4238bec | 2626 | /** Peripheral MCG base pointer */ |
mbed_official | 121:7f86b4238bec | 2627 | #define MCG ((MCG_Type *)MCG_BASE) |
mbed_official | 121:7f86b4238bec | 2628 | /** Array initializer of MCG peripheral base addresses */ |
mbed_official | 121:7f86b4238bec | 2629 | #define MCG_BASE_ADDRS { MCG_BASE } |
mbed_official | 121:7f86b4238bec | 2630 | /** Array initializer of MCG peripheral base pointers */ |
mbed_official | 121:7f86b4238bec | 2631 | #define MCG_BASE_PTRS { MCG } |
mbed_official | 121:7f86b4238bec | 2632 | |
mbed_official | 121:7f86b4238bec | 2633 | /*! |
mbed_official | 121:7f86b4238bec | 2634 | * @} |
mbed_official | 121:7f86b4238bec | 2635 | */ /* end of group MCG_Peripheral_Access_Layer */ |
mbed_official | 121:7f86b4238bec | 2636 | |
mbed_official | 121:7f86b4238bec | 2637 | |
mbed_official | 121:7f86b4238bec | 2638 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 2639 | -- MCM Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 2640 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 2641 | |
mbed_official | 121:7f86b4238bec | 2642 | /*! |
mbed_official | 121:7f86b4238bec | 2643 | * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 2644 | * @{ |
mbed_official | 121:7f86b4238bec | 2645 | */ |
mbed_official | 121:7f86b4238bec | 2646 | |
mbed_official | 121:7f86b4238bec | 2647 | /** MCM - Register Layout Typedef */ |
mbed_official | 121:7f86b4238bec | 2648 | typedef struct { |
mbed_official | 121:7f86b4238bec | 2649 | uint8_t RESERVED_0[8]; |
mbed_official | 121:7f86b4238bec | 2650 | __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */ |
mbed_official | 121:7f86b4238bec | 2651 | __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */ |
mbed_official | 121:7f86b4238bec | 2652 | __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */ |
mbed_official | 121:7f86b4238bec | 2653 | uint8_t RESERVED_1[48]; |
mbed_official | 121:7f86b4238bec | 2654 | __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */ |
mbed_official | 121:7f86b4238bec | 2655 | } MCM_Type; |
mbed_official | 121:7f86b4238bec | 2656 | |
mbed_official | 121:7f86b4238bec | 2657 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 2658 | -- MCM Register Masks |
mbed_official | 121:7f86b4238bec | 2659 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 2660 | |
mbed_official | 121:7f86b4238bec | 2661 | /*! |
mbed_official | 121:7f86b4238bec | 2662 | * @addtogroup MCM_Register_Masks MCM Register Masks |
mbed_official | 121:7f86b4238bec | 2663 | * @{ |
mbed_official | 121:7f86b4238bec | 2664 | */ |
mbed_official | 121:7f86b4238bec | 2665 | |
mbed_official | 121:7f86b4238bec | 2666 | /*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */ |
mbed_official | 121:7f86b4238bec | 2667 | #define MCM_PLASC_ASC_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 2668 | #define MCM_PLASC_ASC_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 2669 | #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK) |
mbed_official | 121:7f86b4238bec | 2670 | |
mbed_official | 121:7f86b4238bec | 2671 | /*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */ |
mbed_official | 121:7f86b4238bec | 2672 | #define MCM_PLAMC_AMC_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 2673 | #define MCM_PLAMC_AMC_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 2674 | #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK) |
mbed_official | 121:7f86b4238bec | 2675 | |
mbed_official | 121:7f86b4238bec | 2676 | /*! @name PLACR - Platform Control Register */ |
mbed_official | 121:7f86b4238bec | 2677 | #define MCM_PLACR_ARB_MASK (0x200U) |
mbed_official | 121:7f86b4238bec | 2678 | #define MCM_PLACR_ARB_SHIFT (9U) |
mbed_official | 121:7f86b4238bec | 2679 | #define MCM_PLACR_ARB(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ARB_SHIFT)) & MCM_PLACR_ARB_MASK) |
mbed_official | 121:7f86b4238bec | 2680 | #define MCM_PLACR_CFCC_MASK (0x400U) |
mbed_official | 121:7f86b4238bec | 2681 | #define MCM_PLACR_CFCC_SHIFT (10U) |
mbed_official | 121:7f86b4238bec | 2682 | #define MCM_PLACR_CFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_CFCC_SHIFT)) & MCM_PLACR_CFCC_MASK) |
mbed_official | 121:7f86b4238bec | 2683 | #define MCM_PLACR_DFCDA_MASK (0x800U) |
mbed_official | 121:7f86b4238bec | 2684 | #define MCM_PLACR_DFCDA_SHIFT (11U) |
mbed_official | 121:7f86b4238bec | 2685 | #define MCM_PLACR_DFCDA(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCDA_SHIFT)) & MCM_PLACR_DFCDA_MASK) |
mbed_official | 121:7f86b4238bec | 2686 | #define MCM_PLACR_DFCIC_MASK (0x1000U) |
mbed_official | 121:7f86b4238bec | 2687 | #define MCM_PLACR_DFCIC_SHIFT (12U) |
mbed_official | 121:7f86b4238bec | 2688 | #define MCM_PLACR_DFCIC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCIC_SHIFT)) & MCM_PLACR_DFCIC_MASK) |
mbed_official | 121:7f86b4238bec | 2689 | #define MCM_PLACR_DFCC_MASK (0x2000U) |
mbed_official | 121:7f86b4238bec | 2690 | #define MCM_PLACR_DFCC_SHIFT (13U) |
mbed_official | 121:7f86b4238bec | 2691 | #define MCM_PLACR_DFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCC_SHIFT)) & MCM_PLACR_DFCC_MASK) |
mbed_official | 121:7f86b4238bec | 2692 | #define MCM_PLACR_EFDS_MASK (0x4000U) |
mbed_official | 121:7f86b4238bec | 2693 | #define MCM_PLACR_EFDS_SHIFT (14U) |
mbed_official | 121:7f86b4238bec | 2694 | #define MCM_PLACR_EFDS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_EFDS_SHIFT)) & MCM_PLACR_EFDS_MASK) |
mbed_official | 121:7f86b4238bec | 2695 | #define MCM_PLACR_DFCS_MASK (0x8000U) |
mbed_official | 121:7f86b4238bec | 2696 | #define MCM_PLACR_DFCS_SHIFT (15U) |
mbed_official | 121:7f86b4238bec | 2697 | #define MCM_PLACR_DFCS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCS_SHIFT)) & MCM_PLACR_DFCS_MASK) |
mbed_official | 121:7f86b4238bec | 2698 | #define MCM_PLACR_ESFC_MASK (0x10000U) |
mbed_official | 121:7f86b4238bec | 2699 | #define MCM_PLACR_ESFC_SHIFT (16U) |
mbed_official | 121:7f86b4238bec | 2700 | #define MCM_PLACR_ESFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ESFC_SHIFT)) & MCM_PLACR_ESFC_MASK) |
mbed_official | 121:7f86b4238bec | 2701 | |
mbed_official | 121:7f86b4238bec | 2702 | /*! @name CPO - Compute Operation Control Register */ |
mbed_official | 121:7f86b4238bec | 2703 | #define MCM_CPO_CPOREQ_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 2704 | #define MCM_CPO_CPOREQ_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 2705 | #define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK) |
mbed_official | 121:7f86b4238bec | 2706 | #define MCM_CPO_CPOACK_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 2707 | #define MCM_CPO_CPOACK_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 2708 | #define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK) |
mbed_official | 121:7f86b4238bec | 2709 | #define MCM_CPO_CPOWOI_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 2710 | #define MCM_CPO_CPOWOI_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 2711 | #define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK) |
mbed_official | 121:7f86b4238bec | 2712 | |
mbed_official | 121:7f86b4238bec | 2713 | |
mbed_official | 121:7f86b4238bec | 2714 | /*! |
mbed_official | 121:7f86b4238bec | 2715 | * @} |
mbed_official | 121:7f86b4238bec | 2716 | */ /* end of group MCM_Register_Masks */ |
mbed_official | 121:7f86b4238bec | 2717 | |
mbed_official | 121:7f86b4238bec | 2718 | |
mbed_official | 121:7f86b4238bec | 2719 | /* MCM - Peripheral instance base addresses */ |
mbed_official | 121:7f86b4238bec | 2720 | /** Peripheral MCM base address */ |
mbed_official | 121:7f86b4238bec | 2721 | #define MCM_BASE (0xF0003000u) |
mbed_official | 121:7f86b4238bec | 2722 | /** Peripheral MCM base pointer */ |
mbed_official | 121:7f86b4238bec | 2723 | #define MCM ((MCM_Type *)MCM_BASE) |
mbed_official | 121:7f86b4238bec | 2724 | /** Array initializer of MCM peripheral base addresses */ |
mbed_official | 121:7f86b4238bec | 2725 | #define MCM_BASE_ADDRS { MCM_BASE } |
mbed_official | 121:7f86b4238bec | 2726 | /** Array initializer of MCM peripheral base pointers */ |
mbed_official | 121:7f86b4238bec | 2727 | #define MCM_BASE_PTRS { MCM } |
mbed_official | 121:7f86b4238bec | 2728 | |
mbed_official | 121:7f86b4238bec | 2729 | /*! |
mbed_official | 121:7f86b4238bec | 2730 | * @} |
mbed_official | 121:7f86b4238bec | 2731 | */ /* end of group MCM_Peripheral_Access_Layer */ |
mbed_official | 121:7f86b4238bec | 2732 | |
mbed_official | 121:7f86b4238bec | 2733 | |
mbed_official | 121:7f86b4238bec | 2734 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 2735 | -- MTB Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 2736 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 2737 | |
mbed_official | 121:7f86b4238bec | 2738 | /*! |
mbed_official | 121:7f86b4238bec | 2739 | * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 2740 | * @{ |
mbed_official | 121:7f86b4238bec | 2741 | */ |
mbed_official | 121:7f86b4238bec | 2742 | |
mbed_official | 121:7f86b4238bec | 2743 | /** MTB - Register Layout Typedef */ |
mbed_official | 121:7f86b4238bec | 2744 | typedef struct { |
mbed_official | 121:7f86b4238bec | 2745 | __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */ |
mbed_official | 121:7f86b4238bec | 2746 | __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */ |
mbed_official | 121:7f86b4238bec | 2747 | __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */ |
mbed_official | 121:7f86b4238bec | 2748 | __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */ |
mbed_official | 121:7f86b4238bec | 2749 | uint8_t RESERVED_0[3824]; |
mbed_official | 121:7f86b4238bec | 2750 | __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */ |
mbed_official | 121:7f86b4238bec | 2751 | uint8_t RESERVED_1[156]; |
mbed_official | 121:7f86b4238bec | 2752 | __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */ |
mbed_official | 121:7f86b4238bec | 2753 | __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */ |
mbed_official | 121:7f86b4238bec | 2754 | uint8_t RESERVED_2[8]; |
mbed_official | 121:7f86b4238bec | 2755 | __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */ |
mbed_official | 121:7f86b4238bec | 2756 | __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */ |
mbed_official | 121:7f86b4238bec | 2757 | __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */ |
mbed_official | 121:7f86b4238bec | 2758 | __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */ |
mbed_official | 121:7f86b4238bec | 2759 | uint8_t RESERVED_3[8]; |
mbed_official | 121:7f86b4238bec | 2760 | __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */ |
mbed_official | 121:7f86b4238bec | 2761 | __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */ |
mbed_official | 121:7f86b4238bec | 2762 | __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */ |
mbed_official | 121:7f86b4238bec | 2763 | __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ |
mbed_official | 121:7f86b4238bec | 2764 | } MTB_Type; |
mbed_official | 121:7f86b4238bec | 2765 | |
mbed_official | 121:7f86b4238bec | 2766 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 2767 | -- MTB Register Masks |
mbed_official | 121:7f86b4238bec | 2768 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 2769 | |
mbed_official | 121:7f86b4238bec | 2770 | /*! |
mbed_official | 121:7f86b4238bec | 2771 | * @addtogroup MTB_Register_Masks MTB Register Masks |
mbed_official | 121:7f86b4238bec | 2772 | * @{ |
mbed_official | 121:7f86b4238bec | 2773 | */ |
mbed_official | 121:7f86b4238bec | 2774 | |
mbed_official | 121:7f86b4238bec | 2775 | /*! @name POSITION - MTB Position Register */ |
mbed_official | 121:7f86b4238bec | 2776 | #define MTB_POSITION_WRAP_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 2777 | #define MTB_POSITION_WRAP_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 2778 | #define MTB_POSITION_WRAP(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_WRAP_SHIFT)) & MTB_POSITION_WRAP_MASK) |
mbed_official | 121:7f86b4238bec | 2779 | #define MTB_POSITION_POINTER_MASK (0xFFFFFFF8U) |
mbed_official | 121:7f86b4238bec | 2780 | #define MTB_POSITION_POINTER_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 2781 | #define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_POINTER_SHIFT)) & MTB_POSITION_POINTER_MASK) |
mbed_official | 121:7f86b4238bec | 2782 | |
mbed_official | 121:7f86b4238bec | 2783 | /*! @name MASTER - MTB Master Register */ |
mbed_official | 121:7f86b4238bec | 2784 | #define MTB_MASTER_MASK_MASK (0x1FU) |
mbed_official | 121:7f86b4238bec | 2785 | #define MTB_MASTER_MASK_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 2786 | #define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_MASK_SHIFT)) & MTB_MASTER_MASK_MASK) |
mbed_official | 121:7f86b4238bec | 2787 | #define MTB_MASTER_TSTARTEN_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 2788 | #define MTB_MASTER_TSTARTEN_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 2789 | #define MTB_MASTER_TSTARTEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTARTEN_SHIFT)) & MTB_MASTER_TSTARTEN_MASK) |
mbed_official | 121:7f86b4238bec | 2790 | #define MTB_MASTER_TSTOPEN_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 2791 | #define MTB_MASTER_TSTOPEN_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 2792 | #define MTB_MASTER_TSTOPEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTOPEN_SHIFT)) & MTB_MASTER_TSTOPEN_MASK) |
mbed_official | 121:7f86b4238bec | 2793 | #define MTB_MASTER_SFRWPRIV_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 2794 | #define MTB_MASTER_SFRWPRIV_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 2795 | #define MTB_MASTER_SFRWPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_SFRWPRIV_SHIFT)) & MTB_MASTER_SFRWPRIV_MASK) |
mbed_official | 121:7f86b4238bec | 2796 | #define MTB_MASTER_RAMPRIV_MASK (0x100U) |
mbed_official | 121:7f86b4238bec | 2797 | #define MTB_MASTER_RAMPRIV_SHIFT (8U) |
mbed_official | 121:7f86b4238bec | 2798 | #define MTB_MASTER_RAMPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_RAMPRIV_SHIFT)) & MTB_MASTER_RAMPRIV_MASK) |
mbed_official | 121:7f86b4238bec | 2799 | #define MTB_MASTER_HALTREQ_MASK (0x200U) |
mbed_official | 121:7f86b4238bec | 2800 | #define MTB_MASTER_HALTREQ_SHIFT (9U) |
mbed_official | 121:7f86b4238bec | 2801 | #define MTB_MASTER_HALTREQ(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_HALTREQ_SHIFT)) & MTB_MASTER_HALTREQ_MASK) |
mbed_official | 121:7f86b4238bec | 2802 | #define MTB_MASTER_EN_MASK (0x80000000U) |
mbed_official | 121:7f86b4238bec | 2803 | #define MTB_MASTER_EN_SHIFT (31U) |
mbed_official | 121:7f86b4238bec | 2804 | #define MTB_MASTER_EN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_EN_SHIFT)) & MTB_MASTER_EN_MASK) |
mbed_official | 121:7f86b4238bec | 2805 | |
mbed_official | 121:7f86b4238bec | 2806 | /*! @name FLOW - MTB Flow Register */ |
mbed_official | 121:7f86b4238bec | 2807 | #define MTB_FLOW_AUTOSTOP_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 2808 | #define MTB_FLOW_AUTOSTOP_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 2809 | #define MTB_FLOW_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOSTOP_SHIFT)) & MTB_FLOW_AUTOSTOP_MASK) |
mbed_official | 121:7f86b4238bec | 2810 | #define MTB_FLOW_AUTOHALT_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 2811 | #define MTB_FLOW_AUTOHALT_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 2812 | #define MTB_FLOW_AUTOHALT(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOHALT_SHIFT)) & MTB_FLOW_AUTOHALT_MASK) |
mbed_official | 121:7f86b4238bec | 2813 | #define MTB_FLOW_WATERMARK_MASK (0xFFFFFFF8U) |
mbed_official | 121:7f86b4238bec | 2814 | #define MTB_FLOW_WATERMARK_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 2815 | #define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_WATERMARK_SHIFT)) & MTB_FLOW_WATERMARK_MASK) |
mbed_official | 121:7f86b4238bec | 2816 | |
mbed_official | 121:7f86b4238bec | 2817 | /*! @name BASE - MTB Base Register */ |
mbed_official | 121:7f86b4238bec | 2818 | #define MTB_BASE_BASEADDR_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 2819 | #define MTB_BASE_BASEADDR_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 2820 | #define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x)) << MTB_BASE_BASEADDR_SHIFT)) & MTB_BASE_BASEADDR_MASK) |
mbed_official | 121:7f86b4238bec | 2821 | |
mbed_official | 121:7f86b4238bec | 2822 | /*! @name MODECTRL - Integration Mode Control Register */ |
mbed_official | 121:7f86b4238bec | 2823 | #define MTB_MODECTRL_MODECTRL_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 2824 | #define MTB_MODECTRL_MODECTRL_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 2825 | #define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x)) << MTB_MODECTRL_MODECTRL_SHIFT)) & MTB_MODECTRL_MODECTRL_MASK) |
mbed_official | 121:7f86b4238bec | 2826 | |
mbed_official | 121:7f86b4238bec | 2827 | /*! @name TAGSET - Claim TAG Set Register */ |
mbed_official | 121:7f86b4238bec | 2828 | #define MTB_TAGSET_TAGSET_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 2829 | #define MTB_TAGSET_TAGSET_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 2830 | #define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x)) << MTB_TAGSET_TAGSET_SHIFT)) & MTB_TAGSET_TAGSET_MASK) |
mbed_official | 121:7f86b4238bec | 2831 | |
mbed_official | 121:7f86b4238bec | 2832 | /*! @name TAGCLEAR - Claim TAG Clear Register */ |
mbed_official | 121:7f86b4238bec | 2833 | #define MTB_TAGCLEAR_TAGCLEAR_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 2834 | #define MTB_TAGCLEAR_TAGCLEAR_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 2835 | #define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x)) << MTB_TAGCLEAR_TAGCLEAR_SHIFT)) & MTB_TAGCLEAR_TAGCLEAR_MASK) |
mbed_official | 121:7f86b4238bec | 2836 | |
mbed_official | 121:7f86b4238bec | 2837 | /*! @name LOCKACCESS - Lock Access Register */ |
mbed_official | 121:7f86b4238bec | 2838 | #define MTB_LOCKACCESS_LOCKACCESS_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 2839 | #define MTB_LOCKACCESS_LOCKACCESS_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 2840 | #define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x)) << MTB_LOCKACCESS_LOCKACCESS_SHIFT)) & MTB_LOCKACCESS_LOCKACCESS_MASK) |
mbed_official | 121:7f86b4238bec | 2841 | |
mbed_official | 121:7f86b4238bec | 2842 | /*! @name LOCKSTAT - Lock Status Register */ |
mbed_official | 121:7f86b4238bec | 2843 | #define MTB_LOCKSTAT_LOCKSTAT_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 2844 | #define MTB_LOCKSTAT_LOCKSTAT_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 2845 | #define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x)) << MTB_LOCKSTAT_LOCKSTAT_SHIFT)) & MTB_LOCKSTAT_LOCKSTAT_MASK) |
mbed_official | 121:7f86b4238bec | 2846 | |
mbed_official | 121:7f86b4238bec | 2847 | /*! @name AUTHSTAT - Authentication Status Register */ |
mbed_official | 121:7f86b4238bec | 2848 | #define MTB_AUTHSTAT_BIT0_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 2849 | #define MTB_AUTHSTAT_BIT0_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 2850 | #define MTB_AUTHSTAT_BIT0(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT0_SHIFT)) & MTB_AUTHSTAT_BIT0_MASK) |
mbed_official | 121:7f86b4238bec | 2851 | #define MTB_AUTHSTAT_BIT1_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 2852 | #define MTB_AUTHSTAT_BIT1_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 2853 | #define MTB_AUTHSTAT_BIT1(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT1_SHIFT)) & MTB_AUTHSTAT_BIT1_MASK) |
mbed_official | 121:7f86b4238bec | 2854 | #define MTB_AUTHSTAT_BIT2_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 2855 | #define MTB_AUTHSTAT_BIT2_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 2856 | #define MTB_AUTHSTAT_BIT2(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT2_SHIFT)) & MTB_AUTHSTAT_BIT2_MASK) |
mbed_official | 121:7f86b4238bec | 2857 | #define MTB_AUTHSTAT_BIT3_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 2858 | #define MTB_AUTHSTAT_BIT3_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 2859 | #define MTB_AUTHSTAT_BIT3(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT3_SHIFT)) & MTB_AUTHSTAT_BIT3_MASK) |
mbed_official | 121:7f86b4238bec | 2860 | |
mbed_official | 121:7f86b4238bec | 2861 | /*! @name DEVICEARCH - Device Architecture Register */ |
mbed_official | 121:7f86b4238bec | 2862 | #define MTB_DEVICEARCH_DEVICEARCH_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 2863 | #define MTB_DEVICEARCH_DEVICEARCH_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 2864 | #define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICEARCH_DEVICEARCH_SHIFT)) & MTB_DEVICEARCH_DEVICEARCH_MASK) |
mbed_official | 121:7f86b4238bec | 2865 | |
mbed_official | 121:7f86b4238bec | 2866 | /*! @name DEVICECFG - Device Configuration Register */ |
mbed_official | 121:7f86b4238bec | 2867 | #define MTB_DEVICECFG_DEVICECFG_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 2868 | #define MTB_DEVICECFG_DEVICECFG_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 2869 | #define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICECFG_DEVICECFG_SHIFT)) & MTB_DEVICECFG_DEVICECFG_MASK) |
mbed_official | 121:7f86b4238bec | 2870 | |
mbed_official | 121:7f86b4238bec | 2871 | /*! @name DEVICETYPID - Device Type Identifier Register */ |
mbed_official | 121:7f86b4238bec | 2872 | #define MTB_DEVICETYPID_DEVICETYPID_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 2873 | #define MTB_DEVICETYPID_DEVICETYPID_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 2874 | #define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICETYPID_DEVICETYPID_SHIFT)) & MTB_DEVICETYPID_DEVICETYPID_MASK) |
mbed_official | 121:7f86b4238bec | 2875 | |
mbed_official | 121:7f86b4238bec | 2876 | /*! @name PERIPHID - Peripheral ID Register */ |
mbed_official | 121:7f86b4238bec | 2877 | #define MTB_PERIPHID_PERIPHID_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 2878 | #define MTB_PERIPHID_PERIPHID_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 2879 | #define MTB_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID_PERIPHID_SHIFT)) & MTB_PERIPHID_PERIPHID_MASK) |
mbed_official | 121:7f86b4238bec | 2880 | |
mbed_official | 121:7f86b4238bec | 2881 | /* The count of MTB_PERIPHID */ |
mbed_official | 121:7f86b4238bec | 2882 | #define MTB_PERIPHID_COUNT (8U) |
mbed_official | 121:7f86b4238bec | 2883 | |
mbed_official | 121:7f86b4238bec | 2884 | /*! @name COMPID - Component ID Register */ |
mbed_official | 121:7f86b4238bec | 2885 | #define MTB_COMPID_COMPID_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 2886 | #define MTB_COMPID_COMPID_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 2887 | #define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << MTB_COMPID_COMPID_SHIFT)) & MTB_COMPID_COMPID_MASK) |
mbed_official | 121:7f86b4238bec | 2888 | |
mbed_official | 121:7f86b4238bec | 2889 | /* The count of MTB_COMPID */ |
mbed_official | 121:7f86b4238bec | 2890 | #define MTB_COMPID_COUNT (4U) |
mbed_official | 121:7f86b4238bec | 2891 | |
mbed_official | 121:7f86b4238bec | 2892 | |
mbed_official | 121:7f86b4238bec | 2893 | /*! |
mbed_official | 121:7f86b4238bec | 2894 | * @} |
mbed_official | 121:7f86b4238bec | 2895 | */ /* end of group MTB_Register_Masks */ |
mbed_official | 121:7f86b4238bec | 2896 | |
mbed_official | 121:7f86b4238bec | 2897 | |
mbed_official | 121:7f86b4238bec | 2898 | /* MTB - Peripheral instance base addresses */ |
mbed_official | 121:7f86b4238bec | 2899 | /** Peripheral MTB base address */ |
mbed_official | 121:7f86b4238bec | 2900 | #define MTB_BASE (0xF0000000u) |
mbed_official | 121:7f86b4238bec | 2901 | /** Peripheral MTB base pointer */ |
mbed_official | 121:7f86b4238bec | 2902 | #define MTB ((MTB_Type *)MTB_BASE) |
mbed_official | 121:7f86b4238bec | 2903 | /** Array initializer of MTB peripheral base addresses */ |
mbed_official | 121:7f86b4238bec | 2904 | #define MTB_BASE_ADDRS { MTB_BASE } |
mbed_official | 121:7f86b4238bec | 2905 | /** Array initializer of MTB peripheral base pointers */ |
mbed_official | 121:7f86b4238bec | 2906 | #define MTB_BASE_PTRS { MTB } |
mbed_official | 121:7f86b4238bec | 2907 | |
mbed_official | 121:7f86b4238bec | 2908 | /*! |
mbed_official | 121:7f86b4238bec | 2909 | * @} |
mbed_official | 121:7f86b4238bec | 2910 | */ /* end of group MTB_Peripheral_Access_Layer */ |
mbed_official | 121:7f86b4238bec | 2911 | |
mbed_official | 121:7f86b4238bec | 2912 | |
mbed_official | 121:7f86b4238bec | 2913 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 2914 | -- MTBDWT Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 2915 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 2916 | |
mbed_official | 121:7f86b4238bec | 2917 | /*! |
mbed_official | 121:7f86b4238bec | 2918 | * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 2919 | * @{ |
mbed_official | 121:7f86b4238bec | 2920 | */ |
mbed_official | 121:7f86b4238bec | 2921 | |
mbed_official | 121:7f86b4238bec | 2922 | /** MTBDWT - Register Layout Typedef */ |
mbed_official | 121:7f86b4238bec | 2923 | typedef struct { |
mbed_official | 121:7f86b4238bec | 2924 | __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */ |
mbed_official | 121:7f86b4238bec | 2925 | uint8_t RESERVED_0[28]; |
mbed_official | 121:7f86b4238bec | 2926 | struct { /* offset: 0x20, array step: 0x10 */ |
mbed_official | 121:7f86b4238bec | 2927 | __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */ |
mbed_official | 121:7f86b4238bec | 2928 | __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */ |
mbed_official | 121:7f86b4238bec | 2929 | __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */ |
mbed_official | 121:7f86b4238bec | 2930 | uint8_t RESERVED_0[4]; |
mbed_official | 121:7f86b4238bec | 2931 | } COMPARATOR[2]; |
mbed_official | 121:7f86b4238bec | 2932 | uint8_t RESERVED_1[448]; |
mbed_official | 121:7f86b4238bec | 2933 | __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */ |
mbed_official | 121:7f86b4238bec | 2934 | uint8_t RESERVED_2[3524]; |
mbed_official | 121:7f86b4238bec | 2935 | __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */ |
mbed_official | 121:7f86b4238bec | 2936 | __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */ |
mbed_official | 121:7f86b4238bec | 2937 | __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */ |
mbed_official | 121:7f86b4238bec | 2938 | __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ |
mbed_official | 121:7f86b4238bec | 2939 | } MTBDWT_Type; |
mbed_official | 121:7f86b4238bec | 2940 | |
mbed_official | 121:7f86b4238bec | 2941 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 2942 | -- MTBDWT Register Masks |
mbed_official | 121:7f86b4238bec | 2943 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 2944 | |
mbed_official | 121:7f86b4238bec | 2945 | /*! |
mbed_official | 121:7f86b4238bec | 2946 | * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks |
mbed_official | 121:7f86b4238bec | 2947 | * @{ |
mbed_official | 121:7f86b4238bec | 2948 | */ |
mbed_official | 121:7f86b4238bec | 2949 | |
mbed_official | 121:7f86b4238bec | 2950 | /*! @name CTRL - MTB DWT Control Register */ |
mbed_official | 121:7f86b4238bec | 2951 | #define MTBDWT_CTRL_DWTCFGCTRL_MASK (0xFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 2952 | #define MTBDWT_CTRL_DWTCFGCTRL_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 2953 | #define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_DWTCFGCTRL_SHIFT)) & MTBDWT_CTRL_DWTCFGCTRL_MASK) |
mbed_official | 121:7f86b4238bec | 2954 | #define MTBDWT_CTRL_NUMCMP_MASK (0xF0000000U) |
mbed_official | 121:7f86b4238bec | 2955 | #define MTBDWT_CTRL_NUMCMP_SHIFT (28U) |
mbed_official | 121:7f86b4238bec | 2956 | #define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_NUMCMP_SHIFT)) & MTBDWT_CTRL_NUMCMP_MASK) |
mbed_official | 121:7f86b4238bec | 2957 | |
mbed_official | 121:7f86b4238bec | 2958 | /*! @name COMP - MTB_DWT Comparator Register */ |
mbed_official | 121:7f86b4238bec | 2959 | #define MTBDWT_COMP_COMP_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 2960 | #define MTBDWT_COMP_COMP_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 2961 | #define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMP_COMP_SHIFT)) & MTBDWT_COMP_COMP_MASK) |
mbed_official | 121:7f86b4238bec | 2962 | |
mbed_official | 121:7f86b4238bec | 2963 | /* The count of MTBDWT_COMP */ |
mbed_official | 121:7f86b4238bec | 2964 | #define MTBDWT_COMP_COUNT (2U) |
mbed_official | 121:7f86b4238bec | 2965 | |
mbed_official | 121:7f86b4238bec | 2966 | /*! @name MASK - MTB_DWT Comparator Mask Register */ |
mbed_official | 121:7f86b4238bec | 2967 | #define MTBDWT_MASK_MASK_MASK (0x1FU) |
mbed_official | 121:7f86b4238bec | 2968 | #define MTBDWT_MASK_MASK_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 2969 | #define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_MASK_MASK_SHIFT)) & MTBDWT_MASK_MASK_MASK) |
mbed_official | 121:7f86b4238bec | 2970 | |
mbed_official | 121:7f86b4238bec | 2971 | /* The count of MTBDWT_MASK */ |
mbed_official | 121:7f86b4238bec | 2972 | #define MTBDWT_MASK_COUNT (2U) |
mbed_official | 121:7f86b4238bec | 2973 | |
mbed_official | 121:7f86b4238bec | 2974 | /*! @name FCT - MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1 */ |
mbed_official | 121:7f86b4238bec | 2975 | #define MTBDWT_FCT_FUNCTION_MASK (0xFU) |
mbed_official | 121:7f86b4238bec | 2976 | #define MTBDWT_FCT_FUNCTION_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 2977 | #define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_FUNCTION_SHIFT)) & MTBDWT_FCT_FUNCTION_MASK) |
mbed_official | 121:7f86b4238bec | 2978 | #define MTBDWT_FCT_DATAVMATCH_MASK (0x100U) |
mbed_official | 121:7f86b4238bec | 2979 | #define MTBDWT_FCT_DATAVMATCH_SHIFT (8U) |
mbed_official | 121:7f86b4238bec | 2980 | #define MTBDWT_FCT_DATAVMATCH(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVMATCH_SHIFT)) & MTBDWT_FCT_DATAVMATCH_MASK) |
mbed_official | 121:7f86b4238bec | 2981 | #define MTBDWT_FCT_DATAVSIZE_MASK (0xC00U) |
mbed_official | 121:7f86b4238bec | 2982 | #define MTBDWT_FCT_DATAVSIZE_SHIFT (10U) |
mbed_official | 121:7f86b4238bec | 2983 | #define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVSIZE_SHIFT)) & MTBDWT_FCT_DATAVSIZE_MASK) |
mbed_official | 121:7f86b4238bec | 2984 | #define MTBDWT_FCT_DATAVADDR0_MASK (0xF000U) |
mbed_official | 121:7f86b4238bec | 2985 | #define MTBDWT_FCT_DATAVADDR0_SHIFT (12U) |
mbed_official | 121:7f86b4238bec | 2986 | #define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVADDR0_SHIFT)) & MTBDWT_FCT_DATAVADDR0_MASK) |
mbed_official | 121:7f86b4238bec | 2987 | #define MTBDWT_FCT_MATCHED_MASK (0x1000000U) |
mbed_official | 121:7f86b4238bec | 2988 | #define MTBDWT_FCT_MATCHED_SHIFT (24U) |
mbed_official | 121:7f86b4238bec | 2989 | #define MTBDWT_FCT_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_MATCHED_SHIFT)) & MTBDWT_FCT_MATCHED_MASK) |
mbed_official | 121:7f86b4238bec | 2990 | |
mbed_official | 121:7f86b4238bec | 2991 | /* The count of MTBDWT_FCT */ |
mbed_official | 121:7f86b4238bec | 2992 | #define MTBDWT_FCT_COUNT (2U) |
mbed_official | 121:7f86b4238bec | 2993 | |
mbed_official | 121:7f86b4238bec | 2994 | /*! @name TBCTRL - MTB_DWT Trace Buffer Control Register */ |
mbed_official | 121:7f86b4238bec | 2995 | #define MTBDWT_TBCTRL_ACOMP0_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 2996 | #define MTBDWT_TBCTRL_ACOMP0_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 2997 | #define MTBDWT_TBCTRL_ACOMP0(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP0_SHIFT)) & MTBDWT_TBCTRL_ACOMP0_MASK) |
mbed_official | 121:7f86b4238bec | 2998 | #define MTBDWT_TBCTRL_ACOMP1_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 2999 | #define MTBDWT_TBCTRL_ACOMP1_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 3000 | #define MTBDWT_TBCTRL_ACOMP1(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP1_SHIFT)) & MTBDWT_TBCTRL_ACOMP1_MASK) |
mbed_official | 121:7f86b4238bec | 3001 | #define MTBDWT_TBCTRL_NUMCOMP_MASK (0xF0000000U) |
mbed_official | 121:7f86b4238bec | 3002 | #define MTBDWT_TBCTRL_NUMCOMP_SHIFT (28U) |
mbed_official | 121:7f86b4238bec | 3003 | #define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_NUMCOMP_SHIFT)) & MTBDWT_TBCTRL_NUMCOMP_MASK) |
mbed_official | 121:7f86b4238bec | 3004 | |
mbed_official | 121:7f86b4238bec | 3005 | /*! @name DEVICECFG - Device Configuration Register */ |
mbed_official | 121:7f86b4238bec | 3006 | #define MTBDWT_DEVICECFG_DEVICECFG_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 3007 | #define MTBDWT_DEVICECFG_DEVICECFG_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3008 | #define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICECFG_DEVICECFG_SHIFT)) & MTBDWT_DEVICECFG_DEVICECFG_MASK) |
mbed_official | 121:7f86b4238bec | 3009 | |
mbed_official | 121:7f86b4238bec | 3010 | /*! @name DEVICETYPID - Device Type Identifier Register */ |
mbed_official | 121:7f86b4238bec | 3011 | #define MTBDWT_DEVICETYPID_DEVICETYPID_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 3012 | #define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3013 | #define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT)) & MTBDWT_DEVICETYPID_DEVICETYPID_MASK) |
mbed_official | 121:7f86b4238bec | 3014 | |
mbed_official | 121:7f86b4238bec | 3015 | /*! @name PERIPHID - Peripheral ID Register */ |
mbed_official | 121:7f86b4238bec | 3016 | #define MTBDWT_PERIPHID_PERIPHID_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 3017 | #define MTBDWT_PERIPHID_PERIPHID_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3018 | #define MTBDWT_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID_PERIPHID_SHIFT)) & MTBDWT_PERIPHID_PERIPHID_MASK) |
mbed_official | 121:7f86b4238bec | 3019 | |
mbed_official | 121:7f86b4238bec | 3020 | /* The count of MTBDWT_PERIPHID */ |
mbed_official | 121:7f86b4238bec | 3021 | #define MTBDWT_PERIPHID_COUNT (8U) |
mbed_official | 121:7f86b4238bec | 3022 | |
mbed_official | 121:7f86b4238bec | 3023 | /*! @name COMPID - Component ID Register */ |
mbed_official | 121:7f86b4238bec | 3024 | #define MTBDWT_COMPID_COMPID_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 3025 | #define MTBDWT_COMPID_COMPID_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3026 | #define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMPID_COMPID_SHIFT)) & MTBDWT_COMPID_COMPID_MASK) |
mbed_official | 121:7f86b4238bec | 3027 | |
mbed_official | 121:7f86b4238bec | 3028 | /* The count of MTBDWT_COMPID */ |
mbed_official | 121:7f86b4238bec | 3029 | #define MTBDWT_COMPID_COUNT (4U) |
mbed_official | 121:7f86b4238bec | 3030 | |
mbed_official | 121:7f86b4238bec | 3031 | |
mbed_official | 121:7f86b4238bec | 3032 | /*! |
mbed_official | 121:7f86b4238bec | 3033 | * @} |
mbed_official | 121:7f86b4238bec | 3034 | */ /* end of group MTBDWT_Register_Masks */ |
mbed_official | 121:7f86b4238bec | 3035 | |
mbed_official | 121:7f86b4238bec | 3036 | |
mbed_official | 121:7f86b4238bec | 3037 | /* MTBDWT - Peripheral instance base addresses */ |
mbed_official | 121:7f86b4238bec | 3038 | /** Peripheral MTBDWT base address */ |
mbed_official | 121:7f86b4238bec | 3039 | #define MTBDWT_BASE (0xF0001000u) |
mbed_official | 121:7f86b4238bec | 3040 | /** Peripheral MTBDWT base pointer */ |
mbed_official | 121:7f86b4238bec | 3041 | #define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE) |
mbed_official | 121:7f86b4238bec | 3042 | /** Array initializer of MTBDWT peripheral base addresses */ |
mbed_official | 121:7f86b4238bec | 3043 | #define MTBDWT_BASE_ADDRS { MTBDWT_BASE } |
mbed_official | 121:7f86b4238bec | 3044 | /** Array initializer of MTBDWT peripheral base pointers */ |
mbed_official | 121:7f86b4238bec | 3045 | #define MTBDWT_BASE_PTRS { MTBDWT } |
mbed_official | 121:7f86b4238bec | 3046 | |
mbed_official | 121:7f86b4238bec | 3047 | /*! |
mbed_official | 121:7f86b4238bec | 3048 | * @} |
mbed_official | 121:7f86b4238bec | 3049 | */ /* end of group MTBDWT_Peripheral_Access_Layer */ |
mbed_official | 121:7f86b4238bec | 3050 | |
mbed_official | 121:7f86b4238bec | 3051 | |
mbed_official | 121:7f86b4238bec | 3052 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 3053 | -- NV Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 3054 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 3055 | |
mbed_official | 121:7f86b4238bec | 3056 | /*! |
mbed_official | 121:7f86b4238bec | 3057 | * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 3058 | * @{ |
mbed_official | 121:7f86b4238bec | 3059 | */ |
mbed_official | 121:7f86b4238bec | 3060 | |
mbed_official | 121:7f86b4238bec | 3061 | /** NV - Register Layout Typedef */ |
mbed_official | 121:7f86b4238bec | 3062 | typedef struct { |
mbed_official | 121:7f86b4238bec | 3063 | __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */ |
mbed_official | 121:7f86b4238bec | 3064 | __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */ |
mbed_official | 121:7f86b4238bec | 3065 | __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */ |
mbed_official | 121:7f86b4238bec | 3066 | __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */ |
mbed_official | 121:7f86b4238bec | 3067 | __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */ |
mbed_official | 121:7f86b4238bec | 3068 | __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */ |
mbed_official | 121:7f86b4238bec | 3069 | __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */ |
mbed_official | 121:7f86b4238bec | 3070 | __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */ |
mbed_official | 121:7f86b4238bec | 3071 | __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */ |
mbed_official | 121:7f86b4238bec | 3072 | __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */ |
mbed_official | 121:7f86b4238bec | 3073 | __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */ |
mbed_official | 121:7f86b4238bec | 3074 | __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */ |
mbed_official | 121:7f86b4238bec | 3075 | __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */ |
mbed_official | 121:7f86b4238bec | 3076 | __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */ |
mbed_official | 121:7f86b4238bec | 3077 | } NV_Type; |
mbed_official | 121:7f86b4238bec | 3078 | |
mbed_official | 121:7f86b4238bec | 3079 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 3080 | -- NV Register Masks |
mbed_official | 121:7f86b4238bec | 3081 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 3082 | |
mbed_official | 121:7f86b4238bec | 3083 | /*! |
mbed_official | 121:7f86b4238bec | 3084 | * @addtogroup NV_Register_Masks NV Register Masks |
mbed_official | 121:7f86b4238bec | 3085 | * @{ |
mbed_official | 121:7f86b4238bec | 3086 | */ |
mbed_official | 121:7f86b4238bec | 3087 | |
mbed_official | 121:7f86b4238bec | 3088 | /*! @name BACKKEY3 - Backdoor Comparison Key 3. */ |
mbed_official | 121:7f86b4238bec | 3089 | #define NV_BACKKEY3_KEY_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 3090 | #define NV_BACKKEY3_KEY_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3091 | #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK) |
mbed_official | 121:7f86b4238bec | 3092 | |
mbed_official | 121:7f86b4238bec | 3093 | /*! @name BACKKEY2 - Backdoor Comparison Key 2. */ |
mbed_official | 121:7f86b4238bec | 3094 | #define NV_BACKKEY2_KEY_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 3095 | #define NV_BACKKEY2_KEY_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3096 | #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK) |
mbed_official | 121:7f86b4238bec | 3097 | |
mbed_official | 121:7f86b4238bec | 3098 | /*! @name BACKKEY1 - Backdoor Comparison Key 1. */ |
mbed_official | 121:7f86b4238bec | 3099 | #define NV_BACKKEY1_KEY_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 3100 | #define NV_BACKKEY1_KEY_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3101 | #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK) |
mbed_official | 121:7f86b4238bec | 3102 | |
mbed_official | 121:7f86b4238bec | 3103 | /*! @name BACKKEY0 - Backdoor Comparison Key 0. */ |
mbed_official | 121:7f86b4238bec | 3104 | #define NV_BACKKEY0_KEY_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 3105 | #define NV_BACKKEY0_KEY_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3106 | #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK) |
mbed_official | 121:7f86b4238bec | 3107 | |
mbed_official | 121:7f86b4238bec | 3108 | /*! @name BACKKEY7 - Backdoor Comparison Key 7. */ |
mbed_official | 121:7f86b4238bec | 3109 | #define NV_BACKKEY7_KEY_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 3110 | #define NV_BACKKEY7_KEY_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3111 | #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK) |
mbed_official | 121:7f86b4238bec | 3112 | |
mbed_official | 121:7f86b4238bec | 3113 | /*! @name BACKKEY6 - Backdoor Comparison Key 6. */ |
mbed_official | 121:7f86b4238bec | 3114 | #define NV_BACKKEY6_KEY_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 3115 | #define NV_BACKKEY6_KEY_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3116 | #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK) |
mbed_official | 121:7f86b4238bec | 3117 | |
mbed_official | 121:7f86b4238bec | 3118 | /*! @name BACKKEY5 - Backdoor Comparison Key 5. */ |
mbed_official | 121:7f86b4238bec | 3119 | #define NV_BACKKEY5_KEY_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 3120 | #define NV_BACKKEY5_KEY_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3121 | #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK) |
mbed_official | 121:7f86b4238bec | 3122 | |
mbed_official | 121:7f86b4238bec | 3123 | /*! @name BACKKEY4 - Backdoor Comparison Key 4. */ |
mbed_official | 121:7f86b4238bec | 3124 | #define NV_BACKKEY4_KEY_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 3125 | #define NV_BACKKEY4_KEY_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3126 | #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK) |
mbed_official | 121:7f86b4238bec | 3127 | |
mbed_official | 121:7f86b4238bec | 3128 | /*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */ |
mbed_official | 121:7f86b4238bec | 3129 | #define NV_FPROT3_PROT_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 3130 | #define NV_FPROT3_PROT_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3131 | #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK) |
mbed_official | 121:7f86b4238bec | 3132 | |
mbed_official | 121:7f86b4238bec | 3133 | /*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */ |
mbed_official | 121:7f86b4238bec | 3134 | #define NV_FPROT2_PROT_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 3135 | #define NV_FPROT2_PROT_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3136 | #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK) |
mbed_official | 121:7f86b4238bec | 3137 | |
mbed_official | 121:7f86b4238bec | 3138 | /*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */ |
mbed_official | 121:7f86b4238bec | 3139 | #define NV_FPROT1_PROT_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 3140 | #define NV_FPROT1_PROT_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3141 | #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK) |
mbed_official | 121:7f86b4238bec | 3142 | |
mbed_official | 121:7f86b4238bec | 3143 | /*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */ |
mbed_official | 121:7f86b4238bec | 3144 | #define NV_FPROT0_PROT_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 3145 | #define NV_FPROT0_PROT_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3146 | #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK) |
mbed_official | 121:7f86b4238bec | 3147 | |
mbed_official | 121:7f86b4238bec | 3148 | /*! @name FSEC - Non-volatile Flash Security Register */ |
mbed_official | 121:7f86b4238bec | 3149 | #define NV_FSEC_SEC_MASK (0x3U) |
mbed_official | 121:7f86b4238bec | 3150 | #define NV_FSEC_SEC_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3151 | #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK) |
mbed_official | 121:7f86b4238bec | 3152 | #define NV_FSEC_FSLACC_MASK (0xCU) |
mbed_official | 121:7f86b4238bec | 3153 | #define NV_FSEC_FSLACC_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 3154 | #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK) |
mbed_official | 121:7f86b4238bec | 3155 | #define NV_FSEC_MEEN_MASK (0x30U) |
mbed_official | 121:7f86b4238bec | 3156 | #define NV_FSEC_MEEN_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 3157 | #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK) |
mbed_official | 121:7f86b4238bec | 3158 | #define NV_FSEC_KEYEN_MASK (0xC0U) |
mbed_official | 121:7f86b4238bec | 3159 | #define NV_FSEC_KEYEN_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 3160 | #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK) |
mbed_official | 121:7f86b4238bec | 3161 | |
mbed_official | 121:7f86b4238bec | 3162 | /*! @name FOPT - Non-volatile Flash Option Register */ |
mbed_official | 121:7f86b4238bec | 3163 | #define NV_FOPT_LPBOOT0_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 3164 | #define NV_FOPT_LPBOOT0_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3165 | #define NV_FOPT_LPBOOT0(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT0_SHIFT)) & NV_FOPT_LPBOOT0_MASK) |
mbed_official | 121:7f86b4238bec | 3166 | #define NV_FOPT_BOOTPIN_OPT_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 3167 | #define NV_FOPT_BOOTPIN_OPT_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 3168 | #define NV_FOPT_BOOTPIN_OPT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_BOOTPIN_OPT_SHIFT)) & NV_FOPT_BOOTPIN_OPT_MASK) |
mbed_official | 121:7f86b4238bec | 3169 | #define NV_FOPT_NMI_DIS_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 3170 | #define NV_FOPT_NMI_DIS_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 3171 | #define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK) |
mbed_official | 121:7f86b4238bec | 3172 | #define NV_FOPT_RESET_PIN_CFG_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 3173 | #define NV_FOPT_RESET_PIN_CFG_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 3174 | #define NV_FOPT_RESET_PIN_CFG(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_RESET_PIN_CFG_SHIFT)) & NV_FOPT_RESET_PIN_CFG_MASK) |
mbed_official | 121:7f86b4238bec | 3175 | #define NV_FOPT_LPBOOT1_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 3176 | #define NV_FOPT_LPBOOT1_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 3177 | #define NV_FOPT_LPBOOT1(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT1_SHIFT)) & NV_FOPT_LPBOOT1_MASK) |
mbed_official | 121:7f86b4238bec | 3178 | #define NV_FOPT_FAST_INIT_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 3179 | #define NV_FOPT_FAST_INIT_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 3180 | #define NV_FOPT_FAST_INIT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_FAST_INIT_SHIFT)) & NV_FOPT_FAST_INIT_MASK) |
mbed_official | 121:7f86b4238bec | 3181 | #define NV_FOPT_BOOTSRC_SEL_MASK (0xC0U) |
mbed_official | 121:7f86b4238bec | 3182 | #define NV_FOPT_BOOTSRC_SEL_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 3183 | #define NV_FOPT_BOOTSRC_SEL(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_BOOTSRC_SEL_SHIFT)) & NV_FOPT_BOOTSRC_SEL_MASK) |
mbed_official | 121:7f86b4238bec | 3184 | |
mbed_official | 121:7f86b4238bec | 3185 | |
mbed_official | 121:7f86b4238bec | 3186 | /*! |
mbed_official | 121:7f86b4238bec | 3187 | * @} |
mbed_official | 121:7f86b4238bec | 3188 | */ /* end of group NV_Register_Masks */ |
mbed_official | 121:7f86b4238bec | 3189 | |
mbed_official | 121:7f86b4238bec | 3190 | |
mbed_official | 121:7f86b4238bec | 3191 | /* NV - Peripheral instance base addresses */ |
mbed_official | 121:7f86b4238bec | 3192 | /** Peripheral FTFA_FlashConfig base address */ |
mbed_official | 121:7f86b4238bec | 3193 | #define FTFA_FlashConfig_BASE (0x400u) |
mbed_official | 121:7f86b4238bec | 3194 | /** Peripheral FTFA_FlashConfig base pointer */ |
mbed_official | 121:7f86b4238bec | 3195 | #define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE) |
mbed_official | 121:7f86b4238bec | 3196 | /** Array initializer of NV peripheral base addresses */ |
mbed_official | 121:7f86b4238bec | 3197 | #define NV_BASE_ADDRS { FTFA_FlashConfig_BASE } |
mbed_official | 121:7f86b4238bec | 3198 | /** Array initializer of NV peripheral base pointers */ |
mbed_official | 121:7f86b4238bec | 3199 | #define NV_BASE_PTRS { FTFA_FlashConfig } |
mbed_official | 121:7f86b4238bec | 3200 | |
mbed_official | 121:7f86b4238bec | 3201 | /*! |
mbed_official | 121:7f86b4238bec | 3202 | * @} |
mbed_official | 121:7f86b4238bec | 3203 | */ /* end of group NV_Peripheral_Access_Layer */ |
mbed_official | 121:7f86b4238bec | 3204 | |
mbed_official | 121:7f86b4238bec | 3205 | |
mbed_official | 121:7f86b4238bec | 3206 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 3207 | -- OSC Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 3208 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 3209 | |
mbed_official | 121:7f86b4238bec | 3210 | /*! |
mbed_official | 121:7f86b4238bec | 3211 | * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 3212 | * @{ |
mbed_official | 121:7f86b4238bec | 3213 | */ |
mbed_official | 121:7f86b4238bec | 3214 | |
mbed_official | 121:7f86b4238bec | 3215 | /** OSC - Register Layout Typedef */ |
mbed_official | 121:7f86b4238bec | 3216 | typedef struct { |
mbed_official | 121:7f86b4238bec | 3217 | __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */ |
mbed_official | 121:7f86b4238bec | 3218 | } OSC_Type; |
mbed_official | 121:7f86b4238bec | 3219 | |
mbed_official | 121:7f86b4238bec | 3220 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 3221 | -- OSC Register Masks |
mbed_official | 121:7f86b4238bec | 3222 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 3223 | |
mbed_official | 121:7f86b4238bec | 3224 | /*! |
mbed_official | 121:7f86b4238bec | 3225 | * @addtogroup OSC_Register_Masks OSC Register Masks |
mbed_official | 121:7f86b4238bec | 3226 | * @{ |
mbed_official | 121:7f86b4238bec | 3227 | */ |
mbed_official | 121:7f86b4238bec | 3228 | |
mbed_official | 121:7f86b4238bec | 3229 | /*! @name CR - OSC Control Register */ |
mbed_official | 121:7f86b4238bec | 3230 | #define OSC_CR_SC16P_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 3231 | #define OSC_CR_SC16P_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3232 | #define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK) |
mbed_official | 121:7f86b4238bec | 3233 | #define OSC_CR_SC8P_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 3234 | #define OSC_CR_SC8P_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 3235 | #define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK) |
mbed_official | 121:7f86b4238bec | 3236 | #define OSC_CR_SC4P_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 3237 | #define OSC_CR_SC4P_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 3238 | #define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK) |
mbed_official | 121:7f86b4238bec | 3239 | #define OSC_CR_SC2P_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 3240 | #define OSC_CR_SC2P_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 3241 | #define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK) |
mbed_official | 121:7f86b4238bec | 3242 | #define OSC_CR_EREFSTEN_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 3243 | #define OSC_CR_EREFSTEN_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 3244 | #define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK) |
mbed_official | 121:7f86b4238bec | 3245 | #define OSC_CR_ERCLKEN_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 3246 | #define OSC_CR_ERCLKEN_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 3247 | #define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK) |
mbed_official | 121:7f86b4238bec | 3248 | |
mbed_official | 121:7f86b4238bec | 3249 | |
mbed_official | 121:7f86b4238bec | 3250 | /*! |
mbed_official | 121:7f86b4238bec | 3251 | * @} |
mbed_official | 121:7f86b4238bec | 3252 | */ /* end of group OSC_Register_Masks */ |
mbed_official | 121:7f86b4238bec | 3253 | |
mbed_official | 121:7f86b4238bec | 3254 | |
mbed_official | 121:7f86b4238bec | 3255 | /* OSC - Peripheral instance base addresses */ |
mbed_official | 121:7f86b4238bec | 3256 | /** Peripheral OSC0 base address */ |
mbed_official | 121:7f86b4238bec | 3257 | #define OSC0_BASE (0x40065000u) |
mbed_official | 121:7f86b4238bec | 3258 | /** Peripheral OSC0 base pointer */ |
mbed_official | 121:7f86b4238bec | 3259 | #define OSC0 ((OSC_Type *)OSC0_BASE) |
mbed_official | 121:7f86b4238bec | 3260 | /** Array initializer of OSC peripheral base addresses */ |
mbed_official | 121:7f86b4238bec | 3261 | #define OSC_BASE_ADDRS { OSC0_BASE } |
mbed_official | 121:7f86b4238bec | 3262 | /** Array initializer of OSC peripheral base pointers */ |
mbed_official | 121:7f86b4238bec | 3263 | #define OSC_BASE_PTRS { OSC0 } |
mbed_official | 121:7f86b4238bec | 3264 | |
mbed_official | 121:7f86b4238bec | 3265 | /*! |
mbed_official | 121:7f86b4238bec | 3266 | * @} |
mbed_official | 121:7f86b4238bec | 3267 | */ /* end of group OSC_Peripheral_Access_Layer */ |
mbed_official | 121:7f86b4238bec | 3268 | |
mbed_official | 121:7f86b4238bec | 3269 | |
mbed_official | 121:7f86b4238bec | 3270 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 3271 | -- PIT Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 3272 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 3273 | |
mbed_official | 121:7f86b4238bec | 3274 | /*! |
mbed_official | 121:7f86b4238bec | 3275 | * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 3276 | * @{ |
mbed_official | 121:7f86b4238bec | 3277 | */ |
mbed_official | 121:7f86b4238bec | 3278 | |
mbed_official | 121:7f86b4238bec | 3279 | /** PIT - Register Layout Typedef */ |
mbed_official | 121:7f86b4238bec | 3280 | typedef struct { |
mbed_official | 121:7f86b4238bec | 3281 | __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */ |
mbed_official | 121:7f86b4238bec | 3282 | uint8_t RESERVED_0[220]; |
mbed_official | 121:7f86b4238bec | 3283 | __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */ |
mbed_official | 121:7f86b4238bec | 3284 | __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */ |
mbed_official | 121:7f86b4238bec | 3285 | uint8_t RESERVED_1[24]; |
mbed_official | 121:7f86b4238bec | 3286 | struct { /* offset: 0x100, array step: 0x10 */ |
mbed_official | 121:7f86b4238bec | 3287 | __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */ |
mbed_official | 121:7f86b4238bec | 3288 | __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */ |
mbed_official | 121:7f86b4238bec | 3289 | __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */ |
mbed_official | 121:7f86b4238bec | 3290 | __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */ |
mbed_official | 121:7f86b4238bec | 3291 | } CHANNEL[2]; |
mbed_official | 121:7f86b4238bec | 3292 | } PIT_Type; |
mbed_official | 121:7f86b4238bec | 3293 | |
mbed_official | 121:7f86b4238bec | 3294 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 3295 | -- PIT Register Masks |
mbed_official | 121:7f86b4238bec | 3296 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 3297 | |
mbed_official | 121:7f86b4238bec | 3298 | /*! |
mbed_official | 121:7f86b4238bec | 3299 | * @addtogroup PIT_Register_Masks PIT Register Masks |
mbed_official | 121:7f86b4238bec | 3300 | * @{ |
mbed_official | 121:7f86b4238bec | 3301 | */ |
mbed_official | 121:7f86b4238bec | 3302 | |
mbed_official | 121:7f86b4238bec | 3303 | /*! @name MCR - PIT Module Control Register */ |
mbed_official | 121:7f86b4238bec | 3304 | #define PIT_MCR_FRZ_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 3305 | #define PIT_MCR_FRZ_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3306 | #define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK) |
mbed_official | 121:7f86b4238bec | 3307 | #define PIT_MCR_MDIS_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 3308 | #define PIT_MCR_MDIS_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 3309 | #define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK) |
mbed_official | 121:7f86b4238bec | 3310 | |
mbed_official | 121:7f86b4238bec | 3311 | /*! @name LTMR64H - PIT Upper Lifetime Timer Register */ |
mbed_official | 121:7f86b4238bec | 3312 | #define PIT_LTMR64H_LTH_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 3313 | #define PIT_LTMR64H_LTH_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3314 | #define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK) |
mbed_official | 121:7f86b4238bec | 3315 | |
mbed_official | 121:7f86b4238bec | 3316 | /*! @name LTMR64L - PIT Lower Lifetime Timer Register */ |
mbed_official | 121:7f86b4238bec | 3317 | #define PIT_LTMR64L_LTL_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 3318 | #define PIT_LTMR64L_LTL_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3319 | #define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK) |
mbed_official | 121:7f86b4238bec | 3320 | |
mbed_official | 121:7f86b4238bec | 3321 | /*! @name LDVAL - Timer Load Value Register */ |
mbed_official | 121:7f86b4238bec | 3322 | #define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 3323 | #define PIT_LDVAL_TSV_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3324 | #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK) |
mbed_official | 121:7f86b4238bec | 3325 | |
mbed_official | 121:7f86b4238bec | 3326 | /* The count of PIT_LDVAL */ |
mbed_official | 121:7f86b4238bec | 3327 | #define PIT_LDVAL_COUNT (2U) |
mbed_official | 121:7f86b4238bec | 3328 | |
mbed_official | 121:7f86b4238bec | 3329 | /*! @name CVAL - Current Timer Value Register */ |
mbed_official | 121:7f86b4238bec | 3330 | #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 3331 | #define PIT_CVAL_TVL_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3332 | #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK) |
mbed_official | 121:7f86b4238bec | 3333 | |
mbed_official | 121:7f86b4238bec | 3334 | /* The count of PIT_CVAL */ |
mbed_official | 121:7f86b4238bec | 3335 | #define PIT_CVAL_COUNT (2U) |
mbed_official | 121:7f86b4238bec | 3336 | |
mbed_official | 121:7f86b4238bec | 3337 | /*! @name TCTRL - Timer Control Register */ |
mbed_official | 121:7f86b4238bec | 3338 | #define PIT_TCTRL_TEN_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 3339 | #define PIT_TCTRL_TEN_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3340 | #define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK) |
mbed_official | 121:7f86b4238bec | 3341 | #define PIT_TCTRL_TIE_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 3342 | #define PIT_TCTRL_TIE_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 3343 | #define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK) |
mbed_official | 121:7f86b4238bec | 3344 | #define PIT_TCTRL_CHN_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 3345 | #define PIT_TCTRL_CHN_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 3346 | #define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK) |
mbed_official | 121:7f86b4238bec | 3347 | |
mbed_official | 121:7f86b4238bec | 3348 | /* The count of PIT_TCTRL */ |
mbed_official | 121:7f86b4238bec | 3349 | #define PIT_TCTRL_COUNT (2U) |
mbed_official | 121:7f86b4238bec | 3350 | |
mbed_official | 121:7f86b4238bec | 3351 | /*! @name TFLG - Timer Flag Register */ |
mbed_official | 121:7f86b4238bec | 3352 | #define PIT_TFLG_TIF_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 3353 | #define PIT_TFLG_TIF_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3354 | #define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK) |
mbed_official | 121:7f86b4238bec | 3355 | |
mbed_official | 121:7f86b4238bec | 3356 | /* The count of PIT_TFLG */ |
mbed_official | 121:7f86b4238bec | 3357 | #define PIT_TFLG_COUNT (2U) |
mbed_official | 121:7f86b4238bec | 3358 | |
mbed_official | 121:7f86b4238bec | 3359 | |
mbed_official | 121:7f86b4238bec | 3360 | /*! |
mbed_official | 121:7f86b4238bec | 3361 | * @} |
mbed_official | 121:7f86b4238bec | 3362 | */ /* end of group PIT_Register_Masks */ |
mbed_official | 121:7f86b4238bec | 3363 | |
mbed_official | 121:7f86b4238bec | 3364 | |
mbed_official | 121:7f86b4238bec | 3365 | /* PIT - Peripheral instance base addresses */ |
mbed_official | 121:7f86b4238bec | 3366 | /** Peripheral PIT base address */ |
mbed_official | 121:7f86b4238bec | 3367 | #define PIT_BASE (0x40037000u) |
mbed_official | 121:7f86b4238bec | 3368 | /** Peripheral PIT base pointer */ |
mbed_official | 121:7f86b4238bec | 3369 | #define PIT ((PIT_Type *)PIT_BASE) |
mbed_official | 121:7f86b4238bec | 3370 | /** Array initializer of PIT peripheral base addresses */ |
mbed_official | 121:7f86b4238bec | 3371 | #define PIT_BASE_ADDRS { PIT_BASE } |
mbed_official | 121:7f86b4238bec | 3372 | /** Array initializer of PIT peripheral base pointers */ |
mbed_official | 121:7f86b4238bec | 3373 | #define PIT_BASE_PTRS { PIT } |
mbed_official | 121:7f86b4238bec | 3374 | /** Interrupt vectors for the PIT peripheral type */ |
mbed_official | 121:7f86b4238bec | 3375 | #define PIT_IRQS { PIT_IRQn, PIT_IRQn } |
mbed_official | 121:7f86b4238bec | 3376 | |
mbed_official | 121:7f86b4238bec | 3377 | /*! |
mbed_official | 121:7f86b4238bec | 3378 | * @} |
mbed_official | 121:7f86b4238bec | 3379 | */ /* end of group PIT_Peripheral_Access_Layer */ |
mbed_official | 121:7f86b4238bec | 3380 | |
mbed_official | 121:7f86b4238bec | 3381 | |
mbed_official | 121:7f86b4238bec | 3382 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 3383 | -- PMC Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 3384 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 3385 | |
mbed_official | 121:7f86b4238bec | 3386 | /*! |
mbed_official | 121:7f86b4238bec | 3387 | * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 3388 | * @{ |
mbed_official | 121:7f86b4238bec | 3389 | */ |
mbed_official | 121:7f86b4238bec | 3390 | |
mbed_official | 121:7f86b4238bec | 3391 | /** PMC - Register Layout Typedef */ |
mbed_official | 121:7f86b4238bec | 3392 | typedef struct { |
mbed_official | 121:7f86b4238bec | 3393 | __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */ |
mbed_official | 121:7f86b4238bec | 3394 | __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */ |
mbed_official | 121:7f86b4238bec | 3395 | __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */ |
mbed_official | 121:7f86b4238bec | 3396 | } PMC_Type; |
mbed_official | 121:7f86b4238bec | 3397 | |
mbed_official | 121:7f86b4238bec | 3398 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 3399 | -- PMC Register Masks |
mbed_official | 121:7f86b4238bec | 3400 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 3401 | |
mbed_official | 121:7f86b4238bec | 3402 | /*! |
mbed_official | 121:7f86b4238bec | 3403 | * @addtogroup PMC_Register_Masks PMC Register Masks |
mbed_official | 121:7f86b4238bec | 3404 | * @{ |
mbed_official | 121:7f86b4238bec | 3405 | */ |
mbed_official | 121:7f86b4238bec | 3406 | |
mbed_official | 121:7f86b4238bec | 3407 | /*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */ |
mbed_official | 121:7f86b4238bec | 3408 | #define PMC_LVDSC1_LVDV_MASK (0x3U) |
mbed_official | 121:7f86b4238bec | 3409 | #define PMC_LVDSC1_LVDV_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3410 | #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK) |
mbed_official | 121:7f86b4238bec | 3411 | #define PMC_LVDSC1_LVDRE_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 3412 | #define PMC_LVDSC1_LVDRE_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 3413 | #define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK) |
mbed_official | 121:7f86b4238bec | 3414 | #define PMC_LVDSC1_LVDIE_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 3415 | #define PMC_LVDSC1_LVDIE_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 3416 | #define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK) |
mbed_official | 121:7f86b4238bec | 3417 | #define PMC_LVDSC1_LVDACK_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 3418 | #define PMC_LVDSC1_LVDACK_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 3419 | #define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK) |
mbed_official | 121:7f86b4238bec | 3420 | #define PMC_LVDSC1_LVDF_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 3421 | #define PMC_LVDSC1_LVDF_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 3422 | #define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK) |
mbed_official | 121:7f86b4238bec | 3423 | |
mbed_official | 121:7f86b4238bec | 3424 | /*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */ |
mbed_official | 121:7f86b4238bec | 3425 | #define PMC_LVDSC2_LVWV_MASK (0x3U) |
mbed_official | 121:7f86b4238bec | 3426 | #define PMC_LVDSC2_LVWV_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3427 | #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK) |
mbed_official | 121:7f86b4238bec | 3428 | #define PMC_LVDSC2_LVWIE_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 3429 | #define PMC_LVDSC2_LVWIE_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 3430 | #define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK) |
mbed_official | 121:7f86b4238bec | 3431 | #define PMC_LVDSC2_LVWACK_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 3432 | #define PMC_LVDSC2_LVWACK_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 3433 | #define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK) |
mbed_official | 121:7f86b4238bec | 3434 | #define PMC_LVDSC2_LVWF_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 3435 | #define PMC_LVDSC2_LVWF_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 3436 | #define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK) |
mbed_official | 121:7f86b4238bec | 3437 | |
mbed_official | 121:7f86b4238bec | 3438 | /*! @name REGSC - Regulator Status And Control register */ |
mbed_official | 121:7f86b4238bec | 3439 | #define PMC_REGSC_BGBE_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 3440 | #define PMC_REGSC_BGBE_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3441 | #define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK) |
mbed_official | 121:7f86b4238bec | 3442 | #define PMC_REGSC_REGONS_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 3443 | #define PMC_REGSC_REGONS_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 3444 | #define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK) |
mbed_official | 121:7f86b4238bec | 3445 | #define PMC_REGSC_ACKISO_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 3446 | #define PMC_REGSC_ACKISO_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 3447 | #define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK) |
mbed_official | 121:7f86b4238bec | 3448 | #define PMC_REGSC_BGEN_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 3449 | #define PMC_REGSC_BGEN_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 3450 | #define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK) |
mbed_official | 121:7f86b4238bec | 3451 | #define PMC_REGSC_VLPO_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 3452 | #define PMC_REGSC_VLPO_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 3453 | #define PMC_REGSC_VLPO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_VLPO_SHIFT)) & PMC_REGSC_VLPO_MASK) |
mbed_official | 121:7f86b4238bec | 3454 | |
mbed_official | 121:7f86b4238bec | 3455 | |
mbed_official | 121:7f86b4238bec | 3456 | /*! |
mbed_official | 121:7f86b4238bec | 3457 | * @} |
mbed_official | 121:7f86b4238bec | 3458 | */ /* end of group PMC_Register_Masks */ |
mbed_official | 121:7f86b4238bec | 3459 | |
mbed_official | 121:7f86b4238bec | 3460 | |
mbed_official | 121:7f86b4238bec | 3461 | /* PMC - Peripheral instance base addresses */ |
mbed_official | 121:7f86b4238bec | 3462 | /** Peripheral PMC base address */ |
mbed_official | 121:7f86b4238bec | 3463 | #define PMC_BASE (0x4007D000u) |
mbed_official | 121:7f86b4238bec | 3464 | /** Peripheral PMC base pointer */ |
mbed_official | 121:7f86b4238bec | 3465 | #define PMC ((PMC_Type *)PMC_BASE) |
mbed_official | 121:7f86b4238bec | 3466 | /** Array initializer of PMC peripheral base addresses */ |
mbed_official | 121:7f86b4238bec | 3467 | #define PMC_BASE_ADDRS { PMC_BASE } |
mbed_official | 121:7f86b4238bec | 3468 | /** Array initializer of PMC peripheral base pointers */ |
mbed_official | 121:7f86b4238bec | 3469 | #define PMC_BASE_PTRS { PMC } |
mbed_official | 121:7f86b4238bec | 3470 | /** Interrupt vectors for the PMC peripheral type */ |
mbed_official | 121:7f86b4238bec | 3471 | #define PMC_IRQS { PMC_IRQn } |
mbed_official | 121:7f86b4238bec | 3472 | |
mbed_official | 121:7f86b4238bec | 3473 | /*! |
mbed_official | 121:7f86b4238bec | 3474 | * @} |
mbed_official | 121:7f86b4238bec | 3475 | */ /* end of group PMC_Peripheral_Access_Layer */ |
mbed_official | 121:7f86b4238bec | 3476 | |
mbed_official | 121:7f86b4238bec | 3477 | |
mbed_official | 121:7f86b4238bec | 3478 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 3479 | -- PORT Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 3480 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 3481 | |
mbed_official | 121:7f86b4238bec | 3482 | /*! |
mbed_official | 121:7f86b4238bec | 3483 | * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 3484 | * @{ |
mbed_official | 121:7f86b4238bec | 3485 | */ |
mbed_official | 121:7f86b4238bec | 3486 | |
mbed_official | 121:7f86b4238bec | 3487 | /** PORT - Register Layout Typedef */ |
mbed_official | 121:7f86b4238bec | 3488 | typedef struct { |
mbed_official | 121:7f86b4238bec | 3489 | __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */ |
mbed_official | 121:7f86b4238bec | 3490 | __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */ |
mbed_official | 121:7f86b4238bec | 3491 | __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */ |
mbed_official | 121:7f86b4238bec | 3492 | uint8_t RESERVED_0[24]; |
mbed_official | 121:7f86b4238bec | 3493 | __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */ |
mbed_official | 121:7f86b4238bec | 3494 | } PORT_Type; |
mbed_official | 121:7f86b4238bec | 3495 | |
mbed_official | 121:7f86b4238bec | 3496 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 3497 | -- PORT Register Masks |
mbed_official | 121:7f86b4238bec | 3498 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 3499 | |
mbed_official | 121:7f86b4238bec | 3500 | /*! |
mbed_official | 121:7f86b4238bec | 3501 | * @addtogroup PORT_Register_Masks PORT Register Masks |
mbed_official | 121:7f86b4238bec | 3502 | * @{ |
mbed_official | 121:7f86b4238bec | 3503 | */ |
mbed_official | 121:7f86b4238bec | 3504 | |
mbed_official | 121:7f86b4238bec | 3505 | /*! @name PCR - Pin Control Register n */ |
mbed_official | 121:7f86b4238bec | 3506 | #define PORT_PCR_PS_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 3507 | #define PORT_PCR_PS_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3508 | #define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK) |
mbed_official | 121:7f86b4238bec | 3509 | #define PORT_PCR_PE_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 3510 | #define PORT_PCR_PE_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 3511 | #define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK) |
mbed_official | 121:7f86b4238bec | 3512 | #define PORT_PCR_SRE_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 3513 | #define PORT_PCR_SRE_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 3514 | #define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK) |
mbed_official | 121:7f86b4238bec | 3515 | #define PORT_PCR_PFE_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 3516 | #define PORT_PCR_PFE_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 3517 | #define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK) |
mbed_official | 121:7f86b4238bec | 3518 | #define PORT_PCR_DSE_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 3519 | #define PORT_PCR_DSE_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 3520 | #define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK) |
mbed_official | 121:7f86b4238bec | 3521 | #define PORT_PCR_MUX_MASK (0x700U) |
mbed_official | 121:7f86b4238bec | 3522 | #define PORT_PCR_MUX_SHIFT (8U) |
mbed_official | 121:7f86b4238bec | 3523 | #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK) |
mbed_official | 121:7f86b4238bec | 3524 | #define PORT_PCR_IRQC_MASK (0xF0000U) |
mbed_official | 121:7f86b4238bec | 3525 | #define PORT_PCR_IRQC_SHIFT (16U) |
mbed_official | 121:7f86b4238bec | 3526 | #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK) |
mbed_official | 121:7f86b4238bec | 3527 | #define PORT_PCR_ISF_MASK (0x1000000U) |
mbed_official | 121:7f86b4238bec | 3528 | #define PORT_PCR_ISF_SHIFT (24U) |
mbed_official | 121:7f86b4238bec | 3529 | #define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK) |
mbed_official | 121:7f86b4238bec | 3530 | |
mbed_official | 121:7f86b4238bec | 3531 | /* The count of PORT_PCR */ |
mbed_official | 121:7f86b4238bec | 3532 | #define PORT_PCR_COUNT (32U) |
mbed_official | 121:7f86b4238bec | 3533 | |
mbed_official | 121:7f86b4238bec | 3534 | /*! @name GPCLR - Global Pin Control Low Register */ |
mbed_official | 121:7f86b4238bec | 3535 | #define PORT_GPCLR_GPWD_MASK (0xFFFFU) |
mbed_official | 121:7f86b4238bec | 3536 | #define PORT_GPCLR_GPWD_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3537 | #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK) |
mbed_official | 121:7f86b4238bec | 3538 | #define PORT_GPCLR_GPWE_MASK (0xFFFF0000U) |
mbed_official | 121:7f86b4238bec | 3539 | #define PORT_GPCLR_GPWE_SHIFT (16U) |
mbed_official | 121:7f86b4238bec | 3540 | #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK) |
mbed_official | 121:7f86b4238bec | 3541 | |
mbed_official | 121:7f86b4238bec | 3542 | /*! @name GPCHR - Global Pin Control High Register */ |
mbed_official | 121:7f86b4238bec | 3543 | #define PORT_GPCHR_GPWD_MASK (0xFFFFU) |
mbed_official | 121:7f86b4238bec | 3544 | #define PORT_GPCHR_GPWD_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3545 | #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK) |
mbed_official | 121:7f86b4238bec | 3546 | #define PORT_GPCHR_GPWE_MASK (0xFFFF0000U) |
mbed_official | 121:7f86b4238bec | 3547 | #define PORT_GPCHR_GPWE_SHIFT (16U) |
mbed_official | 121:7f86b4238bec | 3548 | #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK) |
mbed_official | 121:7f86b4238bec | 3549 | |
mbed_official | 121:7f86b4238bec | 3550 | /*! @name ISFR - Interrupt Status Flag Register */ |
mbed_official | 121:7f86b4238bec | 3551 | #define PORT_ISFR_ISF_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 3552 | #define PORT_ISFR_ISF_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3553 | #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK) |
mbed_official | 121:7f86b4238bec | 3554 | |
mbed_official | 121:7f86b4238bec | 3555 | |
mbed_official | 121:7f86b4238bec | 3556 | /*! |
mbed_official | 121:7f86b4238bec | 3557 | * @} |
mbed_official | 121:7f86b4238bec | 3558 | */ /* end of group PORT_Register_Masks */ |
mbed_official | 121:7f86b4238bec | 3559 | |
mbed_official | 121:7f86b4238bec | 3560 | |
mbed_official | 121:7f86b4238bec | 3561 | /* PORT - Peripheral instance base addresses */ |
mbed_official | 121:7f86b4238bec | 3562 | /** Peripheral PORTA base address */ |
mbed_official | 121:7f86b4238bec | 3563 | #define PORTA_BASE (0x40049000u) |
mbed_official | 121:7f86b4238bec | 3564 | /** Peripheral PORTA base pointer */ |
mbed_official | 121:7f86b4238bec | 3565 | #define PORTA ((PORT_Type *)PORTA_BASE) |
mbed_official | 121:7f86b4238bec | 3566 | /** Peripheral PORTB base address */ |
mbed_official | 121:7f86b4238bec | 3567 | #define PORTB_BASE (0x4004A000u) |
mbed_official | 121:7f86b4238bec | 3568 | /** Peripheral PORTB base pointer */ |
mbed_official | 121:7f86b4238bec | 3569 | #define PORTB ((PORT_Type *)PORTB_BASE) |
mbed_official | 121:7f86b4238bec | 3570 | /** Peripheral PORTC base address */ |
mbed_official | 121:7f86b4238bec | 3571 | #define PORTC_BASE (0x4004B000u) |
mbed_official | 121:7f86b4238bec | 3572 | /** Peripheral PORTC base pointer */ |
mbed_official | 121:7f86b4238bec | 3573 | #define PORTC ((PORT_Type *)PORTC_BASE) |
mbed_official | 121:7f86b4238bec | 3574 | /** Peripheral PORTD base address */ |
mbed_official | 121:7f86b4238bec | 3575 | #define PORTD_BASE (0x4004C000u) |
mbed_official | 121:7f86b4238bec | 3576 | /** Peripheral PORTD base pointer */ |
mbed_official | 121:7f86b4238bec | 3577 | #define PORTD ((PORT_Type *)PORTD_BASE) |
mbed_official | 121:7f86b4238bec | 3578 | /** Peripheral PORTE base address */ |
mbed_official | 121:7f86b4238bec | 3579 | #define PORTE_BASE (0x4004D000u) |
mbed_official | 121:7f86b4238bec | 3580 | /** Peripheral PORTE base pointer */ |
mbed_official | 121:7f86b4238bec | 3581 | #define PORTE ((PORT_Type *)PORTE_BASE) |
mbed_official | 121:7f86b4238bec | 3582 | /** Array initializer of PORT peripheral base addresses */ |
mbed_official | 121:7f86b4238bec | 3583 | #define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE } |
mbed_official | 121:7f86b4238bec | 3584 | /** Array initializer of PORT peripheral base pointers */ |
mbed_official | 121:7f86b4238bec | 3585 | #define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE } |
mbed_official | 121:7f86b4238bec | 3586 | /** Interrupt vectors for the PORT peripheral type */ |
mbed_official | 121:7f86b4238bec | 3587 | #define PORT_IRQS { PORTA_IRQn, PORTB_PORTC_PORTD_PORTE_IRQn, PORTB_PORTC_PORTD_PORTE_IRQn, PORTB_PORTC_PORTD_PORTE_IRQn, PORTB_PORTC_PORTD_PORTE_IRQn } |
mbed_official | 121:7f86b4238bec | 3588 | |
mbed_official | 121:7f86b4238bec | 3589 | /*! |
mbed_official | 121:7f86b4238bec | 3590 | * @} |
mbed_official | 121:7f86b4238bec | 3591 | */ /* end of group PORT_Peripheral_Access_Layer */ |
mbed_official | 121:7f86b4238bec | 3592 | |
mbed_official | 121:7f86b4238bec | 3593 | |
mbed_official | 121:7f86b4238bec | 3594 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 3595 | -- RCM Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 3596 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 3597 | |
mbed_official | 121:7f86b4238bec | 3598 | /*! |
mbed_official | 121:7f86b4238bec | 3599 | * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 3600 | * @{ |
mbed_official | 121:7f86b4238bec | 3601 | */ |
mbed_official | 121:7f86b4238bec | 3602 | |
mbed_official | 121:7f86b4238bec | 3603 | /** RCM - Register Layout Typedef */ |
mbed_official | 121:7f86b4238bec | 3604 | typedef struct { |
mbed_official | 121:7f86b4238bec | 3605 | __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */ |
mbed_official | 121:7f86b4238bec | 3606 | __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */ |
mbed_official | 121:7f86b4238bec | 3607 | uint8_t RESERVED_0[2]; |
mbed_official | 121:7f86b4238bec | 3608 | __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */ |
mbed_official | 121:7f86b4238bec | 3609 | __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */ |
mbed_official | 121:7f86b4238bec | 3610 | __IO uint8_t FM; /**< Force Mode Register, offset: 0x6 */ |
mbed_official | 121:7f86b4238bec | 3611 | __IO uint8_t MR; /**< Mode Register, offset: 0x7 */ |
mbed_official | 121:7f86b4238bec | 3612 | __IO uint8_t SSRS0; /**< Sticky System Reset Status Register 0, offset: 0x8 */ |
mbed_official | 121:7f86b4238bec | 3613 | __IO uint8_t SSRS1; /**< Sticky System Reset Status Register 1, offset: 0x9 */ |
mbed_official | 121:7f86b4238bec | 3614 | } RCM_Type; |
mbed_official | 121:7f86b4238bec | 3615 | |
mbed_official | 121:7f86b4238bec | 3616 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 3617 | -- RCM Register Masks |
mbed_official | 121:7f86b4238bec | 3618 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 3619 | |
mbed_official | 121:7f86b4238bec | 3620 | /*! |
mbed_official | 121:7f86b4238bec | 3621 | * @addtogroup RCM_Register_Masks RCM Register Masks |
mbed_official | 121:7f86b4238bec | 3622 | * @{ |
mbed_official | 121:7f86b4238bec | 3623 | */ |
mbed_official | 121:7f86b4238bec | 3624 | |
mbed_official | 121:7f86b4238bec | 3625 | /*! @name SRS0 - System Reset Status Register 0 */ |
mbed_official | 121:7f86b4238bec | 3626 | #define RCM_SRS0_WAKEUP_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 3627 | #define RCM_SRS0_WAKEUP_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3628 | #define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK) |
mbed_official | 121:7f86b4238bec | 3629 | #define RCM_SRS0_LVD_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 3630 | #define RCM_SRS0_LVD_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 3631 | #define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK) |
mbed_official | 121:7f86b4238bec | 3632 | #define RCM_SRS0_WDOG_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 3633 | #define RCM_SRS0_WDOG_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 3634 | #define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK) |
mbed_official | 121:7f86b4238bec | 3635 | #define RCM_SRS0_PIN_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 3636 | #define RCM_SRS0_PIN_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 3637 | #define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK) |
mbed_official | 121:7f86b4238bec | 3638 | #define RCM_SRS0_POR_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 3639 | #define RCM_SRS0_POR_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 3640 | #define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK) |
mbed_official | 121:7f86b4238bec | 3641 | |
mbed_official | 121:7f86b4238bec | 3642 | /*! @name SRS1 - System Reset Status Register 1 */ |
mbed_official | 121:7f86b4238bec | 3643 | #define RCM_SRS1_LOCKUP_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 3644 | #define RCM_SRS1_LOCKUP_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 3645 | #define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK) |
mbed_official | 121:7f86b4238bec | 3646 | #define RCM_SRS1_SW_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 3647 | #define RCM_SRS1_SW_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 3648 | #define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK) |
mbed_official | 121:7f86b4238bec | 3649 | #define RCM_SRS1_MDM_AP_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 3650 | #define RCM_SRS1_MDM_AP_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 3651 | #define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK) |
mbed_official | 121:7f86b4238bec | 3652 | #define RCM_SRS1_SACKERR_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 3653 | #define RCM_SRS1_SACKERR_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 3654 | #define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK) |
mbed_official | 121:7f86b4238bec | 3655 | |
mbed_official | 121:7f86b4238bec | 3656 | /*! @name RPFC - Reset Pin Filter Control register */ |
mbed_official | 121:7f86b4238bec | 3657 | #define RCM_RPFC_RSTFLTSRW_MASK (0x3U) |
mbed_official | 121:7f86b4238bec | 3658 | #define RCM_RPFC_RSTFLTSRW_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3659 | #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK) |
mbed_official | 121:7f86b4238bec | 3660 | #define RCM_RPFC_RSTFLTSS_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 3661 | #define RCM_RPFC_RSTFLTSS_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 3662 | #define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK) |
mbed_official | 121:7f86b4238bec | 3663 | |
mbed_official | 121:7f86b4238bec | 3664 | /*! @name RPFW - Reset Pin Filter Width register */ |
mbed_official | 121:7f86b4238bec | 3665 | #define RCM_RPFW_RSTFLTSEL_MASK (0x1FU) |
mbed_official | 121:7f86b4238bec | 3666 | #define RCM_RPFW_RSTFLTSEL_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3667 | #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK) |
mbed_official | 121:7f86b4238bec | 3668 | |
mbed_official | 121:7f86b4238bec | 3669 | /*! @name FM - Force Mode Register */ |
mbed_official | 121:7f86b4238bec | 3670 | #define RCM_FM_FORCEROM_MASK (0x6U) |
mbed_official | 121:7f86b4238bec | 3671 | #define RCM_FM_FORCEROM_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 3672 | #define RCM_FM_FORCEROM(x) (((uint8_t)(((uint8_t)(x)) << RCM_FM_FORCEROM_SHIFT)) & RCM_FM_FORCEROM_MASK) |
mbed_official | 121:7f86b4238bec | 3673 | |
mbed_official | 121:7f86b4238bec | 3674 | /*! @name MR - Mode Register */ |
mbed_official | 121:7f86b4238bec | 3675 | #define RCM_MR_BOOTROM_MASK (0x6U) |
mbed_official | 121:7f86b4238bec | 3676 | #define RCM_MR_BOOTROM_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 3677 | #define RCM_MR_BOOTROM(x) (((uint8_t)(((uint8_t)(x)) << RCM_MR_BOOTROM_SHIFT)) & RCM_MR_BOOTROM_MASK) |
mbed_official | 121:7f86b4238bec | 3678 | |
mbed_official | 121:7f86b4238bec | 3679 | /*! @name SSRS0 - Sticky System Reset Status Register 0 */ |
mbed_official | 121:7f86b4238bec | 3680 | #define RCM_SSRS0_SWAKEUP_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 3681 | #define RCM_SSRS0_SWAKEUP_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3682 | #define RCM_SSRS0_SWAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWAKEUP_SHIFT)) & RCM_SSRS0_SWAKEUP_MASK) |
mbed_official | 121:7f86b4238bec | 3683 | #define RCM_SSRS0_SLVD_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 3684 | #define RCM_SSRS0_SLVD_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 3685 | #define RCM_SSRS0_SLVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLVD_SHIFT)) & RCM_SSRS0_SLVD_MASK) |
mbed_official | 121:7f86b4238bec | 3686 | #define RCM_SSRS0_SWDOG_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 3687 | #define RCM_SSRS0_SWDOG_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 3688 | #define RCM_SSRS0_SWDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWDOG_SHIFT)) & RCM_SSRS0_SWDOG_MASK) |
mbed_official | 121:7f86b4238bec | 3689 | #define RCM_SSRS0_SPIN_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 3690 | #define RCM_SSRS0_SPIN_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 3691 | #define RCM_SSRS0_SPIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPIN_SHIFT)) & RCM_SSRS0_SPIN_MASK) |
mbed_official | 121:7f86b4238bec | 3692 | #define RCM_SSRS0_SPOR_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 3693 | #define RCM_SSRS0_SPOR_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 3694 | #define RCM_SSRS0_SPOR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPOR_SHIFT)) & RCM_SSRS0_SPOR_MASK) |
mbed_official | 121:7f86b4238bec | 3695 | |
mbed_official | 121:7f86b4238bec | 3696 | /*! @name SSRS1 - Sticky System Reset Status Register 1 */ |
mbed_official | 121:7f86b4238bec | 3697 | #define RCM_SSRS1_SLOCKUP_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 3698 | #define RCM_SSRS1_SLOCKUP_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 3699 | #define RCM_SSRS1_SLOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SLOCKUP_SHIFT)) & RCM_SSRS1_SLOCKUP_MASK) |
mbed_official | 121:7f86b4238bec | 3700 | #define RCM_SSRS1_SSW_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 3701 | #define RCM_SSRS1_SSW_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 3702 | #define RCM_SSRS1_SSW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSW_SHIFT)) & RCM_SSRS1_SSW_MASK) |
mbed_official | 121:7f86b4238bec | 3703 | #define RCM_SSRS1_SMDM_AP_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 3704 | #define RCM_SSRS1_SMDM_AP_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 3705 | #define RCM_SSRS1_SMDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SMDM_AP_SHIFT)) & RCM_SSRS1_SMDM_AP_MASK) |
mbed_official | 121:7f86b4238bec | 3706 | #define RCM_SSRS1_SSACKERR_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 3707 | #define RCM_SSRS1_SSACKERR_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 3708 | #define RCM_SSRS1_SSACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSACKERR_SHIFT)) & RCM_SSRS1_SSACKERR_MASK) |
mbed_official | 121:7f86b4238bec | 3709 | |
mbed_official | 121:7f86b4238bec | 3710 | |
mbed_official | 121:7f86b4238bec | 3711 | /*! |
mbed_official | 121:7f86b4238bec | 3712 | * @} |
mbed_official | 121:7f86b4238bec | 3713 | */ /* end of group RCM_Register_Masks */ |
mbed_official | 121:7f86b4238bec | 3714 | |
mbed_official | 121:7f86b4238bec | 3715 | |
mbed_official | 121:7f86b4238bec | 3716 | /* RCM - Peripheral instance base addresses */ |
mbed_official | 121:7f86b4238bec | 3717 | /** Peripheral RCM base address */ |
mbed_official | 121:7f86b4238bec | 3718 | #define RCM_BASE (0x4007F000u) |
mbed_official | 121:7f86b4238bec | 3719 | /** Peripheral RCM base pointer */ |
mbed_official | 121:7f86b4238bec | 3720 | #define RCM ((RCM_Type *)RCM_BASE) |
mbed_official | 121:7f86b4238bec | 3721 | /** Array initializer of RCM peripheral base addresses */ |
mbed_official | 121:7f86b4238bec | 3722 | #define RCM_BASE_ADDRS { RCM_BASE } |
mbed_official | 121:7f86b4238bec | 3723 | /** Array initializer of RCM peripheral base pointers */ |
mbed_official | 121:7f86b4238bec | 3724 | #define RCM_BASE_PTRS { RCM } |
mbed_official | 121:7f86b4238bec | 3725 | |
mbed_official | 121:7f86b4238bec | 3726 | /*! |
mbed_official | 121:7f86b4238bec | 3727 | * @} |
mbed_official | 121:7f86b4238bec | 3728 | */ /* end of group RCM_Peripheral_Access_Layer */ |
mbed_official | 121:7f86b4238bec | 3729 | |
mbed_official | 121:7f86b4238bec | 3730 | |
mbed_official | 121:7f86b4238bec | 3731 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 3732 | -- RFSYS Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 3733 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 3734 | |
mbed_official | 121:7f86b4238bec | 3735 | /*! |
mbed_official | 121:7f86b4238bec | 3736 | * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 3737 | * @{ |
mbed_official | 121:7f86b4238bec | 3738 | */ |
mbed_official | 121:7f86b4238bec | 3739 | |
mbed_official | 121:7f86b4238bec | 3740 | /** RFSYS - Register Layout Typedef */ |
mbed_official | 121:7f86b4238bec | 3741 | typedef struct { |
mbed_official | 121:7f86b4238bec | 3742 | __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */ |
mbed_official | 121:7f86b4238bec | 3743 | } RFSYS_Type; |
mbed_official | 121:7f86b4238bec | 3744 | |
mbed_official | 121:7f86b4238bec | 3745 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 3746 | -- RFSYS Register Masks |
mbed_official | 121:7f86b4238bec | 3747 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 3748 | |
mbed_official | 121:7f86b4238bec | 3749 | /*! |
mbed_official | 121:7f86b4238bec | 3750 | * @addtogroup RFSYS_Register_Masks RFSYS Register Masks |
mbed_official | 121:7f86b4238bec | 3751 | * @{ |
mbed_official | 121:7f86b4238bec | 3752 | */ |
mbed_official | 121:7f86b4238bec | 3753 | |
mbed_official | 121:7f86b4238bec | 3754 | /*! @name REG - Register file register */ |
mbed_official | 121:7f86b4238bec | 3755 | #define RFSYS_REG_LL_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 3756 | #define RFSYS_REG_LL_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3757 | #define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK) |
mbed_official | 121:7f86b4238bec | 3758 | #define RFSYS_REG_LH_MASK (0xFF00U) |
mbed_official | 121:7f86b4238bec | 3759 | #define RFSYS_REG_LH_SHIFT (8U) |
mbed_official | 121:7f86b4238bec | 3760 | #define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK) |
mbed_official | 121:7f86b4238bec | 3761 | #define RFSYS_REG_HL_MASK (0xFF0000U) |
mbed_official | 121:7f86b4238bec | 3762 | #define RFSYS_REG_HL_SHIFT (16U) |
mbed_official | 121:7f86b4238bec | 3763 | #define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK) |
mbed_official | 121:7f86b4238bec | 3764 | #define RFSYS_REG_HH_MASK (0xFF000000U) |
mbed_official | 121:7f86b4238bec | 3765 | #define RFSYS_REG_HH_SHIFT (24U) |
mbed_official | 121:7f86b4238bec | 3766 | #define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK) |
mbed_official | 121:7f86b4238bec | 3767 | |
mbed_official | 121:7f86b4238bec | 3768 | /* The count of RFSYS_REG */ |
mbed_official | 121:7f86b4238bec | 3769 | #define RFSYS_REG_COUNT (8U) |
mbed_official | 121:7f86b4238bec | 3770 | |
mbed_official | 121:7f86b4238bec | 3771 | |
mbed_official | 121:7f86b4238bec | 3772 | /*! |
mbed_official | 121:7f86b4238bec | 3773 | * @} |
mbed_official | 121:7f86b4238bec | 3774 | */ /* end of group RFSYS_Register_Masks */ |
mbed_official | 121:7f86b4238bec | 3775 | |
mbed_official | 121:7f86b4238bec | 3776 | |
mbed_official | 121:7f86b4238bec | 3777 | /* RFSYS - Peripheral instance base addresses */ |
mbed_official | 121:7f86b4238bec | 3778 | /** Peripheral RFSYS base address */ |
mbed_official | 121:7f86b4238bec | 3779 | #define RFSYS_BASE (0x40041000u) |
mbed_official | 121:7f86b4238bec | 3780 | /** Peripheral RFSYS base pointer */ |
mbed_official | 121:7f86b4238bec | 3781 | #define RFSYS ((RFSYS_Type *)RFSYS_BASE) |
mbed_official | 121:7f86b4238bec | 3782 | /** Array initializer of RFSYS peripheral base addresses */ |
mbed_official | 121:7f86b4238bec | 3783 | #define RFSYS_BASE_ADDRS { RFSYS_BASE } |
mbed_official | 121:7f86b4238bec | 3784 | /** Array initializer of RFSYS peripheral base pointers */ |
mbed_official | 121:7f86b4238bec | 3785 | #define RFSYS_BASE_PTRS { RFSYS } |
mbed_official | 121:7f86b4238bec | 3786 | |
mbed_official | 121:7f86b4238bec | 3787 | /*! |
mbed_official | 121:7f86b4238bec | 3788 | * @} |
mbed_official | 121:7f86b4238bec | 3789 | */ /* end of group RFSYS_Peripheral_Access_Layer */ |
mbed_official | 121:7f86b4238bec | 3790 | |
mbed_official | 121:7f86b4238bec | 3791 | |
mbed_official | 121:7f86b4238bec | 3792 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 3793 | -- ROM Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 3794 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 3795 | |
mbed_official | 121:7f86b4238bec | 3796 | /*! |
mbed_official | 121:7f86b4238bec | 3797 | * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 3798 | * @{ |
mbed_official | 121:7f86b4238bec | 3799 | */ |
mbed_official | 121:7f86b4238bec | 3800 | |
mbed_official | 121:7f86b4238bec | 3801 | /** ROM - Register Layout Typedef */ |
mbed_official | 121:7f86b4238bec | 3802 | typedef struct { |
mbed_official | 121:7f86b4238bec | 3803 | __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */ |
mbed_official | 121:7f86b4238bec | 3804 | __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */ |
mbed_official | 121:7f86b4238bec | 3805 | uint8_t RESERVED_0[4028]; |
mbed_official | 121:7f86b4238bec | 3806 | __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */ |
mbed_official | 121:7f86b4238bec | 3807 | __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */ |
mbed_official | 121:7f86b4238bec | 3808 | __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */ |
mbed_official | 121:7f86b4238bec | 3809 | __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */ |
mbed_official | 121:7f86b4238bec | 3810 | __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */ |
mbed_official | 121:7f86b4238bec | 3811 | __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */ |
mbed_official | 121:7f86b4238bec | 3812 | __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */ |
mbed_official | 121:7f86b4238bec | 3813 | __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */ |
mbed_official | 121:7f86b4238bec | 3814 | __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */ |
mbed_official | 121:7f86b4238bec | 3815 | __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ |
mbed_official | 121:7f86b4238bec | 3816 | } ROM_Type; |
mbed_official | 121:7f86b4238bec | 3817 | |
mbed_official | 121:7f86b4238bec | 3818 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 3819 | -- ROM Register Masks |
mbed_official | 121:7f86b4238bec | 3820 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 3821 | |
mbed_official | 121:7f86b4238bec | 3822 | /*! |
mbed_official | 121:7f86b4238bec | 3823 | * @addtogroup ROM_Register_Masks ROM Register Masks |
mbed_official | 121:7f86b4238bec | 3824 | * @{ |
mbed_official | 121:7f86b4238bec | 3825 | */ |
mbed_official | 121:7f86b4238bec | 3826 | |
mbed_official | 121:7f86b4238bec | 3827 | /*! @name ENTRY - Entry */ |
mbed_official | 121:7f86b4238bec | 3828 | #define ROM_ENTRY_ENTRY_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 3829 | #define ROM_ENTRY_ENTRY_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3830 | #define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x)) << ROM_ENTRY_ENTRY_SHIFT)) & ROM_ENTRY_ENTRY_MASK) |
mbed_official | 121:7f86b4238bec | 3831 | |
mbed_official | 121:7f86b4238bec | 3832 | /* The count of ROM_ENTRY */ |
mbed_official | 121:7f86b4238bec | 3833 | #define ROM_ENTRY_COUNT (3U) |
mbed_official | 121:7f86b4238bec | 3834 | |
mbed_official | 121:7f86b4238bec | 3835 | /*! @name TABLEMARK - End of Table Marker Register */ |
mbed_official | 121:7f86b4238bec | 3836 | #define ROM_TABLEMARK_MARK_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 3837 | #define ROM_TABLEMARK_MARK_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3838 | #define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x)) << ROM_TABLEMARK_MARK_SHIFT)) & ROM_TABLEMARK_MARK_MASK) |
mbed_official | 121:7f86b4238bec | 3839 | |
mbed_official | 121:7f86b4238bec | 3840 | /*! @name SYSACCESS - System Access Register */ |
mbed_official | 121:7f86b4238bec | 3841 | #define ROM_SYSACCESS_SYSACCESS_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 3842 | #define ROM_SYSACCESS_SYSACCESS_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3843 | #define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x)) << ROM_SYSACCESS_SYSACCESS_SHIFT)) & ROM_SYSACCESS_SYSACCESS_MASK) |
mbed_official | 121:7f86b4238bec | 3844 | |
mbed_official | 121:7f86b4238bec | 3845 | /*! @name PERIPHID4 - Peripheral ID Register */ |
mbed_official | 121:7f86b4238bec | 3846 | #define ROM_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 3847 | #define ROM_PERIPHID4_PERIPHID_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3848 | #define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID4_PERIPHID_SHIFT)) & ROM_PERIPHID4_PERIPHID_MASK) |
mbed_official | 121:7f86b4238bec | 3849 | |
mbed_official | 121:7f86b4238bec | 3850 | /*! @name PERIPHID5 - Peripheral ID Register */ |
mbed_official | 121:7f86b4238bec | 3851 | #define ROM_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 3852 | #define ROM_PERIPHID5_PERIPHID_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3853 | #define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID5_PERIPHID_SHIFT)) & ROM_PERIPHID5_PERIPHID_MASK) |
mbed_official | 121:7f86b4238bec | 3854 | |
mbed_official | 121:7f86b4238bec | 3855 | /*! @name PERIPHID6 - Peripheral ID Register */ |
mbed_official | 121:7f86b4238bec | 3856 | #define ROM_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 3857 | #define ROM_PERIPHID6_PERIPHID_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3858 | #define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID6_PERIPHID_SHIFT)) & ROM_PERIPHID6_PERIPHID_MASK) |
mbed_official | 121:7f86b4238bec | 3859 | |
mbed_official | 121:7f86b4238bec | 3860 | /*! @name PERIPHID7 - Peripheral ID Register */ |
mbed_official | 121:7f86b4238bec | 3861 | #define ROM_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 3862 | #define ROM_PERIPHID7_PERIPHID_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3863 | #define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID7_PERIPHID_SHIFT)) & ROM_PERIPHID7_PERIPHID_MASK) |
mbed_official | 121:7f86b4238bec | 3864 | |
mbed_official | 121:7f86b4238bec | 3865 | /*! @name PERIPHID0 - Peripheral ID Register */ |
mbed_official | 121:7f86b4238bec | 3866 | #define ROM_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 3867 | #define ROM_PERIPHID0_PERIPHID_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3868 | #define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID0_PERIPHID_SHIFT)) & ROM_PERIPHID0_PERIPHID_MASK) |
mbed_official | 121:7f86b4238bec | 3869 | |
mbed_official | 121:7f86b4238bec | 3870 | /*! @name PERIPHID1 - Peripheral ID Register */ |
mbed_official | 121:7f86b4238bec | 3871 | #define ROM_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 3872 | #define ROM_PERIPHID1_PERIPHID_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3873 | #define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID1_PERIPHID_SHIFT)) & ROM_PERIPHID1_PERIPHID_MASK) |
mbed_official | 121:7f86b4238bec | 3874 | |
mbed_official | 121:7f86b4238bec | 3875 | /*! @name PERIPHID2 - Peripheral ID Register */ |
mbed_official | 121:7f86b4238bec | 3876 | #define ROM_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 3877 | #define ROM_PERIPHID2_PERIPHID_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3878 | #define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID2_PERIPHID_SHIFT)) & ROM_PERIPHID2_PERIPHID_MASK) |
mbed_official | 121:7f86b4238bec | 3879 | |
mbed_official | 121:7f86b4238bec | 3880 | /*! @name PERIPHID3 - Peripheral ID Register */ |
mbed_official | 121:7f86b4238bec | 3881 | #define ROM_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 3882 | #define ROM_PERIPHID3_PERIPHID_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3883 | #define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID3_PERIPHID_SHIFT)) & ROM_PERIPHID3_PERIPHID_MASK) |
mbed_official | 121:7f86b4238bec | 3884 | |
mbed_official | 121:7f86b4238bec | 3885 | /*! @name COMPID - Component ID Register */ |
mbed_official | 121:7f86b4238bec | 3886 | #define ROM_COMPID_COMPID_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 3887 | #define ROM_COMPID_COMPID_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3888 | #define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << ROM_COMPID_COMPID_SHIFT)) & ROM_COMPID_COMPID_MASK) |
mbed_official | 121:7f86b4238bec | 3889 | |
mbed_official | 121:7f86b4238bec | 3890 | /* The count of ROM_COMPID */ |
mbed_official | 121:7f86b4238bec | 3891 | #define ROM_COMPID_COUNT (4U) |
mbed_official | 121:7f86b4238bec | 3892 | |
mbed_official | 121:7f86b4238bec | 3893 | |
mbed_official | 121:7f86b4238bec | 3894 | /*! |
mbed_official | 121:7f86b4238bec | 3895 | * @} |
mbed_official | 121:7f86b4238bec | 3896 | */ /* end of group ROM_Register_Masks */ |
mbed_official | 121:7f86b4238bec | 3897 | |
mbed_official | 121:7f86b4238bec | 3898 | |
mbed_official | 121:7f86b4238bec | 3899 | /* ROM - Peripheral instance base addresses */ |
mbed_official | 121:7f86b4238bec | 3900 | /** Peripheral ROM base address */ |
mbed_official | 121:7f86b4238bec | 3901 | #define ROM_BASE (0xF0002000u) |
mbed_official | 121:7f86b4238bec | 3902 | /** Peripheral ROM base pointer */ |
mbed_official | 121:7f86b4238bec | 3903 | #define ROM ((ROM_Type *)ROM_BASE) |
mbed_official | 121:7f86b4238bec | 3904 | /** Array initializer of ROM peripheral base addresses */ |
mbed_official | 121:7f86b4238bec | 3905 | #define ROM_BASE_ADDRS { ROM_BASE } |
mbed_official | 121:7f86b4238bec | 3906 | /** Array initializer of ROM peripheral base pointers */ |
mbed_official | 121:7f86b4238bec | 3907 | #define ROM_BASE_PTRS { ROM } |
mbed_official | 121:7f86b4238bec | 3908 | |
mbed_official | 121:7f86b4238bec | 3909 | /*! |
mbed_official | 121:7f86b4238bec | 3910 | * @} |
mbed_official | 121:7f86b4238bec | 3911 | */ /* end of group ROM_Peripheral_Access_Layer */ |
mbed_official | 121:7f86b4238bec | 3912 | |
mbed_official | 121:7f86b4238bec | 3913 | |
mbed_official | 121:7f86b4238bec | 3914 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 3915 | -- RTC Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 3916 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 3917 | |
mbed_official | 121:7f86b4238bec | 3918 | /*! |
mbed_official | 121:7f86b4238bec | 3919 | * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 3920 | * @{ |
mbed_official | 121:7f86b4238bec | 3921 | */ |
mbed_official | 121:7f86b4238bec | 3922 | |
mbed_official | 121:7f86b4238bec | 3923 | /** RTC - Register Layout Typedef */ |
mbed_official | 121:7f86b4238bec | 3924 | typedef struct { |
mbed_official | 121:7f86b4238bec | 3925 | __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */ |
mbed_official | 121:7f86b4238bec | 3926 | __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */ |
mbed_official | 121:7f86b4238bec | 3927 | __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */ |
mbed_official | 121:7f86b4238bec | 3928 | __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */ |
mbed_official | 121:7f86b4238bec | 3929 | __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */ |
mbed_official | 121:7f86b4238bec | 3930 | __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */ |
mbed_official | 121:7f86b4238bec | 3931 | __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */ |
mbed_official | 121:7f86b4238bec | 3932 | __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */ |
mbed_official | 121:7f86b4238bec | 3933 | } RTC_Type; |
mbed_official | 121:7f86b4238bec | 3934 | |
mbed_official | 121:7f86b4238bec | 3935 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 3936 | -- RTC Register Masks |
mbed_official | 121:7f86b4238bec | 3937 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 3938 | |
mbed_official | 121:7f86b4238bec | 3939 | /*! |
mbed_official | 121:7f86b4238bec | 3940 | * @addtogroup RTC_Register_Masks RTC Register Masks |
mbed_official | 121:7f86b4238bec | 3941 | * @{ |
mbed_official | 121:7f86b4238bec | 3942 | */ |
mbed_official | 121:7f86b4238bec | 3943 | |
mbed_official | 121:7f86b4238bec | 3944 | /*! @name TSR - RTC Time Seconds Register */ |
mbed_official | 121:7f86b4238bec | 3945 | #define RTC_TSR_TSR_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 3946 | #define RTC_TSR_TSR_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3947 | #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK) |
mbed_official | 121:7f86b4238bec | 3948 | |
mbed_official | 121:7f86b4238bec | 3949 | /*! @name TPR - RTC Time Prescaler Register */ |
mbed_official | 121:7f86b4238bec | 3950 | #define RTC_TPR_TPR_MASK (0xFFFFU) |
mbed_official | 121:7f86b4238bec | 3951 | #define RTC_TPR_TPR_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3952 | #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK) |
mbed_official | 121:7f86b4238bec | 3953 | |
mbed_official | 121:7f86b4238bec | 3954 | /*! @name TAR - RTC Time Alarm Register */ |
mbed_official | 121:7f86b4238bec | 3955 | #define RTC_TAR_TAR_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 3956 | #define RTC_TAR_TAR_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3957 | #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK) |
mbed_official | 121:7f86b4238bec | 3958 | |
mbed_official | 121:7f86b4238bec | 3959 | /*! @name TCR - RTC Time Compensation Register */ |
mbed_official | 121:7f86b4238bec | 3960 | #define RTC_TCR_TCR_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 3961 | #define RTC_TCR_TCR_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3962 | #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK) |
mbed_official | 121:7f86b4238bec | 3963 | #define RTC_TCR_CIR_MASK (0xFF00U) |
mbed_official | 121:7f86b4238bec | 3964 | #define RTC_TCR_CIR_SHIFT (8U) |
mbed_official | 121:7f86b4238bec | 3965 | #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK) |
mbed_official | 121:7f86b4238bec | 3966 | #define RTC_TCR_TCV_MASK (0xFF0000U) |
mbed_official | 121:7f86b4238bec | 3967 | #define RTC_TCR_TCV_SHIFT (16U) |
mbed_official | 121:7f86b4238bec | 3968 | #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK) |
mbed_official | 121:7f86b4238bec | 3969 | #define RTC_TCR_CIC_MASK (0xFF000000U) |
mbed_official | 121:7f86b4238bec | 3970 | #define RTC_TCR_CIC_SHIFT (24U) |
mbed_official | 121:7f86b4238bec | 3971 | #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK) |
mbed_official | 121:7f86b4238bec | 3972 | |
mbed_official | 121:7f86b4238bec | 3973 | /*! @name CR - RTC Control Register */ |
mbed_official | 121:7f86b4238bec | 3974 | #define RTC_CR_SWR_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 3975 | #define RTC_CR_SWR_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 3976 | #define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK) |
mbed_official | 121:7f86b4238bec | 3977 | #define RTC_CR_WPE_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 3978 | #define RTC_CR_WPE_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 3979 | #define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK) |
mbed_official | 121:7f86b4238bec | 3980 | #define RTC_CR_SUP_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 3981 | #define RTC_CR_SUP_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 3982 | #define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK) |
mbed_official | 121:7f86b4238bec | 3983 | #define RTC_CR_UM_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 3984 | #define RTC_CR_UM_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 3985 | #define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK) |
mbed_official | 121:7f86b4238bec | 3986 | #define RTC_CR_WPS_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 3987 | #define RTC_CR_WPS_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 3988 | #define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK) |
mbed_official | 121:7f86b4238bec | 3989 | #define RTC_CR_OSCE_MASK (0x100U) |
mbed_official | 121:7f86b4238bec | 3990 | #define RTC_CR_OSCE_SHIFT (8U) |
mbed_official | 121:7f86b4238bec | 3991 | #define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK) |
mbed_official | 121:7f86b4238bec | 3992 | #define RTC_CR_CLKO_MASK (0x200U) |
mbed_official | 121:7f86b4238bec | 3993 | #define RTC_CR_CLKO_SHIFT (9U) |
mbed_official | 121:7f86b4238bec | 3994 | #define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK) |
mbed_official | 121:7f86b4238bec | 3995 | #define RTC_CR_SC16P_MASK (0x400U) |
mbed_official | 121:7f86b4238bec | 3996 | #define RTC_CR_SC16P_SHIFT (10U) |
mbed_official | 121:7f86b4238bec | 3997 | #define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK) |
mbed_official | 121:7f86b4238bec | 3998 | #define RTC_CR_SC8P_MASK (0x800U) |
mbed_official | 121:7f86b4238bec | 3999 | #define RTC_CR_SC8P_SHIFT (11U) |
mbed_official | 121:7f86b4238bec | 4000 | #define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK) |
mbed_official | 121:7f86b4238bec | 4001 | #define RTC_CR_SC4P_MASK (0x1000U) |
mbed_official | 121:7f86b4238bec | 4002 | #define RTC_CR_SC4P_SHIFT (12U) |
mbed_official | 121:7f86b4238bec | 4003 | #define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK) |
mbed_official | 121:7f86b4238bec | 4004 | #define RTC_CR_SC2P_MASK (0x2000U) |
mbed_official | 121:7f86b4238bec | 4005 | #define RTC_CR_SC2P_SHIFT (13U) |
mbed_official | 121:7f86b4238bec | 4006 | #define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK) |
mbed_official | 121:7f86b4238bec | 4007 | |
mbed_official | 121:7f86b4238bec | 4008 | /*! @name SR - RTC Status Register */ |
mbed_official | 121:7f86b4238bec | 4009 | #define RTC_SR_TIF_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 4010 | #define RTC_SR_TIF_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 4011 | #define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK) |
mbed_official | 121:7f86b4238bec | 4012 | #define RTC_SR_TOF_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 4013 | #define RTC_SR_TOF_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 4014 | #define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK) |
mbed_official | 121:7f86b4238bec | 4015 | #define RTC_SR_TAF_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 4016 | #define RTC_SR_TAF_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 4017 | #define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK) |
mbed_official | 121:7f86b4238bec | 4018 | #define RTC_SR_TCE_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 4019 | #define RTC_SR_TCE_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 4020 | #define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK) |
mbed_official | 121:7f86b4238bec | 4021 | |
mbed_official | 121:7f86b4238bec | 4022 | /*! @name LR - RTC Lock Register */ |
mbed_official | 121:7f86b4238bec | 4023 | #define RTC_LR_TCL_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 4024 | #define RTC_LR_TCL_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 4025 | #define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK) |
mbed_official | 121:7f86b4238bec | 4026 | #define RTC_LR_CRL_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 4027 | #define RTC_LR_CRL_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 4028 | #define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK) |
mbed_official | 121:7f86b4238bec | 4029 | #define RTC_LR_SRL_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 4030 | #define RTC_LR_SRL_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 4031 | #define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK) |
mbed_official | 121:7f86b4238bec | 4032 | #define RTC_LR_LRL_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 4033 | #define RTC_LR_LRL_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 4034 | #define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK) |
mbed_official | 121:7f86b4238bec | 4035 | |
mbed_official | 121:7f86b4238bec | 4036 | /*! @name IER - RTC Interrupt Enable Register */ |
mbed_official | 121:7f86b4238bec | 4037 | #define RTC_IER_TIIE_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 4038 | #define RTC_IER_TIIE_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 4039 | #define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK) |
mbed_official | 121:7f86b4238bec | 4040 | #define RTC_IER_TOIE_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 4041 | #define RTC_IER_TOIE_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 4042 | #define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK) |
mbed_official | 121:7f86b4238bec | 4043 | #define RTC_IER_TAIE_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 4044 | #define RTC_IER_TAIE_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 4045 | #define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK) |
mbed_official | 121:7f86b4238bec | 4046 | #define RTC_IER_TSIE_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 4047 | #define RTC_IER_TSIE_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 4048 | #define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK) |
mbed_official | 121:7f86b4238bec | 4049 | #define RTC_IER_WPON_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 4050 | #define RTC_IER_WPON_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 4051 | #define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK) |
mbed_official | 121:7f86b4238bec | 4052 | |
mbed_official | 121:7f86b4238bec | 4053 | |
mbed_official | 121:7f86b4238bec | 4054 | /*! |
mbed_official | 121:7f86b4238bec | 4055 | * @} |
mbed_official | 121:7f86b4238bec | 4056 | */ /* end of group RTC_Register_Masks */ |
mbed_official | 121:7f86b4238bec | 4057 | |
mbed_official | 121:7f86b4238bec | 4058 | |
mbed_official | 121:7f86b4238bec | 4059 | /* RTC - Peripheral instance base addresses */ |
mbed_official | 121:7f86b4238bec | 4060 | /** Peripheral RTC base address */ |
mbed_official | 121:7f86b4238bec | 4061 | #define RTC_BASE (0x4003D000u) |
mbed_official | 121:7f86b4238bec | 4062 | /** Peripheral RTC base pointer */ |
mbed_official | 121:7f86b4238bec | 4063 | #define RTC ((RTC_Type *)RTC_BASE) |
mbed_official | 121:7f86b4238bec | 4064 | /** Array initializer of RTC peripheral base addresses */ |
mbed_official | 121:7f86b4238bec | 4065 | #define RTC_BASE_ADDRS { RTC_BASE } |
mbed_official | 121:7f86b4238bec | 4066 | /** Array initializer of RTC peripheral base pointers */ |
mbed_official | 121:7f86b4238bec | 4067 | #define RTC_BASE_PTRS { RTC } |
mbed_official | 121:7f86b4238bec | 4068 | /** Interrupt vectors for the RTC peripheral type */ |
mbed_official | 121:7f86b4238bec | 4069 | #define RTC_IRQS { RTC_IRQn } |
mbed_official | 121:7f86b4238bec | 4070 | #define RTC_SECONDS_IRQS { RTC_Seconds_IRQn } |
mbed_official | 121:7f86b4238bec | 4071 | |
mbed_official | 121:7f86b4238bec | 4072 | /*! |
mbed_official | 121:7f86b4238bec | 4073 | * @} |
mbed_official | 121:7f86b4238bec | 4074 | */ /* end of group RTC_Peripheral_Access_Layer */ |
mbed_official | 121:7f86b4238bec | 4075 | |
mbed_official | 121:7f86b4238bec | 4076 | |
mbed_official | 121:7f86b4238bec | 4077 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 4078 | -- SIM Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 4079 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 4080 | |
mbed_official | 121:7f86b4238bec | 4081 | /*! |
mbed_official | 121:7f86b4238bec | 4082 | * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 4083 | * @{ |
mbed_official | 121:7f86b4238bec | 4084 | */ |
mbed_official | 121:7f86b4238bec | 4085 | |
mbed_official | 121:7f86b4238bec | 4086 | /** SIM - Register Layout Typedef */ |
mbed_official | 121:7f86b4238bec | 4087 | typedef struct { |
mbed_official | 121:7f86b4238bec | 4088 | __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */ |
mbed_official | 121:7f86b4238bec | 4089 | uint8_t RESERVED_0[4096]; |
mbed_official | 121:7f86b4238bec | 4090 | __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */ |
mbed_official | 121:7f86b4238bec | 4091 | uint8_t RESERVED_1[4]; |
mbed_official | 121:7f86b4238bec | 4092 | __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */ |
mbed_official | 121:7f86b4238bec | 4093 | __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */ |
mbed_official | 121:7f86b4238bec | 4094 | uint8_t RESERVED_2[4]; |
mbed_official | 121:7f86b4238bec | 4095 | __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */ |
mbed_official | 121:7f86b4238bec | 4096 | uint8_t RESERVED_3[8]; |
mbed_official | 121:7f86b4238bec | 4097 | __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */ |
mbed_official | 121:7f86b4238bec | 4098 | uint8_t RESERVED_4[12]; |
mbed_official | 121:7f86b4238bec | 4099 | __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */ |
mbed_official | 121:7f86b4238bec | 4100 | __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */ |
mbed_official | 121:7f86b4238bec | 4101 | __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */ |
mbed_official | 121:7f86b4238bec | 4102 | __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */ |
mbed_official | 121:7f86b4238bec | 4103 | __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */ |
mbed_official | 121:7f86b4238bec | 4104 | uint8_t RESERVED_5[4]; |
mbed_official | 121:7f86b4238bec | 4105 | __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */ |
mbed_official | 121:7f86b4238bec | 4106 | __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */ |
mbed_official | 121:7f86b4238bec | 4107 | uint8_t RESERVED_6[4]; |
mbed_official | 121:7f86b4238bec | 4108 | __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */ |
mbed_official | 121:7f86b4238bec | 4109 | __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */ |
mbed_official | 121:7f86b4238bec | 4110 | __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */ |
mbed_official | 121:7f86b4238bec | 4111 | uint8_t RESERVED_7[156]; |
mbed_official | 121:7f86b4238bec | 4112 | __IO uint32_t COPC; /**< COP Control Register, offset: 0x1100 */ |
mbed_official | 121:7f86b4238bec | 4113 | __O uint32_t SRVCOP; /**< Service COP, offset: 0x1104 */ |
mbed_official | 121:7f86b4238bec | 4114 | } SIM_Type; |
mbed_official | 121:7f86b4238bec | 4115 | |
mbed_official | 121:7f86b4238bec | 4116 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 4117 | -- SIM Register Masks |
mbed_official | 121:7f86b4238bec | 4118 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 4119 | |
mbed_official | 121:7f86b4238bec | 4120 | /*! |
mbed_official | 121:7f86b4238bec | 4121 | * @addtogroup SIM_Register_Masks SIM Register Masks |
mbed_official | 121:7f86b4238bec | 4122 | * @{ |
mbed_official | 121:7f86b4238bec | 4123 | */ |
mbed_official | 121:7f86b4238bec | 4124 | |
mbed_official | 121:7f86b4238bec | 4125 | /*! @name SOPT1 - System Options Register 1 */ |
mbed_official | 121:7f86b4238bec | 4126 | #define SIM_SOPT1_OSC32KOUT_MASK (0x30000U) |
mbed_official | 121:7f86b4238bec | 4127 | #define SIM_SOPT1_OSC32KOUT_SHIFT (16U) |
mbed_official | 121:7f86b4238bec | 4128 | #define SIM_SOPT1_OSC32KOUT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KOUT_SHIFT)) & SIM_SOPT1_OSC32KOUT_MASK) |
mbed_official | 121:7f86b4238bec | 4129 | #define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U) |
mbed_official | 121:7f86b4238bec | 4130 | #define SIM_SOPT1_OSC32KSEL_SHIFT (18U) |
mbed_official | 121:7f86b4238bec | 4131 | #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK) |
mbed_official | 121:7f86b4238bec | 4132 | |
mbed_official | 121:7f86b4238bec | 4133 | /*! @name SOPT2 - System Options Register 2 */ |
mbed_official | 121:7f86b4238bec | 4134 | #define SIM_SOPT2_RTCCLKOUTSEL_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 4135 | #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 4136 | #define SIM_SOPT2_RTCCLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK) |
mbed_official | 121:7f86b4238bec | 4137 | #define SIM_SOPT2_CLKOUTSEL_MASK (0xE0U) |
mbed_official | 121:7f86b4238bec | 4138 | #define SIM_SOPT2_CLKOUTSEL_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 4139 | #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK) |
mbed_official | 121:7f86b4238bec | 4140 | #define SIM_SOPT2_USBSRC_MASK (0x40000U) |
mbed_official | 121:7f86b4238bec | 4141 | #define SIM_SOPT2_USBSRC_SHIFT (18U) |
mbed_official | 121:7f86b4238bec | 4142 | #define SIM_SOPT2_USBSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK) |
mbed_official | 121:7f86b4238bec | 4143 | #define SIM_SOPT2_FLEXIOSRC_MASK (0xC00000U) |
mbed_official | 121:7f86b4238bec | 4144 | #define SIM_SOPT2_FLEXIOSRC_SHIFT (22U) |
mbed_official | 121:7f86b4238bec | 4145 | #define SIM_SOPT2_FLEXIOSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FLEXIOSRC_SHIFT)) & SIM_SOPT2_FLEXIOSRC_MASK) |
mbed_official | 121:7f86b4238bec | 4146 | #define SIM_SOPT2_TPMSRC_MASK (0x3000000U) |
mbed_official | 121:7f86b4238bec | 4147 | #define SIM_SOPT2_TPMSRC_SHIFT (24U) |
mbed_official | 121:7f86b4238bec | 4148 | #define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TPMSRC_SHIFT)) & SIM_SOPT2_TPMSRC_MASK) |
mbed_official | 121:7f86b4238bec | 4149 | #define SIM_SOPT2_LPUART0SRC_MASK (0xC000000U) |
mbed_official | 121:7f86b4238bec | 4150 | #define SIM_SOPT2_LPUART0SRC_SHIFT (26U) |
mbed_official | 121:7f86b4238bec | 4151 | #define SIM_SOPT2_LPUART0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_LPUART0SRC_SHIFT)) & SIM_SOPT2_LPUART0SRC_MASK) |
mbed_official | 121:7f86b4238bec | 4152 | #define SIM_SOPT2_LPUART1SRC_MASK (0x30000000U) |
mbed_official | 121:7f86b4238bec | 4153 | #define SIM_SOPT2_LPUART1SRC_SHIFT (28U) |
mbed_official | 121:7f86b4238bec | 4154 | #define SIM_SOPT2_LPUART1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_LPUART1SRC_SHIFT)) & SIM_SOPT2_LPUART1SRC_MASK) |
mbed_official | 121:7f86b4238bec | 4155 | |
mbed_official | 121:7f86b4238bec | 4156 | /*! @name SOPT4 - System Options Register 4 */ |
mbed_official | 121:7f86b4238bec | 4157 | #define SIM_SOPT4_TPM1CH0SRC_MASK (0xC0000U) |
mbed_official | 121:7f86b4238bec | 4158 | #define SIM_SOPT4_TPM1CH0SRC_SHIFT (18U) |
mbed_official | 121:7f86b4238bec | 4159 | #define SIM_SOPT4_TPM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM1CH0SRC_SHIFT)) & SIM_SOPT4_TPM1CH0SRC_MASK) |
mbed_official | 121:7f86b4238bec | 4160 | #define SIM_SOPT4_TPM2CH0SRC_MASK (0x100000U) |
mbed_official | 121:7f86b4238bec | 4161 | #define SIM_SOPT4_TPM2CH0SRC_SHIFT (20U) |
mbed_official | 121:7f86b4238bec | 4162 | #define SIM_SOPT4_TPM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM2CH0SRC_SHIFT)) & SIM_SOPT4_TPM2CH0SRC_MASK) |
mbed_official | 121:7f86b4238bec | 4163 | #define SIM_SOPT4_TPM0CLKSEL_MASK (0x1000000U) |
mbed_official | 121:7f86b4238bec | 4164 | #define SIM_SOPT4_TPM0CLKSEL_SHIFT (24U) |
mbed_official | 121:7f86b4238bec | 4165 | #define SIM_SOPT4_TPM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM0CLKSEL_SHIFT)) & SIM_SOPT4_TPM0CLKSEL_MASK) |
mbed_official | 121:7f86b4238bec | 4166 | #define SIM_SOPT4_TPM1CLKSEL_MASK (0x2000000U) |
mbed_official | 121:7f86b4238bec | 4167 | #define SIM_SOPT4_TPM1CLKSEL_SHIFT (25U) |
mbed_official | 121:7f86b4238bec | 4168 | #define SIM_SOPT4_TPM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM1CLKSEL_SHIFT)) & SIM_SOPT4_TPM1CLKSEL_MASK) |
mbed_official | 121:7f86b4238bec | 4169 | #define SIM_SOPT4_TPM2CLKSEL_MASK (0x4000000U) |
mbed_official | 121:7f86b4238bec | 4170 | #define SIM_SOPT4_TPM2CLKSEL_SHIFT (26U) |
mbed_official | 121:7f86b4238bec | 4171 | #define SIM_SOPT4_TPM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM2CLKSEL_SHIFT)) & SIM_SOPT4_TPM2CLKSEL_MASK) |
mbed_official | 121:7f86b4238bec | 4172 | |
mbed_official | 121:7f86b4238bec | 4173 | /*! @name SOPT5 - System Options Register 5 */ |
mbed_official | 121:7f86b4238bec | 4174 | #define SIM_SOPT5_LPUART0TXSRC_MASK (0x3U) |
mbed_official | 121:7f86b4238bec | 4175 | #define SIM_SOPT5_LPUART0TXSRC_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 4176 | #define SIM_SOPT5_LPUART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0TXSRC_SHIFT)) & SIM_SOPT5_LPUART0TXSRC_MASK) |
mbed_official | 121:7f86b4238bec | 4177 | #define SIM_SOPT5_LPUART0RXSRC_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 4178 | #define SIM_SOPT5_LPUART0RXSRC_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 4179 | #define SIM_SOPT5_LPUART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0RXSRC_SHIFT)) & SIM_SOPT5_LPUART0RXSRC_MASK) |
mbed_official | 121:7f86b4238bec | 4180 | #define SIM_SOPT5_LPUART1TXSRC_MASK (0x30U) |
mbed_official | 121:7f86b4238bec | 4181 | #define SIM_SOPT5_LPUART1TXSRC_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 4182 | #define SIM_SOPT5_LPUART1TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART1TXSRC_SHIFT)) & SIM_SOPT5_LPUART1TXSRC_MASK) |
mbed_official | 121:7f86b4238bec | 4183 | #define SIM_SOPT5_LPUART1RXSRC_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 4184 | #define SIM_SOPT5_LPUART1RXSRC_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 4185 | #define SIM_SOPT5_LPUART1RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART1RXSRC_SHIFT)) & SIM_SOPT5_LPUART1RXSRC_MASK) |
mbed_official | 121:7f86b4238bec | 4186 | #define SIM_SOPT5_LPUART0ODE_MASK (0x10000U) |
mbed_official | 121:7f86b4238bec | 4187 | #define SIM_SOPT5_LPUART0ODE_SHIFT (16U) |
mbed_official | 121:7f86b4238bec | 4188 | #define SIM_SOPT5_LPUART0ODE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0ODE_SHIFT)) & SIM_SOPT5_LPUART0ODE_MASK) |
mbed_official | 121:7f86b4238bec | 4189 | #define SIM_SOPT5_LPUART1ODE_MASK (0x20000U) |
mbed_official | 121:7f86b4238bec | 4190 | #define SIM_SOPT5_LPUART1ODE_SHIFT (17U) |
mbed_official | 121:7f86b4238bec | 4191 | #define SIM_SOPT5_LPUART1ODE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART1ODE_SHIFT)) & SIM_SOPT5_LPUART1ODE_MASK) |
mbed_official | 121:7f86b4238bec | 4192 | #define SIM_SOPT5_UART2ODE_MASK (0x40000U) |
mbed_official | 121:7f86b4238bec | 4193 | #define SIM_SOPT5_UART2ODE_SHIFT (18U) |
mbed_official | 121:7f86b4238bec | 4194 | #define SIM_SOPT5_UART2ODE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART2ODE_SHIFT)) & SIM_SOPT5_UART2ODE_MASK) |
mbed_official | 121:7f86b4238bec | 4195 | |
mbed_official | 121:7f86b4238bec | 4196 | /*! @name SOPT7 - System Options Register 7 */ |
mbed_official | 121:7f86b4238bec | 4197 | #define SIM_SOPT7_ADC0TRGSEL_MASK (0xFU) |
mbed_official | 121:7f86b4238bec | 4198 | #define SIM_SOPT7_ADC0TRGSEL_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 4199 | #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK) |
mbed_official | 121:7f86b4238bec | 4200 | #define SIM_SOPT7_ADC0PRETRGSEL_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 4201 | #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 4202 | #define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK) |
mbed_official | 121:7f86b4238bec | 4203 | #define SIM_SOPT7_ADC0ALTTRGEN_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 4204 | #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 4205 | #define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK) |
mbed_official | 121:7f86b4238bec | 4206 | |
mbed_official | 121:7f86b4238bec | 4207 | /*! @name SDID - System Device Identification Register */ |
mbed_official | 121:7f86b4238bec | 4208 | #define SIM_SDID_PINID_MASK (0xFU) |
mbed_official | 121:7f86b4238bec | 4209 | #define SIM_SDID_PINID_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 4210 | #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK) |
mbed_official | 121:7f86b4238bec | 4211 | #define SIM_SDID_REVID_MASK (0xF000U) |
mbed_official | 121:7f86b4238bec | 4212 | #define SIM_SDID_REVID_SHIFT (12U) |
mbed_official | 121:7f86b4238bec | 4213 | #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK) |
mbed_official | 121:7f86b4238bec | 4214 | #define SIM_SDID_SRAMSIZE_MASK (0xF0000U) |
mbed_official | 121:7f86b4238bec | 4215 | #define SIM_SDID_SRAMSIZE_SHIFT (16U) |
mbed_official | 121:7f86b4238bec | 4216 | #define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SRAMSIZE_SHIFT)) & SIM_SDID_SRAMSIZE_MASK) |
mbed_official | 121:7f86b4238bec | 4217 | #define SIM_SDID_SERIESID_MASK (0xF00000U) |
mbed_official | 121:7f86b4238bec | 4218 | #define SIM_SDID_SERIESID_SHIFT (20U) |
mbed_official | 121:7f86b4238bec | 4219 | #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK) |
mbed_official | 121:7f86b4238bec | 4220 | #define SIM_SDID_SUBFAMID_MASK (0xF000000U) |
mbed_official | 121:7f86b4238bec | 4221 | #define SIM_SDID_SUBFAMID_SHIFT (24U) |
mbed_official | 121:7f86b4238bec | 4222 | #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK) |
mbed_official | 121:7f86b4238bec | 4223 | #define SIM_SDID_FAMID_MASK (0xF0000000U) |
mbed_official | 121:7f86b4238bec | 4224 | #define SIM_SDID_FAMID_SHIFT (28U) |
mbed_official | 121:7f86b4238bec | 4225 | #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK) |
mbed_official | 121:7f86b4238bec | 4226 | |
mbed_official | 121:7f86b4238bec | 4227 | /*! @name SCGC4 - System Clock Gating Control Register 4 */ |
mbed_official | 121:7f86b4238bec | 4228 | #define SIM_SCGC4_I2C0_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 4229 | #define SIM_SCGC4_I2C0_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 4230 | #define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK) |
mbed_official | 121:7f86b4238bec | 4231 | #define SIM_SCGC4_I2C1_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 4232 | #define SIM_SCGC4_I2C1_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 4233 | #define SIM_SCGC4_I2C1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK) |
mbed_official | 121:7f86b4238bec | 4234 | #define SIM_SCGC4_UART2_MASK (0x1000U) |
mbed_official | 121:7f86b4238bec | 4235 | #define SIM_SCGC4_UART2_SHIFT (12U) |
mbed_official | 121:7f86b4238bec | 4236 | #define SIM_SCGC4_UART2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK) |
mbed_official | 121:7f86b4238bec | 4237 | #define SIM_SCGC4_USBFS_MASK (0x40000U) |
mbed_official | 121:7f86b4238bec | 4238 | #define SIM_SCGC4_USBFS_SHIFT (18U) |
mbed_official | 121:7f86b4238bec | 4239 | #define SIM_SCGC4_USBFS(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBFS_SHIFT)) & SIM_SCGC4_USBFS_MASK) |
mbed_official | 121:7f86b4238bec | 4240 | #define SIM_SCGC4_CMP0_MASK (0x80000U) |
mbed_official | 121:7f86b4238bec | 4241 | #define SIM_SCGC4_CMP0_SHIFT (19U) |
mbed_official | 121:7f86b4238bec | 4242 | #define SIM_SCGC4_CMP0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP0_SHIFT)) & SIM_SCGC4_CMP0_MASK) |
mbed_official | 121:7f86b4238bec | 4243 | #define SIM_SCGC4_VREF_MASK (0x100000U) |
mbed_official | 121:7f86b4238bec | 4244 | #define SIM_SCGC4_VREF_SHIFT (20U) |
mbed_official | 121:7f86b4238bec | 4245 | #define SIM_SCGC4_VREF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK) |
mbed_official | 121:7f86b4238bec | 4246 | #define SIM_SCGC4_SPI0_MASK (0x400000U) |
mbed_official | 121:7f86b4238bec | 4247 | #define SIM_SCGC4_SPI0_SHIFT (22U) |
mbed_official | 121:7f86b4238bec | 4248 | #define SIM_SCGC4_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_SPI0_SHIFT)) & SIM_SCGC4_SPI0_MASK) |
mbed_official | 121:7f86b4238bec | 4249 | #define SIM_SCGC4_SPI1_MASK (0x800000U) |
mbed_official | 121:7f86b4238bec | 4250 | #define SIM_SCGC4_SPI1_SHIFT (23U) |
mbed_official | 121:7f86b4238bec | 4251 | #define SIM_SCGC4_SPI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_SPI1_SHIFT)) & SIM_SCGC4_SPI1_MASK) |
mbed_official | 121:7f86b4238bec | 4252 | |
mbed_official | 121:7f86b4238bec | 4253 | /*! @name SCGC5 - System Clock Gating Control Register 5 */ |
mbed_official | 121:7f86b4238bec | 4254 | #define SIM_SCGC5_LPTMR_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 4255 | #define SIM_SCGC5_LPTMR_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 4256 | #define SIM_SCGC5_LPTMR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK) |
mbed_official | 121:7f86b4238bec | 4257 | #define SIM_SCGC5_PORTA_MASK (0x200U) |
mbed_official | 121:7f86b4238bec | 4258 | #define SIM_SCGC5_PORTA_SHIFT (9U) |
mbed_official | 121:7f86b4238bec | 4259 | #define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK) |
mbed_official | 121:7f86b4238bec | 4260 | #define SIM_SCGC5_PORTB_MASK (0x400U) |
mbed_official | 121:7f86b4238bec | 4261 | #define SIM_SCGC5_PORTB_SHIFT (10U) |
mbed_official | 121:7f86b4238bec | 4262 | #define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK) |
mbed_official | 121:7f86b4238bec | 4263 | #define SIM_SCGC5_PORTC_MASK (0x800U) |
mbed_official | 121:7f86b4238bec | 4264 | #define SIM_SCGC5_PORTC_SHIFT (11U) |
mbed_official | 121:7f86b4238bec | 4265 | #define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK) |
mbed_official | 121:7f86b4238bec | 4266 | #define SIM_SCGC5_PORTD_MASK (0x1000U) |
mbed_official | 121:7f86b4238bec | 4267 | #define SIM_SCGC5_PORTD_SHIFT (12U) |
mbed_official | 121:7f86b4238bec | 4268 | #define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK) |
mbed_official | 121:7f86b4238bec | 4269 | #define SIM_SCGC5_PORTE_MASK (0x2000U) |
mbed_official | 121:7f86b4238bec | 4270 | #define SIM_SCGC5_PORTE_SHIFT (13U) |
mbed_official | 121:7f86b4238bec | 4271 | #define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK) |
mbed_official | 121:7f86b4238bec | 4272 | #define SIM_SCGC5_LPUART0_MASK (0x100000U) |
mbed_official | 121:7f86b4238bec | 4273 | #define SIM_SCGC5_LPUART0_SHIFT (20U) |
mbed_official | 121:7f86b4238bec | 4274 | #define SIM_SCGC5_LPUART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPUART0_SHIFT)) & SIM_SCGC5_LPUART0_MASK) |
mbed_official | 121:7f86b4238bec | 4275 | #define SIM_SCGC5_LPUART1_MASK (0x200000U) |
mbed_official | 121:7f86b4238bec | 4276 | #define SIM_SCGC5_LPUART1_SHIFT (21U) |
mbed_official | 121:7f86b4238bec | 4277 | #define SIM_SCGC5_LPUART1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPUART1_SHIFT)) & SIM_SCGC5_LPUART1_MASK) |
mbed_official | 121:7f86b4238bec | 4278 | #define SIM_SCGC5_FLEXIO_MASK (0x80000000U) |
mbed_official | 121:7f86b4238bec | 4279 | #define SIM_SCGC5_FLEXIO_SHIFT (31U) |
mbed_official | 121:7f86b4238bec | 4280 | #define SIM_SCGC5_FLEXIO(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_FLEXIO_SHIFT)) & SIM_SCGC5_FLEXIO_MASK) |
mbed_official | 121:7f86b4238bec | 4281 | |
mbed_official | 121:7f86b4238bec | 4282 | /*! @name SCGC6 - System Clock Gating Control Register 6 */ |
mbed_official | 121:7f86b4238bec | 4283 | #define SIM_SCGC6_FTF_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 4284 | #define SIM_SCGC6_FTF_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 4285 | #define SIM_SCGC6_FTF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK) |
mbed_official | 121:7f86b4238bec | 4286 | #define SIM_SCGC6_DMAMUX_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 4287 | #define SIM_SCGC6_DMAMUX_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 4288 | #define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK) |
mbed_official | 121:7f86b4238bec | 4289 | #define SIM_SCGC6_CRC_MASK (0x40000U) |
mbed_official | 121:7f86b4238bec | 4290 | #define SIM_SCGC6_CRC_SHIFT (18U) |
mbed_official | 121:7f86b4238bec | 4291 | #define SIM_SCGC6_CRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK) |
mbed_official | 121:7f86b4238bec | 4292 | #define SIM_SCGC6_PIT_MASK (0x800000U) |
mbed_official | 121:7f86b4238bec | 4293 | #define SIM_SCGC6_PIT_SHIFT (23U) |
mbed_official | 121:7f86b4238bec | 4294 | #define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK) |
mbed_official | 121:7f86b4238bec | 4295 | #define SIM_SCGC6_TPM0_MASK (0x1000000U) |
mbed_official | 121:7f86b4238bec | 4296 | #define SIM_SCGC6_TPM0_SHIFT (24U) |
mbed_official | 121:7f86b4238bec | 4297 | #define SIM_SCGC6_TPM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM0_SHIFT)) & SIM_SCGC6_TPM0_MASK) |
mbed_official | 121:7f86b4238bec | 4298 | #define SIM_SCGC6_TPM1_MASK (0x2000000U) |
mbed_official | 121:7f86b4238bec | 4299 | #define SIM_SCGC6_TPM1_SHIFT (25U) |
mbed_official | 121:7f86b4238bec | 4300 | #define SIM_SCGC6_TPM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM1_SHIFT)) & SIM_SCGC6_TPM1_MASK) |
mbed_official | 121:7f86b4238bec | 4301 | #define SIM_SCGC6_TPM2_MASK (0x4000000U) |
mbed_official | 121:7f86b4238bec | 4302 | #define SIM_SCGC6_TPM2_SHIFT (26U) |
mbed_official | 121:7f86b4238bec | 4303 | #define SIM_SCGC6_TPM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM2_SHIFT)) & SIM_SCGC6_TPM2_MASK) |
mbed_official | 121:7f86b4238bec | 4304 | #define SIM_SCGC6_ADC0_MASK (0x8000000U) |
mbed_official | 121:7f86b4238bec | 4305 | #define SIM_SCGC6_ADC0_SHIFT (27U) |
mbed_official | 121:7f86b4238bec | 4306 | #define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK) |
mbed_official | 121:7f86b4238bec | 4307 | #define SIM_SCGC6_RTC_MASK (0x20000000U) |
mbed_official | 121:7f86b4238bec | 4308 | #define SIM_SCGC6_RTC_SHIFT (29U) |
mbed_official | 121:7f86b4238bec | 4309 | #define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK) |
mbed_official | 121:7f86b4238bec | 4310 | |
mbed_official | 121:7f86b4238bec | 4311 | /*! @name SCGC7 - System Clock Gating Control Register 7 */ |
mbed_official | 121:7f86b4238bec | 4312 | #define SIM_SCGC7_DMA_MASK (0x100U) |
mbed_official | 121:7f86b4238bec | 4313 | #define SIM_SCGC7_DMA_SHIFT (8U) |
mbed_official | 121:7f86b4238bec | 4314 | #define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK) |
mbed_official | 121:7f86b4238bec | 4315 | |
mbed_official | 121:7f86b4238bec | 4316 | /*! @name CLKDIV1 - System Clock Divider Register 1 */ |
mbed_official | 121:7f86b4238bec | 4317 | #define SIM_CLKDIV1_OUTDIV4_MASK (0x70000U) |
mbed_official | 121:7f86b4238bec | 4318 | #define SIM_CLKDIV1_OUTDIV4_SHIFT (16U) |
mbed_official | 121:7f86b4238bec | 4319 | #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK) |
mbed_official | 121:7f86b4238bec | 4320 | #define SIM_CLKDIV1_OUTDIV1_MASK (0xF0000000U) |
mbed_official | 121:7f86b4238bec | 4321 | #define SIM_CLKDIV1_OUTDIV1_SHIFT (28U) |
mbed_official | 121:7f86b4238bec | 4322 | #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK) |
mbed_official | 121:7f86b4238bec | 4323 | |
mbed_official | 121:7f86b4238bec | 4324 | /*! @name FCFG1 - Flash Configuration Register 1 */ |
mbed_official | 121:7f86b4238bec | 4325 | #define SIM_FCFG1_FLASHDIS_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 4326 | #define SIM_FCFG1_FLASHDIS_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 4327 | #define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK) |
mbed_official | 121:7f86b4238bec | 4328 | #define SIM_FCFG1_FLASHDOZE_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 4329 | #define SIM_FCFG1_FLASHDOZE_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 4330 | #define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK) |
mbed_official | 121:7f86b4238bec | 4331 | #define SIM_FCFG1_PFSIZE_MASK (0xF000000U) |
mbed_official | 121:7f86b4238bec | 4332 | #define SIM_FCFG1_PFSIZE_SHIFT (24U) |
mbed_official | 121:7f86b4238bec | 4333 | #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK) |
mbed_official | 121:7f86b4238bec | 4334 | |
mbed_official | 121:7f86b4238bec | 4335 | /*! @name FCFG2 - Flash Configuration Register 2 */ |
mbed_official | 121:7f86b4238bec | 4336 | #define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U) |
mbed_official | 121:7f86b4238bec | 4337 | #define SIM_FCFG2_MAXADDR0_SHIFT (24U) |
mbed_official | 121:7f86b4238bec | 4338 | #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK) |
mbed_official | 121:7f86b4238bec | 4339 | |
mbed_official | 121:7f86b4238bec | 4340 | /*! @name UIDMH - Unique Identification Register Mid-High */ |
mbed_official | 121:7f86b4238bec | 4341 | #define SIM_UIDMH_UID_MASK (0xFFFFU) |
mbed_official | 121:7f86b4238bec | 4342 | #define SIM_UIDMH_UID_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 4343 | #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK) |
mbed_official | 121:7f86b4238bec | 4344 | |
mbed_official | 121:7f86b4238bec | 4345 | /*! @name UIDML - Unique Identification Register Mid Low */ |
mbed_official | 121:7f86b4238bec | 4346 | #define SIM_UIDML_UID_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 4347 | #define SIM_UIDML_UID_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 4348 | #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK) |
mbed_official | 121:7f86b4238bec | 4349 | |
mbed_official | 121:7f86b4238bec | 4350 | /*! @name UIDL - Unique Identification Register Low */ |
mbed_official | 121:7f86b4238bec | 4351 | #define SIM_UIDL_UID_MASK (0xFFFFFFFFU) |
mbed_official | 121:7f86b4238bec | 4352 | #define SIM_UIDL_UID_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 4353 | #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK) |
mbed_official | 121:7f86b4238bec | 4354 | |
mbed_official | 121:7f86b4238bec | 4355 | /*! @name COPC - COP Control Register */ |
mbed_official | 121:7f86b4238bec | 4356 | #define SIM_COPC_COPW_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 4357 | #define SIM_COPC_COPW_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 4358 | #define SIM_COPC_COPW(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPW_SHIFT)) & SIM_COPC_COPW_MASK) |
mbed_official | 121:7f86b4238bec | 4359 | #define SIM_COPC_COPCLKS_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 4360 | #define SIM_COPC_COPCLKS_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 4361 | #define SIM_COPC_COPCLKS(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPCLKS_SHIFT)) & SIM_COPC_COPCLKS_MASK) |
mbed_official | 121:7f86b4238bec | 4362 | #define SIM_COPC_COPT_MASK (0xCU) |
mbed_official | 121:7f86b4238bec | 4363 | #define SIM_COPC_COPT_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 4364 | #define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPT_SHIFT)) & SIM_COPC_COPT_MASK) |
mbed_official | 121:7f86b4238bec | 4365 | #define SIM_COPC_COPSTPEN_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 4366 | #define SIM_COPC_COPSTPEN_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 4367 | #define SIM_COPC_COPSTPEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPSTPEN_SHIFT)) & SIM_COPC_COPSTPEN_MASK) |
mbed_official | 121:7f86b4238bec | 4368 | #define SIM_COPC_COPDBGEN_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 4369 | #define SIM_COPC_COPDBGEN_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 4370 | #define SIM_COPC_COPDBGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPDBGEN_SHIFT)) & SIM_COPC_COPDBGEN_MASK) |
mbed_official | 121:7f86b4238bec | 4371 | #define SIM_COPC_COPCLKSEL_MASK (0xC0U) |
mbed_official | 121:7f86b4238bec | 4372 | #define SIM_COPC_COPCLKSEL_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 4373 | #define SIM_COPC_COPCLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPCLKSEL_SHIFT)) & SIM_COPC_COPCLKSEL_MASK) |
mbed_official | 121:7f86b4238bec | 4374 | |
mbed_official | 121:7f86b4238bec | 4375 | /*! @name SRVCOP - Service COP */ |
mbed_official | 121:7f86b4238bec | 4376 | #define SIM_SRVCOP_SRVCOP_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 4377 | #define SIM_SRVCOP_SRVCOP_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 4378 | #define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRVCOP_SRVCOP_SHIFT)) & SIM_SRVCOP_SRVCOP_MASK) |
mbed_official | 121:7f86b4238bec | 4379 | |
mbed_official | 121:7f86b4238bec | 4380 | |
mbed_official | 121:7f86b4238bec | 4381 | /*! |
mbed_official | 121:7f86b4238bec | 4382 | * @} |
mbed_official | 121:7f86b4238bec | 4383 | */ /* end of group SIM_Register_Masks */ |
mbed_official | 121:7f86b4238bec | 4384 | |
mbed_official | 121:7f86b4238bec | 4385 | |
mbed_official | 121:7f86b4238bec | 4386 | /* SIM - Peripheral instance base addresses */ |
mbed_official | 121:7f86b4238bec | 4387 | /** Peripheral SIM base address */ |
mbed_official | 121:7f86b4238bec | 4388 | #define SIM_BASE (0x40047000u) |
mbed_official | 121:7f86b4238bec | 4389 | /** Peripheral SIM base pointer */ |
mbed_official | 121:7f86b4238bec | 4390 | #define SIM ((SIM_Type *)SIM_BASE) |
mbed_official | 121:7f86b4238bec | 4391 | /** Array initializer of SIM peripheral base addresses */ |
mbed_official | 121:7f86b4238bec | 4392 | #define SIM_BASE_ADDRS { SIM_BASE } |
mbed_official | 121:7f86b4238bec | 4393 | /** Array initializer of SIM peripheral base pointers */ |
mbed_official | 121:7f86b4238bec | 4394 | #define SIM_BASE_PTRS { SIM } |
mbed_official | 121:7f86b4238bec | 4395 | |
mbed_official | 121:7f86b4238bec | 4396 | /*! |
mbed_official | 121:7f86b4238bec | 4397 | * @} |
mbed_official | 121:7f86b4238bec | 4398 | */ /* end of group SIM_Peripheral_Access_Layer */ |
mbed_official | 121:7f86b4238bec | 4399 | |
mbed_official | 121:7f86b4238bec | 4400 | |
mbed_official | 121:7f86b4238bec | 4401 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 4402 | -- SMC Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 4403 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 4404 | |
mbed_official | 121:7f86b4238bec | 4405 | /*! |
mbed_official | 121:7f86b4238bec | 4406 | * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 4407 | * @{ |
mbed_official | 121:7f86b4238bec | 4408 | */ |
mbed_official | 121:7f86b4238bec | 4409 | |
mbed_official | 121:7f86b4238bec | 4410 | /** SMC - Register Layout Typedef */ |
mbed_official | 121:7f86b4238bec | 4411 | typedef struct { |
mbed_official | 121:7f86b4238bec | 4412 | __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */ |
mbed_official | 121:7f86b4238bec | 4413 | __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */ |
mbed_official | 121:7f86b4238bec | 4414 | __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */ |
mbed_official | 121:7f86b4238bec | 4415 | __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */ |
mbed_official | 121:7f86b4238bec | 4416 | } SMC_Type; |
mbed_official | 121:7f86b4238bec | 4417 | |
mbed_official | 121:7f86b4238bec | 4418 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 4419 | -- SMC Register Masks |
mbed_official | 121:7f86b4238bec | 4420 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 4421 | |
mbed_official | 121:7f86b4238bec | 4422 | /*! |
mbed_official | 121:7f86b4238bec | 4423 | * @addtogroup SMC_Register_Masks SMC Register Masks |
mbed_official | 121:7f86b4238bec | 4424 | * @{ |
mbed_official | 121:7f86b4238bec | 4425 | */ |
mbed_official | 121:7f86b4238bec | 4426 | |
mbed_official | 121:7f86b4238bec | 4427 | /*! @name PMPROT - Power Mode Protection register */ |
mbed_official | 121:7f86b4238bec | 4428 | #define SMC_PMPROT_AVLLS_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 4429 | #define SMC_PMPROT_AVLLS_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 4430 | #define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK) |
mbed_official | 121:7f86b4238bec | 4431 | #define SMC_PMPROT_ALLS_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 4432 | #define SMC_PMPROT_ALLS_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 4433 | #define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK) |
mbed_official | 121:7f86b4238bec | 4434 | #define SMC_PMPROT_AVLP_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 4435 | #define SMC_PMPROT_AVLP_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 4436 | #define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK) |
mbed_official | 121:7f86b4238bec | 4437 | |
mbed_official | 121:7f86b4238bec | 4438 | /*! @name PMCTRL - Power Mode Control register */ |
mbed_official | 121:7f86b4238bec | 4439 | #define SMC_PMCTRL_STOPM_MASK (0x7U) |
mbed_official | 121:7f86b4238bec | 4440 | #define SMC_PMCTRL_STOPM_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 4441 | #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK) |
mbed_official | 121:7f86b4238bec | 4442 | #define SMC_PMCTRL_STOPA_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 4443 | #define SMC_PMCTRL_STOPA_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 4444 | #define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK) |
mbed_official | 121:7f86b4238bec | 4445 | #define SMC_PMCTRL_RUNM_MASK (0x60U) |
mbed_official | 121:7f86b4238bec | 4446 | #define SMC_PMCTRL_RUNM_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 4447 | #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK) |
mbed_official | 121:7f86b4238bec | 4448 | |
mbed_official | 121:7f86b4238bec | 4449 | /*! @name STOPCTRL - Stop Control Register */ |
mbed_official | 121:7f86b4238bec | 4450 | #define SMC_STOPCTRL_VLLSM_MASK (0x7U) |
mbed_official | 121:7f86b4238bec | 4451 | #define SMC_STOPCTRL_VLLSM_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 4452 | #define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_VLLSM_SHIFT)) & SMC_STOPCTRL_VLLSM_MASK) |
mbed_official | 121:7f86b4238bec | 4453 | #define SMC_STOPCTRL_LPOPO_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 4454 | #define SMC_STOPCTRL_LPOPO_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 4455 | #define SMC_STOPCTRL_LPOPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_LPOPO_SHIFT)) & SMC_STOPCTRL_LPOPO_MASK) |
mbed_official | 121:7f86b4238bec | 4456 | #define SMC_STOPCTRL_PORPO_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 4457 | #define SMC_STOPCTRL_PORPO_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 4458 | #define SMC_STOPCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PORPO_SHIFT)) & SMC_STOPCTRL_PORPO_MASK) |
mbed_official | 121:7f86b4238bec | 4459 | #define SMC_STOPCTRL_PSTOPO_MASK (0xC0U) |
mbed_official | 121:7f86b4238bec | 4460 | #define SMC_STOPCTRL_PSTOPO_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 4461 | #define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PSTOPO_SHIFT)) & SMC_STOPCTRL_PSTOPO_MASK) |
mbed_official | 121:7f86b4238bec | 4462 | |
mbed_official | 121:7f86b4238bec | 4463 | /*! @name PMSTAT - Power Mode Status register */ |
mbed_official | 121:7f86b4238bec | 4464 | #define SMC_PMSTAT_PMSTAT_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 4465 | #define SMC_PMSTAT_PMSTAT_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 4466 | #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK) |
mbed_official | 121:7f86b4238bec | 4467 | |
mbed_official | 121:7f86b4238bec | 4468 | |
mbed_official | 121:7f86b4238bec | 4469 | /*! |
mbed_official | 121:7f86b4238bec | 4470 | * @} |
mbed_official | 121:7f86b4238bec | 4471 | */ /* end of group SMC_Register_Masks */ |
mbed_official | 121:7f86b4238bec | 4472 | |
mbed_official | 121:7f86b4238bec | 4473 | |
mbed_official | 121:7f86b4238bec | 4474 | /* SMC - Peripheral instance base addresses */ |
mbed_official | 121:7f86b4238bec | 4475 | /** Peripheral SMC base address */ |
mbed_official | 121:7f86b4238bec | 4476 | #define SMC_BASE (0x4007E000u) |
mbed_official | 121:7f86b4238bec | 4477 | /** Peripheral SMC base pointer */ |
mbed_official | 121:7f86b4238bec | 4478 | #define SMC ((SMC_Type *)SMC_BASE) |
mbed_official | 121:7f86b4238bec | 4479 | /** Array initializer of SMC peripheral base addresses */ |
mbed_official | 121:7f86b4238bec | 4480 | #define SMC_BASE_ADDRS { SMC_BASE } |
mbed_official | 121:7f86b4238bec | 4481 | /** Array initializer of SMC peripheral base pointers */ |
mbed_official | 121:7f86b4238bec | 4482 | #define SMC_BASE_PTRS { SMC } |
mbed_official | 121:7f86b4238bec | 4483 | |
mbed_official | 121:7f86b4238bec | 4484 | /*! |
mbed_official | 121:7f86b4238bec | 4485 | * @} |
mbed_official | 121:7f86b4238bec | 4486 | */ /* end of group SMC_Peripheral_Access_Layer */ |
mbed_official | 121:7f86b4238bec | 4487 | |
mbed_official | 121:7f86b4238bec | 4488 | |
mbed_official | 121:7f86b4238bec | 4489 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 4490 | -- SPI Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 4491 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 4492 | |
mbed_official | 121:7f86b4238bec | 4493 | /*! |
mbed_official | 121:7f86b4238bec | 4494 | * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 4495 | * @{ |
mbed_official | 121:7f86b4238bec | 4496 | */ |
mbed_official | 121:7f86b4238bec | 4497 | |
mbed_official | 121:7f86b4238bec | 4498 | /** SPI - Register Layout Typedef */ |
mbed_official | 121:7f86b4238bec | 4499 | typedef struct { |
mbed_official | 121:7f86b4238bec | 4500 | __IO uint8_t S; /**< SPI Status Register, offset: 0x0 */ |
mbed_official | 121:7f86b4238bec | 4501 | __IO uint8_t BR; /**< SPI Baud Rate Register, offset: 0x1 */ |
mbed_official | 121:7f86b4238bec | 4502 | __IO uint8_t C2; /**< SPI Control Register 2, offset: 0x2 */ |
mbed_official | 121:7f86b4238bec | 4503 | __IO uint8_t C1; /**< SPI Control Register 1, offset: 0x3 */ |
mbed_official | 121:7f86b4238bec | 4504 | __IO uint8_t ML; /**< SPI Match Register low, offset: 0x4 */ |
mbed_official | 121:7f86b4238bec | 4505 | __IO uint8_t MH; /**< SPI match register high, offset: 0x5 */ |
mbed_official | 121:7f86b4238bec | 4506 | __IO uint8_t DL; /**< SPI Data Register low, offset: 0x6 */ |
mbed_official | 121:7f86b4238bec | 4507 | __IO uint8_t DH; /**< SPI data register high, offset: 0x7 */ |
mbed_official | 121:7f86b4238bec | 4508 | uint8_t RESERVED_0[2]; |
mbed_official | 121:7f86b4238bec | 4509 | __IO uint8_t CI; /**< SPI clear interrupt register, offset: 0xA */ |
mbed_official | 121:7f86b4238bec | 4510 | __IO uint8_t C3; /**< SPI control register 3, offset: 0xB */ |
mbed_official | 121:7f86b4238bec | 4511 | } SPI_Type; |
mbed_official | 121:7f86b4238bec | 4512 | |
mbed_official | 121:7f86b4238bec | 4513 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 4514 | -- SPI Register Masks |
mbed_official | 121:7f86b4238bec | 4515 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 4516 | |
mbed_official | 121:7f86b4238bec | 4517 | /*! |
mbed_official | 121:7f86b4238bec | 4518 | * @addtogroup SPI_Register_Masks SPI Register Masks |
mbed_official | 121:7f86b4238bec | 4519 | * @{ |
mbed_official | 121:7f86b4238bec | 4520 | */ |
mbed_official | 121:7f86b4238bec | 4521 | |
mbed_official | 121:7f86b4238bec | 4522 | /*! @name S - SPI Status Register */ |
mbed_official | 121:7f86b4238bec | 4523 | #define SPI_S_RFIFOEF_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 4524 | #define SPI_S_RFIFOEF_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 4525 | #define SPI_S_RFIFOEF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_RFIFOEF_SHIFT)) & SPI_S_RFIFOEF_MASK) |
mbed_official | 121:7f86b4238bec | 4526 | #define SPI_S_TXFULLF_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 4527 | #define SPI_S_TXFULLF_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 4528 | #define SPI_S_TXFULLF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_TXFULLF_SHIFT)) & SPI_S_TXFULLF_MASK) |
mbed_official | 121:7f86b4238bec | 4529 | #define SPI_S_TNEAREF_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 4530 | #define SPI_S_TNEAREF_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 4531 | #define SPI_S_TNEAREF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_TNEAREF_SHIFT)) & SPI_S_TNEAREF_MASK) |
mbed_official | 121:7f86b4238bec | 4532 | #define SPI_S_RNFULLF_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 4533 | #define SPI_S_RNFULLF_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 4534 | #define SPI_S_RNFULLF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_RNFULLF_SHIFT)) & SPI_S_RNFULLF_MASK) |
mbed_official | 121:7f86b4238bec | 4535 | #define SPI_S_MODF_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 4536 | #define SPI_S_MODF_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 4537 | #define SPI_S_MODF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_MODF_SHIFT)) & SPI_S_MODF_MASK) |
mbed_official | 121:7f86b4238bec | 4538 | #define SPI_S_SPTEF_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 4539 | #define SPI_S_SPTEF_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 4540 | #define SPI_S_SPTEF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPTEF_SHIFT)) & SPI_S_SPTEF_MASK) |
mbed_official | 121:7f86b4238bec | 4541 | #define SPI_S_SPMF_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 4542 | #define SPI_S_SPMF_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 4543 | #define SPI_S_SPMF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPMF_SHIFT)) & SPI_S_SPMF_MASK) |
mbed_official | 121:7f86b4238bec | 4544 | #define SPI_S_SPRF_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 4545 | #define SPI_S_SPRF_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 4546 | #define SPI_S_SPRF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPRF_SHIFT)) & SPI_S_SPRF_MASK) |
mbed_official | 121:7f86b4238bec | 4547 | |
mbed_official | 121:7f86b4238bec | 4548 | /*! @name BR - SPI Baud Rate Register */ |
mbed_official | 121:7f86b4238bec | 4549 | #define SPI_BR_SPR_MASK (0xFU) |
mbed_official | 121:7f86b4238bec | 4550 | #define SPI_BR_SPR_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 4551 | #define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x)) << SPI_BR_SPR_SHIFT)) & SPI_BR_SPR_MASK) |
mbed_official | 121:7f86b4238bec | 4552 | #define SPI_BR_SPPR_MASK (0x70U) |
mbed_official | 121:7f86b4238bec | 4553 | #define SPI_BR_SPPR_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 4554 | #define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x)) << SPI_BR_SPPR_SHIFT)) & SPI_BR_SPPR_MASK) |
mbed_official | 121:7f86b4238bec | 4555 | |
mbed_official | 121:7f86b4238bec | 4556 | /*! @name C2 - SPI Control Register 2 */ |
mbed_official | 121:7f86b4238bec | 4557 | #define SPI_C2_SPC0_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 4558 | #define SPI_C2_SPC0_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 4559 | #define SPI_C2_SPC0(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPC0_SHIFT)) & SPI_C2_SPC0_MASK) |
mbed_official | 121:7f86b4238bec | 4560 | #define SPI_C2_SPISWAI_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 4561 | #define SPI_C2_SPISWAI_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 4562 | #define SPI_C2_SPISWAI(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPISWAI_SHIFT)) & SPI_C2_SPISWAI_MASK) |
mbed_official | 121:7f86b4238bec | 4563 | #define SPI_C2_RXDMAE_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 4564 | #define SPI_C2_RXDMAE_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 4565 | #define SPI_C2_RXDMAE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_RXDMAE_SHIFT)) & SPI_C2_RXDMAE_MASK) |
mbed_official | 121:7f86b4238bec | 4566 | #define SPI_C2_BIDIROE_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 4567 | #define SPI_C2_BIDIROE_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 4568 | #define SPI_C2_BIDIROE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_BIDIROE_SHIFT)) & SPI_C2_BIDIROE_MASK) |
mbed_official | 121:7f86b4238bec | 4569 | #define SPI_C2_MODFEN_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 4570 | #define SPI_C2_MODFEN_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 4571 | #define SPI_C2_MODFEN(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_MODFEN_SHIFT)) & SPI_C2_MODFEN_MASK) |
mbed_official | 121:7f86b4238bec | 4572 | #define SPI_C2_TXDMAE_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 4573 | #define SPI_C2_TXDMAE_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 4574 | #define SPI_C2_TXDMAE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_TXDMAE_SHIFT)) & SPI_C2_TXDMAE_MASK) |
mbed_official | 121:7f86b4238bec | 4575 | #define SPI_C2_SPIMODE_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 4576 | #define SPI_C2_SPIMODE_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 4577 | #define SPI_C2_SPIMODE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPIMODE_SHIFT)) & SPI_C2_SPIMODE_MASK) |
mbed_official | 121:7f86b4238bec | 4578 | #define SPI_C2_SPMIE_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 4579 | #define SPI_C2_SPMIE_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 4580 | #define SPI_C2_SPMIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPMIE_SHIFT)) & SPI_C2_SPMIE_MASK) |
mbed_official | 121:7f86b4238bec | 4581 | |
mbed_official | 121:7f86b4238bec | 4582 | /*! @name C1 - SPI Control Register 1 */ |
mbed_official | 121:7f86b4238bec | 4583 | #define SPI_C1_LSBFE_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 4584 | #define SPI_C1_LSBFE_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 4585 | #define SPI_C1_LSBFE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_LSBFE_SHIFT)) & SPI_C1_LSBFE_MASK) |
mbed_official | 121:7f86b4238bec | 4586 | #define SPI_C1_SSOE_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 4587 | #define SPI_C1_SSOE_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 4588 | #define SPI_C1_SSOE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SSOE_SHIFT)) & SPI_C1_SSOE_MASK) |
mbed_official | 121:7f86b4238bec | 4589 | #define SPI_C1_CPHA_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 4590 | #define SPI_C1_CPHA_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 4591 | #define SPI_C1_CPHA(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_CPHA_SHIFT)) & SPI_C1_CPHA_MASK) |
mbed_official | 121:7f86b4238bec | 4592 | #define SPI_C1_CPOL_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 4593 | #define SPI_C1_CPOL_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 4594 | #define SPI_C1_CPOL(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_CPOL_SHIFT)) & SPI_C1_CPOL_MASK) |
mbed_official | 121:7f86b4238bec | 4595 | #define SPI_C1_MSTR_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 4596 | #define SPI_C1_MSTR_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 4597 | #define SPI_C1_MSTR(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_MSTR_SHIFT)) & SPI_C1_MSTR_MASK) |
mbed_official | 121:7f86b4238bec | 4598 | #define SPI_C1_SPTIE_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 4599 | #define SPI_C1_SPTIE_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 4600 | #define SPI_C1_SPTIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPTIE_SHIFT)) & SPI_C1_SPTIE_MASK) |
mbed_official | 121:7f86b4238bec | 4601 | #define SPI_C1_SPE_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 4602 | #define SPI_C1_SPE_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 4603 | #define SPI_C1_SPE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPE_SHIFT)) & SPI_C1_SPE_MASK) |
mbed_official | 121:7f86b4238bec | 4604 | #define SPI_C1_SPIE_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 4605 | #define SPI_C1_SPIE_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 4606 | #define SPI_C1_SPIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPIE_SHIFT)) & SPI_C1_SPIE_MASK) |
mbed_official | 121:7f86b4238bec | 4607 | |
mbed_official | 121:7f86b4238bec | 4608 | /*! @name ML - SPI Match Register low */ |
mbed_official | 121:7f86b4238bec | 4609 | #define SPI_ML_Bits_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 4610 | #define SPI_ML_Bits_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 4611 | #define SPI_ML_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_ML_Bits_SHIFT)) & SPI_ML_Bits_MASK) |
mbed_official | 121:7f86b4238bec | 4612 | |
mbed_official | 121:7f86b4238bec | 4613 | /*! @name MH - SPI match register high */ |
mbed_official | 121:7f86b4238bec | 4614 | #define SPI_MH_Bits_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 4615 | #define SPI_MH_Bits_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 4616 | #define SPI_MH_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_MH_Bits_SHIFT)) & SPI_MH_Bits_MASK) |
mbed_official | 121:7f86b4238bec | 4617 | |
mbed_official | 121:7f86b4238bec | 4618 | /*! @name DL - SPI Data Register low */ |
mbed_official | 121:7f86b4238bec | 4619 | #define SPI_DL_Bits_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 4620 | #define SPI_DL_Bits_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 4621 | #define SPI_DL_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_DL_Bits_SHIFT)) & SPI_DL_Bits_MASK) |
mbed_official | 121:7f86b4238bec | 4622 | |
mbed_official | 121:7f86b4238bec | 4623 | /*! @name DH - SPI data register high */ |
mbed_official | 121:7f86b4238bec | 4624 | #define SPI_DH_Bits_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 4625 | #define SPI_DH_Bits_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 4626 | #define SPI_DH_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_DH_Bits_SHIFT)) & SPI_DH_Bits_MASK) |
mbed_official | 121:7f86b4238bec | 4627 | |
mbed_official | 121:7f86b4238bec | 4628 | /*! @name CI - SPI clear interrupt register */ |
mbed_official | 121:7f86b4238bec | 4629 | #define SPI_CI_SPRFCI_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 4630 | #define SPI_CI_SPRFCI_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 4631 | #define SPI_CI_SPRFCI(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_SPRFCI_SHIFT)) & SPI_CI_SPRFCI_MASK) |
mbed_official | 121:7f86b4238bec | 4632 | #define SPI_CI_SPTEFCI_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 4633 | #define SPI_CI_SPTEFCI_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 4634 | #define SPI_CI_SPTEFCI(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_SPTEFCI_SHIFT)) & SPI_CI_SPTEFCI_MASK) |
mbed_official | 121:7f86b4238bec | 4635 | #define SPI_CI_RNFULLFCI_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 4636 | #define SPI_CI_RNFULLFCI_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 4637 | #define SPI_CI_RNFULLFCI(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_RNFULLFCI_SHIFT)) & SPI_CI_RNFULLFCI_MASK) |
mbed_official | 121:7f86b4238bec | 4638 | #define SPI_CI_TNEAREFCI_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 4639 | #define SPI_CI_TNEAREFCI_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 4640 | #define SPI_CI_TNEAREFCI(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_TNEAREFCI_SHIFT)) & SPI_CI_TNEAREFCI_MASK) |
mbed_official | 121:7f86b4238bec | 4641 | #define SPI_CI_RXFOF_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 4642 | #define SPI_CI_RXFOF_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 4643 | #define SPI_CI_RXFOF(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_RXFOF_SHIFT)) & SPI_CI_RXFOF_MASK) |
mbed_official | 121:7f86b4238bec | 4644 | #define SPI_CI_TXFOF_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 4645 | #define SPI_CI_TXFOF_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 4646 | #define SPI_CI_TXFOF(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_TXFOF_SHIFT)) & SPI_CI_TXFOF_MASK) |
mbed_official | 121:7f86b4238bec | 4647 | #define SPI_CI_RXFERR_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 4648 | #define SPI_CI_RXFERR_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 4649 | #define SPI_CI_RXFERR(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_RXFERR_SHIFT)) & SPI_CI_RXFERR_MASK) |
mbed_official | 121:7f86b4238bec | 4650 | #define SPI_CI_TXFERR_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 4651 | #define SPI_CI_TXFERR_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 4652 | #define SPI_CI_TXFERR(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_TXFERR_SHIFT)) & SPI_CI_TXFERR_MASK) |
mbed_official | 121:7f86b4238bec | 4653 | |
mbed_official | 121:7f86b4238bec | 4654 | /*! @name C3 - SPI control register 3 */ |
mbed_official | 121:7f86b4238bec | 4655 | #define SPI_C3_FIFOMODE_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 4656 | #define SPI_C3_FIFOMODE_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 4657 | #define SPI_C3_FIFOMODE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_FIFOMODE_SHIFT)) & SPI_C3_FIFOMODE_MASK) |
mbed_official | 121:7f86b4238bec | 4658 | #define SPI_C3_RNFULLIEN_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 4659 | #define SPI_C3_RNFULLIEN_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 4660 | #define SPI_C3_RNFULLIEN(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_RNFULLIEN_SHIFT)) & SPI_C3_RNFULLIEN_MASK) |
mbed_official | 121:7f86b4238bec | 4661 | #define SPI_C3_TNEARIEN_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 4662 | #define SPI_C3_TNEARIEN_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 4663 | #define SPI_C3_TNEARIEN(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_TNEARIEN_SHIFT)) & SPI_C3_TNEARIEN_MASK) |
mbed_official | 121:7f86b4238bec | 4664 | #define SPI_C3_INTCLR_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 4665 | #define SPI_C3_INTCLR_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 4666 | #define SPI_C3_INTCLR(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_INTCLR_SHIFT)) & SPI_C3_INTCLR_MASK) |
mbed_official | 121:7f86b4238bec | 4667 | #define SPI_C3_RNFULLF_MARK_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 4668 | #define SPI_C3_RNFULLF_MARK_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 4669 | #define SPI_C3_RNFULLF_MARK(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_RNFULLF_MARK_SHIFT)) & SPI_C3_RNFULLF_MARK_MASK) |
mbed_official | 121:7f86b4238bec | 4670 | #define SPI_C3_TNEAREF_MARK_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 4671 | #define SPI_C3_TNEAREF_MARK_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 4672 | #define SPI_C3_TNEAREF_MARK(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_TNEAREF_MARK_SHIFT)) & SPI_C3_TNEAREF_MARK_MASK) |
mbed_official | 121:7f86b4238bec | 4673 | |
mbed_official | 121:7f86b4238bec | 4674 | |
mbed_official | 121:7f86b4238bec | 4675 | /*! |
mbed_official | 121:7f86b4238bec | 4676 | * @} |
mbed_official | 121:7f86b4238bec | 4677 | */ /* end of group SPI_Register_Masks */ |
mbed_official | 121:7f86b4238bec | 4678 | |
mbed_official | 121:7f86b4238bec | 4679 | |
mbed_official | 121:7f86b4238bec | 4680 | /* SPI - Peripheral instance base addresses */ |
mbed_official | 121:7f86b4238bec | 4681 | /** Peripheral SPI0 base address */ |
mbed_official | 121:7f86b4238bec | 4682 | #define SPI0_BASE (0x40076000u) |
mbed_official | 121:7f86b4238bec | 4683 | /** Peripheral SPI0 base pointer */ |
mbed_official | 121:7f86b4238bec | 4684 | #define SPI0 ((SPI_Type *)SPI0_BASE) |
mbed_official | 121:7f86b4238bec | 4685 | /** Peripheral SPI1 base address */ |
mbed_official | 121:7f86b4238bec | 4686 | #define SPI1_BASE (0x40077000u) |
mbed_official | 121:7f86b4238bec | 4687 | /** Peripheral SPI1 base pointer */ |
mbed_official | 121:7f86b4238bec | 4688 | #define SPI1 ((SPI_Type *)SPI1_BASE) |
mbed_official | 121:7f86b4238bec | 4689 | /** Array initializer of SPI peripheral base addresses */ |
mbed_official | 121:7f86b4238bec | 4690 | #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE } |
mbed_official | 121:7f86b4238bec | 4691 | /** Array initializer of SPI peripheral base pointers */ |
mbed_official | 121:7f86b4238bec | 4692 | #define SPI_BASE_PTRS { SPI0, SPI1 } |
mbed_official | 121:7f86b4238bec | 4693 | /** Interrupt vectors for the SPI peripheral type */ |
mbed_official | 121:7f86b4238bec | 4694 | #define SPI_IRQS { SPI0_IRQn, SPI1_IRQn } |
mbed_official | 121:7f86b4238bec | 4695 | |
mbed_official | 121:7f86b4238bec | 4696 | /*! |
mbed_official | 121:7f86b4238bec | 4697 | * @} |
mbed_official | 121:7f86b4238bec | 4698 | */ /* end of group SPI_Peripheral_Access_Layer */ |
mbed_official | 121:7f86b4238bec | 4699 | |
mbed_official | 121:7f86b4238bec | 4700 | |
mbed_official | 121:7f86b4238bec | 4701 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 4702 | -- TPM Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 4703 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 4704 | |
mbed_official | 121:7f86b4238bec | 4705 | /*! |
mbed_official | 121:7f86b4238bec | 4706 | * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 4707 | * @{ |
mbed_official | 121:7f86b4238bec | 4708 | */ |
mbed_official | 121:7f86b4238bec | 4709 | |
mbed_official | 121:7f86b4238bec | 4710 | /** TPM - Register Layout Typedef */ |
mbed_official | 121:7f86b4238bec | 4711 | typedef struct { |
mbed_official | 121:7f86b4238bec | 4712 | __IO uint32_t SC; /**< Status and Control, offset: 0x0 */ |
mbed_official | 121:7f86b4238bec | 4713 | __IO uint32_t CNT; /**< Counter, offset: 0x4 */ |
mbed_official | 121:7f86b4238bec | 4714 | __IO uint32_t MOD; /**< Modulo, offset: 0x8 */ |
mbed_official | 121:7f86b4238bec | 4715 | struct { /* offset: 0xC, array step: 0x8 */ |
mbed_official | 121:7f86b4238bec | 4716 | __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */ |
mbed_official | 121:7f86b4238bec | 4717 | __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */ |
mbed_official | 121:7f86b4238bec | 4718 | } CONTROLS[6]; |
mbed_official | 121:7f86b4238bec | 4719 | uint8_t RESERVED_0[20]; |
mbed_official | 121:7f86b4238bec | 4720 | __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */ |
mbed_official | 121:7f86b4238bec | 4721 | uint8_t RESERVED_1[28]; |
mbed_official | 121:7f86b4238bec | 4722 | __IO uint32_t POL; /**< Channel Polarity, offset: 0x70 */ |
mbed_official | 121:7f86b4238bec | 4723 | uint8_t RESERVED_2[16]; |
mbed_official | 121:7f86b4238bec | 4724 | __IO uint32_t CONF; /**< Configuration, offset: 0x84 */ |
mbed_official | 121:7f86b4238bec | 4725 | } TPM_Type; |
mbed_official | 121:7f86b4238bec | 4726 | |
mbed_official | 121:7f86b4238bec | 4727 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 4728 | -- TPM Register Masks |
mbed_official | 121:7f86b4238bec | 4729 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 4730 | |
mbed_official | 121:7f86b4238bec | 4731 | /*! |
mbed_official | 121:7f86b4238bec | 4732 | * @addtogroup TPM_Register_Masks TPM Register Masks |
mbed_official | 121:7f86b4238bec | 4733 | * @{ |
mbed_official | 121:7f86b4238bec | 4734 | */ |
mbed_official | 121:7f86b4238bec | 4735 | |
mbed_official | 121:7f86b4238bec | 4736 | /*! @name SC - Status and Control */ |
mbed_official | 121:7f86b4238bec | 4737 | #define TPM_SC_PS_MASK (0x7U) |
mbed_official | 121:7f86b4238bec | 4738 | #define TPM_SC_PS_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 4739 | #define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK) |
mbed_official | 121:7f86b4238bec | 4740 | #define TPM_SC_CMOD_MASK (0x18U) |
mbed_official | 121:7f86b4238bec | 4741 | #define TPM_SC_CMOD_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 4742 | #define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK) |
mbed_official | 121:7f86b4238bec | 4743 | #define TPM_SC_CPWMS_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 4744 | #define TPM_SC_CPWMS_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 4745 | #define TPM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK) |
mbed_official | 121:7f86b4238bec | 4746 | #define TPM_SC_TOIE_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 4747 | #define TPM_SC_TOIE_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 4748 | #define TPM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK) |
mbed_official | 121:7f86b4238bec | 4749 | #define TPM_SC_TOF_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 4750 | #define TPM_SC_TOF_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 4751 | #define TPM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK) |
mbed_official | 121:7f86b4238bec | 4752 | #define TPM_SC_DMA_MASK (0x100U) |
mbed_official | 121:7f86b4238bec | 4753 | #define TPM_SC_DMA_SHIFT (8U) |
mbed_official | 121:7f86b4238bec | 4754 | #define TPM_SC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK) |
mbed_official | 121:7f86b4238bec | 4755 | |
mbed_official | 121:7f86b4238bec | 4756 | /*! @name CNT - Counter */ |
mbed_official | 121:7f86b4238bec | 4757 | #define TPM_CNT_COUNT_MASK (0xFFFFU) |
mbed_official | 121:7f86b4238bec | 4758 | #define TPM_CNT_COUNT_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 4759 | #define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK) |
mbed_official | 121:7f86b4238bec | 4760 | |
mbed_official | 121:7f86b4238bec | 4761 | /*! @name MOD - Modulo */ |
mbed_official | 121:7f86b4238bec | 4762 | #define TPM_MOD_MOD_MASK (0xFFFFU) |
mbed_official | 121:7f86b4238bec | 4763 | #define TPM_MOD_MOD_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 4764 | #define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK) |
mbed_official | 121:7f86b4238bec | 4765 | |
mbed_official | 121:7f86b4238bec | 4766 | /*! @name CnSC - Channel (n) Status and Control */ |
mbed_official | 121:7f86b4238bec | 4767 | #define TPM_CnSC_DMA_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 4768 | #define TPM_CnSC_DMA_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 4769 | #define TPM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK) |
mbed_official | 121:7f86b4238bec | 4770 | #define TPM_CnSC_ELSA_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 4771 | #define TPM_CnSC_ELSA_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 4772 | #define TPM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK) |
mbed_official | 121:7f86b4238bec | 4773 | #define TPM_CnSC_ELSB_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 4774 | #define TPM_CnSC_ELSB_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 4775 | #define TPM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK) |
mbed_official | 121:7f86b4238bec | 4776 | #define TPM_CnSC_MSA_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 4777 | #define TPM_CnSC_MSA_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 4778 | #define TPM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK) |
mbed_official | 121:7f86b4238bec | 4779 | #define TPM_CnSC_MSB_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 4780 | #define TPM_CnSC_MSB_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 4781 | #define TPM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK) |
mbed_official | 121:7f86b4238bec | 4782 | #define TPM_CnSC_CHIE_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 4783 | #define TPM_CnSC_CHIE_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 4784 | #define TPM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK) |
mbed_official | 121:7f86b4238bec | 4785 | #define TPM_CnSC_CHF_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 4786 | #define TPM_CnSC_CHF_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 4787 | #define TPM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK) |
mbed_official | 121:7f86b4238bec | 4788 | |
mbed_official | 121:7f86b4238bec | 4789 | /* The count of TPM_CnSC */ |
mbed_official | 121:7f86b4238bec | 4790 | #define TPM_CnSC_COUNT (6U) |
mbed_official | 121:7f86b4238bec | 4791 | |
mbed_official | 121:7f86b4238bec | 4792 | /*! @name CnV - Channel (n) Value */ |
mbed_official | 121:7f86b4238bec | 4793 | #define TPM_CnV_VAL_MASK (0xFFFFU) |
mbed_official | 121:7f86b4238bec | 4794 | #define TPM_CnV_VAL_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 4795 | #define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK) |
mbed_official | 121:7f86b4238bec | 4796 | |
mbed_official | 121:7f86b4238bec | 4797 | /* The count of TPM_CnV */ |
mbed_official | 121:7f86b4238bec | 4798 | #define TPM_CnV_COUNT (6U) |
mbed_official | 121:7f86b4238bec | 4799 | |
mbed_official | 121:7f86b4238bec | 4800 | /*! @name STATUS - Capture and Compare Status */ |
mbed_official | 121:7f86b4238bec | 4801 | #define TPM_STATUS_CH0F_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 4802 | #define TPM_STATUS_CH0F_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 4803 | #define TPM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK) |
mbed_official | 121:7f86b4238bec | 4804 | #define TPM_STATUS_CH1F_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 4805 | #define TPM_STATUS_CH1F_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 4806 | #define TPM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK) |
mbed_official | 121:7f86b4238bec | 4807 | #define TPM_STATUS_CH2F_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 4808 | #define TPM_STATUS_CH2F_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 4809 | #define TPM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH2F_SHIFT)) & TPM_STATUS_CH2F_MASK) |
mbed_official | 121:7f86b4238bec | 4810 | #define TPM_STATUS_CH3F_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 4811 | #define TPM_STATUS_CH3F_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 4812 | #define TPM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH3F_SHIFT)) & TPM_STATUS_CH3F_MASK) |
mbed_official | 121:7f86b4238bec | 4813 | #define TPM_STATUS_CH4F_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 4814 | #define TPM_STATUS_CH4F_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 4815 | #define TPM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH4F_SHIFT)) & TPM_STATUS_CH4F_MASK) |
mbed_official | 121:7f86b4238bec | 4816 | #define TPM_STATUS_CH5F_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 4817 | #define TPM_STATUS_CH5F_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 4818 | #define TPM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH5F_SHIFT)) & TPM_STATUS_CH5F_MASK) |
mbed_official | 121:7f86b4238bec | 4819 | #define TPM_STATUS_TOF_MASK (0x100U) |
mbed_official | 121:7f86b4238bec | 4820 | #define TPM_STATUS_TOF_SHIFT (8U) |
mbed_official | 121:7f86b4238bec | 4821 | #define TPM_STATUS_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK) |
mbed_official | 121:7f86b4238bec | 4822 | |
mbed_official | 121:7f86b4238bec | 4823 | /*! @name POL - Channel Polarity */ |
mbed_official | 121:7f86b4238bec | 4824 | #define TPM_POL_POL0_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 4825 | #define TPM_POL_POL0_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 4826 | #define TPM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL0_SHIFT)) & TPM_POL_POL0_MASK) |
mbed_official | 121:7f86b4238bec | 4827 | #define TPM_POL_POL1_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 4828 | #define TPM_POL_POL1_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 4829 | #define TPM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL1_SHIFT)) & TPM_POL_POL1_MASK) |
mbed_official | 121:7f86b4238bec | 4830 | #define TPM_POL_POL2_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 4831 | #define TPM_POL_POL2_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 4832 | #define TPM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL2_SHIFT)) & TPM_POL_POL2_MASK) |
mbed_official | 121:7f86b4238bec | 4833 | #define TPM_POL_POL3_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 4834 | #define TPM_POL_POL3_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 4835 | #define TPM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL3_SHIFT)) & TPM_POL_POL3_MASK) |
mbed_official | 121:7f86b4238bec | 4836 | #define TPM_POL_POL4_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 4837 | #define TPM_POL_POL4_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 4838 | #define TPM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL4_SHIFT)) & TPM_POL_POL4_MASK) |
mbed_official | 121:7f86b4238bec | 4839 | #define TPM_POL_POL5_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 4840 | #define TPM_POL_POL5_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 4841 | #define TPM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL5_SHIFT)) & TPM_POL_POL5_MASK) |
mbed_official | 121:7f86b4238bec | 4842 | |
mbed_official | 121:7f86b4238bec | 4843 | /*! @name CONF - Configuration */ |
mbed_official | 121:7f86b4238bec | 4844 | #define TPM_CONF_DOZEEN_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 4845 | #define TPM_CONF_DOZEEN_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 4846 | #define TPM_CONF_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK) |
mbed_official | 121:7f86b4238bec | 4847 | #define TPM_CONF_DBGMODE_MASK (0xC0U) |
mbed_official | 121:7f86b4238bec | 4848 | #define TPM_CONF_DBGMODE_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 4849 | #define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK) |
mbed_official | 121:7f86b4238bec | 4850 | #define TPM_CONF_GTBSYNC_MASK (0x100U) |
mbed_official | 121:7f86b4238bec | 4851 | #define TPM_CONF_GTBSYNC_SHIFT (8U) |
mbed_official | 121:7f86b4238bec | 4852 | #define TPM_CONF_GTBSYNC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBSYNC_SHIFT)) & TPM_CONF_GTBSYNC_MASK) |
mbed_official | 121:7f86b4238bec | 4853 | #define TPM_CONF_GTBEEN_MASK (0x200U) |
mbed_official | 121:7f86b4238bec | 4854 | #define TPM_CONF_GTBEEN_SHIFT (9U) |
mbed_official | 121:7f86b4238bec | 4855 | #define TPM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK) |
mbed_official | 121:7f86b4238bec | 4856 | #define TPM_CONF_CSOT_MASK (0x10000U) |
mbed_official | 121:7f86b4238bec | 4857 | #define TPM_CONF_CSOT_SHIFT (16U) |
mbed_official | 121:7f86b4238bec | 4858 | #define TPM_CONF_CSOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK) |
mbed_official | 121:7f86b4238bec | 4859 | #define TPM_CONF_CSOO_MASK (0x20000U) |
mbed_official | 121:7f86b4238bec | 4860 | #define TPM_CONF_CSOO_SHIFT (17U) |
mbed_official | 121:7f86b4238bec | 4861 | #define TPM_CONF_CSOO(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK) |
mbed_official | 121:7f86b4238bec | 4862 | #define TPM_CONF_CROT_MASK (0x40000U) |
mbed_official | 121:7f86b4238bec | 4863 | #define TPM_CONF_CROT_SHIFT (18U) |
mbed_official | 121:7f86b4238bec | 4864 | #define TPM_CONF_CROT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK) |
mbed_official | 121:7f86b4238bec | 4865 | #define TPM_CONF_CPOT_MASK (0x80000U) |
mbed_official | 121:7f86b4238bec | 4866 | #define TPM_CONF_CPOT_SHIFT (19U) |
mbed_official | 121:7f86b4238bec | 4867 | #define TPM_CONF_CPOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CPOT_SHIFT)) & TPM_CONF_CPOT_MASK) |
mbed_official | 121:7f86b4238bec | 4868 | #define TPM_CONF_TRGPOL_MASK (0x400000U) |
mbed_official | 121:7f86b4238bec | 4869 | #define TPM_CONF_TRGPOL_SHIFT (22U) |
mbed_official | 121:7f86b4238bec | 4870 | #define TPM_CONF_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGPOL_SHIFT)) & TPM_CONF_TRGPOL_MASK) |
mbed_official | 121:7f86b4238bec | 4871 | #define TPM_CONF_TRGSRC_MASK (0x800000U) |
mbed_official | 121:7f86b4238bec | 4872 | #define TPM_CONF_TRGSRC_SHIFT (23U) |
mbed_official | 121:7f86b4238bec | 4873 | #define TPM_CONF_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSRC_SHIFT)) & TPM_CONF_TRGSRC_MASK) |
mbed_official | 121:7f86b4238bec | 4874 | #define TPM_CONF_TRGSEL_MASK (0xF000000U) |
mbed_official | 121:7f86b4238bec | 4875 | #define TPM_CONF_TRGSEL_SHIFT (24U) |
mbed_official | 121:7f86b4238bec | 4876 | #define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK) |
mbed_official | 121:7f86b4238bec | 4877 | |
mbed_official | 121:7f86b4238bec | 4878 | |
mbed_official | 121:7f86b4238bec | 4879 | /*! |
mbed_official | 121:7f86b4238bec | 4880 | * @} |
mbed_official | 121:7f86b4238bec | 4881 | */ /* end of group TPM_Register_Masks */ |
mbed_official | 121:7f86b4238bec | 4882 | |
mbed_official | 121:7f86b4238bec | 4883 | |
mbed_official | 121:7f86b4238bec | 4884 | /* TPM - Peripheral instance base addresses */ |
mbed_official | 121:7f86b4238bec | 4885 | /** Peripheral TPM0 base address */ |
mbed_official | 121:7f86b4238bec | 4886 | #define TPM0_BASE (0x40038000u) |
mbed_official | 121:7f86b4238bec | 4887 | /** Peripheral TPM0 base pointer */ |
mbed_official | 121:7f86b4238bec | 4888 | #define TPM0 ((TPM_Type *)TPM0_BASE) |
mbed_official | 121:7f86b4238bec | 4889 | /** Peripheral TPM1 base address */ |
mbed_official | 121:7f86b4238bec | 4890 | #define TPM1_BASE (0x40039000u) |
mbed_official | 121:7f86b4238bec | 4891 | /** Peripheral TPM1 base pointer */ |
mbed_official | 121:7f86b4238bec | 4892 | #define TPM1 ((TPM_Type *)TPM1_BASE) |
mbed_official | 121:7f86b4238bec | 4893 | /** Peripheral TPM2 base address */ |
mbed_official | 121:7f86b4238bec | 4894 | #define TPM2_BASE (0x4003A000u) |
mbed_official | 121:7f86b4238bec | 4895 | /** Peripheral TPM2 base pointer */ |
mbed_official | 121:7f86b4238bec | 4896 | #define TPM2 ((TPM_Type *)TPM2_BASE) |
mbed_official | 121:7f86b4238bec | 4897 | /** Array initializer of TPM peripheral base addresses */ |
mbed_official | 121:7f86b4238bec | 4898 | #define TPM_BASE_ADDRS { TPM0_BASE, TPM1_BASE, TPM2_BASE } |
mbed_official | 121:7f86b4238bec | 4899 | /** Array initializer of TPM peripheral base pointers */ |
mbed_official | 121:7f86b4238bec | 4900 | #define TPM_BASE_PTRS { TPM0, TPM1, TPM2 } |
mbed_official | 121:7f86b4238bec | 4901 | /** Interrupt vectors for the TPM peripheral type */ |
mbed_official | 121:7f86b4238bec | 4902 | #define TPM_IRQS { TPM0_IRQn, TPM1_IRQn, TPM2_IRQn } |
mbed_official | 121:7f86b4238bec | 4903 | |
mbed_official | 121:7f86b4238bec | 4904 | /*! |
mbed_official | 121:7f86b4238bec | 4905 | * @} |
mbed_official | 121:7f86b4238bec | 4906 | */ /* end of group TPM_Peripheral_Access_Layer */ |
mbed_official | 121:7f86b4238bec | 4907 | |
mbed_official | 121:7f86b4238bec | 4908 | |
mbed_official | 121:7f86b4238bec | 4909 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 4910 | -- UART Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 4911 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 4912 | |
mbed_official | 121:7f86b4238bec | 4913 | /*! |
mbed_official | 121:7f86b4238bec | 4914 | * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 4915 | * @{ |
mbed_official | 121:7f86b4238bec | 4916 | */ |
mbed_official | 121:7f86b4238bec | 4917 | |
mbed_official | 121:7f86b4238bec | 4918 | /** UART - Register Layout Typedef */ |
mbed_official | 121:7f86b4238bec | 4919 | typedef struct { |
mbed_official | 121:7f86b4238bec | 4920 | __IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */ |
mbed_official | 121:7f86b4238bec | 4921 | __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */ |
mbed_official | 121:7f86b4238bec | 4922 | __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */ |
mbed_official | 121:7f86b4238bec | 4923 | __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */ |
mbed_official | 121:7f86b4238bec | 4924 | __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */ |
mbed_official | 121:7f86b4238bec | 4925 | __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */ |
mbed_official | 121:7f86b4238bec | 4926 | __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */ |
mbed_official | 121:7f86b4238bec | 4927 | __IO uint8_t D; /**< UART Data Register, offset: 0x7 */ |
mbed_official | 121:7f86b4238bec | 4928 | __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */ |
mbed_official | 121:7f86b4238bec | 4929 | __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */ |
mbed_official | 121:7f86b4238bec | 4930 | __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */ |
mbed_official | 121:7f86b4238bec | 4931 | __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */ |
mbed_official | 121:7f86b4238bec | 4932 | uint8_t RESERVED_0[12]; |
mbed_official | 121:7f86b4238bec | 4933 | __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */ |
mbed_official | 121:7f86b4238bec | 4934 | __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */ |
mbed_official | 121:7f86b4238bec | 4935 | __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */ |
mbed_official | 121:7f86b4238bec | 4936 | __IO uint8_t WP7816; /**< UART 7816 Wait Parameter Register, offset: 0x1B */ |
mbed_official | 121:7f86b4238bec | 4937 | __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */ |
mbed_official | 121:7f86b4238bec | 4938 | __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */ |
mbed_official | 121:7f86b4238bec | 4939 | __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */ |
mbed_official | 121:7f86b4238bec | 4940 | __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */ |
mbed_official | 121:7f86b4238bec | 4941 | uint8_t RESERVED_1[26]; |
mbed_official | 121:7f86b4238bec | 4942 | __IO uint8_t AP7816A_T0; /**< UART 7816 ATR Duration Timer Register A, offset: 0x3A */ |
mbed_official | 121:7f86b4238bec | 4943 | __IO uint8_t AP7816B_T0; /**< UART 7816 ATR Duration Timer Register B, offset: 0x3B */ |
mbed_official | 121:7f86b4238bec | 4944 | union { /* offset: 0x3C */ |
mbed_official | 121:7f86b4238bec | 4945 | struct { /* offset: 0x3C */ |
mbed_official | 121:7f86b4238bec | 4946 | __IO uint8_t WP7816A_T0; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */ |
mbed_official | 121:7f86b4238bec | 4947 | __IO uint8_t WP7816B_T0; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */ |
mbed_official | 121:7f86b4238bec | 4948 | } TYPE0; |
mbed_official | 121:7f86b4238bec | 4949 | struct { /* offset: 0x3C */ |
mbed_official | 121:7f86b4238bec | 4950 | __IO uint8_t WP7816A_T1; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */ |
mbed_official | 121:7f86b4238bec | 4951 | __IO uint8_t WP7816B_T1; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */ |
mbed_official | 121:7f86b4238bec | 4952 | } TYPE1; |
mbed_official | 121:7f86b4238bec | 4953 | }; |
mbed_official | 121:7f86b4238bec | 4954 | __IO uint8_t WGP7816_T1; /**< UART 7816 Wait and Guard Parameter Register, offset: 0x3E */ |
mbed_official | 121:7f86b4238bec | 4955 | __IO uint8_t WP7816C_T1; /**< UART 7816 Wait Parameter Register C, offset: 0x3F */ |
mbed_official | 121:7f86b4238bec | 4956 | } UART_Type; |
mbed_official | 121:7f86b4238bec | 4957 | |
mbed_official | 121:7f86b4238bec | 4958 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 4959 | -- UART Register Masks |
mbed_official | 121:7f86b4238bec | 4960 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 4961 | |
mbed_official | 121:7f86b4238bec | 4962 | /*! |
mbed_official | 121:7f86b4238bec | 4963 | * @addtogroup UART_Register_Masks UART Register Masks |
mbed_official | 121:7f86b4238bec | 4964 | * @{ |
mbed_official | 121:7f86b4238bec | 4965 | */ |
mbed_official | 121:7f86b4238bec | 4966 | |
mbed_official | 121:7f86b4238bec | 4967 | /*! @name BDH - UART Baud Rate Registers: High */ |
mbed_official | 121:7f86b4238bec | 4968 | #define UART_BDH_SBR_MASK (0x1FU) |
mbed_official | 121:7f86b4238bec | 4969 | #define UART_BDH_SBR_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 4970 | #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBR_SHIFT)) & UART_BDH_SBR_MASK) |
mbed_official | 121:7f86b4238bec | 4971 | #define UART_BDH_RXEDGIE_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 4972 | #define UART_BDH_RXEDGIE_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 4973 | #define UART_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_RXEDGIE_SHIFT)) & UART_BDH_RXEDGIE_MASK) |
mbed_official | 121:7f86b4238bec | 4974 | |
mbed_official | 121:7f86b4238bec | 4975 | /*! @name BDL - UART Baud Rate Registers: Low */ |
mbed_official | 121:7f86b4238bec | 4976 | #define UART_BDL_SBR_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 4977 | #define UART_BDL_SBR_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 4978 | #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDL_SBR_SHIFT)) & UART_BDL_SBR_MASK) |
mbed_official | 121:7f86b4238bec | 4979 | |
mbed_official | 121:7f86b4238bec | 4980 | /*! @name C1 - UART Control Register 1 */ |
mbed_official | 121:7f86b4238bec | 4981 | #define UART_C1_PT_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 4982 | #define UART_C1_PT_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 4983 | #define UART_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PT_SHIFT)) & UART_C1_PT_MASK) |
mbed_official | 121:7f86b4238bec | 4984 | #define UART_C1_PE_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 4985 | #define UART_C1_PE_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 4986 | #define UART_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PE_SHIFT)) & UART_C1_PE_MASK) |
mbed_official | 121:7f86b4238bec | 4987 | #define UART_C1_ILT_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 4988 | #define UART_C1_ILT_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 4989 | #define UART_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_ILT_SHIFT)) & UART_C1_ILT_MASK) |
mbed_official | 121:7f86b4238bec | 4990 | #define UART_C1_WAKE_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 4991 | #define UART_C1_WAKE_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 4992 | #define UART_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_WAKE_SHIFT)) & UART_C1_WAKE_MASK) |
mbed_official | 121:7f86b4238bec | 4993 | #define UART_C1_M_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 4994 | #define UART_C1_M_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 4995 | #define UART_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_M_SHIFT)) & UART_C1_M_MASK) |
mbed_official | 121:7f86b4238bec | 4996 | #define UART_C1_RSRC_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 4997 | #define UART_C1_RSRC_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 4998 | #define UART_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_RSRC_SHIFT)) & UART_C1_RSRC_MASK) |
mbed_official | 121:7f86b4238bec | 4999 | #define UART_C1_LOOPS_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 5000 | #define UART_C1_LOOPS_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 5001 | #define UART_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_LOOPS_SHIFT)) & UART_C1_LOOPS_MASK) |
mbed_official | 121:7f86b4238bec | 5002 | |
mbed_official | 121:7f86b4238bec | 5003 | /*! @name C2 - UART Control Register 2 */ |
mbed_official | 121:7f86b4238bec | 5004 | #define UART_C2_SBK_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 5005 | #define UART_C2_SBK_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 5006 | #define UART_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_SBK_SHIFT)) & UART_C2_SBK_MASK) |
mbed_official | 121:7f86b4238bec | 5007 | #define UART_C2_RWU_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 5008 | #define UART_C2_RWU_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 5009 | #define UART_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RWU_SHIFT)) & UART_C2_RWU_MASK) |
mbed_official | 121:7f86b4238bec | 5010 | #define UART_C2_RE_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 5011 | #define UART_C2_RE_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 5012 | #define UART_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RE_SHIFT)) & UART_C2_RE_MASK) |
mbed_official | 121:7f86b4238bec | 5013 | #define UART_C2_TE_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 5014 | #define UART_C2_TE_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 5015 | #define UART_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TE_SHIFT)) & UART_C2_TE_MASK) |
mbed_official | 121:7f86b4238bec | 5016 | #define UART_C2_ILIE_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 5017 | #define UART_C2_ILIE_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 5018 | #define UART_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_ILIE_SHIFT)) & UART_C2_ILIE_MASK) |
mbed_official | 121:7f86b4238bec | 5019 | #define UART_C2_RIE_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 5020 | #define UART_C2_RIE_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 5021 | #define UART_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RIE_SHIFT)) & UART_C2_RIE_MASK) |
mbed_official | 121:7f86b4238bec | 5022 | #define UART_C2_TCIE_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 5023 | #define UART_C2_TCIE_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 5024 | #define UART_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TCIE_SHIFT)) & UART_C2_TCIE_MASK) |
mbed_official | 121:7f86b4238bec | 5025 | #define UART_C2_TIE_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 5026 | #define UART_C2_TIE_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 5027 | #define UART_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TIE_SHIFT)) & UART_C2_TIE_MASK) |
mbed_official | 121:7f86b4238bec | 5028 | |
mbed_official | 121:7f86b4238bec | 5029 | /*! @name S1 - UART Status Register 1 */ |
mbed_official | 121:7f86b4238bec | 5030 | #define UART_S1_PF_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 5031 | #define UART_S1_PF_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 5032 | #define UART_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_PF_SHIFT)) & UART_S1_PF_MASK) |
mbed_official | 121:7f86b4238bec | 5033 | #define UART_S1_FE_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 5034 | #define UART_S1_FE_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 5035 | #define UART_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_FE_SHIFT)) & UART_S1_FE_MASK) |
mbed_official | 121:7f86b4238bec | 5036 | #define UART_S1_NF_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 5037 | #define UART_S1_NF_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 5038 | #define UART_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_NF_SHIFT)) & UART_S1_NF_MASK) |
mbed_official | 121:7f86b4238bec | 5039 | #define UART_S1_OR_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 5040 | #define UART_S1_OR_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 5041 | #define UART_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_OR_SHIFT)) & UART_S1_OR_MASK) |
mbed_official | 121:7f86b4238bec | 5042 | #define UART_S1_IDLE_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 5043 | #define UART_S1_IDLE_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 5044 | #define UART_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_IDLE_SHIFT)) & UART_S1_IDLE_MASK) |
mbed_official | 121:7f86b4238bec | 5045 | #define UART_S1_RDRF_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 5046 | #define UART_S1_RDRF_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 5047 | #define UART_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_RDRF_SHIFT)) & UART_S1_RDRF_MASK) |
mbed_official | 121:7f86b4238bec | 5048 | #define UART_S1_TC_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 5049 | #define UART_S1_TC_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 5050 | #define UART_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TC_SHIFT)) & UART_S1_TC_MASK) |
mbed_official | 121:7f86b4238bec | 5051 | #define UART_S1_TDRE_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 5052 | #define UART_S1_TDRE_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 5053 | #define UART_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TDRE_SHIFT)) & UART_S1_TDRE_MASK) |
mbed_official | 121:7f86b4238bec | 5054 | |
mbed_official | 121:7f86b4238bec | 5055 | /*! @name S2 - UART Status Register 2 */ |
mbed_official | 121:7f86b4238bec | 5056 | #define UART_S2_RAF_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 5057 | #define UART_S2_RAF_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 5058 | #define UART_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RAF_SHIFT)) & UART_S2_RAF_MASK) |
mbed_official | 121:7f86b4238bec | 5059 | #define UART_S2_BRK13_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 5060 | #define UART_S2_BRK13_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 5061 | #define UART_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_BRK13_SHIFT)) & UART_S2_BRK13_MASK) |
mbed_official | 121:7f86b4238bec | 5062 | #define UART_S2_RWUID_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 5063 | #define UART_S2_RWUID_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 5064 | #define UART_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RWUID_SHIFT)) & UART_S2_RWUID_MASK) |
mbed_official | 121:7f86b4238bec | 5065 | #define UART_S2_RXINV_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 5066 | #define UART_S2_RXINV_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 5067 | #define UART_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXINV_SHIFT)) & UART_S2_RXINV_MASK) |
mbed_official | 121:7f86b4238bec | 5068 | #define UART_S2_MSBF_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 5069 | #define UART_S2_MSBF_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 5070 | #define UART_S2_MSBF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_MSBF_SHIFT)) & UART_S2_MSBF_MASK) |
mbed_official | 121:7f86b4238bec | 5071 | #define UART_S2_RXEDGIF_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 5072 | #define UART_S2_RXEDGIF_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 5073 | #define UART_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXEDGIF_SHIFT)) & UART_S2_RXEDGIF_MASK) |
mbed_official | 121:7f86b4238bec | 5074 | |
mbed_official | 121:7f86b4238bec | 5075 | /*! @name C3 - UART Control Register 3 */ |
mbed_official | 121:7f86b4238bec | 5076 | #define UART_C3_PEIE_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 5077 | #define UART_C3_PEIE_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 5078 | #define UART_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_PEIE_SHIFT)) & UART_C3_PEIE_MASK) |
mbed_official | 121:7f86b4238bec | 5079 | #define UART_C3_FEIE_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 5080 | #define UART_C3_FEIE_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 5081 | #define UART_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_FEIE_SHIFT)) & UART_C3_FEIE_MASK) |
mbed_official | 121:7f86b4238bec | 5082 | #define UART_C3_NEIE_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 5083 | #define UART_C3_NEIE_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 5084 | #define UART_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_NEIE_SHIFT)) & UART_C3_NEIE_MASK) |
mbed_official | 121:7f86b4238bec | 5085 | #define UART_C3_ORIE_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 5086 | #define UART_C3_ORIE_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 5087 | #define UART_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_ORIE_SHIFT)) & UART_C3_ORIE_MASK) |
mbed_official | 121:7f86b4238bec | 5088 | #define UART_C3_TXINV_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 5089 | #define UART_C3_TXINV_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 5090 | #define UART_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXINV_SHIFT)) & UART_C3_TXINV_MASK) |
mbed_official | 121:7f86b4238bec | 5091 | #define UART_C3_TXDIR_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 5092 | #define UART_C3_TXDIR_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 5093 | #define UART_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXDIR_SHIFT)) & UART_C3_TXDIR_MASK) |
mbed_official | 121:7f86b4238bec | 5094 | #define UART_C3_T8_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 5095 | #define UART_C3_T8_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 5096 | #define UART_C3_T8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_T8_SHIFT)) & UART_C3_T8_MASK) |
mbed_official | 121:7f86b4238bec | 5097 | #define UART_C3_R8_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 5098 | #define UART_C3_R8_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 5099 | #define UART_C3_R8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_R8_SHIFT)) & UART_C3_R8_MASK) |
mbed_official | 121:7f86b4238bec | 5100 | |
mbed_official | 121:7f86b4238bec | 5101 | /*! @name D - UART Data Register */ |
mbed_official | 121:7f86b4238bec | 5102 | #define UART_D_RT_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 5103 | #define UART_D_RT_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 5104 | #define UART_D_RT(x) (((uint8_t)(((uint8_t)(x)) << UART_D_RT_SHIFT)) & UART_D_RT_MASK) |
mbed_official | 121:7f86b4238bec | 5105 | |
mbed_official | 121:7f86b4238bec | 5106 | /*! @name MA1 - UART Match Address Registers 1 */ |
mbed_official | 121:7f86b4238bec | 5107 | #define UART_MA1_MA_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 5108 | #define UART_MA1_MA_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 5109 | #define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA1_MA_SHIFT)) & UART_MA1_MA_MASK) |
mbed_official | 121:7f86b4238bec | 5110 | |
mbed_official | 121:7f86b4238bec | 5111 | /*! @name MA2 - UART Match Address Registers 2 */ |
mbed_official | 121:7f86b4238bec | 5112 | #define UART_MA2_MA_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 5113 | #define UART_MA2_MA_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 5114 | #define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA2_MA_SHIFT)) & UART_MA2_MA_MASK) |
mbed_official | 121:7f86b4238bec | 5115 | |
mbed_official | 121:7f86b4238bec | 5116 | /*! @name C4 - UART Control Register 4 */ |
mbed_official | 121:7f86b4238bec | 5117 | #define UART_C4_BRFA_MASK (0x1FU) |
mbed_official | 121:7f86b4238bec | 5118 | #define UART_C4_BRFA_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 5119 | #define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_BRFA_SHIFT)) & UART_C4_BRFA_MASK) |
mbed_official | 121:7f86b4238bec | 5120 | #define UART_C4_M10_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 5121 | #define UART_C4_M10_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 5122 | #define UART_C4_M10(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_M10_SHIFT)) & UART_C4_M10_MASK) |
mbed_official | 121:7f86b4238bec | 5123 | #define UART_C4_MAEN2_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 5124 | #define UART_C4_MAEN2_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 5125 | #define UART_C4_MAEN2(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN2_SHIFT)) & UART_C4_MAEN2_MASK) |
mbed_official | 121:7f86b4238bec | 5126 | #define UART_C4_MAEN1_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 5127 | #define UART_C4_MAEN1_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 5128 | #define UART_C4_MAEN1(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN1_SHIFT)) & UART_C4_MAEN1_MASK) |
mbed_official | 121:7f86b4238bec | 5129 | |
mbed_official | 121:7f86b4238bec | 5130 | /*! @name C5 - UART Control Register 5 */ |
mbed_official | 121:7f86b4238bec | 5131 | #define UART_C5_RDMAS_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 5132 | #define UART_C5_RDMAS_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 5133 | #define UART_C5_RDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_RDMAS_SHIFT)) & UART_C5_RDMAS_MASK) |
mbed_official | 121:7f86b4238bec | 5134 | #define UART_C5_TDMAS_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 5135 | #define UART_C5_TDMAS_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 5136 | #define UART_C5_TDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_TDMAS_SHIFT)) & UART_C5_TDMAS_MASK) |
mbed_official | 121:7f86b4238bec | 5137 | |
mbed_official | 121:7f86b4238bec | 5138 | /*! @name C7816 - UART 7816 Control Register */ |
mbed_official | 121:7f86b4238bec | 5139 | #define UART_C7816_ISO_7816E_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 5140 | #define UART_C7816_ISO_7816E_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 5141 | #define UART_C7816_ISO_7816E(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ISO_7816E_SHIFT)) & UART_C7816_ISO_7816E_MASK) |
mbed_official | 121:7f86b4238bec | 5142 | #define UART_C7816_TTYPE_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 5143 | #define UART_C7816_TTYPE_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 5144 | #define UART_C7816_TTYPE(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_TTYPE_SHIFT)) & UART_C7816_TTYPE_MASK) |
mbed_official | 121:7f86b4238bec | 5145 | #define UART_C7816_INIT_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 5146 | #define UART_C7816_INIT_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 5147 | #define UART_C7816_INIT(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_INIT_SHIFT)) & UART_C7816_INIT_MASK) |
mbed_official | 121:7f86b4238bec | 5148 | #define UART_C7816_ANACK_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 5149 | #define UART_C7816_ANACK_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 5150 | #define UART_C7816_ANACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ANACK_SHIFT)) & UART_C7816_ANACK_MASK) |
mbed_official | 121:7f86b4238bec | 5151 | #define UART_C7816_ONACK_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 5152 | #define UART_C7816_ONACK_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 5153 | #define UART_C7816_ONACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ONACK_SHIFT)) & UART_C7816_ONACK_MASK) |
mbed_official | 121:7f86b4238bec | 5154 | |
mbed_official | 121:7f86b4238bec | 5155 | /*! @name IE7816 - UART 7816 Interrupt Enable Register */ |
mbed_official | 121:7f86b4238bec | 5156 | #define UART_IE7816_RXTE_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 5157 | #define UART_IE7816_RXTE_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 5158 | #define UART_IE7816_RXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_RXTE_SHIFT)) & UART_IE7816_RXTE_MASK) |
mbed_official | 121:7f86b4238bec | 5159 | #define UART_IE7816_TXTE_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 5160 | #define UART_IE7816_TXTE_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 5161 | #define UART_IE7816_TXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_TXTE_SHIFT)) & UART_IE7816_TXTE_MASK) |
mbed_official | 121:7f86b4238bec | 5162 | #define UART_IE7816_GTVE_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 5163 | #define UART_IE7816_GTVE_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 5164 | #define UART_IE7816_GTVE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_GTVE_SHIFT)) & UART_IE7816_GTVE_MASK) |
mbed_official | 121:7f86b4238bec | 5165 | #define UART_IE7816_ADTE_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 5166 | #define UART_IE7816_ADTE_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 5167 | #define UART_IE7816_ADTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_ADTE_SHIFT)) & UART_IE7816_ADTE_MASK) |
mbed_official | 121:7f86b4238bec | 5168 | #define UART_IE7816_INITDE_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 5169 | #define UART_IE7816_INITDE_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 5170 | #define UART_IE7816_INITDE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_INITDE_SHIFT)) & UART_IE7816_INITDE_MASK) |
mbed_official | 121:7f86b4238bec | 5171 | #define UART_IE7816_BWTE_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 5172 | #define UART_IE7816_BWTE_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 5173 | #define UART_IE7816_BWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_BWTE_SHIFT)) & UART_IE7816_BWTE_MASK) |
mbed_official | 121:7f86b4238bec | 5174 | #define UART_IE7816_CWTE_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 5175 | #define UART_IE7816_CWTE_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 5176 | #define UART_IE7816_CWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_CWTE_SHIFT)) & UART_IE7816_CWTE_MASK) |
mbed_official | 121:7f86b4238bec | 5177 | #define UART_IE7816_WTE_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 5178 | #define UART_IE7816_WTE_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 5179 | #define UART_IE7816_WTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_WTE_SHIFT)) & UART_IE7816_WTE_MASK) |
mbed_official | 121:7f86b4238bec | 5180 | |
mbed_official | 121:7f86b4238bec | 5181 | /*! @name IS7816 - UART 7816 Interrupt Status Register */ |
mbed_official | 121:7f86b4238bec | 5182 | #define UART_IS7816_RXT_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 5183 | #define UART_IS7816_RXT_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 5184 | #define UART_IS7816_RXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_RXT_SHIFT)) & UART_IS7816_RXT_MASK) |
mbed_official | 121:7f86b4238bec | 5185 | #define UART_IS7816_TXT_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 5186 | #define UART_IS7816_TXT_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 5187 | #define UART_IS7816_TXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_TXT_SHIFT)) & UART_IS7816_TXT_MASK) |
mbed_official | 121:7f86b4238bec | 5188 | #define UART_IS7816_GTV_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 5189 | #define UART_IS7816_GTV_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 5190 | #define UART_IS7816_GTV(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_GTV_SHIFT)) & UART_IS7816_GTV_MASK) |
mbed_official | 121:7f86b4238bec | 5191 | #define UART_IS7816_ADT_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 5192 | #define UART_IS7816_ADT_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 5193 | #define UART_IS7816_ADT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_ADT_SHIFT)) & UART_IS7816_ADT_MASK) |
mbed_official | 121:7f86b4238bec | 5194 | #define UART_IS7816_INITD_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 5195 | #define UART_IS7816_INITD_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 5196 | #define UART_IS7816_INITD(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_INITD_SHIFT)) & UART_IS7816_INITD_MASK) |
mbed_official | 121:7f86b4238bec | 5197 | #define UART_IS7816_BWT_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 5198 | #define UART_IS7816_BWT_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 5199 | #define UART_IS7816_BWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_BWT_SHIFT)) & UART_IS7816_BWT_MASK) |
mbed_official | 121:7f86b4238bec | 5200 | #define UART_IS7816_CWT_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 5201 | #define UART_IS7816_CWT_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 5202 | #define UART_IS7816_CWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_CWT_SHIFT)) & UART_IS7816_CWT_MASK) |
mbed_official | 121:7f86b4238bec | 5203 | #define UART_IS7816_WT_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 5204 | #define UART_IS7816_WT_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 5205 | #define UART_IS7816_WT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_WT_SHIFT)) & UART_IS7816_WT_MASK) |
mbed_official | 121:7f86b4238bec | 5206 | |
mbed_official | 121:7f86b4238bec | 5207 | /*! @name WP7816 - UART 7816 Wait Parameter Register */ |
mbed_official | 121:7f86b4238bec | 5208 | #define UART_WP7816_WTX_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 5209 | #define UART_WP7816_WTX_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 5210 | #define UART_WP7816_WTX(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816_WTX_SHIFT)) & UART_WP7816_WTX_MASK) |
mbed_official | 121:7f86b4238bec | 5211 | |
mbed_official | 121:7f86b4238bec | 5212 | /*! @name WN7816 - UART 7816 Wait N Register */ |
mbed_official | 121:7f86b4238bec | 5213 | #define UART_WN7816_GTN_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 5214 | #define UART_WN7816_GTN_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 5215 | #define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x)) << UART_WN7816_GTN_SHIFT)) & UART_WN7816_GTN_MASK) |
mbed_official | 121:7f86b4238bec | 5216 | |
mbed_official | 121:7f86b4238bec | 5217 | /*! @name WF7816 - UART 7816 Wait FD Register */ |
mbed_official | 121:7f86b4238bec | 5218 | #define UART_WF7816_GTFD_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 5219 | #define UART_WF7816_GTFD_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 5220 | #define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x)) << UART_WF7816_GTFD_SHIFT)) & UART_WF7816_GTFD_MASK) |
mbed_official | 121:7f86b4238bec | 5221 | |
mbed_official | 121:7f86b4238bec | 5222 | /*! @name ET7816 - UART 7816 Error Threshold Register */ |
mbed_official | 121:7f86b4238bec | 5223 | #define UART_ET7816_RXTHRESHOLD_MASK (0xFU) |
mbed_official | 121:7f86b4238bec | 5224 | #define UART_ET7816_RXTHRESHOLD_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 5225 | #define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_RXTHRESHOLD_SHIFT)) & UART_ET7816_RXTHRESHOLD_MASK) |
mbed_official | 121:7f86b4238bec | 5226 | #define UART_ET7816_TXTHRESHOLD_MASK (0xF0U) |
mbed_official | 121:7f86b4238bec | 5227 | #define UART_ET7816_TXTHRESHOLD_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 5228 | #define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_TXTHRESHOLD_SHIFT)) & UART_ET7816_TXTHRESHOLD_MASK) |
mbed_official | 121:7f86b4238bec | 5229 | |
mbed_official | 121:7f86b4238bec | 5230 | /*! @name TL7816 - UART 7816 Transmit Length Register */ |
mbed_official | 121:7f86b4238bec | 5231 | #define UART_TL7816_TLEN_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 5232 | #define UART_TL7816_TLEN_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 5233 | #define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x)) << UART_TL7816_TLEN_SHIFT)) & UART_TL7816_TLEN_MASK) |
mbed_official | 121:7f86b4238bec | 5234 | |
mbed_official | 121:7f86b4238bec | 5235 | /*! @name AP7816A_T0 - UART 7816 ATR Duration Timer Register A */ |
mbed_official | 121:7f86b4238bec | 5236 | #define UART_AP7816A_T0_ADTI_H_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 5237 | #define UART_AP7816A_T0_ADTI_H_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 5238 | #define UART_AP7816A_T0_ADTI_H(x) (((uint8_t)(((uint8_t)(x)) << UART_AP7816A_T0_ADTI_H_SHIFT)) & UART_AP7816A_T0_ADTI_H_MASK) |
mbed_official | 121:7f86b4238bec | 5239 | |
mbed_official | 121:7f86b4238bec | 5240 | /*! @name AP7816B_T0 - UART 7816 ATR Duration Timer Register B */ |
mbed_official | 121:7f86b4238bec | 5241 | #define UART_AP7816B_T0_ADTI_L_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 5242 | #define UART_AP7816B_T0_ADTI_L_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 5243 | #define UART_AP7816B_T0_ADTI_L(x) (((uint8_t)(((uint8_t)(x)) << UART_AP7816B_T0_ADTI_L_SHIFT)) & UART_AP7816B_T0_ADTI_L_MASK) |
mbed_official | 121:7f86b4238bec | 5244 | |
mbed_official | 121:7f86b4238bec | 5245 | /*! @name WP7816A_T0 - UART 7816 Wait Parameter Register A */ |
mbed_official | 121:7f86b4238bec | 5246 | #define UART_WP7816A_T0_WI_H_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 5247 | #define UART_WP7816A_T0_WI_H_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 5248 | #define UART_WP7816A_T0_WI_H(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816A_T0_WI_H_SHIFT)) & UART_WP7816A_T0_WI_H_MASK) |
mbed_official | 121:7f86b4238bec | 5249 | |
mbed_official | 121:7f86b4238bec | 5250 | /*! @name WP7816B_T0 - UART 7816 Wait Parameter Register B */ |
mbed_official | 121:7f86b4238bec | 5251 | #define UART_WP7816B_T0_WI_L_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 5252 | #define UART_WP7816B_T0_WI_L_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 5253 | #define UART_WP7816B_T0_WI_L(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816B_T0_WI_L_SHIFT)) & UART_WP7816B_T0_WI_L_MASK) |
mbed_official | 121:7f86b4238bec | 5254 | |
mbed_official | 121:7f86b4238bec | 5255 | /*! @name WP7816A_T1 - UART 7816 Wait Parameter Register A */ |
mbed_official | 121:7f86b4238bec | 5256 | #define UART_WP7816A_T1_BWI_H_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 5257 | #define UART_WP7816A_T1_BWI_H_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 5258 | #define UART_WP7816A_T1_BWI_H(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816A_T1_BWI_H_SHIFT)) & UART_WP7816A_T1_BWI_H_MASK) |
mbed_official | 121:7f86b4238bec | 5259 | |
mbed_official | 121:7f86b4238bec | 5260 | /*! @name WP7816B_T1 - UART 7816 Wait Parameter Register B */ |
mbed_official | 121:7f86b4238bec | 5261 | #define UART_WP7816B_T1_BWI_L_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 5262 | #define UART_WP7816B_T1_BWI_L_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 5263 | #define UART_WP7816B_T1_BWI_L(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816B_T1_BWI_L_SHIFT)) & UART_WP7816B_T1_BWI_L_MASK) |
mbed_official | 121:7f86b4238bec | 5264 | |
mbed_official | 121:7f86b4238bec | 5265 | /*! @name WGP7816_T1 - UART 7816 Wait and Guard Parameter Register */ |
mbed_official | 121:7f86b4238bec | 5266 | #define UART_WGP7816_T1_BGI_MASK (0xFU) |
mbed_official | 121:7f86b4238bec | 5267 | #define UART_WGP7816_T1_BGI_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 5268 | #define UART_WGP7816_T1_BGI(x) (((uint8_t)(((uint8_t)(x)) << UART_WGP7816_T1_BGI_SHIFT)) & UART_WGP7816_T1_BGI_MASK) |
mbed_official | 121:7f86b4238bec | 5269 | #define UART_WGP7816_T1_CWI1_MASK (0xF0U) |
mbed_official | 121:7f86b4238bec | 5270 | #define UART_WGP7816_T1_CWI1_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 5271 | #define UART_WGP7816_T1_CWI1(x) (((uint8_t)(((uint8_t)(x)) << UART_WGP7816_T1_CWI1_SHIFT)) & UART_WGP7816_T1_CWI1_MASK) |
mbed_official | 121:7f86b4238bec | 5272 | |
mbed_official | 121:7f86b4238bec | 5273 | /*! @name WP7816C_T1 - UART 7816 Wait Parameter Register C */ |
mbed_official | 121:7f86b4238bec | 5274 | #define UART_WP7816C_T1_CWI2_MASK (0x1FU) |
mbed_official | 121:7f86b4238bec | 5275 | #define UART_WP7816C_T1_CWI2_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 5276 | #define UART_WP7816C_T1_CWI2(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816C_T1_CWI2_SHIFT)) & UART_WP7816C_T1_CWI2_MASK) |
mbed_official | 121:7f86b4238bec | 5277 | |
mbed_official | 121:7f86b4238bec | 5278 | |
mbed_official | 121:7f86b4238bec | 5279 | /*! |
mbed_official | 121:7f86b4238bec | 5280 | * @} |
mbed_official | 121:7f86b4238bec | 5281 | */ /* end of group UART_Register_Masks */ |
mbed_official | 121:7f86b4238bec | 5282 | |
mbed_official | 121:7f86b4238bec | 5283 | |
mbed_official | 121:7f86b4238bec | 5284 | /* UART - Peripheral instance base addresses */ |
mbed_official | 121:7f86b4238bec | 5285 | /** Peripheral UART2 base address */ |
mbed_official | 121:7f86b4238bec | 5286 | #define UART2_BASE (0x4006C000u) |
mbed_official | 121:7f86b4238bec | 5287 | /** Peripheral UART2 base pointer */ |
mbed_official | 121:7f86b4238bec | 5288 | #define UART2 ((UART_Type *)UART2_BASE) |
mbed_official | 121:7f86b4238bec | 5289 | /** Array initializer of UART peripheral base addresses */ |
mbed_official | 121:7f86b4238bec | 5290 | #define UART_BASE_ADDRS { 0u, 0u, UART2_BASE } |
mbed_official | 121:7f86b4238bec | 5291 | /** Array initializer of UART peripheral base pointers */ |
mbed_official | 121:7f86b4238bec | 5292 | #define UART_BASE_PTRS { (UART_Type *)0u, (UART_Type *)0u, UART2 } |
mbed_official | 121:7f86b4238bec | 5293 | /** Interrupt vectors for the UART peripheral type */ |
mbed_official | 121:7f86b4238bec | 5294 | #define UART_RX_TX_IRQS { NotAvail_IRQn, NotAvail_IRQn, UART2_FLEXIO_IRQn } |
mbed_official | 121:7f86b4238bec | 5295 | #define UART_ERR_IRQS { NotAvail_IRQn, NotAvail_IRQn, UART2_FLEXIO_IRQn } |
mbed_official | 121:7f86b4238bec | 5296 | |
mbed_official | 121:7f86b4238bec | 5297 | /*! |
mbed_official | 121:7f86b4238bec | 5298 | * @} |
mbed_official | 121:7f86b4238bec | 5299 | */ /* end of group UART_Peripheral_Access_Layer */ |
mbed_official | 121:7f86b4238bec | 5300 | |
mbed_official | 121:7f86b4238bec | 5301 | |
mbed_official | 121:7f86b4238bec | 5302 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 5303 | -- USB Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 5304 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 5305 | |
mbed_official | 121:7f86b4238bec | 5306 | /*! |
mbed_official | 121:7f86b4238bec | 5307 | * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 5308 | * @{ |
mbed_official | 121:7f86b4238bec | 5309 | */ |
mbed_official | 121:7f86b4238bec | 5310 | |
mbed_official | 121:7f86b4238bec | 5311 | /** USB - Register Layout Typedef */ |
mbed_official | 121:7f86b4238bec | 5312 | typedef struct { |
mbed_official | 121:7f86b4238bec | 5313 | __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */ |
mbed_official | 121:7f86b4238bec | 5314 | uint8_t RESERVED_0[3]; |
mbed_official | 121:7f86b4238bec | 5315 | __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */ |
mbed_official | 121:7f86b4238bec | 5316 | uint8_t RESERVED_1[3]; |
mbed_official | 121:7f86b4238bec | 5317 | __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */ |
mbed_official | 121:7f86b4238bec | 5318 | uint8_t RESERVED_2[3]; |
mbed_official | 121:7f86b4238bec | 5319 | __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */ |
mbed_official | 121:7f86b4238bec | 5320 | uint8_t RESERVED_3[15]; |
mbed_official | 121:7f86b4238bec | 5321 | __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */ |
mbed_official | 121:7f86b4238bec | 5322 | uint8_t RESERVED_4[99]; |
mbed_official | 121:7f86b4238bec | 5323 | __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */ |
mbed_official | 121:7f86b4238bec | 5324 | uint8_t RESERVED_5[3]; |
mbed_official | 121:7f86b4238bec | 5325 | __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */ |
mbed_official | 121:7f86b4238bec | 5326 | uint8_t RESERVED_6[3]; |
mbed_official | 121:7f86b4238bec | 5327 | __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */ |
mbed_official | 121:7f86b4238bec | 5328 | uint8_t RESERVED_7[3]; |
mbed_official | 121:7f86b4238bec | 5329 | __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */ |
mbed_official | 121:7f86b4238bec | 5330 | uint8_t RESERVED_8[3]; |
mbed_official | 121:7f86b4238bec | 5331 | __I uint8_t STAT; /**< Status register, offset: 0x90 */ |
mbed_official | 121:7f86b4238bec | 5332 | uint8_t RESERVED_9[3]; |
mbed_official | 121:7f86b4238bec | 5333 | __IO uint8_t CTL; /**< Control register, offset: 0x94 */ |
mbed_official | 121:7f86b4238bec | 5334 | uint8_t RESERVED_10[3]; |
mbed_official | 121:7f86b4238bec | 5335 | __IO uint8_t ADDR; /**< Address register, offset: 0x98 */ |
mbed_official | 121:7f86b4238bec | 5336 | uint8_t RESERVED_11[3]; |
mbed_official | 121:7f86b4238bec | 5337 | __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */ |
mbed_official | 121:7f86b4238bec | 5338 | uint8_t RESERVED_12[3]; |
mbed_official | 121:7f86b4238bec | 5339 | __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */ |
mbed_official | 121:7f86b4238bec | 5340 | uint8_t RESERVED_13[3]; |
mbed_official | 121:7f86b4238bec | 5341 | __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */ |
mbed_official | 121:7f86b4238bec | 5342 | uint8_t RESERVED_14[11]; |
mbed_official | 121:7f86b4238bec | 5343 | __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */ |
mbed_official | 121:7f86b4238bec | 5344 | uint8_t RESERVED_15[3]; |
mbed_official | 121:7f86b4238bec | 5345 | __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */ |
mbed_official | 121:7f86b4238bec | 5346 | uint8_t RESERVED_16[11]; |
mbed_official | 121:7f86b4238bec | 5347 | struct { /* offset: 0xC0, array step: 0x4 */ |
mbed_official | 121:7f86b4238bec | 5348 | __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */ |
mbed_official | 121:7f86b4238bec | 5349 | uint8_t RESERVED_0[3]; |
mbed_official | 121:7f86b4238bec | 5350 | } ENDPOINT[16]; |
mbed_official | 121:7f86b4238bec | 5351 | __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */ |
mbed_official | 121:7f86b4238bec | 5352 | uint8_t RESERVED_17[3]; |
mbed_official | 121:7f86b4238bec | 5353 | __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */ |
mbed_official | 121:7f86b4238bec | 5354 | uint8_t RESERVED_18[3]; |
mbed_official | 121:7f86b4238bec | 5355 | __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */ |
mbed_official | 121:7f86b4238bec | 5356 | uint8_t RESERVED_19[3]; |
mbed_official | 121:7f86b4238bec | 5357 | __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */ |
mbed_official | 121:7f86b4238bec | 5358 | uint8_t RESERVED_20[7]; |
mbed_official | 121:7f86b4238bec | 5359 | __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */ |
mbed_official | 121:7f86b4238bec | 5360 | uint8_t RESERVED_21[15]; |
mbed_official | 121:7f86b4238bec | 5361 | __IO uint8_t KEEP_ALIVE_CTRL; /**< Keep Alive mode control, offset: 0x124 */ |
mbed_official | 121:7f86b4238bec | 5362 | uint8_t RESERVED_22[3]; |
mbed_official | 121:7f86b4238bec | 5363 | __IO uint8_t KEEP_ALIVE_WKCTRL; /**< Keep Alive mode wakeup control, offset: 0x128 */ |
mbed_official | 121:7f86b4238bec | 5364 | uint8_t RESERVED_23[23]; |
mbed_official | 121:7f86b4238bec | 5365 | __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */ |
mbed_official | 121:7f86b4238bec | 5366 | uint8_t RESERVED_24[3]; |
mbed_official | 121:7f86b4238bec | 5367 | __IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48M oscillator enable register, offset: 0x144 */ |
mbed_official | 121:7f86b4238bec | 5368 | uint8_t RESERVED_25[15]; |
mbed_official | 121:7f86b4238bec | 5369 | __IO uint8_t CLK_RECOVER_INT_EN; /**< Clock recovery combined interrupt enable, offset: 0x154 */ |
mbed_official | 121:7f86b4238bec | 5370 | uint8_t RESERVED_26[7]; |
mbed_official | 121:7f86b4238bec | 5371 | __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */ |
mbed_official | 121:7f86b4238bec | 5372 | } USB_Type; |
mbed_official | 121:7f86b4238bec | 5373 | |
mbed_official | 121:7f86b4238bec | 5374 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 5375 | -- USB Register Masks |
mbed_official | 121:7f86b4238bec | 5376 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 5377 | |
mbed_official | 121:7f86b4238bec | 5378 | /*! |
mbed_official | 121:7f86b4238bec | 5379 | * @addtogroup USB_Register_Masks USB Register Masks |
mbed_official | 121:7f86b4238bec | 5380 | * @{ |
mbed_official | 121:7f86b4238bec | 5381 | */ |
mbed_official | 121:7f86b4238bec | 5382 | |
mbed_official | 121:7f86b4238bec | 5383 | /*! @name PERID - Peripheral ID register */ |
mbed_official | 121:7f86b4238bec | 5384 | #define USB_PERID_ID_MASK (0x3FU) |
mbed_official | 121:7f86b4238bec | 5385 | #define USB_PERID_ID_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 5386 | #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK) |
mbed_official | 121:7f86b4238bec | 5387 | |
mbed_official | 121:7f86b4238bec | 5388 | /*! @name IDCOMP - Peripheral ID Complement register */ |
mbed_official | 121:7f86b4238bec | 5389 | #define USB_IDCOMP_NID_MASK (0x3FU) |
mbed_official | 121:7f86b4238bec | 5390 | #define USB_IDCOMP_NID_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 5391 | #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK) |
mbed_official | 121:7f86b4238bec | 5392 | |
mbed_official | 121:7f86b4238bec | 5393 | /*! @name REV - Peripheral Revision register */ |
mbed_official | 121:7f86b4238bec | 5394 | #define USB_REV_REV_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 5395 | #define USB_REV_REV_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 5396 | #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK) |
mbed_official | 121:7f86b4238bec | 5397 | |
mbed_official | 121:7f86b4238bec | 5398 | /*! @name ADDINFO - Peripheral Additional Info register */ |
mbed_official | 121:7f86b4238bec | 5399 | #define USB_ADDINFO_IEHOST_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 5400 | #define USB_ADDINFO_IEHOST_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 5401 | #define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK) |
mbed_official | 121:7f86b4238bec | 5402 | |
mbed_official | 121:7f86b4238bec | 5403 | /*! @name OTGCTL - OTG Control register */ |
mbed_official | 121:7f86b4238bec | 5404 | #define USB_OTGCTL_DPHIGH_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 5405 | #define USB_OTGCTL_DPHIGH_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 5406 | #define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK) |
mbed_official | 121:7f86b4238bec | 5407 | |
mbed_official | 121:7f86b4238bec | 5408 | /*! @name ISTAT - Interrupt Status register */ |
mbed_official | 121:7f86b4238bec | 5409 | #define USB_ISTAT_USBRST_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 5410 | #define USB_ISTAT_USBRST_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 5411 | #define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK) |
mbed_official | 121:7f86b4238bec | 5412 | #define USB_ISTAT_ERROR_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 5413 | #define USB_ISTAT_ERROR_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 5414 | #define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK) |
mbed_official | 121:7f86b4238bec | 5415 | #define USB_ISTAT_SOFTOK_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 5416 | #define USB_ISTAT_SOFTOK_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 5417 | #define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK) |
mbed_official | 121:7f86b4238bec | 5418 | #define USB_ISTAT_TOKDNE_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 5419 | #define USB_ISTAT_TOKDNE_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 5420 | #define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK) |
mbed_official | 121:7f86b4238bec | 5421 | #define USB_ISTAT_SLEEP_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 5422 | #define USB_ISTAT_SLEEP_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 5423 | #define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK) |
mbed_official | 121:7f86b4238bec | 5424 | #define USB_ISTAT_RESUME_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 5425 | #define USB_ISTAT_RESUME_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 5426 | #define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK) |
mbed_official | 121:7f86b4238bec | 5427 | #define USB_ISTAT_STALL_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 5428 | #define USB_ISTAT_STALL_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 5429 | #define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK) |
mbed_official | 121:7f86b4238bec | 5430 | |
mbed_official | 121:7f86b4238bec | 5431 | /*! @name INTEN - Interrupt Enable register */ |
mbed_official | 121:7f86b4238bec | 5432 | #define USB_INTEN_USBRSTEN_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 5433 | #define USB_INTEN_USBRSTEN_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 5434 | #define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK) |
mbed_official | 121:7f86b4238bec | 5435 | #define USB_INTEN_ERROREN_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 5436 | #define USB_INTEN_ERROREN_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 5437 | #define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK) |
mbed_official | 121:7f86b4238bec | 5438 | #define USB_INTEN_SOFTOKEN_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 5439 | #define USB_INTEN_SOFTOKEN_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 5440 | #define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK) |
mbed_official | 121:7f86b4238bec | 5441 | #define USB_INTEN_TOKDNEEN_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 5442 | #define USB_INTEN_TOKDNEEN_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 5443 | #define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK) |
mbed_official | 121:7f86b4238bec | 5444 | #define USB_INTEN_SLEEPEN_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 5445 | #define USB_INTEN_SLEEPEN_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 5446 | #define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK) |
mbed_official | 121:7f86b4238bec | 5447 | #define USB_INTEN_RESUMEEN_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 5448 | #define USB_INTEN_RESUMEEN_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 5449 | #define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK) |
mbed_official | 121:7f86b4238bec | 5450 | #define USB_INTEN_STALLEN_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 5451 | #define USB_INTEN_STALLEN_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 5452 | #define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK) |
mbed_official | 121:7f86b4238bec | 5453 | |
mbed_official | 121:7f86b4238bec | 5454 | /*! @name ERRSTAT - Error Interrupt Status register */ |
mbed_official | 121:7f86b4238bec | 5455 | #define USB_ERRSTAT_PIDERR_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 5456 | #define USB_ERRSTAT_PIDERR_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 5457 | #define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK) |
mbed_official | 121:7f86b4238bec | 5458 | #define USB_ERRSTAT_CRC5_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 5459 | #define USB_ERRSTAT_CRC5_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 5460 | #define USB_ERRSTAT_CRC5(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5_SHIFT)) & USB_ERRSTAT_CRC5_MASK) |
mbed_official | 121:7f86b4238bec | 5461 | #define USB_ERRSTAT_CRC16_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 5462 | #define USB_ERRSTAT_CRC16_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 5463 | #define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK) |
mbed_official | 121:7f86b4238bec | 5464 | #define USB_ERRSTAT_DFN8_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 5465 | #define USB_ERRSTAT_DFN8_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 5466 | #define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK) |
mbed_official | 121:7f86b4238bec | 5467 | #define USB_ERRSTAT_BTOERR_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 5468 | #define USB_ERRSTAT_BTOERR_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 5469 | #define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK) |
mbed_official | 121:7f86b4238bec | 5470 | #define USB_ERRSTAT_DMAERR_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 5471 | #define USB_ERRSTAT_DMAERR_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 5472 | #define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK) |
mbed_official | 121:7f86b4238bec | 5473 | #define USB_ERRSTAT_BTSERR_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 5474 | #define USB_ERRSTAT_BTSERR_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 5475 | #define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK) |
mbed_official | 121:7f86b4238bec | 5476 | |
mbed_official | 121:7f86b4238bec | 5477 | /*! @name ERREN - Error Interrupt Enable register */ |
mbed_official | 121:7f86b4238bec | 5478 | #define USB_ERREN_PIDERREN_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 5479 | #define USB_ERREN_PIDERREN_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 5480 | #define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK) |
mbed_official | 121:7f86b4238bec | 5481 | #define USB_ERREN_CRC5EOFEN_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 5482 | #define USB_ERREN_CRC5EOFEN_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 5483 | #define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK) |
mbed_official | 121:7f86b4238bec | 5484 | #define USB_ERREN_CRC16EN_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 5485 | #define USB_ERREN_CRC16EN_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 5486 | #define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK) |
mbed_official | 121:7f86b4238bec | 5487 | #define USB_ERREN_DFN8EN_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 5488 | #define USB_ERREN_DFN8EN_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 5489 | #define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK) |
mbed_official | 121:7f86b4238bec | 5490 | #define USB_ERREN_BTOERREN_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 5491 | #define USB_ERREN_BTOERREN_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 5492 | #define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK) |
mbed_official | 121:7f86b4238bec | 5493 | #define USB_ERREN_DMAERREN_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 5494 | #define USB_ERREN_DMAERREN_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 5495 | #define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK) |
mbed_official | 121:7f86b4238bec | 5496 | #define USB_ERREN_BTSERREN_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 5497 | #define USB_ERREN_BTSERREN_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 5498 | #define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK) |
mbed_official | 121:7f86b4238bec | 5499 | |
mbed_official | 121:7f86b4238bec | 5500 | /*! @name STAT - Status register */ |
mbed_official | 121:7f86b4238bec | 5501 | #define USB_STAT_ODD_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 5502 | #define USB_STAT_ODD_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 5503 | #define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK) |
mbed_official | 121:7f86b4238bec | 5504 | #define USB_STAT_TX_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 5505 | #define USB_STAT_TX_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 5506 | #define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK) |
mbed_official | 121:7f86b4238bec | 5507 | #define USB_STAT_ENDP_MASK (0xF0U) |
mbed_official | 121:7f86b4238bec | 5508 | #define USB_STAT_ENDP_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 5509 | #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK) |
mbed_official | 121:7f86b4238bec | 5510 | |
mbed_official | 121:7f86b4238bec | 5511 | /*! @name CTL - Control register */ |
mbed_official | 121:7f86b4238bec | 5512 | #define USB_CTL_USBENSOFEN_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 5513 | #define USB_CTL_USBENSOFEN_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 5514 | #define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK) |
mbed_official | 121:7f86b4238bec | 5515 | #define USB_CTL_ODDRST_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 5516 | #define USB_CTL_ODDRST_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 5517 | #define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK) |
mbed_official | 121:7f86b4238bec | 5518 | #define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 5519 | #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 5520 | #define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK) |
mbed_official | 121:7f86b4238bec | 5521 | #define USB_CTL_SE0_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 5522 | #define USB_CTL_SE0_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 5523 | #define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK) |
mbed_official | 121:7f86b4238bec | 5524 | #define USB_CTL_JSTATE_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 5525 | #define USB_CTL_JSTATE_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 5526 | #define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK) |
mbed_official | 121:7f86b4238bec | 5527 | |
mbed_official | 121:7f86b4238bec | 5528 | /*! @name ADDR - Address register */ |
mbed_official | 121:7f86b4238bec | 5529 | #define USB_ADDR_ADDR_MASK (0x7FU) |
mbed_official | 121:7f86b4238bec | 5530 | #define USB_ADDR_ADDR_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 5531 | #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK) |
mbed_official | 121:7f86b4238bec | 5532 | |
mbed_official | 121:7f86b4238bec | 5533 | /*! @name BDTPAGE1 - BDT Page register 1 */ |
mbed_official | 121:7f86b4238bec | 5534 | #define USB_BDTPAGE1_BDTBA_MASK (0xFEU) |
mbed_official | 121:7f86b4238bec | 5535 | #define USB_BDTPAGE1_BDTBA_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 5536 | #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK) |
mbed_official | 121:7f86b4238bec | 5537 | |
mbed_official | 121:7f86b4238bec | 5538 | /*! @name FRMNUML - Frame Number register Low */ |
mbed_official | 121:7f86b4238bec | 5539 | #define USB_FRMNUML_FRM_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 5540 | #define USB_FRMNUML_FRM_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 5541 | #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK) |
mbed_official | 121:7f86b4238bec | 5542 | |
mbed_official | 121:7f86b4238bec | 5543 | /*! @name FRMNUMH - Frame Number register High */ |
mbed_official | 121:7f86b4238bec | 5544 | #define USB_FRMNUMH_FRM_MASK (0x7U) |
mbed_official | 121:7f86b4238bec | 5545 | #define USB_FRMNUMH_FRM_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 5546 | #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK) |
mbed_official | 121:7f86b4238bec | 5547 | |
mbed_official | 121:7f86b4238bec | 5548 | /*! @name BDTPAGE2 - BDT Page Register 2 */ |
mbed_official | 121:7f86b4238bec | 5549 | #define USB_BDTPAGE2_BDTBA_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 5550 | #define USB_BDTPAGE2_BDTBA_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 5551 | #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK) |
mbed_official | 121:7f86b4238bec | 5552 | |
mbed_official | 121:7f86b4238bec | 5553 | /*! @name BDTPAGE3 - BDT Page Register 3 */ |
mbed_official | 121:7f86b4238bec | 5554 | #define USB_BDTPAGE3_BDTBA_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 5555 | #define USB_BDTPAGE3_BDTBA_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 5556 | #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK) |
mbed_official | 121:7f86b4238bec | 5557 | |
mbed_official | 121:7f86b4238bec | 5558 | /*! @name ENDPT - Endpoint Control register */ |
mbed_official | 121:7f86b4238bec | 5559 | #define USB_ENDPT_EPHSHK_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 5560 | #define USB_ENDPT_EPHSHK_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 5561 | #define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK) |
mbed_official | 121:7f86b4238bec | 5562 | #define USB_ENDPT_EPSTALL_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 5563 | #define USB_ENDPT_EPSTALL_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 5564 | #define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK) |
mbed_official | 121:7f86b4238bec | 5565 | #define USB_ENDPT_EPTXEN_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 5566 | #define USB_ENDPT_EPTXEN_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 5567 | #define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK) |
mbed_official | 121:7f86b4238bec | 5568 | #define USB_ENDPT_EPRXEN_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 5569 | #define USB_ENDPT_EPRXEN_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 5570 | #define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK) |
mbed_official | 121:7f86b4238bec | 5571 | #define USB_ENDPT_EPCTLDIS_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 5572 | #define USB_ENDPT_EPCTLDIS_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 5573 | #define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK) |
mbed_official | 121:7f86b4238bec | 5574 | |
mbed_official | 121:7f86b4238bec | 5575 | /* The count of USB_ENDPT */ |
mbed_official | 121:7f86b4238bec | 5576 | #define USB_ENDPT_COUNT (16U) |
mbed_official | 121:7f86b4238bec | 5577 | |
mbed_official | 121:7f86b4238bec | 5578 | /*! @name USBCTRL - USB Control register */ |
mbed_official | 121:7f86b4238bec | 5579 | #define USB_USBCTRL_PDE_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 5580 | #define USB_USBCTRL_PDE_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 5581 | #define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK) |
mbed_official | 121:7f86b4238bec | 5582 | #define USB_USBCTRL_SUSP_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 5583 | #define USB_USBCTRL_SUSP_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 5584 | #define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK) |
mbed_official | 121:7f86b4238bec | 5585 | |
mbed_official | 121:7f86b4238bec | 5586 | /*! @name OBSERVE - USB OTG Observe register */ |
mbed_official | 121:7f86b4238bec | 5587 | #define USB_OBSERVE_DMPD_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 5588 | #define USB_OBSERVE_DMPD_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 5589 | #define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK) |
mbed_official | 121:7f86b4238bec | 5590 | #define USB_OBSERVE_DPPD_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 5591 | #define USB_OBSERVE_DPPD_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 5592 | #define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK) |
mbed_official | 121:7f86b4238bec | 5593 | #define USB_OBSERVE_DPPU_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 5594 | #define USB_OBSERVE_DPPU_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 5595 | #define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK) |
mbed_official | 121:7f86b4238bec | 5596 | |
mbed_official | 121:7f86b4238bec | 5597 | /*! @name CONTROL - USB OTG Control register */ |
mbed_official | 121:7f86b4238bec | 5598 | #define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 5599 | #define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 5600 | #define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK) |
mbed_official | 121:7f86b4238bec | 5601 | |
mbed_official | 121:7f86b4238bec | 5602 | /*! @name USBTRC0 - USB Transceiver Control register 0 */ |
mbed_official | 121:7f86b4238bec | 5603 | #define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 5604 | #define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 5605 | #define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK) |
mbed_official | 121:7f86b4238bec | 5606 | #define USB_USBTRC0_SYNC_DET_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 5607 | #define USB_USBTRC0_SYNC_DET_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 5608 | #define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK) |
mbed_official | 121:7f86b4238bec | 5609 | #define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 5610 | #define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 5611 | #define USB_USBTRC0_USB_CLK_RECOVERY_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK) |
mbed_official | 121:7f86b4238bec | 5612 | #define USB_USBTRC0_USBRESMEN_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 5613 | #define USB_USBTRC0_USBRESMEN_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 5614 | #define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK) |
mbed_official | 121:7f86b4238bec | 5615 | #define USB_USBTRC0_USBRESET_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 5616 | #define USB_USBTRC0_USBRESET_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 5617 | #define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK) |
mbed_official | 121:7f86b4238bec | 5618 | |
mbed_official | 121:7f86b4238bec | 5619 | /*! @name USBFRMADJUST - Frame Adjust Register */ |
mbed_official | 121:7f86b4238bec | 5620 | #define USB_USBFRMADJUST_ADJ_MASK (0xFFU) |
mbed_official | 121:7f86b4238bec | 5621 | #define USB_USBFRMADJUST_ADJ_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 5622 | #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK) |
mbed_official | 121:7f86b4238bec | 5623 | |
mbed_official | 121:7f86b4238bec | 5624 | /*! @name KEEP_ALIVE_CTRL - Keep Alive mode control */ |
mbed_official | 121:7f86b4238bec | 5625 | #define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_MASK (0x1U) |
mbed_official | 121:7f86b4238bec | 5626 | #define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 5627 | #define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_MASK) |
mbed_official | 121:7f86b4238bec | 5628 | #define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 5629 | #define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 5630 | #define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_MASK) |
mbed_official | 121:7f86b4238bec | 5631 | #define USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 5632 | #define USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 5633 | #define USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_MASK) |
mbed_official | 121:7f86b4238bec | 5634 | #define USB_KEEP_ALIVE_CTRL_AHB_DLY_EN_MASK (0x8U) |
mbed_official | 121:7f86b4238bec | 5635 | #define USB_KEEP_ALIVE_CTRL_AHB_DLY_EN_SHIFT (3U) |
mbed_official | 121:7f86b4238bec | 5636 | #define USB_KEEP_ALIVE_CTRL_AHB_DLY_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_AHB_DLY_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_AHB_DLY_EN_MASK) |
mbed_official | 121:7f86b4238bec | 5637 | #define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 5638 | #define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 5639 | #define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_MASK) |
mbed_official | 121:7f86b4238bec | 5640 | #define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 5641 | #define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 5642 | #define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_SHIFT)) & USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_MASK) |
mbed_official | 121:7f86b4238bec | 5643 | |
mbed_official | 121:7f86b4238bec | 5644 | /*! @name KEEP_ALIVE_WKCTRL - Keep Alive mode wakeup control */ |
mbed_official | 121:7f86b4238bec | 5645 | #define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_MASK (0xFU) |
mbed_official | 121:7f86b4238bec | 5646 | #define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 5647 | #define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_SHIFT)) & USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_MASK) |
mbed_official | 121:7f86b4238bec | 5648 | #define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_MASK (0xF0U) |
mbed_official | 121:7f86b4238bec | 5649 | #define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 5650 | #define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_SHIFT)) & USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_MASK) |
mbed_official | 121:7f86b4238bec | 5651 | |
mbed_official | 121:7f86b4238bec | 5652 | /*! @name CLK_RECOVER_CTRL - USB Clock recovery control */ |
mbed_official | 121:7f86b4238bec | 5653 | #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 5654 | #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 5655 | #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK) |
mbed_official | 121:7f86b4238bec | 5656 | #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 5657 | #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 5658 | #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK) |
mbed_official | 121:7f86b4238bec | 5659 | #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 5660 | #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 5661 | #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK) |
mbed_official | 121:7f86b4238bec | 5662 | |
mbed_official | 121:7f86b4238bec | 5663 | /*! @name CLK_RECOVER_IRC_EN - IRC48M oscillator enable register */ |
mbed_official | 121:7f86b4238bec | 5664 | #define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK (0x2U) |
mbed_official | 121:7f86b4238bec | 5665 | #define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT (1U) |
mbed_official | 121:7f86b4238bec | 5666 | #define USB_CLK_RECOVER_IRC_EN_IRC_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK) |
mbed_official | 121:7f86b4238bec | 5667 | |
mbed_official | 121:7f86b4238bec | 5668 | /*! @name CLK_RECOVER_INT_EN - Clock recovery combined interrupt enable */ |
mbed_official | 121:7f86b4238bec | 5669 | #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 5670 | #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 5671 | #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT)) & USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK) |
mbed_official | 121:7f86b4238bec | 5672 | |
mbed_official | 121:7f86b4238bec | 5673 | /*! @name CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status */ |
mbed_official | 121:7f86b4238bec | 5674 | #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U) |
mbed_official | 121:7f86b4238bec | 5675 | #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U) |
mbed_official | 121:7f86b4238bec | 5676 | #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK) |
mbed_official | 121:7f86b4238bec | 5677 | |
mbed_official | 121:7f86b4238bec | 5678 | |
mbed_official | 121:7f86b4238bec | 5679 | /*! |
mbed_official | 121:7f86b4238bec | 5680 | * @} |
mbed_official | 121:7f86b4238bec | 5681 | */ /* end of group USB_Register_Masks */ |
mbed_official | 121:7f86b4238bec | 5682 | |
mbed_official | 121:7f86b4238bec | 5683 | |
mbed_official | 121:7f86b4238bec | 5684 | /* USB - Peripheral instance base addresses */ |
mbed_official | 121:7f86b4238bec | 5685 | /** Peripheral USB0 base address */ |
mbed_official | 121:7f86b4238bec | 5686 | #define USB0_BASE (0x40072000u) |
mbed_official | 121:7f86b4238bec | 5687 | /** Peripheral USB0 base pointer */ |
mbed_official | 121:7f86b4238bec | 5688 | #define USB0 ((USB_Type *)USB0_BASE) |
mbed_official | 121:7f86b4238bec | 5689 | /** Array initializer of USB peripheral base addresses */ |
mbed_official | 121:7f86b4238bec | 5690 | #define USB_BASE_ADDRS { USB0_BASE } |
mbed_official | 121:7f86b4238bec | 5691 | /** Array initializer of USB peripheral base pointers */ |
mbed_official | 121:7f86b4238bec | 5692 | #define USB_BASE_PTRS { USB0 } |
mbed_official | 121:7f86b4238bec | 5693 | /** Interrupt vectors for the USB peripheral type */ |
mbed_official | 121:7f86b4238bec | 5694 | #define USB_IRQS { USB0_IRQn } |
mbed_official | 121:7f86b4238bec | 5695 | |
mbed_official | 121:7f86b4238bec | 5696 | /*! |
mbed_official | 121:7f86b4238bec | 5697 | * @} |
mbed_official | 121:7f86b4238bec | 5698 | */ /* end of group USB_Peripheral_Access_Layer */ |
mbed_official | 121:7f86b4238bec | 5699 | |
mbed_official | 121:7f86b4238bec | 5700 | |
mbed_official | 121:7f86b4238bec | 5701 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 5702 | -- VREF Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 5703 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 5704 | |
mbed_official | 121:7f86b4238bec | 5705 | /*! |
mbed_official | 121:7f86b4238bec | 5706 | * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer |
mbed_official | 121:7f86b4238bec | 5707 | * @{ |
mbed_official | 121:7f86b4238bec | 5708 | */ |
mbed_official | 121:7f86b4238bec | 5709 | |
mbed_official | 121:7f86b4238bec | 5710 | /** VREF - Register Layout Typedef */ |
mbed_official | 121:7f86b4238bec | 5711 | typedef struct { |
mbed_official | 121:7f86b4238bec | 5712 | __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */ |
mbed_official | 121:7f86b4238bec | 5713 | __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */ |
mbed_official | 121:7f86b4238bec | 5714 | } VREF_Type; |
mbed_official | 121:7f86b4238bec | 5715 | |
mbed_official | 121:7f86b4238bec | 5716 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 5717 | -- VREF Register Masks |
mbed_official | 121:7f86b4238bec | 5718 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 5719 | |
mbed_official | 121:7f86b4238bec | 5720 | /*! |
mbed_official | 121:7f86b4238bec | 5721 | * @addtogroup VREF_Register_Masks VREF Register Masks |
mbed_official | 121:7f86b4238bec | 5722 | * @{ |
mbed_official | 121:7f86b4238bec | 5723 | */ |
mbed_official | 121:7f86b4238bec | 5724 | |
mbed_official | 121:7f86b4238bec | 5725 | /*! @name TRM - VREF Trim Register */ |
mbed_official | 121:7f86b4238bec | 5726 | #define VREF_TRM_TRIM_MASK (0x3FU) |
mbed_official | 121:7f86b4238bec | 5727 | #define VREF_TRM_TRIM_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 5728 | #define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK) |
mbed_official | 121:7f86b4238bec | 5729 | #define VREF_TRM_CHOPEN_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 5730 | #define VREF_TRM_CHOPEN_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 5731 | #define VREF_TRM_CHOPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK) |
mbed_official | 121:7f86b4238bec | 5732 | |
mbed_official | 121:7f86b4238bec | 5733 | /*! @name SC - VREF Status and Control Register */ |
mbed_official | 121:7f86b4238bec | 5734 | #define VREF_SC_MODE_LV_MASK (0x3U) |
mbed_official | 121:7f86b4238bec | 5735 | #define VREF_SC_MODE_LV_SHIFT (0U) |
mbed_official | 121:7f86b4238bec | 5736 | #define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK) |
mbed_official | 121:7f86b4238bec | 5737 | #define VREF_SC_VREFST_MASK (0x4U) |
mbed_official | 121:7f86b4238bec | 5738 | #define VREF_SC_VREFST_SHIFT (2U) |
mbed_official | 121:7f86b4238bec | 5739 | #define VREF_SC_VREFST(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK) |
mbed_official | 121:7f86b4238bec | 5740 | #define VREF_SC_ICOMPEN_MASK (0x20U) |
mbed_official | 121:7f86b4238bec | 5741 | #define VREF_SC_ICOMPEN_SHIFT (5U) |
mbed_official | 121:7f86b4238bec | 5742 | #define VREF_SC_ICOMPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_ICOMPEN_SHIFT)) & VREF_SC_ICOMPEN_MASK) |
mbed_official | 121:7f86b4238bec | 5743 | #define VREF_SC_REGEN_MASK (0x40U) |
mbed_official | 121:7f86b4238bec | 5744 | #define VREF_SC_REGEN_SHIFT (6U) |
mbed_official | 121:7f86b4238bec | 5745 | #define VREF_SC_REGEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK) |
mbed_official | 121:7f86b4238bec | 5746 | #define VREF_SC_VREFEN_MASK (0x80U) |
mbed_official | 121:7f86b4238bec | 5747 | #define VREF_SC_VREFEN_SHIFT (7U) |
mbed_official | 121:7f86b4238bec | 5748 | #define VREF_SC_VREFEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK) |
mbed_official | 121:7f86b4238bec | 5749 | |
mbed_official | 121:7f86b4238bec | 5750 | |
mbed_official | 121:7f86b4238bec | 5751 | /*! |
mbed_official | 121:7f86b4238bec | 5752 | * @} |
mbed_official | 121:7f86b4238bec | 5753 | */ /* end of group VREF_Register_Masks */ |
mbed_official | 121:7f86b4238bec | 5754 | |
mbed_official | 121:7f86b4238bec | 5755 | |
mbed_official | 121:7f86b4238bec | 5756 | /* VREF - Peripheral instance base addresses */ |
mbed_official | 121:7f86b4238bec | 5757 | /** Peripheral VREF base address */ |
mbed_official | 121:7f86b4238bec | 5758 | #define VREF_BASE (0x40074000u) |
mbed_official | 121:7f86b4238bec | 5759 | /** Peripheral VREF base pointer */ |
mbed_official | 121:7f86b4238bec | 5760 | #define VREF ((VREF_Type *)VREF_BASE) |
mbed_official | 121:7f86b4238bec | 5761 | /** Array initializer of VREF peripheral base addresses */ |
mbed_official | 121:7f86b4238bec | 5762 | #define VREF_BASE_ADDRS { VREF_BASE } |
mbed_official | 121:7f86b4238bec | 5763 | /** Array initializer of VREF peripheral base pointers */ |
mbed_official | 121:7f86b4238bec | 5764 | #define VREF_BASE_PTRS { VREF } |
mbed_official | 121:7f86b4238bec | 5765 | |
mbed_official | 121:7f86b4238bec | 5766 | /*! |
mbed_official | 121:7f86b4238bec | 5767 | * @} |
mbed_official | 121:7f86b4238bec | 5768 | */ /* end of group VREF_Peripheral_Access_Layer */ |
mbed_official | 121:7f86b4238bec | 5769 | |
mbed_official | 121:7f86b4238bec | 5770 | |
mbed_official | 121:7f86b4238bec | 5771 | /* |
mbed_official | 121:7f86b4238bec | 5772 | ** End of section using anonymous unions |
mbed_official | 121:7f86b4238bec | 5773 | */ |
mbed_official | 121:7f86b4238bec | 5774 | |
mbed_official | 121:7f86b4238bec | 5775 | #if defined(__ARMCC_VERSION) |
mbed_official | 121:7f86b4238bec | 5776 | #pragma pop |
mbed_official | 121:7f86b4238bec | 5777 | #elif defined(__CWCC__) |
mbed_official | 121:7f86b4238bec | 5778 | #pragma pop |
mbed_official | 121:7f86b4238bec | 5779 | #elif defined(__GNUC__) |
mbed_official | 121:7f86b4238bec | 5780 | /* leave anonymous unions enabled */ |
mbed_official | 121:7f86b4238bec | 5781 | #elif defined(__IAR_SYSTEMS_ICC__) |
mbed_official | 121:7f86b4238bec | 5782 | #pragma language=default |
mbed_official | 121:7f86b4238bec | 5783 | #else |
mbed_official | 121:7f86b4238bec | 5784 | #error Not supported compiler type |
mbed_official | 121:7f86b4238bec | 5785 | #endif |
mbed_official | 121:7f86b4238bec | 5786 | |
mbed_official | 121:7f86b4238bec | 5787 | /*! |
mbed_official | 121:7f86b4238bec | 5788 | * @} |
mbed_official | 121:7f86b4238bec | 5789 | */ /* end of group Peripheral_access_layer */ |
mbed_official | 121:7f86b4238bec | 5790 | |
mbed_official | 121:7f86b4238bec | 5791 | |
mbed_official | 121:7f86b4238bec | 5792 | /* ---------------------------------------------------------------------------- |
mbed_official | 121:7f86b4238bec | 5793 | -- SDK Compatibility |
mbed_official | 121:7f86b4238bec | 5794 | ---------------------------------------------------------------------------- */ |
mbed_official | 121:7f86b4238bec | 5795 | |
mbed_official | 121:7f86b4238bec | 5796 | /*! |
mbed_official | 121:7f86b4238bec | 5797 | * @addtogroup SDK_Compatibility_Symbols SDK Compatibility |
mbed_official | 121:7f86b4238bec | 5798 | * @{ |
mbed_official | 121:7f86b4238bec | 5799 | */ |
mbed_official | 121:7f86b4238bec | 5800 | |
mbed_official | 121:7f86b4238bec | 5801 | /* No SDK compatibility issues. */ |
mbed_official | 121:7f86b4238bec | 5802 | |
mbed_official | 121:7f86b4238bec | 5803 | /*! |
mbed_official | 121:7f86b4238bec | 5804 | * @} |
mbed_official | 121:7f86b4238bec | 5805 | */ /* end of group SDK_Compatibility_Symbols */ |
mbed_official | 121:7f86b4238bec | 5806 | |
mbed_official | 121:7f86b4238bec | 5807 | |
mbed_official | 121:7f86b4238bec | 5808 | #endif /* _MKL27Z644_H_ */ |
mbed_official | 121:7f86b4238bec | 5809 |