added prescaler for 16 bit pwm in LPC1347 target
Fork of mbed-dev by
Diff: targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/system_MKL26Z4.h
- Revision:
- 144:ef7eb2e8f9f7
- Parent:
- 0:9b334a45a8ff
--- a/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/system_MKL26Z4.h Tue Aug 02 14:07:36 2016 +0000 +++ b/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/system_MKL26Z4.h Fri Sep 02 15:07:44 2016 +0100 @@ -1,351 +1,351 @@ -/* -** ################################################################### -** Processors: MKL26Z128CAL4 -** MKL26Z128VFM4 -** MKL26Z64VFM4 -** MKL26Z32VM4 -** MKL26Z128VFT4 -** MKL26Z64VFT4 -** MKL26Z32VFT4 -** MKL26Z128VLH4 -** MKL26Z64VLH4 -** MKL26Z32VLH4 -** MKL26Z256VLH4 -** MKL26Z256VLL4 -** MKL26Z128VLL4 -** MKL26Z256VMC4 -** MKL26Z128VMC4 -** MKL26Z256VMP4 -** -** Compilers: Keil ARM C/C++ Compiler -** Freescale C/C++ for Embedded ARM -** GNU C Compiler -** GNU C Compiler - CodeSourcery Sourcery G++ -** IAR ANSI C/C++ Compiler for ARM -** -** Reference manuals: KL26P121M48SF4RM Rev. 3.2, October 2013 -** KL26P121M48SF4RM, Rev.2, Dec 2012 -** -** Version: rev. 1.7, 2015-01-13 -** Build: b150129 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** Copyright (c) 2015 Freescale Semiconductor, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Revisions: -** - rev. 1.0 (2012-12-12) -** Initial version. -** - rev. 1.1 (2013-04-05) -** Changed start of doxygen comment. -** - rev. 1.2 (2013-04-12) -** SystemInit function fixed for clock configuration 1. -** Name of the interrupt num. 31 updated to reflect proper function. -** - rev. 1.3 (2014-05-27) -** Updated to Kinetis SDK support standard. -** MCG OSC clock select supported (MCG_C7[OSCSEL]). -** - rev. 1.4 (2014-07-25) -** System initialization updated: -** - Prefix added to the system initialization parameterization constants to avoid name conflicts.. -** - VLLSx wake-up recovery added. -** - Delay of 1 ms added to SystemInit() to ensure stable FLL output in FEI and FEE MCG modes. -** - rev. 1.5 (2014-08-28) -** Update of system files - default clock configuration changed, fix of OSC initialization. -** Update of startup files - possibility to override DefaultISR added. -** - rev. 1.6 (2014-10-14) -** Renamed interrupt vector LPTimer to LPTMR0 -** - rev. 1.7 (2015-01-13) -** Update of the copyright. -** -** ################################################################### -*/ - -/*! - * @file MKL26Z4 - * @version 1.7 - * @date 2015-01-13 - * @brief Device specific configuration file for MKL26Z4 (header file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#ifndef SYSTEM_MKL26Z4_H_ -#define SYSTEM_MKL26Z4_H_ /**< Symbol preventing repeated inclusion */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include <stdint.h> - - -#ifndef DISABLE_WDOG - #define DISABLE_WDOG 1 -#endif - -#define ACK_ISOLATION 1 - -#ifndef RTC_CLKIN_USED - #define RTC_CLKIN_USED 1 -#endif - - -/* MCG mode constants */ - -#define MCG_MODE_FEI 0U -#define MCG_MODE_FBI 1U -#define MCG_MODE_BLPI 2U -#define MCG_MODE_FEE 3U -#define MCG_MODE_FBE 4U -#define MCG_MODE_BLPE 5U -#define MCG_MODE_PBE 6U -#define MCG_MODE_PEE 7U - -/* Predefined clock setups - 0 ... Default part configuration - Multipurpose Clock Generator (MCG) in FEI mode. - Reference clock source for MCG module: Slow internal reference clock - Core clock = 20.97152MHz - Bus clock = 20.97152MHz - 1 ... Maximum achievable clock frequency configuration - Multipurpose Clock Generator (MCG) in PEE mode. - Reference clock source for MCG module: System oscillator reference clock - Core clock = 48MHz - Bus clock = 24MHz - 2 ... Chip internally clocked, ready for Very Low Power Run mode - Multipurpose Clock Generator (MCG) in BLPI mode. - Reference clock source for MCG module: Fast internal reference clock - Core clock = 4MHz - Bus clock = 0.8MHz - 3 ... Chip externally clocked, ready for Very Low Power Run mode - Multipurpose Clock Generator (MCG) in BLPE mode. - Reference clock source for MCG module: System oscillator reference clock - Core clock = 4MHz - Bus clock = 1MHz - 4 ... USB clock setup - Multipurpose Clock Generator (MCG) in PEE mode. - Reference clock source for MCG module: System oscillator reference clock - Core clock = 48MHz - Bus clock = 24MHz -*/ - -/* Define clock source values */ - -#define CPU_XTAL_CLK_HZ 8000000U /* Value of the external crystal or oscillator clock frequency of the system oscillator (OSC) in Hz */ -#define CPU_INT_SLOW_CLK_HZ 32768U /* Value of the slow internal oscillator clock frequency in Hz */ -#define CPU_INT_FAST_CLK_HZ 4000000U /* Value of the fast internal oscillator clock frequency in Hz */ - -/* RTC oscillator setting */ - -/* Low power mode enable */ -/* SMC_PMPROT: AVLP=1,ALLS=1,AVLLS=1 */ -#define SYSTEM_SMC_PMPROT_VALUE 0x2AU /* SMC_PMPROT */ - -/* Internal reference clock trim */ -/* #undef SLOW_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */ -/* #undef SLOW_FINE_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */ -/* #undef FAST_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */ -/* #undef FAST_FINE_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */ - -#ifdef CLOCK_SETUP -#if (CLOCK_SETUP == 0) - #define DEFAULT_SYSTEM_CLOCK 20971520U /* Default System clock value */ - #define MCG_MODE MCG_MODE_FEI /* Clock generator mode */ - /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */ - #define SYSTEM_MCG_C1_VALUE 0x06U /* MCG_C1 */ - /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */ - #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */ - /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */ - #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */ - /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */ - #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */ - /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */ - #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */ - /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */ - #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */ - /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ - #define SYSTEM_OSC0_CR_VALUE 0x80U /* OSC0_CR */ - /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */ - #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */ - /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=0 */ - #define SYSTEM_SIM_CLKDIV1_VALUE 0x00U /* SIM_CLKDIV1 */ - /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=3 */ - #define SYSTEM_SIM_SOPT1_VALUE 0x000C0000U /* SIM_SOPT1 */ - /* SIM_SOPT2: UART0SRC=0,TPMSRC=1,USBSRC=0,PLLFLLSEL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */ - #define SYSTEM_SIM_SOPT2_VALUE 0x01000000U /* SIM_SOPT2 */ -#elif (CLOCK_SETUP == 1) - #define DEFAULT_SYSTEM_CLOCK 48000000U /* Default System clock value */ - #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */ - /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ - #define SYSTEM_MCG_C1_VALUE 0x1AU /* MCG_C1 */ - /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */ - #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */ - /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */ - #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */ - /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */ - #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */ - /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=3 */ - #define SYSTEM_MCG_C5_VALUE 0x03U /* MCG_C5 */ - /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */ - #define SYSTEM_MCG_C6_VALUE 0x40U /* MCG_C6 */ - /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ - #define SYSTEM_OSC0_CR_VALUE 0x80U /* OSC0_CR */ - /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */ - #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */ - /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */ - #define SYSTEM_SIM_CLKDIV1_VALUE 0x00010000U /* SIM_CLKDIV1 */ - /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=3 */ - #define SYSTEM_SIM_SOPT1_VALUE 0x000C0000U /* SIM_SOPT1 */ - /* SIM_SOPT2: UART0SRC=0,TPMSRC=1,USBSRC=0,PLLFLLSEL=1,CLKOUTSEL=0,RTCCLKOUTSEL=0 */ - #define SYSTEM_SIM_SOPT2_VALUE 0x01010000U /* SIM_SOPT2 */ -#elif (CLOCK_SETUP == 2) - #define DEFAULT_SYSTEM_CLOCK 4000000U /* Default System clock value */ - #define MCG_MODE MCG_MODE_BLPI /* Clock generator mode */ - /* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */ - #define SYSTEM_MCG_C1_VALUE 0x46U /* MCG_C1 */ - /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE0=2,HGO0=0,EREFS0=1,LP=1,IRCS=1 */ - #define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */ - /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */ - #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */ - /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */ - #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */ - /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */ - #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */ - /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */ - #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */ - /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ - #define SYSTEM_OSC0_CR_VALUE 0x80U /* OSC0_CR */ - /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */ - #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */ - /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=4 */ - #define SYSTEM_SIM_CLKDIV1_VALUE 0x00040000U /* SIM_CLKDIV1 */ - /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=3 */ - #define SYSTEM_SIM_SOPT1_VALUE 0x000C0000U /* SIM_SOPT1 */ - /* SIM_SOPT2: UART0SRC=0,TPMSRC=2,USBSRC=0,PLLFLLSEL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */ - #define SYSTEM_SIM_SOPT2_VALUE 0x02000000U /* SIM_SOPT2 */ -#elif (CLOCK_SETUP == 3) - #define DEFAULT_SYSTEM_CLOCK 4000000U /* Default System clock value */ - #define MCG_MODE MCG_MODE_BLPE /* Clock generator mode */ - /* MCG_C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ - #define SYSTEM_MCG_C1_VALUE 0x9AU /* MCG_C1 */ - /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE0=2,HGO0=0,EREFS0=1,LP=1,IRCS=1 */ - #define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */ - /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */ - #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */ - /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */ - #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */ - /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */ - #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */ - /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */ - #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */ - /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ - #define SYSTEM_OSC0_CR_VALUE 0x80U /* OSC0_CR */ - /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */ - #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */ - /* SIM_CLKDIV1: OUTDIV1=1,OUTDIV4=3 */ - #define SYSTEM_SIM_CLKDIV1_VALUE 0x10030000U /* SIM_CLKDIV1 */ - /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=3 */ - #define SYSTEM_SIM_SOPT1_VALUE 0x000C0000U /* SIM_SOPT1 */ - /* SIM_SOPT2: UART0SRC=0,TPMSRC=2,USBSRC=0,PLLFLLSEL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */ - #define SYSTEM_SIM_SOPT2_VALUE 0x02000000U /* SIM_SOPT2 */ -#elif (CLOCK_SETUP == 4) - #define DEFAULT_SYSTEM_CLOCK 48000000U /* Default System clock value */ - #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */ - /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ - #define SYSTEM_MCG_C1_VALUE 0x1AU /* MCG_C1 */ - /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */ - #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */ - /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */ - #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */ - /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */ - #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */ - /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=3 */ - #define SYSTEM_MCG_C5_VALUE 0x03U /* MCG_C5 */ - /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=24 */ - #define SYSTEM_MCG_C6_VALUE 0x58U /* MCG_C6 */ - /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ - #define SYSTEM_OSC0_CR_VALUE 0x80U /* OSC0_CR */ - /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */ - #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */ - /* SIM_CLKDIV1: OUTDIV1=1,OUTDIV4=1 */ - #define SYSTEM_SIM_CLKDIV1_VALUE 0x10010000U /* SIM_CLKDIV1 */ - /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=3 */ - #define SYSTEM_SIM_SOPT1_VALUE 0x000C0000U /* SIM_SOPT1 */ - /* SIM_SOPT2: UART0SRC=0,TPMSRC=1,USBSRC=0,PLLFLLSEL=1,CLKOUTSEL=0,RTCCLKOUTSEL=0 */ - #define SYSTEM_SIM_SOPT2_VALUE 0x01010000U /* SIM_SOPT2 */ -#else - #error The selected clock setup is not supported. -#endif -#else //#ifdef CLOCK_SETUP - #define DEFAULT_SYSTEM_CLOCK 20971520U /* Default System clock value */ -#endif //#ifdef CLOCK_SETUP - - -/** - * @brief System clock frequency (core clock) - * - * The system clock frequency supplied to the SysTick timer and the processor - * core clock. This variable can be used by the user application to setup the - * SysTick timer or configure other parameters. It may also be used by debugger to - * query the frequency of the debug timer or configure the trace clock speed - * SystemCoreClock is initialized with a correct predefined value. - */ -extern uint32_t SystemCoreClock; - -/** - * @brief Setup the microcontroller system. - * - * Typically this function configures the oscillator (PLL) that is part of the - * microcontroller device. For systems with variable clock speed it also updates - * the variable SystemCoreClock. SystemInit is called from startup_device file. - */ -void SystemInit (void); - -/** - * @brief Updates the SystemCoreClock variable. - * - * It must be called whenever the core clock is changed during program - * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates - * the current core clock. - */ -void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* #if !defined(SYSTEM_MKL26Z4_H_) */ +/* +** ################################################################### +** Processors: MKL26Z128CAL4 +** MKL26Z128VFM4 +** MKL26Z64VFM4 +** MKL26Z32VM4 +** MKL26Z128VFT4 +** MKL26Z64VFT4 +** MKL26Z32VFT4 +** MKL26Z128VLH4 +** MKL26Z64VLH4 +** MKL26Z32VLH4 +** MKL26Z256VLH4 +** MKL26Z256VLL4 +** MKL26Z128VLL4 +** MKL26Z256VMC4 +** MKL26Z128VMC4 +** MKL26Z256VMP4 +** +** Compilers: Keil ARM C/C++ Compiler +** Freescale C/C++ for Embedded ARM +** GNU C Compiler +** GNU C Compiler - CodeSourcery Sourcery G++ +** IAR ANSI C/C++ Compiler for ARM +** +** Reference manuals: KL26P121M48SF4RM Rev. 3.2, October 2013 +** KL26P121M48SF4RM, Rev.2, Dec 2012 +** +** Version: rev. 1.7, 2015-01-13 +** Build: b150129 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright (c) 2015 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2012-12-12) +** Initial version. +** - rev. 1.1 (2013-04-05) +** Changed start of doxygen comment. +** - rev. 1.2 (2013-04-12) +** SystemInit function fixed for clock configuration 1. +** Name of the interrupt num. 31 updated to reflect proper function. +** - rev. 1.3 (2014-05-27) +** Updated to Kinetis SDK support standard. +** MCG OSC clock select supported (MCG_C7[OSCSEL]). +** - rev. 1.4 (2014-07-25) +** System initialization updated: +** - Prefix added to the system initialization parameterization constants to avoid name conflicts.. +** - VLLSx wake-up recovery added. +** - Delay of 1 ms added to SystemInit() to ensure stable FLL output in FEI and FEE MCG modes. +** - rev. 1.5 (2014-08-28) +** Update of system files - default clock configuration changed, fix of OSC initialization. +** Update of startup files - possibility to override DefaultISR added. +** - rev. 1.6 (2014-10-14) +** Renamed interrupt vector LPTimer to LPTMR0 +** - rev. 1.7 (2015-01-13) +** Update of the copyright. +** +** ################################################################### +*/ + +/*! + * @file MKL26Z4 + * @version 1.7 + * @date 2015-01-13 + * @brief Device specific configuration file for MKL26Z4 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef SYSTEM_MKL26Z4_H_ +#define SYSTEM_MKL26Z4_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include <stdint.h> + + +#ifndef DISABLE_WDOG + #define DISABLE_WDOG 1 +#endif + +#define ACK_ISOLATION 1 + +#ifndef RTC_CLKIN_USED + #define RTC_CLKIN_USED 1 +#endif + + +/* MCG mode constants */ + +#define MCG_MODE_FEI 0U +#define MCG_MODE_FBI 1U +#define MCG_MODE_BLPI 2U +#define MCG_MODE_FEE 3U +#define MCG_MODE_FBE 4U +#define MCG_MODE_BLPE 5U +#define MCG_MODE_PBE 6U +#define MCG_MODE_PEE 7U + +/* Predefined clock setups + 0 ... Default part configuration + Multipurpose Clock Generator (MCG) in FEI mode. + Reference clock source for MCG module: Slow internal reference clock + Core clock = 20.97152MHz + Bus clock = 20.97152MHz + 1 ... Maximum achievable clock frequency configuration + Multipurpose Clock Generator (MCG) in PEE mode. + Reference clock source for MCG module: System oscillator reference clock + Core clock = 48MHz + Bus clock = 24MHz + 2 ... Chip internally clocked, ready for Very Low Power Run mode + Multipurpose Clock Generator (MCG) in BLPI mode. + Reference clock source for MCG module: Fast internal reference clock + Core clock = 4MHz + Bus clock = 0.8MHz + 3 ... Chip externally clocked, ready for Very Low Power Run mode + Multipurpose Clock Generator (MCG) in BLPE mode. + Reference clock source for MCG module: System oscillator reference clock + Core clock = 4MHz + Bus clock = 1MHz + 4 ... USB clock setup + Multipurpose Clock Generator (MCG) in PEE mode. + Reference clock source for MCG module: System oscillator reference clock + Core clock = 48MHz + Bus clock = 24MHz +*/ + +/* Define clock source values */ + +#define CPU_XTAL_CLK_HZ 8000000U /* Value of the external crystal or oscillator clock frequency of the system oscillator (OSC) in Hz */ +#define CPU_INT_SLOW_CLK_HZ 32768U /* Value of the slow internal oscillator clock frequency in Hz */ +#define CPU_INT_FAST_CLK_HZ 4000000U /* Value of the fast internal oscillator clock frequency in Hz */ + +/* RTC oscillator setting */ + +/* Low power mode enable */ +/* SMC_PMPROT: AVLP=1,ALLS=1,AVLLS=1 */ +#define SYSTEM_SMC_PMPROT_VALUE 0x2AU /* SMC_PMPROT */ + +/* Internal reference clock trim */ +/* #undef SLOW_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */ +/* #undef SLOW_FINE_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */ +/* #undef FAST_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */ +/* #undef FAST_FINE_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */ + +#ifdef CLOCK_SETUP +#if (CLOCK_SETUP == 0) + #define DEFAULT_SYSTEM_CLOCK 20971520U /* Default System clock value */ + #define MCG_MODE MCG_MODE_FEI /* Clock generator mode */ + /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */ + #define SYSTEM_MCG_C1_VALUE 0x06U /* MCG_C1 */ + /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */ + #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */ + /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */ + #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */ + /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */ + #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */ + /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */ + #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */ + /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */ + #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */ + /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ + #define SYSTEM_OSC0_CR_VALUE 0x80U /* OSC0_CR */ + /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */ + #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */ + /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=0 */ + #define SYSTEM_SIM_CLKDIV1_VALUE 0x00U /* SIM_CLKDIV1 */ + /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=3 */ + #define SYSTEM_SIM_SOPT1_VALUE 0x000C0000U /* SIM_SOPT1 */ + /* SIM_SOPT2: UART0SRC=0,TPMSRC=1,USBSRC=0,PLLFLLSEL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */ + #define SYSTEM_SIM_SOPT2_VALUE 0x01000000U /* SIM_SOPT2 */ +#elif (CLOCK_SETUP == 1) + #define DEFAULT_SYSTEM_CLOCK 48000000U /* Default System clock value */ + #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */ + /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ + #define SYSTEM_MCG_C1_VALUE 0x1AU /* MCG_C1 */ + /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */ + #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */ + /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */ + #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */ + /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */ + #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */ + /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=3 */ + #define SYSTEM_MCG_C5_VALUE 0x03U /* MCG_C5 */ + /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */ + #define SYSTEM_MCG_C6_VALUE 0x40U /* MCG_C6 */ + /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ + #define SYSTEM_OSC0_CR_VALUE 0x80U /* OSC0_CR */ + /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */ + #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */ + /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */ + #define SYSTEM_SIM_CLKDIV1_VALUE 0x00010000U /* SIM_CLKDIV1 */ + /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=3 */ + #define SYSTEM_SIM_SOPT1_VALUE 0x000C0000U /* SIM_SOPT1 */ + /* SIM_SOPT2: UART0SRC=0,TPMSRC=1,USBSRC=0,PLLFLLSEL=1,CLKOUTSEL=0,RTCCLKOUTSEL=0 */ + #define SYSTEM_SIM_SOPT2_VALUE 0x01010000U /* SIM_SOPT2 */ +#elif (CLOCK_SETUP == 2) + #define DEFAULT_SYSTEM_CLOCK 4000000U /* Default System clock value */ + #define MCG_MODE MCG_MODE_BLPI /* Clock generator mode */ + /* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */ + #define SYSTEM_MCG_C1_VALUE 0x46U /* MCG_C1 */ + /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE0=2,HGO0=0,EREFS0=1,LP=1,IRCS=1 */ + #define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */ + /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */ + #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */ + /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */ + #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */ + /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */ + #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */ + /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */ + #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */ + /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ + #define SYSTEM_OSC0_CR_VALUE 0x80U /* OSC0_CR */ + /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */ + #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */ + /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=4 */ + #define SYSTEM_SIM_CLKDIV1_VALUE 0x00040000U /* SIM_CLKDIV1 */ + /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=3 */ + #define SYSTEM_SIM_SOPT1_VALUE 0x000C0000U /* SIM_SOPT1 */ + /* SIM_SOPT2: UART0SRC=0,TPMSRC=2,USBSRC=0,PLLFLLSEL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */ + #define SYSTEM_SIM_SOPT2_VALUE 0x02000000U /* SIM_SOPT2 */ +#elif (CLOCK_SETUP == 3) + #define DEFAULT_SYSTEM_CLOCK 4000000U /* Default System clock value */ + #define MCG_MODE MCG_MODE_BLPE /* Clock generator mode */ + /* MCG_C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ + #define SYSTEM_MCG_C1_VALUE 0x9AU /* MCG_C1 */ + /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE0=2,HGO0=0,EREFS0=1,LP=1,IRCS=1 */ + #define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */ + /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */ + #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */ + /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */ + #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */ + /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */ + #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */ + /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */ + #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */ + /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ + #define SYSTEM_OSC0_CR_VALUE 0x80U /* OSC0_CR */ + /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */ + #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */ + /* SIM_CLKDIV1: OUTDIV1=1,OUTDIV4=3 */ + #define SYSTEM_SIM_CLKDIV1_VALUE 0x10030000U /* SIM_CLKDIV1 */ + /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=3 */ + #define SYSTEM_SIM_SOPT1_VALUE 0x000C0000U /* SIM_SOPT1 */ + /* SIM_SOPT2: UART0SRC=0,TPMSRC=2,USBSRC=0,PLLFLLSEL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */ + #define SYSTEM_SIM_SOPT2_VALUE 0x02000000U /* SIM_SOPT2 */ +#elif (CLOCK_SETUP == 4) + #define DEFAULT_SYSTEM_CLOCK 48000000U /* Default System clock value */ + #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */ + /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ + #define SYSTEM_MCG_C1_VALUE 0x1AU /* MCG_C1 */ + /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */ + #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */ + /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */ + #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */ + /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */ + #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */ + /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=3 */ + #define SYSTEM_MCG_C5_VALUE 0x03U /* MCG_C5 */ + /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=24 */ + #define SYSTEM_MCG_C6_VALUE 0x58U /* MCG_C6 */ + /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ + #define SYSTEM_OSC0_CR_VALUE 0x80U /* OSC0_CR */ + /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */ + #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */ + /* SIM_CLKDIV1: OUTDIV1=1,OUTDIV4=1 */ + #define SYSTEM_SIM_CLKDIV1_VALUE 0x10010000U /* SIM_CLKDIV1 */ + /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=3 */ + #define SYSTEM_SIM_SOPT1_VALUE 0x000C0000U /* SIM_SOPT1 */ + /* SIM_SOPT2: UART0SRC=0,TPMSRC=1,USBSRC=0,PLLFLLSEL=1,CLKOUTSEL=0,RTCCLKOUTSEL=0 */ + #define SYSTEM_SIM_SOPT2_VALUE 0x01010000U /* SIM_SOPT2 */ +#else + #error The selected clock setup is not supported. +#endif +#else //#ifdef CLOCK_SETUP + #define DEFAULT_SYSTEM_CLOCK 20971520U /* Default System clock value */ +#endif //#ifdef CLOCK_SETUP + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* #if !defined(SYSTEM_MKL26Z4_H_) */