Diff: targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_gpio.c

Revision:

50:a417edff4437

Parent:

0:9b334a45a8ff

Child:

144:ef7eb2e8f9f7

--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_gpio.c	Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_gpio.c	Fri Jan 15 07:45:16 2016 +0000
@@ -2,10 +2,10 @@
  * @file em_gpio.c
  * @brief General Purpose IO (GPIO) peripheral API
  *   devices.
- * @version 3.20.12
+ * @version 4.2.1
  *******************************************************************************
  * @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
  *******************************************************************************
  *
  * Permission is granted to anyone to use this software for any purpose,
@@ -35,6 +35,7 @@
 #include "em_gpio.h"
 
 #if defined(GPIO_COUNT) && (GPIO_COUNT > 0)
+
 /***************************************************************************//**
  * @addtogroup EM_Library
  * @{
@@ -54,7 +55,9 @@
 
 /** Validation of pin typically usable in assert statements. */
 #define GPIO_DRIVEMODE_VALID(mode)    ((mode) <= 3)
-
+#define GPIO_STRENGHT_VALID(strenght) (!((strenght) & \
+                                         ~(_GPIO_P_CTRL_DRIVESTRENGTH_MASK \
+                                           | _GPIO_P_CTRL_DRIVESTRENGTHALT_MASK)))
 /** @endcond */
 
 
@@ -84,7 +87,7 @@
 #endif
 }
 
-
+#if defined (_GPIO_P_CTRL_DRIVEMODE_MASK)
 /***************************************************************************//**
  * @brief
  *   Sets the drive mode for a GPIO port.
@@ -102,8 +105,30 @@
   GPIO->P[port].CTRL = (GPIO->P[port].CTRL & ~(_GPIO_P_CTRL_DRIVEMODE_MASK))
                        | (mode << _GPIO_P_CTRL_DRIVEMODE_SHIFT);
 }
+#endif
 
 
+#if defined (_GPIO_P_CTRL_DRIVESTRENGTH_MASK)
+/***************************************************************************//**
+ * @brief
+ *   Sets the drive strength for a GPIO port.
+ *
+ * @param[in] port
+ *   The GPIO port to access.
+ *
+ * @param[in] strength
+ *   Drive strength to use for port.
+ ******************************************************************************/
+void GPIO_DriveStrengthSet(GPIO_Port_TypeDef port,
+                           GPIO_DriveStrength_TypeDef strength)
+{
+  EFM_ASSERT(GPIO_PORT_VALID(port) && GPIO_STRENGHT_VALID(strength));
+  BUS_RegMaskedWrite(&GPIO->P[port].CTRL,
+                     _GPIO_P_CTRL_DRIVESTRENGTH_MASK | _GPIO_P_CTRL_DRIVESTRENGTHALT_MASK,
+                     strength);
+}
+#endif
+
 /***************************************************************************//**
  * @brief
  *   Configure GPIO interrupt.
@@ -148,34 +173,36 @@
 {
   uint32_t tmp;
 
-  EFM_ASSERT(GPIO_PORT_VALID(port) && GPIO_PIN_VALID(pin));
+  EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin));
 
   /* There are two registers controlling the interrupt configuration:
    * The EXTIPSELL register controls pins 0-7 and EXTIPSELH controls
    * pins 8-15. */
   if (pin < 8)
   {
-    GPIO->EXTIPSELL = (GPIO->EXTIPSELL & ~(0xF << (4 * pin))) |
-                      (port << (4 * pin));
+    BUS_RegMaskedWrite(&GPIO->EXTIPSELL,
+                       0xF << (4 * pin),
+                       port << (4 * pin));
   }
   else
   {
     tmp             = pin - 8;
-    GPIO->EXTIPSELH = (GPIO->EXTIPSELH & ~(0xF << (4 * tmp))) |
-                      (port << (4 * tmp));
+    BUS_RegMaskedWrite(&GPIO->EXTIPSELH,
+                       0xF << (4 * tmp),
+                       port << (4 * tmp));
   }
 
   /* Enable/disable rising edge */
-  BITBAND_Peripheral(&(GPIO->EXTIRISE), pin, (unsigned int)risingEdge);
+  BUS_RegBitWrite(&(GPIO->EXTIRISE), pin, risingEdge);
 
   /* Enable/disable falling edge */
-  BITBAND_Peripheral(&(GPIO->EXTIFALL), pin, (unsigned int)fallingEdge);
+  BUS_RegBitWrite(&(GPIO->EXTIFALL), pin, fallingEdge);
 
   /* Clear any pending interrupt */
   GPIO->IFC = 1 << pin;
 
   /* Finally enable/disable interrupt */
-  BITBAND_Peripheral(&(GPIO->IEN), pin, (unsigned int)enable);
+  BUS_RegBitWrite(&(GPIO->IEN), pin, enable);
 }
 
 
@@ -201,7 +228,7 @@
                      GPIO_Mode_TypeDef mode,
                      unsigned int out)
 {
-  EFM_ASSERT(GPIO_PORT_VALID(port) && GPIO_PIN_VALID(pin));
+  EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin));
 
   /* If disabling pin, do not modify DOUT in order to reduce chance for */
   /* glitch/spike (may not be sufficient precaution in all use cases) */
@@ -209,11 +236,11 @@
   {
     if (out)
     {
-      GPIO->P[port].DOUTSET = 1 << pin;
+      GPIO_PinOutSet(port, pin);
     }
     else
     {
-      GPIO->P[port].DOUTCLR = 1 << pin;
+      GPIO_PinOutClear(port, pin);
     }
   }
 
@@ -221,28 +248,72 @@
    * register controls pins 0-7 and MODEH controls pins 8-15. */
   if (pin < 8)
   {
-    GPIO->P[port].MODEL = (GPIO->P[port].MODEL & ~(0xF << (pin * 4))) |
-                          (mode << (pin * 4));
+    BUS_RegMaskedWrite(&GPIO->P[port].MODEL,
+                       0xF << (pin * 4),
+                       mode << (pin * 4));
   }
   else
   {
-    GPIO->P[port].MODEH = (GPIO->P[port].MODEH & ~(0xF << ((pin - 8) * 4))) |
-                          (mode << ((pin - 8) * 4));
+    BUS_RegMaskedWrite(&GPIO->P[port].MODEH,
+                       0xF << ((pin - 8) * 4),
+                       mode << ((pin - 8) * 4));
   }
 
   if (mode == gpioModeDisabled)
   {
     if (out)
     {
-      GPIO->P[port].DOUTSET = 1 << pin;
+      GPIO_PinOutSet(port, pin);
     }
     else
     {
-      GPIO->P[port].DOUTCLR = 1 << pin;
+      GPIO_PinOutClear(port, pin);
     }
   }
 }
 
+#if defined( _GPIO_EM4WUEN_MASK )
+/**************************************************************************//**
+ * @brief
+ *   Enable GPIO pin wake-up from EM4. When the function exits,
+ *   EM4 mode can be safely entered.
+ *
+ * @note
+ *   It is assumed that the GPIO pin modes are set correctly.
+ *   Valid modes are @ref gpioModeInput and @ref gpioModeInputPull.
+ *
+ * @param[in] pinmask
+ *   Bitmask containing the bitwise logic OR of which GPIO pin(s) to enable.
+ *   Refer to Reference Manuals for pinmask to GPIO port/pin mapping.
+ * @param[in] polaritymask
+ *   Bitmask containing the bitwise logic OR of GPIO pin(s) wake-up polarity.
+ *   Refer to Reference Manuals for pinmask to GPIO port/pin mapping.
+ *****************************************************************************/
+void GPIO_EM4EnablePinWakeup(uint32_t pinmask, uint32_t polaritymask)
+{
+  EFM_ASSERT((pinmask & ~_GPIO_EM4WUEN_MASK) == 0);
+
+#if defined( _GPIO_EM4WUPOL_MASK )
+  EFM_ASSERT((polaritymask & ~_GPIO_EM4WUPOL_MASK) == 0);
+  GPIO->EM4WUPOL &= ~pinmask;               /* Set wakeup polarity */
+  GPIO->EM4WUPOL |= pinmask & polaritymask;
+#elif defined( _GPIO_EXTILEVEL_MASK )
+  EFM_ASSERT((polaritymask & ~_GPIO_EXTILEVEL_MASK) == 0);
+  GPIO->EXTILEVEL &= ~pinmask;
+  GPIO->EXTILEVEL |= pinmask & polaritymask;
+#endif
+  GPIO->EM4WUEN  |= pinmask;                /* Enable wakeup */
+
+  GPIO_EM4SetPinRetention(true);            /* Enable pin retention */
+
+#if defined( _GPIO_CMD_EM4WUCLR_MASK )
+  GPIO->CMD = GPIO_CMD_EM4WUCLR;            /* Clear wake-up logic */
+#elif defined( _GPIO_IFC_EM4WU_MASK )
+  GPIO_IntClear(pinmask);
+#endif
+}
+#endif
+
 /** @} (end addtogroup GPIO) */
 /** @} (end addtogroup EM_Library) */